JP2010079758A - Method of interrupting automatic rewriting of nonvolatile memory, nonvolatile memory and microcomputer - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To automatically interrupt automatic rewriting processing of a nonvolatile memory within a predetermined time. <P>SOLUTION: In the nonvolatile memory 100, a rewriting control unit 120 executes a control flow comprising a plurality of divided control flows to control rewriting of a memory array 130 according to results of decoding a command input from the outside by a command decoding unit 110. The rewriting control unit 120 interrupts the control flow for each time when one divided control flow is completed, and makes the memory array 130 readable. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a technique that enables a read operation by interrupting automatic rewriting of a rewritable nonvolatile memory. Specifically, the present invention relates to a non-volatile memory with a built-in configuration for interrupting automatic rewriting, and further relates to a microcomputer with a built-in configuration for interrupting automatic rewriting of non-volatile memory by integrating a CPU and a non-volatile memory. is there.

  Some rewritable nonvolatile memories have an automatic rewriting function and an interruption function thereof (see Patent Document 1).

It suspends erasure when a hold signal becomes active during automatic erasure, and resumes erasure according to a predetermined state when the hold signal is inactive.
Japanese Patent No. 3415172

  However, in the nonvolatile memory as described above, in order to interrupt the erasure, it is necessary to input a command instructing the interruption to the nonvolatile memory and activate the hold signal. In recent applications for embedding, a task management method is often employed in which a device is controlled while switching a series of processing (tasks) in units of several ms. On the other hand, since rewriting (erasing and writing) of the nonvolatile memory generally takes several milliseconds to several seconds, even if the nonvolatile memory is rewritten during a certain task, the rewriting is not completed during the task. Further, since the contents of the nonvolatile memory cannot be read during rewriting, the program for the next task stored in the nonvolatile memory cannot be executed, and task switching is hindered. In order to solve this, it is necessary to input a command for instructing interruption in order to measure time using a dedicated timer and interrupt rewriting of the nonvolatile memory at a desired time.

  In view of the above points, an object of the present invention is to enable a nonvolatile memory rewrite process to be automatically interrupted within a predetermined time.

  In order to solve the above-described problem, the non-volatile memory automatic rewrite interruption method of the present invention comprises a predetermined control flow for rewriting a non-volatile memory comprising a plurality of division control flows, By interrupting the execution of the control flow every time one is completed, the rewriting of the non-volatile memory is interrupted to make the non-volatile memory readable.

  Thus, the rewrite control flow is interrupted every time the division control flow is completed, so that the rewrite processing of the nonvolatile memory can be automatically interrupted.

  In the non-volatile memory automatic rewrite interruption method of the present invention, the resumption information necessary for resuming the rewrite of the non-volatile memory from the state where the rewrite of the non-volatile memory is interrupted is stored, and from the resumption information as a control flow It is preferable that the predetermined divided control flow to be determined is executed, and when the predetermined divided control flow is completed, the execution of the control flow is interrupted and the restart information is updated and stored.

  Thereby, after the rewriting process of the nonvolatile memory is automatically interrupted, it can be resumed from that state.

  In the non-volatile memory automatic rewrite interruption method of the present invention described above, in the control flow, first, time measurement by a timer is started, and when the divided control flow is completed, whether or not the time is exceeded is checked. Preferably executes the next divided control flow and interrupts the execution of the control flow if it is exceeded.

  As a result, each time the division control flow is completed, it is checked whether or not the timer has been exceeded, and it is determined whether or not the rewrite control is interrupted, so that the time until the rewrite processing is interrupted is made closer to the desired time. Can do.

  A nonvolatile memory according to the present invention is a rewritable nonvolatile memory, a memory array composed of a plurality of memory cells, a command decoding unit for decoding a command input from the outside of the nonvolatile memory, and a command decoding unit A rewrite control unit that rewrites the memory array according to a predetermined control flow according to the result of decoding, and the control flow is composed of a plurality of division control flows, and is controlled each time one of the plurality of division control flows is completed. By interrupting the execution of the flow, rewriting of the memory array is interrupted so that the memory array can be read.

  Thus, the rewrite control flow is interrupted every time the division control flow is completed, so that the rewrite processing of the nonvolatile memory can be automatically interrupted.

  In the above-described nonvolatile memory of the present invention, the rewrite control unit includes a resumption information holding unit that stores resumption information necessary for resuming rewriting of the memory array from a state where rewriting of the memory array is interrupted. The predetermined division control flow determined from the resumption information held by the resumption information holding unit is executed, and when the predetermined division control flow is completed, the execution of the control flow is interrupted and the resumption information is updated and stored in the resumption information holding unit It is preferable that it is comprised.

  Thereby, after the rewriting process of the nonvolatile memory is automatically interrupted, it can be resumed from that state.

  The non-volatile memory of the present invention includes a timer that measures time and detects that a predetermined time has been exceeded. In the control flow, the timer time measurement is first started, and each time the divided control flow is completed, the timer is started. It is preferable to check whether or not the time is exceeded and execute the next divided control flow if the time is not exceeded, and interrupt the execution of the control flow if the time is exceeded.

  As a result, each time the division control flow is completed, it is checked whether or not the timer has been exceeded, and it is determined whether or not the rewrite control is interrupted, so that the time until the rewrite processing is interrupted is made closer to the desired time. Can do.

  The microcomputer of the present invention is a microcomputer including a rewritable nonvolatile memory and a CPU for rewriting and controlling the nonvolatile memory according to a predetermined control flow, and the control flow is composed of a plurality of divided control flows. Then, every time one of the plurality of divided control flows is completed, the execution of the control flow is interrupted to interrupt the rewriting of the nonvolatile memory so that the nonvolatile memory can be read.

  Thus, the rewrite control flow is interrupted every time the division control flow is completed, so that the rewrite processing of the nonvolatile memory can be automatically interrupted.

  According to the microcomputer of the present invention, the resumption information holding unit for storing resumption information necessary for resuming the rewriting of the nonvolatile memory from the state where the rewriting of the non-volatile memory is suspended is provided, and the resumption information is held as a control flow. Configured to execute a predetermined division control flow determined from the resumption information held by the unit, interrupt execution of the control flow when the predetermined division control flow is completed, and update and store the resumption information in the resumption information holding unit It is preferable that

  Thereby, after the rewriting process of the nonvolatile memory is automatically interrupted, it can be resumed from that state.

  The microcomputer according to the present invention includes a timer that measures time and detects that a predetermined time has been exceeded. In the control flow, the timer time measurement is started first, and the timer is started each time the divided control flow is completed. It is preferable to check whether or not the time is exceeded, and execute the next divided control flow if the time is not exceeded, and interrupt the execution of the control flow if the time is exceeded.

  As a result, each time the division control flow is completed, it is checked whether or not the timer has been exceeded, and it is determined whether or not the rewrite control is interrupted, so that the time until the rewrite processing is interrupted is made closer to the desired time. Can do.

  According to the present invention, the rewriting process of the nonvolatile memory can be automatically interrupted within a predetermined time to enable the reading operation.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, constituent elements having the same functions as those of the other embodiments are denoted by the same reference numerals and description thereof is omitted.

Embodiment 1
FIG. 1 is a block diagram showing a configuration of a flash memory 100 (nonvolatile memory) according to Embodiment 1 of the present invention.

  The flash memory 100 includes a command decoding unit 110 (command decoding unit), a rewrite control unit 120, a memory array 130, and an output control unit 140. In addition, the rewrite control unit 120 includes a restart information holding unit 150.

  The command decode unit 110 receives an address input B100, a data input / output B110, a write enable signal S100, and a read enable signal S110 from outside the flash memory 100.

  When “1” is input to the read enable signal S110, the command decoding unit 110 recognizes that the read access is performed, outputs the value of the address input B100 to the rewrite address bus B120, and sets a value indicating the read access to the command signal B140. Output. When “1” is input to the write enable signal S100, the command decoding unit 110 recognizes the combination of the address input B100 and the data input / output B110 at that time as a command, decodes the command, and rewrites the decoded result to the rewritten address. The rewrite address on the bus B120, the write data on the write data bus B130, and the command signal B140 are output to the rewrite control unit 120.

  The rewrite control unit 120 sequentially outputs an array control signal B150 from the rewrite address bus B120, the write data bus B130, and the command signal B140 according to a predetermined control flow (described later) corresponding to each command, and reads and writes the memory array 130. In addition to controlling the erasure, the command execution state is output to the state signal B160.

  Here, in order to simplify the description, the status signal B160 is 4 bits and indicates “1H” (“H” indicates hexadecimal notation) when the command ends normally, and when the command ends abnormally. “2H”, “4H” when the command is being executed, “8H” when the command is terminated, and “0H” when none of the above is output. To do.

  Further, the rewrite control unit 120 performs writing and reading to the restart information holding unit 150 according to a predetermined control flow.

  The resumption information holding unit 150 stores and holds data (resumption information) indicating the division control flow executed when the command is resumed. In the initial state, it is assumed that the restart information holding unit 150 holds “0H”.

  The memory array 130 includes a plurality of memory cells, and reads, writes, and erases the corresponding memory cells according to the array control signal B150, and the array control signal B150 instructs to read data stored in the memory array 130. In this case, the data of the corresponding memory cell is read and output to the data bus B170.

  When “1” is input to the read enable signal S110 input from the outside of the flash memory 100, the output control unit 140 reads the read data when the status signal B160 output from the rewrite control unit 120 is “0H”. The value of the bus B170 is output to the data input / output B110. When the status signal B160 is other than “0H”, the value of the status signal B160 is output to the data input / output B110.

―Operation―
First, an operation in which an external device (not shown) reads data stored in the memory array 130 from the flash memory 100 configured as described above will be described.

  In order to read the data stored in the flash memory 100, the external device outputs a desired address, for example, address “100H” to the address input B100, and sets the read enable signal S110 to the value “1”.

  Since the read enable signal S110 is “1”, the command decoding unit 110 recognizes the read access and outputs the value of the address input B100 to the rewrite address bus B120, and the command signal B140 receives a value indicating the read access. Output.

  Since the value indicating read access is input to the command signal B140, the rewrite control unit 120 sequentially supplies signals necessary for reading data from the memory array 130 to the array control signal B150 for the address indicated by the rewrite address bus B120. Since the command is not executed, “0H” is output to the status signal B160.

  The memory array 130 reads the data of the memory cell corresponding to the specified address and outputs it to the data bus B170 in accordance with the array control signal B150.

  Since the status signal B160 is “0H”, the output control unit 140 outputs the value of the read data bus B170 to the data input / output B110.

  In this way, the external device can read the data in the flash memory 100 stored at a desired address from the data input / output B110.

  Next, an operation in which an external device issues a desired command, here an erase command, to the flash memory 100 will be described.

  The external device sets the write enable signal S100 to the value “1” and sequentially inputs combinations indicating the erase command to the address input B100 and the data input / output B110.

  The command decoding unit 110 recognizes and decodes the combination of the address input B100 and the data input / output B110 as a command because the write enable signal S100 is “1”, and the decoding result of the command is an erase command. The corresponding address is output to the rewrite address bus B120, and the value indicating the erase command is output to the command signal B140.

  The rewrite control unit 120 receives the value of the command signal B140, sequentially outputs the array control signal B150 in accordance with a predetermined control flow for erasing the memory cell at the corresponding address in the memory array 130, and sends a command to the status signal B160. “4H” indicating that the program is being executed is output.

Memory array 130 in accordance with an array control signal B150, erasing and memory cell corresponding to the skilled address, perform verification of the corresponding memory cell to confirm whether or not it is erased.

  At this time, when the external device performs read access to the flash memory 100 with the read enable signal S110 set to the value “1”, the output control unit 140 transfers the data input / output B110 to the data input / output B110 because the status signal B160 is “4H”. Outputs “4H”.

  In this way, the external device can read “4H” indicating that the command is being executed from the data input / output B 110 by performing read access after issuing the command.

  Similarly, the command normal end, command abnormal end, and command interrupt states can also be read from the data input / output B110.

  Next, a control flow executed by the rewrite control unit 120 when an external device issues an erase command will be described in detail with reference to FIG.

  FIG. 2 is a flowchart showing a control flow when the rewrite control unit 120 executes an erase command.

  The control flow of the erasure command can be classified into two types, verify that verifies whether or not the data stored in the memory array 130 has been erased and erasure that applies an erase pulse to the memory array 130 (Erase). Here, it is assumed that the application of the erase pulse is usually performed in units of 3 ms, and further here, the pulse is divided into 1 ms units and divided into three for the first erase (Erase 1), the second erase (Erase 2), and the third erase (Erase 3). It is assumed that three division control flows are executed. For the above four divided control flows, the verify is “0H”, the first erase (Erase1) is “1H”, the second erase (Erase2) is “2H”, and the third erase (Erase3) is “3H”. , And data (resumption information) indicating the division control flow to be executed next is stored in the resumption information holding unit 150.

  In an initial state, when a signal indicating an erasure command is input from the command signal B 140 to the rewrite control unit 120, the rewrite control unit 120 receives data (resume information) indicating a division control flow to be executed next from the restart information holding unit 150. Read (A).

  Since the restart information holding unit 150 holds “0H” in the initial state, the process branches to the verification execution flow (B0).

  Next, the rewrite control unit 120 sequentially outputs a control signal necessary for setting the voltage for verification to the memory array 130 as the array control signal B150 (C0).

  Next, the rewrite control unit 120 sequentially outputs a control signal necessary for reading to the array control signal B150 in order to confirm (verify) whether or not the corresponding address of the memory array 130 is in the erased state, and the memory array 130 outputs it. Data is sequentially read from the data bus B170 (D0).

  Next, the rewrite control unit 120 determines the verification result (E0). Hereinafter, a case where the verification result is fail will be described.

  In response to the fail result, the rewrite control unit 120 stores “1H” indicating that the next division control flow to be executed is the first erase (Erase1) in the restart information holding unit 150 (F4).

  Next, the rewrite control unit 120 sequentially outputs a control signal necessary for setting a voltage for reading (G) to the array control signal B150 (G), and the control flow is ended.

  At this time, the erase command is interrupted by executing only verification. On the other hand, since the memory array 130 has a voltage setting for reading, the external device can read data from the flash memory 100 by setting the value of the read enable signal S110 to “1”.

  Next, the operation when the erase command is input again while the erase command is interrupted will be described.

  When the erase command is input again, the rewrite control unit 120 reads the data stored in the restart information holding unit 150 (A). As described above, since the restart information holding unit 150 stores the data “1H”, the process branches to the first erase (Erase1) flow (B0) (B1).

  Next, the rewrite control unit 120 sequentially outputs a control signal necessary for setting an erase voltage to the array control signal B150 (C1).

  Next, the rewrite control unit 120 sequentially outputs a control signal necessary for applying the first divided erase pulse to the memory array 130 as the array control signal B150 (D1).

  Next, the rewrite control unit 120 stores “2H” indicating that the next division control flow to be executed is the second erasure (Erase2) in the restart information holding unit 150 (F1).

  Next, the rewrite control unit 120 sequentially outputs a control signal necessary for setting a voltage for reading to the memory array 130 to the array control signal B150 (G), and ends the control flow.

  At this time, the erase command is interrupted by executing only the first erase (Erase1) flow. On the other hand, since the memory array 130 is set to read voltage, an external device (not shown) reads data from the flash memory 100 by setting the value of the read enable signal S110 to “1”. Can do.

  Similarly, when the divided erasing pulse is executed up to the third time, the rewrite control unit 120 stores “0H” indicating that the divided control flow to be executed next is verification in the restart information holding unit 150 (F0). When the command resumes, it is executed again from verify.

  As described above, when the verify and erase pulse application are repeated and the verification passes, the rewrite control unit 120 stores “0H”, which is the initial value, in the restart information holding unit 150 (F0).

  In this way, the control flow of the erase command is divided, the execution of the erase command is interrupted each time the divided individual flows are completed, and the data can be read from the flash memory 100. It becomes easy to embed 100 erasure processes in task management.

<< Embodiment 2 >>
FIG. 3 is a block diagram showing a configuration of the flash memory 200 according to Embodiment 2 of the present invention. As shown in the figure, the flash memory 200 includes a timer 260 in addition to the configuration of the flash memory 100 of the first embodiment.

  The timer 260 starts time measurement when the timer activation signal S220 becomes “1”, and completes time measurement and clears the measurement value when it becomes “0”. When the measured value overflows, “1” is output to the overflow signal S230. Here, in order to simplify the description, the period of the timer 260 is 1 ms.

  In addition to the function of the rewrite control unit 120 of the first embodiment, the rewrite control unit 220 can control the start of the timer 260 by the timer start signal S220 and can detect the overflow of the timer 260 by the overflow signal S230.

―Operation―
An operation in which an external device (not shown) reads data stored in the memory array 130 from the flash memory 200 configured as described above, and an external device performs a desired command, here an erase command, to the flash memory 200. Since the outline of the operation for issuing is the same as in the first embodiment, description thereof is omitted.

  Next, a control flow executed by the rewrite control unit 120 when an external device issues an erase command will be described in detail with reference to FIG.

  FIG. 4 is a flowchart showing a control flow when the rewrite control unit 220 executes an erase command. As shown in the figure, from the flowchart according to the first embodiment, the rewrite control unit 220 outputs “1” to the timer activation signal S220 and starts the time measurement of the timer 260 (TS), and the rewrite control A process (TC) for determining the overflow of the timer 260 by the overflow signal S230 by the unit 220 is added.

  The control flow of the erase command can be classified into two types: verify for confirming whether or not the data stored in the memory array 130 has been erased, and erase for applying an erase pulse to the memory array 130. Here, it is assumed that the verify process takes 0.5 ms. In addition, it is assumed that the application of the erase pulse is normally performed in units of 3 ms, and here, the pulse is divided into 3 units of 1 ms, and the first erase (Erase 1), the second erase (Erase 2), and the third erase (Erase 3) 3 Assume that one split control flow is executed. For the above four divided control flows, the verify is “0H”, the first erase (Erase1) is “1H”, the second erase (Erase2) is “2H”, and the third erase (Erase3) is “3H”. , And data (resumption information) indicating the division control flow to be executed next is stored in the resumption information holding unit 150.

  In the initial state, when a signal indicating an erase command is input from the command signal B140 to the rewrite control unit 120, the rewrite control unit 220 outputs “1” to the timer activation signal S220 and starts measuring the time of the timer 260. (TS).

  Next, the rewrite control unit 220 reads data (resumption information) indicating the division control flow to be executed next from the resumption information holding unit 150 (A).

  Since the restart information holding unit 150 holds “0H” in the initial state, the process branches to the verification execution flow (B0).

  Next, the rewrite control unit 220 sequentially outputs a control signal necessary for setting a voltage for verification to the memory array 130 as an array control signal B150 (C0).

  Next, the rewrite control unit 120 sequentially outputs a control signal necessary for reading to the array control signal B150 in order to confirm (verify) whether or not the corresponding address of the memory array 130 is in the erased state, and the memory array 130 outputs it. Data is read sequentially from the data bus B150 (D0).

  Next, the rewrite control unit 220 determines the verification result (E0). Hereinafter, a case where the verification result is fail will be described.

  In response to the fail result, the rewrite control unit 220 stores “1H” indicating that the next division control flow to be executed is the first erase (Erase1) in the restart information holding unit 150 (F4).

  Next, the rewrite control unit 220 sequentially outputs a control signal necessary for setting a voltage for reading to the array control signal B150 (G).

  Next, the rewrite control unit 220 determines the overflow of the timer 260 based on the overflow signal S230 (TC). At this time, since the processing time related to the verify operation is 0.5 ms, the overflow signal S230 becomes “0”, and the rewrite control unit 220 continuously executes the next division control flow. Read data (A). As described above, since the restart information holding unit 150 stores the data “1H”, the process branches to the first erase (Erase1) flow (B0) (B1).

  Next, the rewrite control unit 220 sequentially outputs control signals necessary for setting the voltage for erasure to the array control signal B150 (C1).

  Next, the rewrite control unit 220 sequentially outputs a control signal necessary for applying the first divided erase pulse to the memory array 130 as the array control signal B150 (D1).

  Next, the rewrite control unit 220 stores “2H” indicating that the next division control flow to be executed is the second erasure (Erase2) in the restart information holding unit 150 (F1).

  Next, the rewrite control unit 220 sequentially outputs a control signal necessary for setting a read voltage to the memory array 130 as an array control signal B150 (G).

  Next, the rewrite control unit 220 determines the overflow of the timer 260 based on the overflow signal S230 (TC). At this time, in addition to the processing time of 0.5 ms related to the verify operation, the first divided erasure is performed and a total time of 1.5 ms has elapsed, so the overflow signal S230 becomes “1” and the control flow ends. .

  At this time, the erase command is interrupted by executing only the verify flow and the first erase (Erase1) flow.

  In this way, the control flow of the erasure command is divided, and each time the divided individual flows are completed, it is checked whether the process has been executed for a predetermined time, and the process has been executed for a predetermined time. In this case, by interrupting the execution of the erase command, the time from the command issuance to the command interruption can be made uniform, so that the rewriting process of the flash memory 100 can be embedded in the task management on the application. It becomes.

<< Embodiment 3 >>
FIG. 5 is a block diagram showing the configuration of the microcomputer 300 according to Embodiment 3 of the present invention. The microcomputer 300 includes a CPU 310 (Central Processing Unit), a built-in flash memory 320 (nonvolatile memory), a built-in ROM 330 (Read Only Memory), and a built-in RAM (Random Access memory) (resumption information holding unit).

  The CPU 310 performs various controls by reading out and decoding the instruction code from the built-in flash memory 320 and the built-in ROM 330 and executing the instruction. Reading of the instruction code is performed by outputting the address of the area where the instruction code to be read is stored to the address bus B300 and setting the value of the read enable signal S300 to “1”. The read instruction code is read into the CPU 310 via the data bus B310.

  The built-in flash memory 320 stores an instruction code and other data in a memory array (not shown). When the read enable signal S300 is “1”, it is designated by an address output to the address bus B300. The instruction code and other data stored in the memory area are output to the data bus B310.

  The built-in flash memory 320 includes a control register 350 used for control for erasing and writing data stored in the memory array. The CPU 310 can erase and write to the memory array of the built-in flash memory 320 by sequentially rewriting the value of the control register 350 in accordance with a predetermined control flow to be described later. When the value of the write enable signal S300 is “1”, the control register 350 stores and holds the value output to the data bus B310 in the register specified by the address output to the address bus B300. ing.

  The built-in ROM 330 stores an instruction code and other data constituting a program for rewriting the built-in flash memory 320. When the read enable signal S300 has a value “1”, the built-in ROM 330 is output to the address bus B300. The instruction code and other data stored in the memory area designated by the address are output to the data bus B310.

  The internal RAM 340 stores an instruction code and other data. When the read enable signal S310 is “1”, the instruction code stored in the memory area specified by the address output to the address bus B300 is stored. And other data are output to the data bus B310. Further, when the write enable signal S300 is “1”, the built-in RAM 340 stores and holds the value output to the data bus B310 in the memory area specified by the address output to the address bus B300. It has become.

  Further, it is assumed that the division control flow to be executed next is stored and held at a predetermined address of the built-in RAM, and “0” is stored in the initial state.

―Operation―
First, an operation in which the CPU 310 in the microcomputer 300 configured as described above executes a program for rewriting data in the internal flash memory 320 stored in the internal ROM 330 will be described.

  In order to read out the instruction code from the built-in ROM 330, the CPU 310 outputs an address corresponding to the built-in ROM 330, for example, the address “300H” to the address bus B300, and further sets the read enable signal S310 to the value “1”. Then, the instruction code is read from the data bus B310, decoded, and the instruction is executed.

  Next, the CPU 310 outputs an address corresponding to the control register 350, for example, the address “200H”, to the address bus B300 in order to sequentially rewrite the value of the control register 350 in accordance with a predetermined control flow to be described later, and the write enable signal S300. Is set to the value “1”, and predetermined data is output to the data bus B310.

  In this way, the CPU 310 can execute the program for rewriting the data in the built-in flash memory 320 stored in the built-in ROM 330 to rewrite the data in the flash memory 320.

  Next, an operation in which the CPU 310 executes a program for rewriting data in the internal flash memory 320 stored in the internal ROM 330 will be described in detail with reference to FIG.

  FIG. 2 is a flowchart showing a control flow when the CPU 310 executes erasure of the flash memory 320, and is exactly the same as the control flow when the rewrite control unit 120 executes the erase command in the first embodiment. A program for realizing the control flow is stored in the built-in ROM 330, and is greatly different in that the CPU 310 executes the program. In the first embodiment, the rewrite control unit 120 outputs the array control signal B150 to erase the memory array 130. However, in this embodiment, the CPU 310 rewrites the control register 350 so that the built-in flash memory 320 is rewritten. Erase the data.

  The control flow of erasure can be classified into two types: verify for confirming whether or not the data stored in the built-in flash memory 320 has been erased, and erase for applying an erase pulse to the built-in flash memory 320. Here, it is assumed that the application of the erase pulse is usually performed in units of 3 ms, and further here, the pulse is divided into 1 ms units and divided into three for the first erase (Erase 1), the second erase (Erase 2), and the third erase (Erase 3). It is assumed that three division control flows are executed. For the above four divided control flows, the verify is “0H”, the first erase (Erase1) is “1H”, the second erase (Erase2) is “2H”, and the third erase (Erase3) is “3H”. , And data (resume information) indicating the division control flow to be executed next is stored at a predetermined address in the built-in RAM 340.

  When the CPU 310 reads and executes the erase program stored in the built-in ROM 330, the CPU 310 first reads data (resumption information) indicating the division control flow to be executed next from the built-in RAM 340 (A).

  Since the internal RAM 340 holds “0H” in the initial state, the CPU 310 branches to the verification execution flow (B0).

  Next, the CPU 310 sequentially sets the control register 350 necessary for setting the voltage for verification in the built-in flash memory 320 (C0).

  Next, the CPU 310 outputs the corresponding address to the address bus B300 and sets the value of the read enable signal S310 to “1” in order to confirm (verify) whether or not the corresponding memory cell of the built-in flash memory 320 is in the erased state. Then, the data of the corresponding memory cell of the built-in flash memory 320 is sequentially read from the data bus B310 (D0).

  Next, the CPU 310 determines the verification result (E0). Hereinafter, a case where the verification result is fail will be described.

  In response to the fail result, the CPU 310 stores “1H” indicating that the next division control flow to be executed is the first erase (Erase1) in the internal RAM 340 (F4).

  Next, the CPU 310 sequentially sets control registers necessary for setting a voltage for reading in the built-in flash memory 320 (G), and ends the control flow.

  At this time, the erasing process is interrupted by executing only the verification. On the other hand, since the built-in flash memory 320 is set to a voltage for reading, the CPU 310 outputs the address of the built-in flash memory 320 to the address bus B300 and sets the value of the read enable signal S110 to “1”. Data can be read from the built-in flash memory 320.

  Next, an operation for executing the erasing process again in a state where the erasing process is interrupted will be described.

  When the CPU 310 again reads and executes the erase program stored in the built-in ROM 330, the CPU 310 reads the resume information data stored in the built-in RAM 340 (A). As described above, since the built-in RAM 340 stores “1H” as the restart information data, it branches to the first erase (Erase1) flow (B0) (B1).

  Next, the CPU 310 sequentially sets the control register 350 necessary for setting the voltage for erasure (C1).

  Next, the CPU 310 sequentially sets the control register 350 necessary for applying the first divided erase pulse to the built-in flash memory 320 (D1).

  Next, the CPU 310 stores “2H” in the built-in RAM 340 indicating that the division control flow to be executed next is the second erase (Erase2) (F1).

  Next, the CPU 310 sequentially sets the control register 350 necessary for setting the voltage for reading in the built-in flash memory 320 (G), and ends the control flow.

  At this time, only the first erase (Erase1) flow is executed and interrupted. On the other hand, since the built-in flash memory 320 has a voltage setting for reading, the CPU 310 can read data from the built-in flash memory 320 by setting the value of the read enable signal S310 to “1”.

  Similarly, when the divided erase pulse is executed up to the third time, the CPU 310 stores “0H” in the built-in RAM 340 indicating that the divided control flow to be executed next is verification (F0). Is executed from.

  As described above, when verify and erase pulse application are repeated and the verify passes, the CPU 310 stores the initial value “0H” in the internal RAM 340 (F0).

  In this way, the control flow of the rewrite process is divided, the execution of the erasure process is interrupted each time the divided individual flows are completed, and data can be read from the built-in flash memory 320. It becomes easy to embed rewrite processing of the flash memory 320 in task management.

<< Embodiment 4 >>
FIG. 6 is a block diagram showing a configuration of microcomputer 400 according to the fourth embodiment of the present invention. As shown in the figure, the microcomputer 400 includes a timer 460 in addition to the configuration of the microcomputer 300 of the third embodiment.

  The timer 460 starts time measurement when the timer activation signal S420 becomes “1”, completes time measurement when the timer activation signal S420 becomes “0”, and clears the measurement value. When the measured value overflows, “1” is output to the overflow signal S430. Here, in order to simplify the description, the period of the timer 460 is 1 ms.

  In addition to the function of CPU 310 of the third embodiment, CPU 410 can control the start of timer 460 by timer start signal S420 and can detect the overflow of timer 460 by overflow signal S430.

―Operation―
The outline of the operation in which the CPU 410 in the microcomputer 400 configured as described above executes a program for rewriting data in the built-in flash memory 320 stored in the built-in ROM 330 is the same as that in the third embodiment, and thus will be described. Is omitted.

  Next, an operation in which the CPU 410 executes a program for rewriting data in the internal flash memory 320 stored in the internal ROM 330 will be described in detail with reference to FIG.

  FIG. 4 is a flowchart showing a control flow when the CPU 410 executes erasure of the flash memory 320. As shown in the figure, from the flowchart according to the third embodiment, the CPU 410 outputs “1” to the timer activation signal S420 to start the time measurement of the timer 460, and the CPU 410 detects the overflow signal S430. Thus, a process (TC) for determining the overflow of the timer 460 is added.

  The control flow of erasure can be classified into two types: verify for confirming whether or not the data stored in the built-in flash memory 320 has been erased, and erase for applying an erase pulse to the built-in flash memory 320. Here, it is assumed that the verify process takes 0.5 ms. In addition, it is assumed that the application of the erase pulse is normally performed in units of 3 ms, and here, the pulse is divided into 3 units of 1 ms, and the first erase (Erase 1), the second erase (Erase 2), and the third erase (Erase 3) 3 Assume that one split control flow is executed. For the above four divided control flows, the verify is “0H”, the first erase (Erase1) is “1H”, the second erase (Erase2) is “2H”, and the third erase (Erase3) is “3H”. , And data (restart information) indicating the division control flow to be executed next is stored in the built-in RAM 340.

  When the CPU 410 reads and executes the erase program stored in the built-in ROM 330, the CPU 410 first outputs a value “1” to the timer activation signal S420 and starts measuring the time of the timer 460 (TS).

  Next, the CPU 410 reads data (resumption information) indicating the next division control flow to be executed from the built-in RAM 340 (A).

  Since the built-in RAM holds “0H” in the initial state, the CPU 310 branches to the verify execution flow (B0).

  Next, the CPU 410 sequentially sets the control register 350 necessary for setting the voltage for verification in the built-in flash memory 320 (C0).

  Next, in order to confirm (verify) whether or not the corresponding memory cell of the built-in flash memory 320 is in the erased state, the corresponding address is output to the address bus B300 and the value of the read enable signal S310 is set to “1”. The data of the corresponding address 320 is sequentially read from the data bus B310 (D0).

  Next, the CPU 410 determines the verification result (E0). Hereinafter, a case where the verification result is fail will be described.

  In response to the fail result, the CPU 410 stores “1H” indicating that the next division control flow to be executed is the first erase (Erase1) in the internal RAM 340 (F4).

  Next, the CPU 410 sequentially sets the control registers necessary for setting the read voltage for the built-in flash memory (G).

  Next, the CPU 410 determines the overflow of the timer 460 based on the overflow signal S430 (TC). At this time, since the processing time related to the verify operation is 0.5 ms, the overflow signal S430 becomes “0”, and the CPU 410 continuously executes the next division control flow, so the resumption information stored in the internal RAM 340 is read (A). . As described above, since the internal RAM 340 stores the data “1H”, the process branches to the first erase (Erase1) flow (B0) (B1).

  Next, the CPU 410 sequentially sets the control register 350 necessary for setting the voltage for erasure (C1).

  Next, the CPU 410 sequentially sets the control register 350 necessary for applying the first divided erase pulse to the built-in flash memory 320 (D1).

  Next, the CPU 410 stores “2H” in the built-in RAM 340 indicating that the division control flow to be executed next is the second erase (Erase2) (F1).

  Next, the CPU 410 sequentially sets the control register 350 necessary for setting the read voltage for the built-in flash memory 320 (G).

  Next, the CPU 410 determines the overflow of the timer 460 based on the overflow signal S430 (TC). At this time, in addition to the time of 0.5 ms related to the verify operation, the first divided erase is performed and the total time of 1.5 ms has elapsed, so the overflow signal S430 becomes “1” and the control flow is ended. At this time, the erase process is interrupted by executing only the verify flow and the first erase (Erase1) flow.

  In this way, the control flow of the rewriting process is divided, and each time the divided individual flows are completed, it is confirmed whether the process has been executed over a predetermined time, and the process is performed over the predetermined time. In such a case, by interrupting the execution of the erasure process, the time from the start of the rewrite process to the process interruption can be made uniform. It becomes easier.

<< Embodiment 5 >>
In the fifth embodiment of the present invention, either the flash memory of the first embodiment or the second embodiment is mounted on the air conditioner system.

  FIG. 7 is a block diagram showing a configuration of an air conditioner system according to Embodiment 5 of the present invention.

  The air conditioner system includes a remote controller 510 and an indoor unit 520. The indoor unit 520 includes a microcomputer 530, a light receiving element 580, an operational amplifier 590, an LCD (liquid crystal display) panel, a speaker, and the like. The microcomputer 530 includes a flash memory 540 and a CPU 550. The flash memory 540 is any of the flash memories described in the first or second embodiment.

  The flash memory 540 and the CPU 550 are connected via an address bus B500, a data bus B510, a write enable signal S500, and a read enable signal S510.

  The remote controller 510 includes a microcomputer 560, an LED 570, an LCD panel, and a keypad (not shown). The microcomputer 560 receives a signal for an operation performed by the user using the keypad, and the indoor unit 520 is received by the LED 570. Transmit to.

  The CPU 550 reads out, decodes and executes an instruction code stored in the flash memory 540, and performs various controls of the air conditioner system while switching tasks in units of several ms.

  In addition, the CPU 550 receives a signal corresponding to the operation of the remote controller 510 through the light receiving element 580 and the operational amplifier 590 and issues a data write command to a predetermined area of the flash memory 540. Specifically, the write data includes a power on / off state, a temperature setting, a cooling / heating state, a fan (FAN) rotation speed, an upper and lower louver angle, and the like.

  Further, the CPU 550 issues an erase command to the flash memory 540 when a predetermined area of the flash memory 540 is filled with the write data.

  The flash memory 540 stores the instruction code and the various types of data described above. When the read enable signal S510 has a value “1”, the flash memory 540 stores the instruction code and the data in the memory area specified by the address output to the address bus B500. Output instruction code and other data to the data bus B510. When the write enable signal S520 is “1”, the combination of the value of the address bus B500 and the value of the data bus B510 is recognized as a command, the command is decoded, and write and erase operations are executed. In response to a write command issued by the CPU 550, a write operation is performed and new data is stored.

In the execution of the erase command of the flash memory, as in the first and second embodiments, the CPU 550 erases the erase operation by interrupting the erase operation every time the divided control flow is executed. Since it is possible to read out the instruction code stored in the flash memory 540 within a predetermined time even after issuing the command, various controls of the air conditioner system can be performed while switching tasks in units of several ms.
<< Other Embodiments >>
Although the present invention has been described based on the above embodiment, the present invention is not limited to the above embodiment, and various modifications can be made without departing from the gist of the present invention. Of course.

  (1) Each of the above devices is specifically a computer system including a microprocessor, ROM, RAM, a hard disk unit, a display unit, a keyboard, a mouse, and the like. A computer program is stored in the RAM or the hard disk unit. Each device achieves its function by the microprocessor operating according to the computer program. Here, the computer program is configured by combining a plurality of instruction codes indicating instructions for the computer in order to achieve a predetermined function.

  (2) A part or all of the components constituting each of the above devices may be configured by one system LSI (Large Scale Integration). The system LSI is an ultra-multifunctional LSI manufactured by integrating a plurality of components on a single chip, and specifically, a computer system including a microprocessor, ROM, RAM, and the like. . A computer program is stored in the RAM. The system LSI achieves its functions by the microprocessor operating according to the computer program. These may be individually made into one chip, or may be made into one chip so as to include a part or all of them.

  Although the system LSI is used here, it may be referred to as an IC, a system LSI, a super LSI, or an ultra LSI depending on the degree of integration.

  Further, the method of circuit integration is not limited to LSI's, and implementation using dedicated circuitry or general purpose processors is also possible. An FPGA (Field Programmable Gate Array) that can be programmed after manufacturing the LSI, or a reconfigurable processor that can reconfigure the connection and setting of circuit cells inside the LSI may be used.

  Furthermore, if integrated circuit technology comes out to replace LSI's as a result of the advancement of semiconductor technology or a derivative other technology, it is naturally also possible to carry out function block integration using this technology. Biotechnology can be applied.

  (3) A part or all of the components constituting each of the above devices may be configured as an IC card that can be attached to and detached from each device or a single module. The IC card or the module is a computer system including a microprocessor, a ROM, a RAM, and the like. The IC card or the module may include the super multifunctional LSI. The IC card or the module achieves its function by the microprocessor operating according to the computer program. This IC card or this module may have tamper resistance.

  (4) The present invention may be the method described above. In addition, the present invention may be a computer program that realizes these methods by a computer, or may be a digital signal composed of the computer program.

  The present invention also provides a computer-readable recording medium such as a flexible disk, hard disk, CD-ROM, MO, DVD, DVD-ROM, DVD-RAM, BD (Blu-Ray Disk). ), Recorded in a semiconductor memory or the like. Further, the present invention may be the computer program or the digital signal recorded on these recording media.

  In the present invention, the computer program or the digital signal may be transmitted via an electric communication line, a wireless or wired communication line, a network represented by the Internet, a data broadcast, or the like.

  In addition, the program or the digital signal is recorded on the recording medium and transferred, or the program or the digital signal is transferred via the network or the like, and is executed by another independent computer system. It is good.

  (5) The above embodiment and the above modifications may be combined.

  The nonvolatile memory automatic rewrite interruption method, nonvolatile memory, and microcomputer according to the present invention have the effect that the nonvolatile memory rewrite process can be automatically interrupted within a predetermined time, for example, temperature setting in an air conditioner system This is useful for systems that need to record data that changes one after another, such as data.

1 is a block diagram showing a configuration of a flash memory 100 according to Embodiment 1 of the present invention. It is a flowchart which shows the control flow in case the rewriting control part 120 which concerns on Embodiment 1 of this invention performs an erasure | elimination command. It is a block diagram which shows the structure of the flash memory 200 concerning Embodiment 2 of this invention. It is a flowchart which shows the control flow in case the rewriting control part 220 which concerns on Embodiment 2 of this invention performs an erasure | elimination command. It is a block diagram which shows the structure of the microcomputer 300 which concerns on Embodiment 3 of this invention. It is a block diagram which shows the structure of the microcomputer 400 which concerns on Embodiment 4 of this invention. It is a block diagram which shows the structure of the air conditioning system which concerns on Embodiment 5 of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 100 Flash memory 110 Command decoding part 120 Rewrite control part 130 Memory array 140 Output control part 150 Restart information holding part 200 Flash memory 220 Rewrite control part 260 Timer 300 Microcomputer 310 CPU
320 Flash memory 330 ROM
340 RAM
350 Control register 400 Microcomputer 410 CPU
460 Timer 510 Remote control 520 Indoor unit 530 Microcomputer 540 Flash memory 550 CPU
B100 Address input B110 Data input / output B120 Rewrite address bus B130 Write data bus B140 Command signal B150 Array control signal B160 Status signal B170 Read data bus B300 Address bus B310 Data bus B500 Address bus B510 Data bus S100 Write enable S110 Read enable S220 Timer start Signal S230 Overflow signal S300 Write enable S310 Read enable S420 Timer start signal S430 Overflow signal S500 Write enable S510 Read enable

Claims (9)

  A predetermined control flow for rewriting the nonvolatile memory is composed of a plurality of divided control flows, and the execution of the control flow is interrupted each time one of the plurality of divided control flows is completed. An automatic rewrite interruption method for a nonvolatile memory, wherein the rewrite is interrupted and the nonvolatile memory is made readable.   Stores resumption information necessary to resume rewriting of the nonvolatile memory from a state where rewriting of the nonvolatile memory is interrupted, and executes a predetermined division control flow determined from the resumption information as the control flow. 2. The non-volatile memory automatic rewrite interruption method according to claim 1, wherein when the predetermined divided control flow is completed, the execution of the control flow is interrupted and the restart information is updated and stored.   In the control flow, first, time measurement by a timer is started. Every time the divided control flow is completed, whether or not the time is exceeded is checked. If it does not exceed, the next divided control flow is executed. 3. The non-volatile memory automatic rewrite interruption method according to claim 1, wherein execution of the control flow is interrupted when there is any. A rewritable nonvolatile memory,
A memory array composed of a plurality of memory cells;
A command decoding unit for decoding commands input from outside the nonvolatile memory;
A rewrite control unit that rewrites the memory array in accordance with a predetermined control flow according to a decoding result of the command decoding unit;
With
The control flow is composed of a plurality of divided control flows,
Each time the control flow is completed, the execution of the control flow is interrupted to interrupt the rewrite of the memory array, and the memory array can be read. Nonvolatile memory characterized by. The rewrite control unit includes a resumption information holding unit that stores resumption information necessary to resume rewriting of the memory array from a state where rewriting of the memory array is interrupted,
As the control flow, a predetermined division control flow determined from the resumption information held by the resumption information holding unit is executed, and when the predetermined division control flow is completed, the execution of the control flow is interrupted and the resumption information The non-volatile memory according to claim 4, wherein the non-volatile memory is configured to be updated and stored in the restart information holding unit. It has a timer that measures the time and detects that the specified time has been exceeded.
In the control flow, first, time measurement of the timer is started, and whenever the division control flow is completed, it is checked whether or not the timer has been exceeded. If not, the next division control flow is executed. 6. The non-volatile memory according to claim 4, wherein execution of the control flow is interrupted if the control flow is exceeded. Rewritable nonvolatile memory,
A microcomputer including a CPU that rewrites and controls the nonvolatile memory according to a predetermined control flow,
The control flow is composed of a plurality of divided control flows,
Each time one of the plurality of divided control flows is completed, the execution of the control flow is interrupted to interrupt the rewriting of the nonvolatile memory so that the nonvolatile memory can be read. A microcomputer characterized by that. A resumption information holding unit that stores resumption information necessary to resume rewriting of the nonvolatile memory from a state where rewriting of the nonvolatile memory is interrupted,
As the control flow, a predetermined division control flow determined from the resumption information held by the resumption information holding unit is executed. When the predetermined division control flow is completed, the execution of the control flow is interrupted, and the resumption information is 8. The microcomputer according to claim 7, wherein the microcomputer is configured to be updated and stored in the restart information holding unit. It has a timer that measures the time and detects that the specified time has been exceeded.
In the control flow, first, time measurement of the timer is started, and whenever the division control flow is completed, it is checked whether or not the timer has been exceeded. If not, the next division control flow is executed. 9. The microcomputer according to claim 7, wherein the microcomputer is configured to suspend execution of the control flow when it exceeds.

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