JP2010074147A - Printed circuit board - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent reduction of a wiring flexibility for the board with use of lands for preventing solder bridge. <P>SOLUTION: A printed circuit board has first solder lands for soldering of an electronic component, second solder lands for accumulation of solder located close to the first lands, and a signal line pattern provided between the first and second lands. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a printed circuit board on which a flat package IC is mounted by solder flow mounting.

  In recent years, the density of component mounting of printed circuit boards is required to be finer, and it is necessary to mount ICs (Integrated Circuits) such as SOP and QFP at narrow intervals. On the other hand, in order to reduce the cost, the ICs of these packages are mounted by flow soldering instead of reflow soldering. In the case of flow soldering, in order to maintain stable soldering without a solder bridge or the like during mounting, it is necessary to closely manage the manufacturing process.

  Therefore, conventionally, a waste land is formed on the downstream side of the IC solder flow direction (hereinafter, simply referred to as a solder flow downstream side) or the most downstream IC land is enlarged to form a solder pool land. Has been done. FIG. 14 shows an example of a SOP solder bridge prevention land. Reference numerals 104 and 102 denote lands (copper foil pattern exposed portions) of the SOP-shaped IC 103. Reference numeral 102 denotes a land of pins on the most downstream side of the solder flow of the IC 103. If the substrate traveling direction in the soldering process is indicated by the arrow in FIG. 14, the solder flow traveling direction is opposite to the illustrated arrow, and the solder flow upstream side and the solder flow downstream side are as shown in FIG. It becomes. The thin solid line drawn so as to overlap the lands 102 and 104 drawn with thick solid lines indicates the pins of the IC 103.

  A solder bridge prevention land 101 is disposed downstream of the land 102 in the solder flow. During the solder flow, the solder is drawn into the solder bridge prevention land 101. Therefore, the surface / interface tension between the lands 104 and 102 on the upstream side of the solder flow and the solder of each pin of the IC 103 is reduced, and solder bridges at the pins of the lands 104 and 102 and the IC 103 are prevented.

  FIG. 15 shows another example of the SOP solder bridge prevention land. The difference from FIG. 14 is that the solder bridge prevention land 111 is formed by enlarging the land of the pin 112 on the most downstream side of the solder flow of the IC 103.

  There are a plurality of prior arts as described above for preventing solder bridges.

  For example, Patent Document 1 discloses that a QFP (Quad Flat Package) land is disposed obliquely with respect to the solder flow direction and a discarded land is formed downstream in the solder flow direction. A substrate pattern for preventing solder bridging is described. Patent Document 2 describes a substrate pattern that prevents a solder bridge by forming a discarded land downstream of the chip component land in the solder flow direction. Patent Document 3 describes a substrate pattern that prevents solder bridging by forming a discarded land downstream of the SOP (Small Outline Package: two-way lead flat package) in the solder flow direction. Patent Document 4 describes a substrate pattern that improves the cutting of solder by slitting a QFP solder pool land and prevents solder bridges.

JP-A-63-213994 JP-A-2-119295 JP-A-4-208594 JP-A-5-315733

  However, when a land for preventing solder bridges such as the above-mentioned discarded land or solder pool land is used, there is a problem that the degree of freedom in designing the pattern on the printed circuit board is lowered. If the degree of freedom in pattern design is low, for example, the area of the pattern for heat dissipation is limited, so that the heat dissipation of the mounted IC may be reduced. As countermeasures, it is necessary to enlarge the printed circuit board to increase the heat radiation pattern, or to add a heat radiation plate separately from the heat radiation pattern. Further, in order to prevent unnecessary radiation noise such as a CPU (Central Processing Unit), the area of the GND (ground) pattern is increased, and when it is necessary to increase the number of connections as much as possible, the area of the GND pattern is secured and the number of connections is increased. Limits arise.

  For example, when mounting a motor driver IC having a heat dissipation pin, a land for preventing solder bridges such as a discarded land or a solder pool land is in the way, and a large area of heat dissipation copper connected to the heat dissipation pin It may be difficult to form a foil pattern. That is, since the land for preventing the solder bridge is large, there is no place for forming the copper foil pattern for heat dissipation. In addition, when the signal line is passed between the heat radiation pin and the place where the heat radiation copper foil pattern can be disposed, the heat radiation pin and the heat radiation copper foil pattern cannot be connected. As a method of solving the latter, there is a method of connecting both (heat dissipation pin and heat dissipation copper foil pattern) using a jumper wire, but the area of the heat dissipation copper foil pattern is limited by the land for the jumper wire. End up.

  Furthermore, recently, there is a tendency to mount an IC with a narrower pin interval (a narrower interval between lands on the substrate) with flow soldering. Land is needed.

  The present invention has been made in view of the above problems, and an object of the present invention is to increase the degree of freedom of wiring on a printed circuit board while preventing solder bridges when mounting an IC.

  In order to solve the above problems, the present invention comprises the following arrangement.

  (1) In a printed board on which an electronic component is soldered by being transported to a solder bath, a first solder land for soldering the electronic component, and a direction in which the printed board is transported with respect to the first solder land A print having a second solder land for storing solder provided on the downstream side, and a signal line pattern having a pattern exposed portion between the first solder land and the second solder land. substrate.

  (2) A first solder land for soldering an electronic component, a second solder land arranged in a row with the first solder land, and between the first solder land and the second solder land. And a signal line pattern provided with a pattern exposure portion.

  (3) In a printed circuit board on which an electronic component is mounted, a mounting portion to which terminals of the electronic component are soldered, a solder pattern portion provided close to the mounting portion, the mounting portion, and the solder pattern portion A printed circuit board comprising a signal line in between.

  (4) In the printed circuit board on which the electronic component is mounted, the first electronic component is soldered to the first mounting portion, and the first electronic component is arranged in a line with the first mounting portion. A printed circuit board comprising a second mounting portion for attaching, and having a signal line between the first mounting portion and the second mounting portion.

  ADVANTAGE OF THE INVENTION According to this invention, the freedom degree of the wiring on a board | substrate can be raised, maintaining the bridge prevention performance at the time of solder flow mounting.

The figure explaining IC package of Example 1 The figure explaining arrangement | positioning of IC and land of the prior art example for the comparison of Example 1 The figure explaining the wiring pattern of the prior art example for the comparison of Example 1 The figure explaining arrangement | positioning of IC and land of Example 1. The figure explaining the wiring pattern of Example 1 The figure explaining IC package of Example 2. The figure explaining arrangement | positioning of IC and land of the prior art example for the comparison of Example 2 The figure explaining the wiring pattern of the prior art example for the comparison of Example 2 The figure explaining arrangement | positioning of IC and land of Example 2. The figure explaining the wiring pattern of Example 2. The figure explaining arrangement | positioning of IC and land of Example 3. The figure explaining arrangement | positioning of IC and land of Example 4. The figure explaining arrangement | positioning of IC and land of another example of Example 4 The figure explaining the solder bridge prevention land of a prior art example The figure explaining the solder bridge prevention land of a prior art example

  Hereinafter, a basic configuration of an image forming apparatus according to an embodiment of the present invention will be described in detail with reference to the drawings. The following embodiments are merely examples, and are not intended to limit the technical scope of the present invention only to them. Hereinafter, the present invention will be described in detail based on examples.

  In the first embodiment, a configuration for connecting a heat dissipation pin (hereinafter referred to as a heat dissipation pin) of a stepping motor driver IC and a solder bridge prevention land (hereinafter referred to as a solder bridge prevention land) will be described.

  In this embodiment, the printed circuit board is a single-sided (single layer) board. Also, flow soldering (hereinafter referred to as flow soldering) is used when mounting components on the printed circuit board of this embodiment. As the material, CEM-3 (Composite Epoxy material-3) or FR-4 (Frame returnant-4) may be used, but FR-1 (paper phenol) is often used from the viewpoint of cost. A single-sided printed circuit board has great restrictions on pattern wiring, and the present invention can be used more efficiently. Of course, even if the substrate has two or more layers, the same effect can be obtained by applying it to the pattern of the layer mounted by flow soldering.

<Stepping motor driver IC package>
FIG. 1 is a diagram illustrating a package of a stepping motor driver IC as an example of an IC according to the present embodiment. This package is an SOP (two-way lead flat package). Reference numeral 10 denotes an IC (bidirectional lead flat package IC) according to the present embodiment. There are 26 pins in total. The pins 11 are normal pins, and have a pitch of 0.8 mm and a pin width of 0.35 mm. On the other hand, the pins 12 and 13 are GND (ground) pins and pins for heat dissipation. An IC chip (not shown) is mounted on a frame connected to the pin 12 and the pin 13, and the pin 12 and the pin 13 are heat dissipation pins that can efficiently dissipate heat from the IC chip. The pins 12 and 13 are wider than the pins 11. The reason why the pins 12 and 13 are wide is to increase the heat dissipation to the substrate pattern.

  In FIG. 1, reference numerals pin 1 to pin 26 indicate pins of the IC 10. pin1 means a pin having a pin number 1. Similarly, pin2 to pin26 mean pins having pin numbers 2 to 26. Pin 25 is the same as pin 12, and pin 26 is the same as pin 13. Pin1 to pin6, pin7 to pin12, pin13 to pin18, and pin19 to pin24 are the same as the pin 11.

<Comparison between the conventional example and this example>
~ About the conventional wiring pattern ~
2 and 3 are diagrams for explaining a pattern of a conventional printed circuit board. In order to facilitate understanding of the effects of the present embodiment, first, a conventional printed circuit board pattern will be described.

  FIG. 2 shows the layout of the IC 10 (shown by broken lines) and lands. Land lnd1 is a land for pin1. In this land, the resist formed on the copper foil is missing in the shape shown in the figure (the shape of the portion without the resist). Similarly, the lands lnd2 to lnd26 are lands for the pins 2 to 26. The lands lnd1 to lnd26 constitute a solder land group for soldering the IC 10.

  The rectangular solder bridge prevention land 22 is a land including the land lnd12, and the solder bridge prevention land 22 has a shape shown in the figure and no resist is formed thereon. Similarly, the solder bridge prevention land 21 is a land including the land lnd13. The solder bridge prevention lands 22 and 21 are formed on the most downstream pins of the IC 10 in the solder flow direction. Note that the direction of travel of the substrate is the direction of the arrow in the figure, and the direction of solder flow progression (hereinafter simply referred to as solder flow) is the opposite direction of the arrow, so the upstream side of the solder flow and the downstream side of the solder flow are shown in the figure. It becomes like this.

  FIG. 3 is a diagram in which the IC 10 is deleted from FIG. 2 and a wiring pattern on the printed board is added. The GND pattern 23 (shown by hatching in the figure) connected to the land lnd25 is intended to ensure heat dissipation by a wide copper foil pattern. However, the size is limited by a pattern connected to pin 3 or a signal line pattern connected to pin 8 (illustrated by a thick black solid line), and a sufficient area cannot be secured. Similarly, the GND pattern 24 connected to the pin 26 is limited in size by a pattern connected to another pin (for example, a pattern connected to the pin 17). Therefore, in order to ensure sufficient heat dissipation in the conventional pattern, the substrate was enlarged to expand the area of the copper foil pattern for heat dissipation to other parts, or another heat sink was provided. . If the area of the copper foil pattern for heat dissipation is increased without changing the size of the substrate, the arrangement of ICs on the printed circuit board is limited (the degree of freedom is reduced).

~ About the pattern of this example ~
Next, the substrate pattern of the present embodiment will be described. 4 and 5 are diagrams for explaining the pattern of this embodiment. The IC 10 is the same as that shown in FIGS. 2 and 3, that is, the IC shown in FIG. Compared to FIG. 2, FIG. 4 shows an increase in copper foil pattern exposed portions (portions where no resist is formed) (pattern exposed portions) 33, 34, and 35. The copper foil pattern exposed portions 33 and 34 have the same size and pitch as the lands lnd 13 to 24. The copper foil pattern exposed portion 35 has the same size and pitch (interval between lands) as the lands lnd1 to lnd12. In addition, since the copper foil pattern exposed portions 33, 34, and 35 are present, the rectangular solder bridge prevention lands 31 and 32 are not configured to include the lands lnd13 and lnd12 unlike the conventional example.

  FIG. 5 is a diagram in which the illustration of the IC 10 is deleted from FIG. 4 and a signal line pattern and the like are added. The difference between FIG. 5 and FIG. 3 is that the solder bridge prevention lands 32 and 31 are first connected to the GND patterns 23 and 24 via the GND patterns 37 and 36 (indicated by shading in the figure). . Thus, the solder bridge prevention lands 32 and 31 are connected to the land lnd25 and the land lnd26 which are lands of the heat dissipation pin of the IC 10 through the GND patterns 37, 36, 23 and 24. Therefore, the copper foil pattern is exposed at a part of the signal line pattern 41 connected to the land lnd14. This is the copper foil pattern exposed portion 33. At the position of the copper foil pattern exposed portion 33, the width of the signal line pattern 41 is the same as that of the land lnd13.

  Similarly, the signal line pattern 42 connected to the land lnd17 has a portion where the copper foil is exposed (copper foil pattern exposed portion 34). With the above pattern, exposed solder portions 33 and 34 having the same size as the lands lnd 13 to 24 are formed. That is, the resist is not applied to the portions of the signal line patterns 41 and 42 sandwiched between the lands lnd13 to lnd24, which are solder land groups, and the solder bridge prevention lands 31, and the copper foil pattern exposed portions 33 and 34 are formed. Yes.

  In FIG. 3, the GND pattern 24 and the solder bridge prevention land 21 are divided by the signal line patterns 29 and 30 connected to the lands lnd14 and lnd17. In FIG. 5, the solder bridge prevention land 31 is connected to a land lnd 26 that is a land of the heat dissipation pin of the IC 10 through the GND pattern 36.

  Similarly, by forming the copper foil pattern exposed portion 35 on the signal line pattern 40, the solder bridge preventing land 32 is connected to the land lnd25 which is a land of the heat dissipation pin through the GND patterns 37 and 23.

  By connecting the land lnd26 which is the land of the heat dissipation pin of the IC 10 and the solder bridge prevention land 31, the heat dissipation of the IC 10 is improved. One reason is that the land lnd26 and the solder bridge prevention land 31 can be connected with a relatively thick pattern like the GND pattern 36. As a result, the thermal resistance between the land lnd26 and the solder bridge prevention land 31 is relatively low. Be able to. The second reason is that since the solder bridge prevention land 31 has a relatively large area, it has a large heat capacity and a large heat radiation area, so that it has excellent heat dissipation. The third reason is that solder is formed on the solder bridge prevention land 31 during flow soldering, and the heat capacity becomes larger than that of the copper foil alone. That is, the pin 26, which is a heat dissipation pin of the IC 10, is connected to the solder bridge prevention land 31 having a relatively low thermal resistance, a large heat capacity, and a high heat dissipation property, so that a high heat dissipation property can be obtained. The connection between the heat radiation pin 25 of the IC 10 and the solder bridge prevention land 38 is the same.

  As described above, it has been described that the heat dissipation from the heat dissipation pin of the IC 10 is improved by the pattern of this embodiment. Next, it demonstrates from a viewpoint with respect to solder bridge prevention.

<Preventing solder bridging in this embodiment>
The copper foil pattern exposed portions 33 and 34 of the present embodiment have the same size as the lands lnd 13 to 24. When the printed circuit board of the present invention is poured into the flow solder bath, the solder to be soldered to the solder bridge prevention land 31 is drawn. In addition, the surface tension (also referred to as interfacial tension) of the solder attached to the pins 13 to 24, lnd26 and the copper foil pattern exposed portions 33 and 34 and the pins of the IC 10 is reduced, and solder bridges at each land and copper foil pattern exposed portion are prevented. Is done.

  If the signal line pattern 41 or 42 is passed between the land of the IC 10 and the solder bridge prevention land without the copper foil pattern exposed portion, the distance between the land (Ind13) of the IC 10 and the solder bridge prevention land 31 is increased. Then, the effectiveness of the solder bridge prevention land 31 to reduce the surface tension (interface tension) of the solder adhering to the land of the IC 10 is weakened, and sufficient solder bridge prevention performance cannot be obtained. Therefore, conventionally, productivity has been improved (to make it difficult to perform solder bridging) at the expense of the freedom of signal line pattern wiring. On the other hand, with this configuration, wiring can be performed without sacrificing the degree of freedom of signal line pattern wiring, and heat dissipation can be improved as in this embodiment.

  In the present embodiment, the size and pitch (interval) of the copper foil pattern exposed portions 33 and 34 are the same as the IC land. However, even if the size and pitch of the exposed part of the copper foil pattern is slightly changed from that of the IC land, the solder bridge prevention function will not be greatly impaired, so the size and pitch should be changed within the range where the solder bridge prevention performance can be obtained. Is possible.

  With the above configuration, according to this embodiment, the signal line pattern can be arranged between the solder land group of the IC and the solder bridge prevention land while maintaining the solder bridge prevention performance, and the heat dissipation of the IC is improved. Can be made.

  In the second embodiment, a configuration for connecting a GND pin of a CPU and a solder bridge prevention land will be described.

<About IC (CPU) package>
FIG. 6 is a diagram illustrating an IC (CPU) package according to the present embodiment. This package is a SOP. Reference numeral 50 denotes the present IC. There are 30 pins in total. The pins 51 are IC pins with a pitch of 0.65 mm and a pin width of 0.24 mm. In the drawing, the symbols pin1 to pin30 indicate the pins of the IC50. pin1 is a pin of pin number 1. Similarly, pins 2 to 30 are pins with pin numbers 2 to 30.

<Comparison between the conventional example and this example>
~ Regarding the conventional pattern ~
7 and 8 are diagrams for explaining a conventional pattern. In order to make the effects of this embodiment easy to understand, a conventional pattern will be described first.

  FIG. 7 shows the arrangement of the IC 50 and the land. The land lnd1 is a land for pin1 (part indicated by a solid line). In this land, the resist formed on the copper foil is missing in the shape shown in the figure (the shape of the portion without the resist). Similarly, lands lnd2 to lnd30 are lands for pins 2 to 30. The IC 50 described in FIG. 6 is a portion indicated by a broken line in the drawing.

  The solder bridge prevention land 52 is a land provided on the downstream side of the land lnd15 in the solder flow direction, and no resist is formed in the shape of 52 in the figure (no resist is applied). Similarly, the solder bridge prevention land 53 is provided downstream of the land lnd16 in the solder flow direction. Note that if the substrate traveling direction during the soldering process is the direction indicated by the arrow in FIG. 7, the solder flow traveling direction (hereinafter simply referred to as solder flow) is opposite to the arrow, so the upstream side of the solder flow and the solder flow The downstream side is as shown in the figure.

  FIG. 8 is a diagram in which the IC 50 diagram is deleted from FIG. 7 and a pattern is added. Pin 1 of the IC 50 is a GND pin and is connected to a solid GND pattern 54 (indicated by hatching in the figure). In general, as the number of GND patterns increases, a high-frequency signal return path is easily formed, and unnecessary radiation noise can be reduced. In particular, it is difficult for a single-layer (single-sided) substrate to increase the number of GND pattern connections due to the limitation of its layer structure.

~ About the pattern of this example ~
Next, the substrate pattern of the present embodiment will be described.

  9 and 10 are diagrams for explaining the pattern of this embodiment. The IC 50 is the same IC (CPU) as that shown in FIGS. 7 and 8, that is, the IC shown in FIG. Compared to FIG. 7, in FIG. 9, copper foil pattern exposed portions (portions where no resist is formed) 64 and 65 are increased. The copper foil pattern exposed portions 64 and 65 have the same size and pitch as the lands lnd16 to lnd30. Reference numerals 62 and 63 denote solder bridge prevention lands in this embodiment. Since the copper foil pattern exposed portions 64 and 65 are increased, the solder bridge prevention land 63 is formed at a position shifted from the position of the solder bridge prevention land 53 (see FIG. 8) of the conventional example.

  FIG. 10 is a diagram obtained by deleting the IC 50 diagram from FIG. 9 and adding a signal line pattern and the like. The difference between FIG. 8 and FIG. 10 is that the solder bridge prevention land 63 of this embodiment is a land of the GND pin of the IC 50 via the GND pattern 66 (shown by hatching) and the solid GND pattern 54. It is connected to lnd1. Therefore, the copper foil pattern is exposed without applying a resist in a part of the pattern connected to the land lnd17 and the land lnd18. This is the copper foil pattern exposed portions 64 and 65. At the positions of the copper foil pattern exposed portions 64 and 65, the widths of the signal line patterns 67 and 68 are the same as the land lnd17 and the land lnd18.

  In FIG. 10, by not applying a part of the resist of the signal line pattern, lands are formed at the copper foil pattern exposed portions 64 and 65 where the copper foil is exposed, and the lands are aligned with the lands of the pins of the IC 50. GND connection is strengthened while preventing solder bridges.

  The reason why the copper foil pattern exposed portions 64 and 65 can prevent solder bridging is the same principle as that described in <Preventing solder bridging in this embodiment> in the first embodiment, and thus the description thereof is omitted here. .

  With the above configuration, according to the present embodiment, it is possible to arrange the signal line between the land group for soldering the IC and the solder bridge prevention land while maintaining the solder bridge prevention performance. Further, the solder bridge prevention land can be made into a solid GND pattern, and unnecessary radiation noise can be reduced.

  In the third embodiment, an arrangement capable of reducing solder bridge prevention lands when two ICs are mounted will be described.

<Regarding the substrate pattern of this embodiment when two ICs are mounted>
FIG. 11 is a diagram showing a substrate pattern of this example. Reference numerals 88 and 80 denote ICs, for example, the same ICs (30 pins) as in the second embodiment (see FIG. 6). The ICs 80 and 88 may be 26-pin ICs (for example, stepping motor driver ICs or the like) as in the first embodiment, in which case the configuration is as shown in FIG. Since the pins and lands of these ICs are the same as those in the first and second embodiments, the description thereof is omitted.

  The IC 88 has a solder bridge prevention land 81. The solder bridge prevention land 81 is a land for preventing solder bridges of the lands lnd1 to lnd15 of the IC 88. On the other hand, the solder bridge prevention land for the lands lnd16 to lnd30 (first solder land group) is not dedicated. That is, there is no solder bridge prevention land 31 (see FIG. 4) or 63 (see FIG. 9) in the case where one IC is mounted as described in the first or second embodiment.

  On the other hand, IC 80, which is another IC, is disposed downstream of IC 88 in the solder flow direction. The lands lnd16 to lnd30 of the IC88 and the lands lnd1 to lnd15 (second solder land group) of the IC80 are arranged in a line in the solder flow direction, and the directions of the lands lnd16 to lnd30 and the lands lnd1 to lnd15 are perpendicular to the solder flow direction. Are aligned. Further, a copper foil pattern exposed portion 84 and a land 86 (also referred to as a dummy land) exist between the land lnd16 of the IC 88 and the land lnd1 of the IC80. The copper foil pattern exposed portion 84 is formed by not applying a part of the resist of the signal line pattern 85. This is the same as the copper foil pattern exposed portions (33, 34 (see FIG. 5), 64, 65 (see FIG. 10)) of Example 1 and Example 2. The land 86 is formed only of the copper foil pattern. That is, the signal line pattern is not partially exposed, and the resist is not applied to them as in the case of 84. The solder bridge prevention lands 82 and 83 are downstream of the IC 80 in the solder flow direction. These solder bridge prevention lands are the same as those in the first and second embodiments.

  In FIG. 11, as described above, the copper foil pattern exposed portion and the dummy land are formed at the same size and pitch as the land between the lands of the two ICs.

<Preventing solder bridging in this embodiment>
Next, it demonstrates from a viewpoint with respect to solder bridge prevention.

  Since the principle that the solder bridge hardly occurs in the lands lnd1 to lnd15 of the IC88 and the lands lnd16 to lnd30 of the IC80 is the same as that of the first embodiment, the description thereof is omitted.

  The reason why solder bridges are unlikely to occur in the lands lnd16 to lnd30 of the IC88, the copper foil pattern exposed portion 84, the land 86, and the lands lnd1 to lnd15 (hereinafter referred to as a series of lands) of the IC80 will be described. When the substrate according to this embodiment is passed through the flow solder bath, the solder to be soldered to the solder bridge prevention land 82 is drawn. Then, the surface tension (interfacial tension) of the solder adhering to the series of lands and the pins of the ICs 80 and 88 is reduced, and solder bridging at each land (series of lands) and the exposed copper foil pattern is prevented. For this reason, it is not necessary to provide a solder bridge prevention land dedicated for the IC 88 on the downstream side of the solder flow of the lands lnd16 to lnd30 which are the lands of the IC88.

  As described above, the arrangement shown in FIG. 11 eliminates the need for solder bridge prevention lands for the lands lnd16 to lnd30 of the IC 88, thereby reducing the board area and improving the degree of freedom of signal line pattern wiring.

  With the above configuration, according to the present embodiment, when two ICs are subjected to single-sided flow soldering, the number of solder bridge prevention lands can be reduced, and the board area can be reduced and the degree of freedom of signal line pattern wiring can be improved. be able to.

  In the fourth embodiment, a configuration in which a solder bridge prevention land is formed on a discarded board of a printed board will be described.

<About the substrate pattern of this example>
FIG. 12 is a substrate pattern diagram of this embodiment. Reference numeral 90 denotes an IC which is the same as that of the second embodiment (see FIG. 6). Reference numeral 97 denotes a printed circuit board (hereinafter simply referred to as a board) on which the IC 90 is mounted. Reference numeral 91 denotes a V-cut portion (groove portion in a V-shape) which is a dividing means for separating the substrate. The substrate 97a is used on the upper side of the drawing from the V-cut portion 91, and the lower side is a portion not used. This is the substrate 97b. Reference numeral 93 denotes a copper foil pattern exposed portion, and reference numerals 92, 98, and 99 denote lands (also referred to as dummy lands). Among these, the lands 92, 98, and 99 are the same as those in the third embodiment. On the other hand, the copper foil pattern exposed portion 93 is formed on a part of the signal line pattern 94 by not applying the resist in the same shape as the lands of the land group (lands lnd16 to lnd30). This is the same as in the second embodiment. Reference numerals 95 and 96 denote solder bridge prevention lands.

  In this embodiment, it is used between the lands 1nd to 30, 92, 98, 99 of the IC 90 to be prevented from solder bridging and the copper foil pattern exposed portion 93 (hereinafter referred to as a series of lands) and the solder bridge preventing lands 95, 96. There is an end portion of the substrate 97a. However, the solder bridge prevention lands 95 and 96 have an effect of reducing the surface tension (interfacial tension) of the solder adhering to a series of lands when performing flow soldering on the discarded substrate 97b, and solder bridges can be prevented.

  In this embodiment, the configuration in which the V-cut portion 91 is used for dividing the substrate has been described. However, even when the substrate is divided by the slit, the same effect can be obtained if the series of lands and the solder bridge prevention lands 95 and 96 are sufficiently close.

  Further, as shown in FIG. 13, the position of the V-cut portion 91 can be moved to the position of the V-cut portion 91a. The V cut portion 91 a is formed in the middle of the solder bridge prevention lands 95 and 96. Compared to FIG. 12, the distance between the lands 98 and 99 and the solder bridge prevention lands 95 and 96 can be narrowed, and the solder bridge prevention effect works more effectively.

  In this embodiment, the V-cut portion is used for dividing the substrate. However, the V-cut portion is an example, and other configurations such as a configuration in which holes are perforated and divided are applicable. It is.

  With the above configuration, according to the present embodiment, a solder bridge prevention land having a large area can be formed on the discarded substrate, and there is an effect of improving the wiring flexibility of the substrate to be used and reducing the substrate area.

Claims (18)

In a printed circuit board where electronic components are soldered by being transported to a solder bath,
A first solder land for soldering the electronic component;
A second solder land for collecting solder, which is provided downstream of the first solder land in the transport direction of the printed circuit board;
A printed circuit board having a signal line pattern having a pattern exposed portion between the first solder land and the second solder land. Furthermore, a heat dissipation pattern for radiating heat generated from the electronic component is provided,
The printed circuit board according to claim 1, wherein the second solder land is connected to a heat dissipation pin of the electronic component through the heat dissipation pattern. In addition, with a ground pattern,
The printed circuit board according to claim 1, wherein the second solder land is connected to the ground pattern.   4. The printed circuit board according to claim 1, wherein a size of the pattern exposed portion is the same as that of the first solder land. 5. A plurality of the first solder lands;
4. The printed circuit board according to claim 1, wherein an interval between the plurality of first solder lands and an interval between the first solder lands and the signal line pattern are the same interval. 5.   6. A dividing part for dividing the printed circuit board is provided between the first solder land and the second solder land or in the middle of the second solder land. The printed circuit board as described in any one of the items.   The printed circuit board according to claim 1, further comprising a land to which no resist is applied between the first solder land and the second solder land.   The printed circuit board according to claim 1, wherein the electronic component includes a flat package IC. A first solder land for soldering electronic components;
A second solder land arranged in line with the first solder land;
A printed circuit board having a signal line pattern having a pattern exposed portion between the first solder land and the second solder land.   The printed circuit board according to claim 9, further comprising a land to which a resist is not applied between the first solder land and the second solder land.   The printed circuit board according to claim 9, wherein the electronic component includes a flat package IC. In printed circuit boards on which electronic components are mounted,
A printed circuit board comprising: a mounting portion to which terminals of the electronic component are soldered; a solder pattern portion provided in proximity to the mounting portion; and a signal line between the mounting portion and the solder pattern portion. substrate. A plurality of the mounting portions are provided,
The printed circuit board according to claim 12, wherein the solder pattern portion is provided close to an end portion in a direction in which a plurality of implementation portions are arranged. Furthermore, it has a heat dissipation pattern to which the heat dissipation pin of the electronic component is connected,
The printed circuit board according to claim 12, wherein the solder pattern portion and the heat dissipation pattern are connected.   The printed circuit board according to claim 12, further comprising a ground pattern, wherein the solder pattern portion is connected to the ground pattern.   The printed circuit board according to claim 12, wherein the electronic component includes a flat package IC. In printed circuit boards on which electronic components are mounted,
A first mounting part to which the first electronic component is soldered;
A second mounting part for soldering the second electronic component, the second mounting part being arranged in a row with the first mounting part, between the first mounting part and the second mounting part A printed circuit board having a signal line.   The printed circuit board according to claim 17, wherein the electronic component includes a flat package IC.

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