JP2010062399A - Semiconductor device and method of manufacturing the same, and electronic apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device having a bottom contact top gate type thin-film transistor excelling in a characteristic with carrier mobility in a channel part secured while being structurally stable. <P>SOLUTION: This semiconductor device 1 includes: a source electrode 13s and a drain electrode 13d embedded in a surface side of a substrate 11; a semiconductor layer 15 formed on the substrate 11 while contacting the source electrode 13s and the drain electrode 13d, and the substrate 11 between them; a gate insulation film 17 formed on the semiconductor layer 15; and a gate electrode 19 formed above the semiconductor layer 15 between the source electrode 13s and the drain electrode 13d through the gate insulation film 17. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor device, a semiconductor device manufacturing method, and an electronic device, and more particularly, to a semiconductor device including a thin film semiconductor layer made of an organic material, a semiconductor device manufacturing method, and an electronic device.

  Thin film transistors (organic TFTs) with semiconductor layers made of organic materials are attracting attention as transistors that can be fabricated on flexible substrates with high throughput and low cost, and are mounted on electronic devices such as flexible displays, ID tags, and sensors. Toward this end, various research and development are progressing.

  In particular, FIG. 11 shows a cross-sectional structure of a bottom contact / top gate type organic TFT, which is one of the organic TFTs. The organic TFT shown in this figure has a configuration in which a gate electrode 109 is disposed on a source electrode 103 s and a drain electrode 103 d wired on a substrate 101 with a semiconductor layer 105 and a gate insulating film 107 interposed therebetween.

  The structural advantages of the bottom contact / top gate type structure are as follows. Similar to the bottom-bottom contact / bottom-gate structure, the source electrode and the drain electrode can be formed by applying a photolithography technique, so that a fine element can be formed. Further, similarly to the top contact / bottom gate structure, since the source electrode and the drain electrode are in contact with the semiconductor layer on the surface, a low contact resistance can be obtained.

  However, it is generally difficult to form a bottom contact / top gate type structure in an organic TFT. This is because the semiconductor layer 105 is damaged when the gate insulating film 107 is formed over the semiconductor layer 105. (Example: When the gate insulating film is an organic material, the solvent dissolves the semiconductor layer. When the gate insulating film is a CVD film, plasma damage is given to the semiconductor layer during film formation.)

  Several methods are known in order to avoid the above-mentioned problems related to the production of bottom contact / top gate type organic TFTs.

  First, there is a method in which a material that does not damage the semiconductor layer, such as a fluororesin, is used as the gate insulating film.

  Second, a method has been proposed in which a semiconductor layer and a gate insulating film deposited on a transfer substrate are transferred and formed on a substrate on which a source electrode and a drain electrode are formed. By applying this method, a pattern can be formed on the substrate on which the source electrode and the drain electrode are formed without damaging the organic semiconductor layer. According to this method, as shown in FIG. 12, the semiconductor layer 105 and the gate are formed on the source electrode 103s and the drain electrode 103d wired on the substrate 101 while maintaining the space A between the source electrode 103s and the drain electrode 103d. The insulating film 107 is transferred to the pattern. Then, a gate electrode 109 is formed on the gate insulating film 107 (see Non-Patent Document 1 below).

"Organic Electronics 8", 2007, p.615-620

However, the above-described bottom contact / top gate type organic TFT has the following problems.
In the configuration shown in FIG. 11, the semiconductor layer 105, the gate insulating film 107, and the gate electrode 109 are formed in a surface shape that follows the uneven shape of the source electrode 103s and the drain electrode 103d wired on the substrate 101. For this reason, a step is formed between the portion where the carrier is injected and the channel layer, and this portion becomes a contact resistance, which causes a deterioration in transistor characteristics.
Furthermore, the uppermost surface of the semiconductor layer serving as the channel portion is not flat in many cases of the organic semiconductor thin film. For this reason, carrier mobility in the channel portion cannot be ensured, which causes a deterioration in transistor characteristics.

On the other hand, in the structure shown in FIG. 12, the semiconductor layer 105, the gate insulating film 107, and the gate electrode 109 have a flat surface regardless of the uneven shape of the source electrode 103s and the drain electrode 103d wired on the substrate 101. It is formed while maintaining its shape. For this reason, it is easy to ensure low contact resistance compared with the structure shown in FIG. In addition, since the channel portion is formed following the flat surface of the gate insulating film, carrier mobility in the channel portion in the semiconductor layer 105 can be easily ensured.
However, in such a configuration, the contact area of the semiconductor layer 105 to the substrate 101 side is small as is apparent from the formation of the space A under the semiconductor layer 105. For this reason, it is structurally unstable, its mechanical strength is weak, and its reliability is poor. In particular, when a plurality of organic TFTs or other elements are formed on a substrate for integration, it is necessary to cover the organic TFT with an interlayer insulating film and form a connection wiring or the like on the upper part. Such structural instability is a factor that causes deterioration of electrical characteristics of the organic TFT.

  Accordingly, the present invention provides a semiconductor device having a bottom contact / top gate type thin film transistor with excellent characteristics, which is structurally stable and has carrier mobility in the channel portion, and a method of manufacturing the semiconductor device, and It is an object to provide an electronic device using a semiconductor device.

  In order to achieve such an object, a semiconductor device of the present invention includes a source electrode and a drain electrode embedded on the surface side of a substrate, a source electrode and a drain electrode, and a substrate between them in contact with the substrate. And a provided semiconductor layer. A gate electrode is provided on the semiconductor layer via a gate insulating film.

  The present invention is also a method for manufacturing a semiconductor device having such a configuration, and the following procedure is performed. First, as a first step, a source electrode and a drain electrode are patterned on a transfer substrate. In the next second step, an insulating film having a flat surface is formed on the transfer substrate in a state where the source electrode and the drain electrode are embedded, thereby forming the substrate. Further, in the third step, the transfer substrate is removed from the substrate side, so that the source electrode and the drain electrode are embedded on the surface side of the substrate. Thereafter, in the fourth step, a stacked body in which the semiconductor layer, the gate insulating film, and the gate electrode are provided in this order on the substrate is in a state where the semiconductor layer is in contact with the substrate between the source electrode and the drain electrode and these electrodes. Form with.

  By such a procedure, as described above, the source electrode and the drain electrode are embedded on the surface side of the substrate, and the semiconductor provided on the substrate in a state where the source electrode and the drain electrode are in contact with the substrate therebetween. A semiconductor device having a layer is obtained.

  Furthermore, the present invention is also an electronic apparatus to which the semiconductor device having the above configuration is applied. The electronic device further includes an interlayer insulating film covering the substrate on which the gate electrode is formed, and an electrode wiring connected to the source electrode or the gate electrode through a connection hole provided in the interlayer insulating film.

  In the semiconductor device having the above-described configuration, since the source electrode and the drain electrode are embedded on the surface side of the substrate, the lower ground of the semiconductor layer provided on the upper portion becomes more flattened. Therefore, in the bottom contact / top gate type thin film transistor configuration in which the semiconductor layer is provided in contact with the source electrode and the drain electrode and the substrate between them, the surface of the semiconductor layer, that is, the semiconductor layer and the gate insulating film above this The interface is flattened over the entire surface directly under the gate.

  As described above, according to the present invention, in the bottom contact / top gate type thin film transistor configuration in which the semiconductor layer is provided in contact with the source electrode and the drain electrode and the substrate therebetween, the semiconductor layer and the gate insulating film on the top Can be flattened. Therefore, it is possible to secure carrier mobility and improve electrical characteristics in a structurally stable bottom contact / top gate type thin film transistor configuration without forming a space or the like under the semiconductor layer. become.

  DESCRIPTION OF EMBODIMENTS Hereinafter, embodiments of the present invention will be described in detail in the order of a semiconductor device, a method for manufacturing a semiconductor device, and an electronic apparatus using the semiconductor device, based on the drawings.

≪Semiconductor device≫
FIG. 1 is a cross-sectional view of a semiconductor device 1 according to an embodiment. The semiconductor device 1 shown in this figure is configured as a bottom gate bottom contact thin film transistor. The semiconductor device 1 shown in this figure includes a source electrode 13 s and a rain electrode 13 d that are embedded on the surface side of a substrate 11.

  Here, the substrate 11 has a structure in which the surface side of a support substrate 11a made of, for example, a plastic substrate, a glass substrate, or a quartz substrate is covered with an insulating film 11b made of an organic material. As the insulating film 11b, for example, a coating system such as a mixture of polyvinylphenol (PVP), polymethylmethacrylate (PMMA), PVP and a crosslinking agent, and octadecyltriclorosilane (OTS). Organic materials are preferably used. The source electrode 13s and the rain electrode 13d made of gold (Au) or the like are embedded on the surface side of the insulating film 11b.

  In the embedded state, the surfaces of the source electrode 13 s and the drain electrode 13 d are arranged at a height that forms the same plane as the surface of the substrate 11. For this reason, the insulating film 11b which comprises the surface of the board | substrate 11 shall be comprised more thickly than the source electrode 13s and the drain electrode 13d.

  In addition, a semiconductor layer 15 is provided on the flat surface of the substrate 11 in which the source electrode 13s and the rain electrode 13d are embedded. It is important that the semiconductor layer 15 is provided in contact with the source electrode 13 s and the drain electrode 13 d arranged opposite to each other and the substrate 11 portion therebetween, and may be patterned on the substrate 11.

  The semiconductor layer 15 is an organic semiconductor layer made of an organic material such as pentacene.

  A gate electrode 19 is laminated on the semiconductor layer 15 with a gate insulating film 17 interposed therebetween. For example, the gate insulating film 17 and the gate electrode 19 may have the same shape as the semiconductor layer 15. The gate insulating film 17 is preferably made of an organic material. Like the insulating film 11b, for example, PVP, PMMA, or a coating organic material such as a mixture of PVP, a crosslinking agent, and OTS is suitable. Used for.

  Here, in the upper part between the source electrode 13s and the drain electrode 13d, the semiconductor layer 15, the gate insulating film 17, and the gate electrode 19 are stacked on the flat substrate 11 including the surfaces of the source electrode 13s and the drain electrode 13d. Has been. For this reason, each interface of these laminated films has a configuration in which flatness is maintained.

  As described above, the organic thin film transistor Tr having the bottom contact / top gate structure in which the semiconductor layer 15 is provided on the source electrode 13 and the drain electrode 13d and the gate electrode 19 is stacked on the gate electrode 19 via the gate insulating film 17 is configured. Has been.

  In the semiconductor device 1 having the organic thin film transistor Tr having the bottom contact / top gate structure having such a configuration, the source electrode 13 s and the drain electrode 13 d are embedded on the surface side of the substrate 11. Then, the surface of the substrate 11 and the surfaces of the source electrode 13s and the drain electrode 13d are arranged at a height that constitutes the same surface, and constitute a flat surface. For this reason, the surface of the semiconductor layer 15, that is, the interface between the semiconductor layer 15 and the upper gate insulating film 17 is kept flat in contact with the source electrode 13s and the drain electrode 13d and the substrate 11 therebetween. Therefore, in the bottom contact / top gate type thin film transistor structure which is structurally stable without forming a space portion under the semiconductor layer 15, the portion where the channel portion is formed in the semiconductor layer 15 can be kept flat. Thus, it is possible to secure the carrier mobility and improve the transistor characteristics.

  Furthermore, in the organic thin film transistor Tr having such a configuration, a portion where the channel portion is formed in the semiconductor layer 15 and a portion other than the portion are arranged on a plane, so that the contact resistance can be reduced. This also makes it possible to improve the transistor characteristics.

  In the example described with reference to FIG. 1, the configuration in which the surface side of the support substrate 11 a is covered with the insulating film 11 b made of an organic material as the substrate 11 has been described. However, the substrate 11 may be made of a single structure as long as the source electrode 13s and the drain electrode 13d are configured to be embedded on the surface side while maintaining insulation, for example, sufficient to hold the film. As long as it has a sufficient thickness, it may be composed of only an insulating film.

<< Semiconductor Device Manufacturing Method-1 >>
Next, an embodiment (first example) of the semiconductor device manufacturing method described above will be described in detail based on the sectional process diagrams of FIGS.

  First, as shown in FIG. 2A, a transfer substrate 21 is prepared, and an adhesive layer 23 is formed on the transfer substrate 21. The transfer substrate 21 can be a plastic substrate, a glass substrate, a silicon substrate, a quartz substrate, or the like, but it is preferable to use a flexible plastic substrate in consideration of pasting and peeling in a later process. The pressure-sensitive adhesive layer 23 is made of a slightly adhesive material such as polydimethylsiloxane (PDMS), polyolefin (Polyolefin), or polyfluoroether diacrylate (PFPE).

  Then, the source electrode 13 s and the drain electrode 13 d are pattern-formed on the transfer substrate 21 via the adhesive layer 23. At this time, the source electrode 13 s and the drain electrode 13 d are formed by first forming a conductive material film made of, for example, gold (Au: 30 nm) on the adhesive layer 23. Here, for example, a conductive ink containing silver fine particles may be formed by coating, and in this case, baking is performed after the film formation. Next, a resist pattern is formed with high accuracy on the conductive material film by lithography, and the conductive material film is etched using the resist pattern as a mask. Thus, the source electrode 13s and the drain electrode 13d are formed by pattern etching of the conductive material film.

  Note that the resist pattern is removed after the etching. The source electrode 13s and the drain electrode 13d may be formed by a lift-off method using a resist pattern formed with high accuracy by a lithography method.

  Next, as shown in FIG. 2B, an insulating film 11b is formed on the transfer substrate 21 in a state where the source electrode 13s and the drain electrode 13d are embedded in a flat surface. As the insulating film 11b, for example, as described above, a coating organic material such as PVP, PMMA, or a mixture of PVP, a crosslinking agent, and OTS is preferably used. In this case, it is important to form the insulating film 11b by, for example, a spin coating method to ensure the surface flatness of the insulating film 11b.

  Note that after the insulating film 11b is formed by coating, the insulating film 11b is cured by natural drying or baking. In the case of firing, heating is performed at a heating temperature (for example, 100 ° C. to 180 ° C.) more suitable for the material constituting the insulating film 11b and the adhesive layer 23. Moreover, the hardening process by ultraviolet irradiation may be sufficient.

  Thereafter, as shown in FIG. 2 (3), a support substrate 11a is prepared. The support substrate 11a is a substrate that finally remains as a constituent material of the semiconductor device. As described above, the support substrate 11a is made of, for example, a plastic substrate, a glass substrate, or a quartz substrate. However, it is preferable to use a light-transmitting substrate in consideration of subsequent steps. Then, the support substrate 11a and the transfer substrate 21 are bonded together in a state where the surface side of the insulating film 11b formed on the transfer substrate 21 is opposed to one main surface side of the support substrate 11a. At this time, it is important that the support substrate 11a and the insulating film 11B are sufficiently adhered using a vacuum vise.

  Thereafter, as shown in FIG. 2 (4), the transfer substrate 21 carrying the adhesive layer 23 is peeled and removed from the support substrate 11a side, and the insulating film 11b, the source electrode 13s, and the drain electrode 13d are formed on the support substrate 11a side. Transcript. As a result, the source electrode 13s and the drain electrode 13d are buried on the surface side of the substrate 11 where the support substrate 11a is covered with the insulating film 11b. Further, in this state, the same surface is constituted by the surface of the substrate 11 and the surfaces of the source electrode 13s and the drain electrode 13d.

  On the other hand, as shown in FIG. 3A, another transfer substrate 25 is prepared, and an adhesive layer 27 is formed on the transfer substrate 25. The transfer substrate 25 and the adhesive layer 27 may be the same as the transfer substrate 21 and the adhesive layer 27 described with reference to FIG. That is, a plastic substrate, a glass substrate, a silicon substrate, a quartz substrate, or the like can be used as the transfer substrate 25, but it is preferable to use a flexible plastic substrate in consideration of pasting and peeling in a later process. In addition, the adhesive layer 27 is made of a fine adhesive material such as PDMS, polyolefin, or PFPE.

  On the adhesive layer 27, the gate electrode layer 19a, the gate insulating film layer 17a, and the semiconductor layer 15a are sequentially stacked from the lower layer side.

  The gate electrode layer 19a is made of, for example, gold (Au), copper (Cu), silver (Ag), or the like, and is formed by vacuum deposition or sputtering. Here, for example, a conductive ink containing conductive fine particles may be applied and formed into a film. In this case, baking is performed after the film formation.

  As the gate insulating film layer 17a, for example, as described above, a coating organic material such as PVP, PMMA, or a mixture of PVP, a crosslinking agent, and OTS is preferably used. Here, for example, spin coating is used. A gate insulating film layer 17a is formed.

  The semiconductor layer 15a is made of an organic semiconductor material such as pentacene, and is formed by a vacuum deposition method, a PVD method, or the like. Here, the semiconductor layer 15a may be formed by coating.

  Next, as shown in FIG. 3B, as described above, the substrate 11 and the transfer substrate 25 on which the semiconductor layer 15a is formed are disposed to face each other. At this time, the exposed surfaces of the source electrode 13 s and the drain electrode 13 d on the substrate 11 and the semiconductor layer 15 a on the transfer substrate 25 are arranged facing each other. In this state, the substrate 11 and the transfer substrate 25 are bonded together. At this time, it is important that the substrate 11 and the semiconductor layer 15a of the transfer substrate 25 are sufficiently brought into close contact with each other using a vacuum vise or the like.

  Thereafter, as shown in FIG. 3 (3), the transfer substrate 25 carrying the adhesive layer 27 is peeled and removed from the substrate 11 side, and the substrate 11 side on which the source electrode 13s and the drain electrode 13d are formed is exposed from the lower layer. The stacked film of the semiconductor layer 15a, the gate insulating film layer 17a, and the gate electrode layer 19a is transferred in order.

  Next, as shown in FIG. 3 (4), the gate electrode 19 is formed by patterning the gate electrode layer 19 a provided on the outermost surface of the substrate 11. At this time, a resist pattern (not shown) is formed on the gate electrode layer 19a with high precision by lithography, and the gate electrode layer 19a is etched using the resist pattern as a mask to pattern the gate electrode 19. The gate electrode 19 is patterned so as to be disposed at least between the source electrode 13s and the drain electrode 13d. Note that after the gate electrode 19 is formed, the resist pattern is removed by chemical treatment.

  Next, as shown in FIG. 3 (5), the gate insulating film layer 17a and the semiconductor layer 15a are etched using the gate electrode 19 as a mask. Here, for example, oxygen plasma etching is performed. As described above, the semiconductor layer 15 provided in contact with the source electrode 13 s and the drain electrode 13 d and the substrate 11 therebetween, the gate insulating film 17 provided on the semiconductor layer 15, and the gate electrode 19 are stacked. A body is patterned on the substrate 11. Then, the bottom contact / top gate type organic thin film transistor Tr described with reference to FIG. 1 is obtained. The organic thin film transistor Tr is structurally stable because the interface between the semiconductor layer 15 and the gate insulating film 17 is kept flat and there is no space.

<< Semiconductor Device Manufacturing Method-2 >>
Next, an embodiment (second example) of the semiconductor device manufacturing method described above will be described in detail based on FIG. 4 together with FIG. In addition, the same code | symbol is attached | subjected to the component similar to a 1st example, and a part of overlapping description is abbreviate | omitted.

  First, the same procedure as described with reference to FIGS. 2 (1) to 2 (4) in the first example is performed, and the source electrode is formed on the surface side of the substrate 11 whose upper surface is covered with the insulating film 11b. 13s and the drain electrode 13d are embedded. The surface of the substrate 11 and the surfaces of the source electrode 13s and the drain electrode 13d constitute the same surface.

  On the other hand, as shown in FIG. 4A, another transfer substrate 25 is prepared, and a soluble sacrificial layer 29 is formed on the transfer substrate 25, which is different from the first example. The transfer substrate 25 is the same as in the first example, and a plastic substrate, a glass substrate, a silicon substrate, a quartz substrate, or the like can be used, but a flexible plastic substrate is used in consideration of pasting and peeling in a later process. It is preferable. The soluble sacrificial layer 29 is made of a water-soluble material such as polyvinyl alcohol (PVA).

  After that, on the soluble sacrificial layer 29, the same gate electrode layer 19a, gate insulating film layer 17a, and semiconductor layer 15a as those in the first example are sequentially stacked from the lower layer side. That is, as the gate electrode layer 19a, a material film of gold (Au), copper (Cu), silver (Ag), or the like is formed by a vacuum evaporation method, a sputtering method, or a coating film formation method. Next, as the gate insulating film layer 17a, an organic material film is formed by a coating film forming method. Thereafter, as the semiconductor layer 15a, an organic semiconductor material film such as pentacene is formed by a vacuum deposition method, a PVD method, or a coating film forming method.

  Next, as shown in FIG. 4B, the substrate 11 described above and the transfer substrate 25 on which the layers up to the semiconductor layer 15a are formed are arranged to face each other. At this time, the exposed surfaces of the source electrode 13 s and the drain electrode 13 d on the substrate 11 and the semiconductor layer 15 a on the transfer substrate 25 are arranged facing each other. In this state, the substrate 11 and the transfer substrate 25 are bonded together. At this time, it is important that the substrate 11 and the semiconductor layer 15a of the transfer substrate 25 are sufficiently brought into close contact with each other using a vacuum vise or the like.

  Thereafter, as shown in FIG. 4 (3), in the second example, the transfer substrate 25 is peeled off from the substrate 11 side by dissolving the water-soluble soluble sacrificial layer 29 in water. Thereby, the laminated film of the semiconductor layer 15a, the gate insulating film layer 17a, and the gate electrode layer 19a is transferred in order from the lower layer to the substrate 11 side on which the source electrode 13s and the drain electrode 13d are formed.

  After the above, it may be performed similarly to the first example. That is, as shown in FIG. 4 (4), the gate electrode 19 is formed by patterning the gate electrode layer 19 a provided on the outermost surface on the substrate 11. At this time, a resist pattern (not shown) is formed on the gate electrode layer 19a with high precision by lithography, and the gate electrode layer 19a is etched using the resist pattern as a mask to pattern the gate electrode 19. The gate electrode 19 is patterned so as to be disposed at least between the source electrode 13s and the drain electrode 13d. Note that after the gate electrode 19 is formed, the resist pattern is removed by chemical treatment.

  Next, as shown in FIG. 4 (5), the gate insulating film layer 17a and the semiconductor layer 15a are etched using the gate electrode 19 as a mask. Here, for example, oxygen plasma etching is performed. As described above, the semiconductor layer 15 provided in contact with the source electrode 13 s and the drain electrode 13 d and the substrate 11 therebetween, the gate insulating film 17 provided on the semiconductor layer 15, and the gate electrode 19 are stacked. A body is patterned on the substrate 11. Then, the bottom contact / top gate type organic thin film transistor Tr described with reference to FIG. 1 is obtained. The organic thin film transistor Tr is structurally stable because the interface between the semiconductor layer 15 and the gate insulating film 17 is kept flat and there is no space.

<< Semiconductor Device Manufacturing Method-3 >>
Next, an embodiment (third example) of the semiconductor device manufacturing method described above will be described in detail based on FIG. 5 together with FIG. In addition, the same code | symbol is attached | subjected to the component similar to a 1st example, and a part of overlapping description is abbreviate | omitted.

  First, the same procedure as described with reference to FIGS. 2 (1) to 2 (4) in the first example is performed, and the source electrode is formed on the surface side of the substrate 11 whose upper surface is covered with the insulating film 11b. 13s and the drain electrode 13d are embedded. The surface of the substrate 11 and the surfaces of the source electrode 13s and the drain electrode 13d constitute the same surface.

  On the other hand, as shown in FIG. 5A, another transfer substrate 25 is prepared, and an adhesive layer is formed as an adhesive layer pattern 27a on the transfer substrate 25, which is different from the first example. That is, the adhesive layer pattern 27a is formed in a pattern extending between the source electrode 13s and the drain electrode 13d embedded in the surface layer of the substrate 11. Further, the adhesive layer pattern 27a is a film larger than the total film thickness of the laminated film so that the laminated film formed in the next step is formed in a state where the laminated film is divided at the upper part and the lower part of the adhesive layer pattern 27a. It is important that it is formed with a thickness.

  The materials of the transfer substrate 25 and the adhesive layer pattern 27a may be the same as those of the transfer substrate 21 and the adhesive layer 23 described with reference to FIG. That is, a plastic substrate, a glass substrate, a silicon substrate, a quartz substrate, or the like can be used as the transfer substrate 25, but it is preferable to use a flexible plastic substrate in consideration of pasting and peeling in a later process. The adhesive layer pattern 27a is made of a fine adhesive material such as PDMS, polyolefin, or PFPE.

  Then, as shown in FIG. 5B, on the transfer substrate 25 on which the adhesive layer pattern 27a is formed, the same gate electrode layer 19a, gate insulating film layer 17a, and semiconductor layer 15a as those in the first example are formed from the lower layer side. Laminate films are sequentially formed. That is, as the gate electrode layer 19a, a material film of gold (Au), copper (Cu), silver (Ag), or the like is formed by a vacuum evaporation method, a sputtering method, or a coating film formation method. Next, as the gate insulating film layer 17a, an organic material film is formed by a coating film forming method. Thereafter, as the semiconductor layer 15a, an organic semiconductor material film such as pentacene is formed by a vacuum deposition method, a PVD method, or a coating film forming method. These laminated films are formed in a state where the upper and lower portions of the adhesive layer pattern 27a are separated.

  Next, as shown in FIG. 5 (3), the substrate 11 described above and the transfer substrate 25 on which the layers up to the semiconductor layer 15a are formed are arranged to face each other. At this time, the exposed surfaces of the source electrode 13 s and the drain electrode 13 d on the substrate 11 and the semiconductor layer 15 a on the transfer substrate 25 are arranged facing each other. In this state, the substrate 11 and the transfer substrate 25 are bonded together. At this time, it is important that the substrate 11 and the semiconductor layer 15a on the adhesive layer pattern 27a in the transfer substrate 25 are sufficiently brought into close contact with each other using a vacuum vise or the like. Particularly in the third example, it is important to perform alignment so that the semiconductor layer 15a on the adhesive layer pattern 27a is disposed between the source electrode 13s and the drain electrode 13d embedded on the surface side of the substrate 11. It is.

  Thereafter, as shown in FIG. 5 (4), the transfer substrate 25 carrying the adhesive layer pattern 27a is peeled and removed from the substrate 11 side. Thus, the laminated film of the semiconductor layer 15a, the gate insulating film layer 17a, and the gate electrode layer 19a formed on the adhesive layer pattern 27a is transferred to the substrate 11 side on which the source electrode 13s and the drain electrode 13d are formed. . At this time, the semiconductor layer 15a, the gate insulating film layer 17a, and the gate electrode layer 19a under the adhesive layer pattern 27a are left as they are on the transfer substrate 25 side and are peeled and removed, so that they are transferred to the substrate 11 side. There is no.

  As described above, the semiconductor layer 15 provided in contact with the source electrode 13 s and the drain electrode 13 d and the substrate 11 therebetween, the gate insulating film 17 provided on the semiconductor layer 15, and the gate electrode 19 are stacked. A body is patterned on the substrate 11. Then, the bottom contact / top gate type organic thin film transistor Tr described with reference to FIG. 1 is obtained. The organic thin film transistor Tr is structurally stable because the interface between the semiconductor layer 15 and the gate insulating film 17 is kept flat and there is no space.

  In addition, the 3rd example demonstrated above can also be combined with the manufacturing method of the 2nd example demonstrated using FIG. In this case, a soluble sacrificial layer pattern may be formed instead of the adhesive layer pattern 27a described in the third example. In the step described in FIG. 5 (4), the transfer sacrificial layer pattern is dissolved. 25 may be removed.

<< Semiconductor Device Manufacturing Method-4 >>
Next, an embodiment (fourth example) of the semiconductor device manufacturing method described above will be described in detail based on the sectional process diagrams of FIGS. In addition, the same code | symbol is attached | subjected to the component similar to a 1st example, and a part of overlapping description is abbreviate | omitted. The fourth example is characterized in that the gate electrode is formed in a separate step in the manufacturing method of the first example described with reference to FIG. 3 and is performed as follows.

  First, the same procedure as described with reference to FIGS. 2 (1) to 2 (4) in the first example is performed, and the source electrode is formed on the surface side of the substrate 11 whose upper surface is covered with the insulating film 11b. 13s and the drain electrode 13d are embedded. The surface of the substrate 11 and the surfaces of the source electrode 13s and the drain electrode 13d constitute the same surface.

  On the other hand, as shown in FIG. 6A, another transfer substrate 25 is prepared, and an adhesive layer 27 is formed on the transfer substrate 25. The transfer substrate 25 and the adhesive layer 27 are the same as in the first example. That is, a plastic substrate, a glass substrate, a silicon substrate, a quartz substrate, or the like can be used as the transfer substrate 25, but it is preferable to use a flexible plastic substrate in consideration of pasting and peeling in a later process. In addition, the adhesive layer 27 is made of a fine adhesive material such as PDMS, polyolefin, or PFPE.

  On the adhesive layer 27, the gate insulating film layer 17a and the semiconductor layer 15a are sequentially stacked from the lower layer side. Here, no gate electrode layer is formed. The gate insulating film layer 17a and the semiconductor layer 15a are the same as in the first example. As the gate insulating film layer 17a, an organic material film is formed by a coating film forming method, and then, as the semiconductor layer 15a, a vacuum evaporation method, An organic semiconductor material film such as pentacene is formed by a PVD method or a coating film forming method.

  Next, as shown in FIG. 6B, the substrate 11 described above and the transfer substrate 25 on which the gate insulating film 17a and the semiconductor layer 15a are formed are disposed to face each other. At this time, the exposed surfaces of the source electrode 13 s and the drain electrode 13 d on the substrate 11 and the semiconductor layer 15 a on the transfer substrate 25 are arranged facing each other. In this state, the substrate 11 and the transfer substrate 25 are bonded together. At this time, it is important that the substrate 11 and the semiconductor layer 15a of the transfer substrate 25 are sufficiently brought into close contact with each other using a vacuum vise or the like.

  Thereafter, as shown in FIG. 6 (3), the transfer substrate 25 carrying the adhesive layer 27 is peeled and removed from the substrate 11 side, and from the lower layer to the substrate 11 side on which the source electrode 13s and the drain electrode 13d are formed. The laminated film of the semiconductor layer 15a and the gate insulating film layer 17a is transferred in order.

  Next, as shown in FIG. 6 (4), the gate electrode 19 is patterned on the gate insulating film layer 17 a provided on the outermost surface of the substrate 11. Here, first, a gate electrode layer made of, for example, gold (Au), copper (Cu), silver (Ag), or the like is added to the gate insulating film layer 17a, and a vacuum deposition method, a sputtering method, or even conductive fine particles are contained. A film is formed by a coating method using the conductive ink. Thereafter, a resist pattern (not shown) is formed with high accuracy on the gate electrode layer 19a by lithography, and the gate electrode layer is etched using this resist pattern as a mask, thereby patterning the gate electrode 19. The gate electrode 19 is patterned so as to be disposed at least between the source electrode 13s and the drain electrode 13d. Note that after the gate electrode 19 is formed, the resist pattern is removed by chemical treatment.

  Next, as shown in FIG. 6 (5), the gate insulating film layer 17a and the semiconductor layer 15a are etched using the gate electrode 19 as a mask. Here, for example, oxygen plasma etching is performed. As described above, the semiconductor layer 15 provided in contact with the source electrode 13 s and the drain electrode 13 d and the substrate 11 therebetween, the gate insulating film 17 provided on the semiconductor layer 15, and the gate electrode 19 are stacked. A body is patterned on the substrate 11. Then, the bottom contact / top gate type organic thin film transistor Tr described with reference to FIG. 1 is obtained. The organic thin film transistor Tr is structurally stable because the interface between the semiconductor layer 15 and the gate insulating film 17 is kept flat and there is no space.

  In addition, the 4th example demonstrated above can also be combined with the manufacturing method of the 2nd example demonstrated using FIG. In this case, a soluble sacrificial layer may be formed instead of the adhesive layer 27 described in the fourth example, and in the step described with reference to FIG. 6 (3), the transfer substrate 25 is removed by dissolving the soluble sacrificial layer. Just do it.

  Further, the fourth example can be combined with the manufacturing method of the third example described with reference to FIG. In this case, in the step described with reference to FIG. 5B in the third example, only the gate insulating film 17a and the semiconductor layer 15a are formed on the transfer substrate 25 on which the adhesive layer pattern 27a is formed. Then, after the step described with reference to FIG. 5 (4) in the third example, a step of forming a gate electrode may be performed.

  In the first to fourth examples described above, the substrate 11 is configured such that the surface side of the support substrate 11a is covered with an insulating film 11b made of an organic material. However, the substrate 11 may be made of a single structure as long as the source electrode 13s and the drain electrode 13d are embedded on the surface side while maintaining insulation, and is composed of only an insulating film, for example. May be. In this case, the insulating film 11b is formed to have a certain thickness in the step shown in FIG. 2 (2), and the transfer substrate 21 is removed from the insulating film 11b without performing the step shown in FIG. 2 (3). Just peel off. Thereby, the source electrode 13 and the drain electrode 13d can be embedded in the surface side of the substrate 11 made of a single structure of the insulating film 11b.

<< Semiconductor Device-2 >>
The semiconductor device 3 shown in FIG. 7 has a configuration in which a plurality of organic thin film transistors Tr and other elements are stacked on the substrate 11 in the semiconductor device including the organic thin film transistor Tr having the bottom contact / top gate structure described in FIG. It is sectional drawing for demonstrating.

  The semiconductor device 3 shown in this figure is provided with an insulating protective film 31 so as to cover the organic thin film transistor Tr having the bottom contact / top gate structure described in FIG. The protective film 31 is made of a material that is low in damage to the organic semiconductor material that forms the semiconductor layer 15 and the gate insulating film 17. Specifically, it is made of a water-soluble resin (for example, polyvinyl alcohol resin), a fluorine-based resin, or a polyparaxylylene derivative. Such a protective film 31 is preferably configured to completely cover the exposed side walls of the semiconductor layer 15 and the gate insulating film 17 made of an organic material.

  The protective film 31 is provided with a connection hole 31 a reaching the gate electrode 19. In addition, the water-soluble resin and the fluorine-based resin constituting the protective film 31 have low damage to the organic semiconductor material, but have low adhesion to other layers. Therefore, the protective film 31 is patterned in a minimum shape that covers the exposed side wall of the stacked body of the semiconductor layer 15, the gate insulating film 17, and the gate electrode 19 that is patterned on the substrate 11. Is preferred.

  An interlayer insulating film 33 is provided so as to cover the substrate 11 on which such a protective film 21 is formed. With this interlayer insulating film 33, the protective film 31 with low adhesion is capped and fixed. Such an interlayer insulating film 33 is made of, for example, an organic material. The interlayer insulating film 33 is provided with a connection hole 33 a reaching the gate electrode 19 in the connection hole 31 a of the protective film 31.

  On the interlayer insulating film 33, a conductive pattern 35 connected to the gate electrode 19 through a connection hole 33a is provided as a gate wiring.

  With the configuration as described above, the stacked body from the semiconductor layer 15 to the gate electrode 19 patterned on the substrate 11 in the organic thin film transistor Tr is fixed to the substrate 11 side by the protective film 31 and the interlayer insulating film 33, It becomes possible to ensure the stability of. Further, the semiconductor layer 15 and the gate are formed by the protective film 31 made of a water-soluble resin (for example, polyvinyl alcohol resin) or a fluorine-based resin that is low in damage to the organic semiconductor material constituting the semiconductor layer 15 or the gate insulating film 17. The exposed surface of the insulating film 17 is covered. For this reason, it is possible to protect the semiconductor layer 15 and the gate insulating film 17 against the upper interlayer insulating film 33, the conductive pattern, and the like, and the deterioration of the transistor characteristics is prevented.

<< Method for Manufacturing Semiconductor Device-2 >>
Next, an embodiment of the method for manufacturing the semiconductor device 3 described above will be described in detail based on the sectional process diagram of FIG.

  First, the bottom contact / top gate type in which the source electrode 13s and the drain electrode 13d are embedded on the surface side of the substrate 11 by any one of the first to fourth examples described with reference to FIGS. An organic thin film transistor Tr is formed.

  Then, as shown in FIG. 8A, a protective film 31 made of, for example, a fluororesin is applied and formed on the entire surface of the substrate 11 so as to cover the organic thin film transistor Tr. Thereafter, the surface of the protective film 31 made of a fluororesin is subjected to an ashing process to improve the wettability of the surface. Thereafter, a resist pattern (not shown) is formed on the protective film 31 made of a fluororesin by lithography, and the protective film 31 is etched with oxygen plasma using this resist pattern as a mask. Thus, the connection hole 31a reaching the gate electrode 19 is formed in the protective film 31, and the protective film 31 is formed in a minimum shape covering the exposed surface of the stacked body of the semiconductor layer 15, the gate insulating film 17, and the gate electrode 19. Pattern. After the patterning is completed, the resist pattern is removed.

  Next, as shown in FIG. 8B, an interlayer insulating film 33 made of, for example, a photoresist is applied and formed on the entire surface of the substrate 11. Thereafter, a connection hole 33a reaching the gate electrode 19 is formed in the interlayer insulating film 33 made of a photoresist by lithography.

  After the above, as shown in FIG. 7, a conductive pattern 35 connected to the gate electrode 19 through the connection hole 33a is formed on the interlayer insulating film 33 as a gate wiring. On the interlayer insulating film 33, a conductive pattern 35 other than the gate wiring is also wired if necessary. If further upper layer wiring is required, the formation of the interlayer insulating film and the formation of the conductive pattern may be repeated, thereby completing the semiconductor device 3.

  According to the above manufacturing method, by providing the protective film 31 that covers the exposed surface of the stacked body of the semiconductor layer 15, the gate insulating film 17, and the gate electrode 19, the semiconductor layer 15 made of an organic material is further formed in the upper layer formation. In addition, damage to the gate insulating film 17 can be prevented. Thereby, it is possible to perform integration while ensuring transistor characteristics in the organic thin film transistor Tr.

≪Electronic equipment≫
FIG. 9 is a cross-sectional view of one pixel of an active matrix display device using an organic electroluminescence element EL as an example of an electronic device including the organic thin film transistor Tr having the bottom contact / top gate structure described in FIG. Indicates.

  The display device 5 shown in this figure is a display device provided with an organic electroluminescent element EL, and is configured as follows.

  That is, the organic thin film transistor Tr in which the source electrode 13s and the drain electrode 13d are embedded on the surface side of the substrate 11 is covered with the protective film 31 and the interlayer insulating film 33 as described with reference to FIG. The conductive pattern 25 is provided as the wiring. Such a substrate 11 is covered with, for example, a planarization insulating film 51 as a second interlayer insulating film. A connection hole 51a reaching the drain electrode 13a of the organic thin film transistor Tr is provided in the interlayer insulating film in which the planarizing insulating film 51 and the interlayer insulating film 33 are stacked.

  Each pixel on the planarization insulating film 51 is provided with an organic electroluminescence element EL connected to the organic thin film transistor Tr through the connection hole 51a. The organic electroluminescent element EL is separated by an insulating pattern 53 provided on the interlayer insulating film 51.

  The organic electroluminescent element EL includes a pixel electrode 55 having a conductive pattern connected to the drain electrode 13d of the organic thin film transistor Tr through a connection hole 51a provided in the interlayer insulating film 51. The pixel electrode 55 is patterned for each pixel, and is used as an anode, for example, and is configured to have light reflectivity.

  The peripheral edge of the pixel electrode 55 is covered with an insulating pattern 53 for separating the organic electroluminescent element EL. The insulating pattern 53 includes an opening window 53a that exposes the pixel electrode 55 widely, and the opening window 53a is a pixel opening of the organic electroluminescent element EL. Such an insulating pattern 53 is configured by using, for example, a photosensitive resin, and is patterned by applying a lithography method.

  An organic layer 57 is provided so as to cover the pixel electrode 55 exposed from the insulating pattern 53. The organic layer 57 has a laminated structure including at least an organic light emitting layer, and if necessary, in order from the anode (here, the pixel electrode 55) side, a hole injection layer, a hole transport layer, an organic light emitting layer, and an electron transport. A layer, an electron injection layer, and other layers are laminated. In addition, for example, the organic layer 57 is formed in a pattern in which a layer including at least the organic light emitting layer is different for each pixel for each wavelength of emitted light generated by each organic electroluminescent element EL. In addition, the pixels of each wavelength may have a common layer. Furthermore, when this organic electroluminescent element EL is comprised as a microresonator structure, the film thickness of the organic layer 57 shall be adjusted according to the wavelength taken out from each organic electroluminescent element EL.

  A common electrode 59 is provided so as to cover the organic layer 57 as described above and sandwich the organic layer 57 between the pixel electrode 55. The common electrode 59 is an electrode on the side from which the light h generated in the organic light emitting layer of the organic electroluminescent element EL is extracted, and is made of a material having optical transparency. Further, here, since the pixel electrode 55 functions as an anode, the common electrode 59 is configured using a material that functions as a cathode at least on the side in contact with the organic layer 57. Furthermore, when this organic electroluminescent element EL is comprised as a microresonator structure, this common electrode 59 shall be the structure which has transflective property.

  Each pixel portion in which the organic layer 57 is sandwiched between the pixel electrode 55 and the common electrode 59 as described above serves as a portion that functions as the organic electroluminescent element EL.

  Although not shown here, the formation surface side of each organic electroluminescent element EL is covered with a sealing resin made of a light-transmitting material, and is further opposed to the light-transmitting material through this sealing resin. The display device 5 is configured with the substrates attached to each other.

  Here, in the display device 5, the organic thin film transistor Tr having the above-described configuration and the organic electroluminescent element EL connected thereto are arranged in each pixel on the surface side of the substrate 11, and the overall circuit configuration is as follows. For example, it is configured as shown in the circuit configuration diagram of FIG.

  As shown in this figure, a display area 11 a and a peripheral area 11 b are set on the substrate 11 of the display device 5. In the display area 11a, a plurality of scanning lines 61 and a plurality of signal lines 63 are wired vertically and horizontally, and configured as a pixel array section in which one pixel a is provided corresponding to each intersection. . Further, a scanning line driving circuit 65 that scans and drives the scanning lines 61 and a signal line driving circuit 67 that supplies a video signal (that is, an input signal) corresponding to luminance information to the signal lines 63 are arranged in the peripheral region 11b. Yes.

  A pixel circuit provided at each intersection of the scanning line 61 and the signal line 63 is configured by, for example, a switching thin film transistor Tr1, a driving thin film transistor Tr2, a storage capacitor Cs, and an organic electroluminescence element EL. The video signal written from the signal line 63 via the switching thin film transistor Tr1 is held in the holding capacitor Cs by driving by the scanning line driving circuit 65, and a current corresponding to the held signal amount is supplied to the driving thin film transistor. The organic electroluminescence device EL is supplied from the Tr2 to the organic electroluminescence device EL, and the organic electroluminescence device EL emits light with luminance according to the current value. The driving thin film transistor Tr2 and the storage capacitor Cs are connected to a common power supply line (Vcc) 69.

  The cross-sectional view of FIG. 9 shows a cross section of a portion where the thin film transistor Tr2 and the organic electroluminescent element EL are stacked in the pixel circuit as described above. The thin film transistor Tr1 shown in the pixel circuit is configured using the same layer as the thin film transistor Tr2. The capacitive element Cs shown in the pixel circuit is formed by stacking the gate electrode-gate insulating film-drain electrode layer portions of the thin film transistor Tr2. Further, the scanning line 61 shown in the pixel circuit is configured by the conductive pattern 25 in the sectional view, and the signal line 63 and the power supply line 69 shown in the pixel circuit are the same as the source electrode 13s and the drain electrode 13d in the sectional view. Constructed with one layer.

  Note that the configuration of the pixel circuit as described above is merely an example, and a capacitor element may be provided in the pixel circuit as necessary, or a plurality of transistors may be provided to configure the pixel circuit. Further, a necessary drive circuit is added to the peripheral region 11b according to the change of the pixel circuit.

  According to the display device 5 configured as described above, since the pixel circuit is configured using the organic thin film transistor Tr having good transistor characteristics as described with reference to FIG. 1, the display characteristics can be improved. It becomes possible. For this reason, for example, a flexible flat panel display (electronic device) using the organic thin film transistor Tr can be realized.

  In the above-described embodiment, an active matrix display device using the organic electroluminescence element EL is illustrated as an example of an electronic apparatus including the organic thin film transistor Tr having the bottom contact / top gate structure described in FIG. . However, the electronic device of the present invention can be widely applied to electronic devices including a thin film transistor. For example, a display device can be applied to a flexible display such as a liquid crystal display device. In addition to the display device, the present invention can be applied to electronic devices such as ID tags and sensors, and similar effects can be obtained.

It is sectional drawing of the semiconductor device of 1st Embodiment. FIG. 4 is a cross-sectional process diagram illustrating a method of manufacturing the semiconductor device illustrated in FIG. 1. FIG. 7 is a cross-sectional process diagram illustrating a first example of a method of manufacturing the semiconductor device illustrated in FIG. 1. FIG. 8 is a cross-sectional process diagram illustrating a second example of the method for manufacturing the semiconductor device illustrated in FIG. 1. FIG. 8 is a cross-sectional process diagram illustrating a third example of the method for manufacturing the semiconductor device illustrated in FIG. 1. FIG. 7 is a cross-sectional process diagram illustrating a fourth example of the method for manufacturing the semiconductor device illustrated in FIG. 1. It is sectional drawing of the semiconductor device of 2nd Embodiment. FIG. 3 is a cross-sectional process diagram illustrating a method for manufacturing the semiconductor device illustrated in FIG. 2. It is sectional drawing which shows an example of a display apparatus as an electronic device of embodiment. It is a circuit block diagram of the display apparatus of FIG. It is sectional drawing of the conventional semiconductor device. It is sectional drawing of the semiconductor device as another conventional example.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1,3 ... Semiconductor device), 5 ... Display apparatus (electronic device), 11 ... Substrate, 11a ... Supporting substrate, 11b ... Insulating film, 13s ... Source electrode, 13d ... Drain electrode, 15 ... Semiconductor layer, 17 ... Gate insulation Film 19, gate electrode 21, 25, transfer substrate 25, conductive pattern (gate wiring) 31 protective film 31 a connection hole 51 flattening insulating film (interlayer insulating film) 55 pixel electrode (Conductive pattern)

Claims (13)

A source electrode and a drain electrode embedded on the surface side of the substrate;
A semiconductor layer provided on the substrate in contact with the source and drain electrodes and the substrate between them; and
A gate insulating film provided on the semiconductor layer;
A semiconductor device comprising: a gate electrode provided on the semiconductor layer between the source electrode and the drain electrode via the gate insulating film. The surfaces of the source electrode and the drain electrode are arranged at a height constituting the same plane as the surface of the substrate,
The semiconductor device according to claim 1, wherein an interface between the semiconductor layer and the gate insulating film forms a plane. The substrate is composed of a support substrate and an insulating film covering the surface of the support substrate,
The semiconductor device according to claim 1, wherein the source electrode and the drain electrode are embedded in the insulating film. The semiconductor device according to claim 1, wherein the semiconductor layer is made of an organic material. The semiconductor layer, the gate insulating film, and the gate electrode constitute a stacked body patterned on the substrate,
An insulating protective film provided on the substrate in a state of covering the stacked body with a connection hole reaching the gate electrode;
The semiconductor device according to claim 1, further comprising: a conductive pattern provided on the protective film in a state of being connected to the gate electrode through the connection hole. A first step of patterning a source electrode and a drain electrode on a transfer substrate;
A second step of forming a flat surface insulating film on the transfer substrate in a state where the source electrode and the drain electrode are embedded;
A third step of removing the transfer substrate from the insulating film side so that the source electrode and the drain electrode are embedded on the surface side of the substrate formed using the insulating film;
A stacked body in which a semiconductor layer, a gate insulating film, and a gate electrode are provided in this order is formed over the substrate in a state where the semiconductor layer is in contact with the substrate between the source electrode and the drain electrode and these electrodes. A manufacturing method of a semiconductor device which performs four steps. In the second step, the substrate including the support substrate and the insulating film is formed by bonding the insulating film to the support substrate;
7. In the third step, the transfer substrate is removed from the substrate side so that the source electrode and the drain electrode are embedded on the surface side of the insulating film bonded onto the support substrate. The manufacturing method of the semiconductor device of description. In the fourth step, a transfer substrate on which a gate electrode, a gate insulating film, and a semiconductor layer are stacked in this order is prepared, and the surface side of the substrate in which the source electrode and the drain electrode are embedded from the transfer substrate side The method for manufacturing a semiconductor device according to claim 6, wherein the semiconductor layer, the gate insulating film, and the gate electrode are transferred. 9. The semiconductor device according to claim 8, wherein, in the fourth step, the gate electrode, the gate insulating film, and the semiconductor layer that are stacked in a patterned state on the transfer substrate side are transferred to the surface side of the substrate. Manufacturing method. In the fourth step, a transfer substrate in which a gate insulating film and a semiconductor layer are stacked in this order is prepared, and the transfer electrode side is provided with the source electrode and the drain electrode on the surface side of the substrate. The method for manufacturing a semiconductor device according to claim 6, wherein the semiconductor layer and the gate insulating film are transferred, and then the gate electrode is formed on the gate insulating film. 11. The method of manufacturing a semiconductor device according to claim 10, wherein in the fourth step, the gate insulating film and the semiconductor layer that are stacked in a patterned state on the transfer substrate side are transferred to the surface side of the substrate. A source electrode and a drain electrode embedded on the surface side of the substrate;
A semiconductor layer provided on the substrate in contact with the source and drain electrodes and the substrate between them; and
A gate insulating film provided on the semiconductor layer;
A gate electrode provided on the semiconductor layer between the source electrode and the drain electrode via the gate insulating film;
An interlayer insulating film covering the substrate on which the gate electrode is provided;
An electronic apparatus comprising a conductive pattern connected to the source electrode or the drain electrode through a connection hole provided in the interlayer insulating film. The electronic device according to claim 12, wherein the conductive pattern is configured as a pixel electrode.

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