JP2010056154A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device which uses a semiconductor substrate of parallel pn structure, having a high breakdown strength and lower loss, while suppressing an increase in the number of manufacturing processes and the manufacturing cost. <P>SOLUTION: The semiconductor device includes a parallel pn layer where an n-type drift region 2 and a p-type partition region 3 are alternately arranged. A non-active region is divided into a second non-active region 17a of unbalanced charge and a first non-active region 17b of balanced charge. In the second non-active region 17a, the width of the n-type drift region 2 is made narrower than that of the p-type partition region 3, and the overall impurity concentration of the p-type partition region 3 is made higher than that of the n-type drift region 2. Since the breakdown strength of a semiconductor substrate in the non-active region 17 increases, the breakdown strength of the semiconductor substrate in the non-active region 17 becomes higher than that of the semiconductor substrate in an active region 18, resulting in an improved overall breakdown strength of the semiconductor substrate. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a vertical semiconductor device for high power, and more particularly to a semiconductor device having a superjunction layer on a part of a semiconductor substrate.

  2. Description of the Related Art Conventionally, in order to reduce the size and performance of power supply equipment in the power electronics field, power semiconductor devices are required to have high breakdown voltage and large current, as well as low loss, high breakdown resistance, and high speed. For this reason, a superjunction substrate has been proposed as the substrate structure of the semiconductor device, and a vertical MOS power device structure has been proposed as the surface structure.

  A superjunction substrate is a first conductivity type semiconductor substrate and a second conductivity type semiconductor layer, and the first conductivity type and second conductivity type semiconductor regions alternate in a direction perpendicular to the semiconductor substrate. (See, for example, Patent Document 1 and Patent Document 2 below). In this superjunction substrate, by forming the superjunction layer, even when the concentrations of the first conductivity type and second conductivity type semiconductor regions are high, the space charge region can be spread over the entire superjunction layer when turned off. it can. Therefore, particularly in a high breakdown voltage semiconductor device, the on-resistance can be made smaller than when a semiconductor substrate having a single conductivity type is used.

Note that in this specification, a semiconductor having n or p means that electrons and holes are majority carriers, respectively. Further, “ ⁺ ” or “ ⁻ ” attached to n or p, such as n ⁺ or n ^−, is relatively higher or lower than the impurity concentration of the semiconductor to which they are not attached. Represents that.

An example of such a vertical MOS device will be described. FIG. 71 is a cross-sectional view showing the configuration of the first conventional superjunction MOS device. FIG. 72 is a plan view showing a superjunction layer of the superjunction MOS device shown in FIG. FIG. 73 is a plan view showing equipotential line distribution generated in the superjunction layer when a voltage is applied to the superjunction MOS device shown in FIG. The equipotential line distribution shown in FIG. 73 is a rough distribution of the equipotential line distribution obtained by the two-dimensional simulation of the cross-sectional view in the width direction and the cross-sectional view in the depth direction of the semiconductor substrate (hereinafter referred to as other figures etc.). The same applies to the diagrams showing the distribution of potential lines). As shown in FIG. 71, an n-type drift region (first conductivity type semiconductor region) 2 and a p-type partition region (second conductivity) are formed on the first main surface of an n ⁺ substrate 1 having a low resistivity which is an n ⁺ drain region. A parallel pn layer (superjunction layer) composed of a type semiconductor region 3 is provided. The joint surface is perpendicular to the first main surface of the n ⁺ substrate 1. On the surface of the parallel pn layer, there are an active region 18 through which a current flows when the semiconductor device is in an on state, and an inactive region 17 (also referred to as a high withstand voltage junction termination structure) for relaxing the electric field strength on the junction surface. 18 is provided outside. The width W _n1 of the n-type drift region 2 and the width W _p1 of the p-type partition region 3 are equal (W _n1 = W _p1 ), and the impurity concentration of the n-type drift region 2 and the impurity concentration of the p-type partition region 3 are equal. . In this manner, a semiconductor substrate (superjunction substrate) having a parallel pn structure including the parallel pn layers in which the n-type drift regions 2 and the p-type partition regions 3 are alternately arranged and the n ⁺ substrate 1 is formed. Has been.

A planar type MOS structure is formed on the first main surface of the parallel pn structure semiconductor substrate. In the active region 18, the p base region 9 is provided in the surface layer of the p-type partition region 3. The p base region 9 protrudes from the n type drift region 2 at the junction between the n type drift region 2 and the p type partition region 3. In the p base region 9, two n ⁺ source regions 11 are provided apart from each other. In the p base region 9, p ⁺ contact regions 10 are provided so as to be in contact with the respective n ⁺ source regions 11. The p ⁺ contact region 10 occupies a part of the lower side of each n ⁺ source region 11.

In addition, the gate electrode 4 is provided on the n-type drift region 2 and the p base region 9 between the n-type drift region 2 and the n ⁺ source region 11 via the gate insulating film 13. . A portion of the surface of the n-type drift region 2 other than the p base region 9 is in contact with the gate insulating film 13. Source electrode 15 is insulated from gate insulating film 13 and is in contact with p ⁺ contact region 10 and n ⁺ source region 11. Therefore, the source electrode 15 is electrically connected to the p-type partition region 3.

In the inactive region 17, an interlayer insulating film 12 is formed on the first main surface of the semiconductor substrate having a parallel pn structure excluding the vicinity of the boundary with the active region 18 and the substrate termination portion. Here, the substrate termination portion refers to an end portion (hereinafter referred to as an X substrate termination portion) on the side where the inactive region 17 is formed on the first main surface of the semiconductor substrate having a parallel pn structure. The interlayer insulating film 12 is in contact with the source electrode 15. An n ⁺ stopper region 5 is provided in the surface layer of the p-type partition region 3 at the substrate termination portion. A stopper electrode 6 is formed on the surface of the n ⁺ stopper region 5. The stopper electrode 6 extends to a part of the surface of the interlayer insulating film 12 and is formed so as to cover the interlayer insulating film 12. The drain electrode 16 is formed on the second main surface of the semiconductor substrate having a parallel pn structure, that is, the surface of the second main surface of the n ⁺ substrate 1.

A p-type semiconductor region 7 is provided on the surface layer of the p-type partition region 3 in the vicinity of the boundary between the non-active region 17 and the active region 18. The p-type semiconductor region 7 protrudes from the n-type drift region 2 at the junction between the n-type drift region 2 and the p-type partition region 3. A p ⁺ high concentration semiconductor region 8 is provided in the p-type semiconductor region 7. The p ⁺ high concentration semiconductor region 8 is in contact with the source electrode 15. A field plate electrode 14 is formed on the surface of the interlayer insulating film 12. The field plate electrode 14 is formed from the inactive region 17 to the active region 18, covers a part of the surface of the source electrode 15, and is short-circuited to the same potential as the source electrode 15.

Further, as shown in FIG. 72, the planar structure of the semiconductor substrate having the parallel pn structure is such that the n-type drift region 2 and the p-type partitioning region 3 are connected to each other at the junction surface thereof in the depth direction Y ( Hereinafter, it is provided in stripes parallel to the Y depth direction. A non-active region 17 is provided so as to surround the active region 18 in the Y depth direction. Further, the outermost periphery (hereinafter referred to as the X source outermost periphery) of the active region 18 in the width direction X (hereinafter referred to as the X width direction) of the semiconductor substrate has a linear shape parallel to the Y depth direction. On the other hand, the outermost periphery (hereinafter referred to as the Y source outermost periphery) of the active region 18 in the Y depth direction has a linear shape parallel to the X width direction. Then, the outermost periphery of the X source and the outermost periphery of the Y source are connected by an arc having a radius R _X1 (= R _Y1 ) and a curvature having a central angle of 90 degrees (hereinafter referred to as an R source outermost periphery). An active region 18 having a corner portion is formed.

Such a vertical MOS device having a parallel pn structure has a charge balance between the impurity concentration of the n-type drift region 2 and the impurity concentration of the p-type partition region 3 when looking only at the active region 18. In addition, the maximum breakdown voltage of the semiconductor substrate can be obtained. However, when viewed from the entire semiconductor substrate, the charge balance between the impurity concentration of the n-type drift region 2 and the impurity concentration of the p-type partition region 3 is lost. When a withstand voltage is applied to the semiconductor substrate, as shown in FIG. 73, in the inactive region 17 (hereinafter referred to as the first region A) near the outermost periphery of the Y source, the electric field concentrated on the surface of the semiconductor substrate, etc. The interval between the potential lines becomes wider (hereinafter referred to as sparse equipotential line distribution). On the other hand, in the inactive region 17 (hereinafter referred to as the second region B) in the vicinity of the outermost periphery of the X source, the interval between the equipotential lines of the electric field concentrated on the surface of the semiconductor substrate is narrowed (hereinafter referred to as the dense equipotential lines). Distribution). The reason is that a parallel pn layer is formed on the semiconductor substrate, and in the inactive region 17, the depletion layer near the surface of the semiconductor substrate is a substrate termination portion in the Y depth direction (hereinafter referred to as a Y substrate termination portion). It is because it spreads toward. Therefore, in the region of the inactive region 17 in the vicinity of the outermost periphery of the R source (hereinafter referred to as the third region C), the closer to the first region A, the sparse equipotential line distribution becomes. The closer it is, the denser the equipotential distribution. As a result, the breakdown voltage of the semiconductor substrate in the inactive region 17 is lower than the breakdown voltage of the semiconductor substrate in the active region 18. That is, the withstand voltage of the inactive region 17 is a factor that determines the overall withstand voltage, so that the withstand voltage of the entire semiconductor substrate is lowered. At this time, when the ratio η≡BV _e / BV of the inactive region withstand voltage BV _{e to} the active region withstand voltage BV is set, η = 0.83 to 0.85 in the semiconductor device of the first conventional example.

  As a method for solving such a problem, the following method has been proposed. FIG. 74 is a plan view showing a configuration of a superjunction MOS device of the second conventional example. In the second conventional superjunction type MOS device, as shown in FIG. 74, in the configuration of the first conventional superjunction type MOS device, the impurity concentration of the n-type drift region 2 in the inactive region 17 is set to the active region. The impurity concentration of the 18 n-type drift region 2 is lower. Similarly, the impurity concentration of the p-type partition region 3 in the non-active region 17 is also lower than the impurity concentration of the p-type partition region 3 in the active region 18 (see, for example, Patent Document 3 below). By the technique of Patent Document 3, in the non-active region 17, not only in the vicinity of the outermost periphery of the active region 18, but also from the outermost periphery of the active region 18 toward the X width direction and the Y depth direction, the first main surface of the semiconductor substrate The depletion layer expands from the second main surface direction. Therefore, the breakdown voltage of the semiconductor substrate in the inactive region 17 can be made higher than the breakdown voltage of the semiconductor substrate in the active region 18 without providing a guard ring or a field plate electrode 14 for relaxing the electric field.

  However, in the above-mentioned Patent Document 3, a multi-stage epitaxial method in which an epitaxial layer is formed by stacking multiple epitaxial layers is used for manufacturing a semiconductor substrate, which increases the manufacturing process and manufacturing cost. Therefore, it is preferable to employ a method of forming a trench in a semiconductor substrate and embedding the trench with an epitaxial layer (hereinafter referred to as a trench embedding method). When the trench embedding method is employed, in order to partially form regions with a low impurity concentration in the n-type drift region 2 and the p-type partition region 3, the impurity concentration is again added to the already formed parallel pn layer. Different parallel pn layers need to be formed again, which complicates the manufacturing process and makes it difficult to manufacture.

Therefore, in the technique of Patent Document 3, the following method is also proposed. FIG. 75 is a cross-sectional view showing the configuration of the superconducting MOS device of the third conventional example. FIG. 76 is a plan view showing a superjunction layer of the superjunction MOS device shown in FIG. 77 is a plan view showing equipotential line distribution generated in the superjunction layer when a voltage is applied to the superjunction MOS device shown in FIG. In the superjunction MOS device of the third conventional example, as shown in FIG. 75, in the configuration of the superjunction MOS device of the first conventional example, the width W _n2 of the n-type drift region 2 of the inactive region 17 is set to be active. It is narrower than the width W _n1 of the n-type drift region 2 in the region 18 (W _n2 <W _n1 ). Similarly, the width W _p2 of the p-type partition region 3 in the non-active region 17 is also narrower than the width W _p1 of the p-type partition region 3 in the active region 18 (W _p2 <W _p1 ). At this time, the width of each of the n-type drift region 2 and the p-type partition region 3 (hereinafter referred to as each width of the parallel pn layer) of the inactive region 17 (hereinafter referred to as the first inactive region 17b) is as follows. _Are equal (W _n2 = W _p2 ). Further, as shown in FIG. 76, each width of the parallel pn layer of the non-active region 17 (hereinafter referred to as the second non-active region 17a) on the parallel pn layer where the active region 18 is formed is defined as active width This is the same as the region 18.

  By the technique shown in the third conventional example, the depletion layer spreads in the inactive region 17 as in the second conventional example. Therefore, in the second region B, which has a dense equipotential line distribution in FIG. 73, a sparse equipotential line distribution can be obtained as shown in FIG. Thereby, the problem of the first conventional example is solved. Further, since the semiconductor substrate can be manufactured by a single trench embedding method, the problem of the second conventional example is also solved. However, in the above-described technique, as shown in FIG. 77, in the third region C, the closer to the outermost periphery of the R source, the easier the electric field concentrates on the surface of the semiconductor substrate, resulting in a dense equipotential line distribution. .

As a method for solving such a problem, the following method has been proposed. FIG. 78 is a cross-sectional view showing the configuration of the superjunction MOS device of the fourth conventional example. FIG. 79 is a plan view showing the superjunction layer of the superjunction MOS device shown in FIG. In the superjunction MOS device of the fourth conventional example, as shown in FIGS. 78 and 79, in the configuration of the superjunction MOS device of the third conventional example, the p-type partition region 3 of the first inactive region 17b The width W _p2 is made wider than the width W _p1 of the p-type partition region 3 of the active region 18 (W _p2 > W _p1 ). In the first inactive region 17b, the total impurity concentration of the p-type partition region 3 is made larger than the total impurity concentration of the n-type drift region 2 (see, for example, Patent Document 4 below). Thereby, in FIG. 77, the electric field in the third region C, which has a dense equipotential line distribution as it approaches the outermost periphery of the R source, can be alleviated, so the problem of the third conventional example is solved.

  As another method for relaxing the electric field concentrated on the surface of the semiconductor substrate, a p-type base layer, an n-type source layer selectively formed on the surface of the p-type base layer, and a p-type active layer An n-type drain layer selectively formed away from the p-type base layer on the surface of the substrate and a p-type base layer in a region sandwiched between the n-type source layer and the p-type active layer via a gate insulating film An n-type semiconductor layer on the surface of the p-type active layer in a region sandwiched between the p-type base layer and the n-type drain layer, from the p-type base layer toward the n-type drain layer. And the p-type semiconductor layer are formed, and these semiconductor layers are alternately and repeatedly arranged, and the n-type semiconductor layer on the n-type drain layer side is a power semiconductor device having a larger dose than the p-type semiconductor layer. (For example, refer to Patent Document 5 below.)

As another method, the following method has been proposed. A P base layer is selectively formed on the surface of the semiconductor substrate, and an N ⁺ source layer and a P ⁺ contact layer as a source of the power MOSFET are selectively formed on the surface of the P base layer in the source region. An N ⁺ contact layer is formed on the surface of the semiconductor substrate so as to be substantially parallel to the P base layer. Between the P base layer and the N ⁺ contact layer, a striped N resurf layer, a P resurf layer, an N resurf layer, and an N ⁻ resurf layer that maintain a withstand voltage in a direction connecting them are formed. Make up structure. The N RESURF layer and the P RESURF layer are alternately and alternately formed in the direction connecting the P base layer and the N ⁺ contact layer and in the substantially vertical direction (see, for example, Patent Document 6 below).

Further, the following method has been proposed as a method for further improving the breakdown voltage in the inactive region rather than the breakdown voltage in the active region. It is divided into an element region and a termination portion, and the depth of the first semiconductor pillar region and the second semiconductor pillar region adjacent to the high-resistance semiconductor layer is between the element central region and the termination portion of the element region, There is a super junction structure portion provided with a boundary region that gradually becomes shallower toward the end portion, and the boundary region is located closer to the end portion than the control electrode. A high-resistance semiconductor layer is provided on the semiconductor layer (n ⁺ drain layer) in the terminal portion, and a field insulating film is provided on the surface thereof. By providing the source electrode in contact with the field insulating film, it is possible to suppress a decrease in breakdown voltage at the terminal portion due to the field plate effect (see, for example, Patent Document 7 below).

  As another method, the following method has been proposed. An n-type semiconductor is epitaxially grown on the n-type low resistance substrate, and a trench is formed in the n-type semiconductor. A p-type semiconductor is epitaxially grown to fill the trench with the p-type semiconductor. After polishing and flattening the surfaces of the n-type region made of n-type semiconductor and the p-type region made of p-type semiconductor, boron is selectively ion-implanted into the p-type region of the region to be the inactive region. Heat treatment is performed in a non-oxidizing atmosphere to activate the implanted boron. Thermal oxidation is performed to form a field oxide film. An element structure on the front surface side of the MOSFET, a source electrode and a channel stopper electrode are formed, and a drain electrode is formed on the back surface of the substrate. The source electrode extends from the active region to the non-active region side and covers a part of the field oxide film in the non-active region as a field plate electrode (see, for example, Patent Document 8 below).

  As another method, the following method has been proposed. A first conductivity type semiconductor layer; a first conductivity type first semiconductor pillar region provided on a main surface of the semiconductor layer; and adjacent to the first semiconductor pillar region, the semiconductor layer A second semiconductor pillar region of a second conductivity type provided on the main surface, a first main electrode provided on the opposite side of the main surface of the semiconductor layer, and an upper surface of the second semiconductor pillar region A first conductivity type first semiconductor region provided on the first semiconductor region; a first conductivity type second semiconductor region selectively provided on a surface of the first semiconductor region; the first semiconductor region; A second main electrode provided on the second semiconductor region; and a first insulation provided on the first semiconductor pillar region, the first semiconductor region, and the second semiconductor region. A control electrode provided on the first insulating film, and a control electrode provided on the control electrode. A second insulating film; and a third insulating film provided on the main surface side of the semiconductor layer at a terminal portion adjacent to the element portion where the control electrode is provided, and the second insulating film The thickness of the insulating film is 1/3 or less of the thickness of the third insulating film (see, for example, Patent Document 9 below).

JP-A-9-266611 JP 2004-119611 A JP 2001-298190 A JP 2005-260199 A JP 2000-286417 A JP 2006-302961 A JP 2007-335844 A JP 2006-210861 A JP 2007-207784 A

  However, in the technique of Patent Document 4 described above, the widths of the parallel pn layers of the inactive region 17 are not changed in the Y depth direction. Therefore, when the charge balance between the total impurity concentration of the n-type drift region 2 and the total impurity concentration of the p-type partition region 3 in the inactive region 17 is extremely changed, the depletion layer moves toward the X substrate end portion in the X width direction. It spreads too far in parallel to the stopper region 5. As a result, the breakdown voltage of the entire semiconductor substrate is reduced.

  In the techniques of Patent Document 7 and Patent Document 8 described above, a high-concentration region is formed in the parallel pn layer under the field plate electrode 14 to improve the breakdown voltage of the entire semiconductor substrate. For this reason, additional processes such as a photolithography process and a thermal diffusion process are performed on the parallel pn layers, which increases the number of manufacturing processes for manufacturing a semiconductor substrate.

  An object of the present invention is to provide a semiconductor device using a semiconductor substrate having a parallel pn structure, which suppresses an increase in manufacturing process and manufacturing cost, and has a high withstand voltage and low loss, in order to eliminate the above-described problems caused by the prior art. And

  In order to solve the above-described problems and achieve the object, a semiconductor device according to a first aspect of the present invention includes a semiconductor substrate having a high impurity concentration, a first conductivity type semiconductor region provided on the surface of the semiconductor substrate, and a first semiconductor region. Parallel pn layers in which two conductivity type semiconductor regions are alternately arranged, a second conductivity type base region provided in a surface layer of the second conductivity type semiconductor region, and a first layer provided in a surface layer of the base region. A source region of one conductivity type, a gate electrode provided on the surface of the parallel pn layer via a gate insulating film, electrically connected to the source region and the base region, and separated from the gate electrode In the semiconductor device, the parallel pn layer is disposed in both an active region in which current flows when the parallel pn layer is in an on state and a non-active region around the active region. p The layer is formed on the first main surface of the semiconductor substrate so that the first conductive type semiconductor region and the second conductive type semiconductor region have a stripe shape, and the non-active region includes a first non-conductive region. An active region and a second non-active region exist, and at least a part of the active region is surrounded by the second non-active region, and the first non-active region includes the first conductive semiconductor region. The total impurity amount and the total impurity amount of the second conductivity type semiconductor region are substantially equal, and in the second inactive region, the width of the second conductivity type semiconductor region is at least part of the parallel pn layer, It is characterized by being gradually widened away from the boundary with the active region, and the total impurity amount of the second conductivity type semiconductor region is larger than the total impurity amount of the first conductivity type semiconductor region.

According to a second aspect of the present invention, in the semiconductor device according to the first aspect, the width W _{n11 of} the first conductivity type semiconductor region at the boundary between the active region and the second inactive region, the active The width W _{p11 of} the second conductivity type semiconductor region at the boundary between the region and the second inactive region, parallel to the depth direction of the semiconductor substrate, from the outermost periphery of the active region to the direction of the second inactive region the distance L _Y1 width W of the first conductivity type semiconductor region at the position of _n12, and the parallel to the depth direction of the semiconductor substrate, the distance from the outermost periphery of the active region in the direction of the second inactive region L _Y1 The width W _p12 of the second conductive type semiconductor region at the position of W _n11 > W _n12 , W _p11 <W _p12 , and W _n11 + W _p11 = W _n12 + W _p12 and tan ⁻¹ ((W _{n11 -W n12) / (2 · L} Y1)) ≦ 2 °, and and satisfies the ^{_{tan -1 ((W p12 -W p11}} ) / (2 · L Y1)) ≦ 2 °.

A semiconductor device according to a third aspect of the invention is characterized in that, in the invention of the second aspect, 1.05 ≦ W _p12 / W _n12 ≦ 2.0 is further satisfied.

A semiconductor device according to a fourth aspect of the present invention is the semiconductor device according to the second aspect, further satisfying 1.05 ≦ W _p12 / W _n12 ≦ 1.3.

A semiconductor device according to a fifth aspect of the invention is characterized in that, in the invention of the second aspect, 1.05 ≦ W _p12 / W _n12 ≦ 1.2 is further satisfied.

  A semiconductor device according to a sixth aspect of the present invention is the semiconductor device according to any one of the first to fifth aspects, wherein the outermost periphery of the active region is substantially parallel to the width direction of the semiconductor substrate. It is formed by a straight part, a second straight part substantially parallel to the depth direction of the semiconductor substrate, and an arcuate part that connects the first straight part and the second straight part.

  According to a seventh aspect of the present invention, in the semiconductor device according to the sixth aspect, the arc-shaped portion is a part of a circumference.

  The semiconductor device according to an eighth aspect of the present invention is the semiconductor device according to the sixth aspect, wherein the arc-shaped portion is a part of the circumference of an ellipse.

  According to a ninth aspect of the present invention, in the semiconductor device of the sixth aspect, the arc-shaped portion is divided into a first curved portion and a second curved portion, and the first curved portion. And a third straight line portion connecting the respective ends of the second curved portion and the second curved portion.

  A semiconductor device according to a tenth aspect of the present invention is the semiconductor device according to any one of the first to ninth aspects, wherein a thickness of the surface of the parallel pn layer of the inactive region is larger than that of the gate insulating film. And a field plate electrode provided on the surface of the parallel pn layer of the inactive region via the insulating film.

  The semiconductor device according to an eleventh aspect of the present invention is the semiconductor device according to the tenth aspect, wherein the outermost periphery of the field plate electrode in the width direction of the semiconductor substrate is in the second inactive region, or In the width direction of the semiconductor substrate, the semiconductor substrate is located at any position on the inner periphery or the outermost periphery of the second inactive region.

  A semiconductor device according to a twelfth aspect of the present invention is the semiconductor device according to the tenth or eleventh aspect, wherein the outermost periphery of the field plate electrode in the depth direction of the semiconductor substrate is in the second inactive region. Alternatively, the semiconductor substrate is located at any position on the inner periphery or the outermost periphery of the second inactive region in the depth direction of the semiconductor substrate.

  According to a thirteenth aspect of the present invention, in the semiconductor device according to any one of the tenth to twelfth aspects, the thickness of the insulating film is substantially uniform.

  A semiconductor device according to a fourteenth aspect of the present invention is the semiconductor device according to any one of the tenth to twelfth aspects, wherein a surface of the insulating film in contact with the field plate electrode is an end of the insulating film. It is characterized by being gradually thinner toward the part.

  A semiconductor device according to a fifteenth aspect of the invention is the semiconductor device according to any one of the tenth to twelfth aspects, wherein the surface of the insulating film in contact with the field plate electrode has two or more steps. And thinning toward the end of the insulating film.

  According to a sixteenth aspect of the present invention, in the semiconductor device according to any one of the tenth to fifteenth aspects, the field plate electrode has the same potential as the source electrode.

  According to a seventeenth aspect of the present invention, in the semiconductor device according to any one of the tenth to sixteenth aspects, the field plate electrode has the same potential as the gate electrode.

  According to an eighteenth aspect of the present invention, in the semiconductor device according to any one of the tenth to seventeenth aspects, the field plate electrode has a floating potential.

  A semiconductor device according to a nineteenth aspect of the present invention is the semiconductor device according to any one of the first to eighteenth aspects, wherein the active region is completely surrounded by the second inactive region, and the depth of the semiconductor substrate is determined. A second non-active region in the direction is surrounded by the first non-active region.

  A semiconductor device according to a twentieth aspect of the present invention is the semiconductor device according to any one of the first to twentieth aspects, wherein at least one of the active region in the width direction of the semiconductor substrate and the arc-shaped portion of the active region. A part of the first non-active region is surrounded by the second non-active region, and the second non-active region and the active region not surrounded by the second non-active region are formed by the first non-active region. It is completely enclosed.

  A semiconductor device according to a twenty-first aspect of the present invention is the semiconductor device according to any one of the first to eighteenth aspects, wherein the active region is completely surrounded by the second non-active region, and the second non-active region is included. The active region is completely surrounded by the first non-active region.

  A semiconductor device according to a twenty-second aspect of the present invention is the semiconductor device according to any one of the first to eighteenth aspects, wherein the non-active region further includes a third non-active region, In the non-active region, the total impurity amount of the first conductive type semiconductor region and the total impurity amount of the second conductive type semiconductor region are substantially equal, and the active region in the width direction of the semiconductor substrate and the arc shape of the active region At least a part of the portion is surrounded by the third inactive region, and the third inactive region is completely surrounded by the second inactive region.

  According to a twenty-third aspect of the present invention, in the semiconductor device according to the twenty-second aspect, the active region is completely surrounded by the third non-active region.

  A semiconductor device according to a twenty-fourth aspect of the present invention is the semiconductor device according to the twenty-second or twenty-third aspect, wherein the first non-active region is disposed outside the second inactive region along an end in the width direction of the semiconductor substrate. One inactive region is formed.

  The semiconductor device according to claim 25 is the semiconductor device according to claim 22 or 23, wherein the second inactive region is completely surrounded by the first inactive region. And

  According to the invention of each claim described above, the total impurity in the first conductivity type semiconductor region is changed by changing the widths of the first conductivity type semiconductor region and the second conductivity type semiconductor region in the second inactive region. The total impurity concentration of the second conductivity type semiconductor region can be made higher than the concentration. Therefore, compared with the conventional semiconductor substrate, the depletion layer near the surface of the semiconductor substrate can be expanded, and the electric field concentration on the surface of the semiconductor substrate near the outermost periphery of the active region can be reduced. Thereby, the breakdown voltage of the semiconductor substrate in the inactive region can be improved, and the breakdown voltage of the inactive region can be made higher than the breakdown voltage of the active region.

  According to the semiconductor device and the manufacturing method thereof according to the present invention, it is possible to obtain a semiconductor device using a parallel pn structure semiconductor substrate with high breakdown voltage and low loss while suppressing an increase in manufacturing process and manufacturing cost.

  Hereinafter, preferred embodiments of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings. Hereinafter, in the description of the embodiment and all the attached drawings, the same reference numerals are given to the same components, and the overlapping description is omitted.

(Embodiment 1)
FIG. 1 is a plan view of the semiconductor device according to the first embodiment. The semiconductor device according to the first embodiment is manufactured using a semiconductor substrate having a parallel pn structure. A semiconductor substrate having a parallel pn structure has an n-type drift region (first conductivity type semiconductor region) 2 and a p-type partition region (first region) on the surface of the first main surface of the n ⁺ substrate having a low resistivity which is an n ⁺ drain region. A parallel pn layer composed of two conductive type semiconductor regions) 3 is provided. As shown in FIG. 70, a vertical MOS structure is formed on the surface of the parallel pn layer. In the first embodiment, the field plate electrode (field plate electrode 14 in FIG. 70) is provided on the outermost periphery of the active region 18.

Further, as shown in FIG. 1, the n-type drift region 2 and the p-type partition region 3 of the parallel pn layer, and the boundary line between the n-type drift region 2 and the p-type partition region 3 are in the depth direction of the semiconductor substrate. It is provided so as to be parallel to Y (Y depth direction). An active region 18 is provided on the first main surface of the semiconductor substrate. The active region 18 includes a straight line parallel to the Y depth direction of the outermost periphery (X source outermost periphery) of the active region 18 in the X width direction and the X width of the outermost periphery (Y source outermost periphery) of the active region 18 in the Y depth direction. A straight line parallel to the direction, a straight line at the outermost circumference of the X source, and a straight line at the outermost circumference of the Y source are composed of a radius parallel to the X width direction (hereinafter referred to as a first X distance) R _X1 and a central angle of 90 degrees. It has a shape connected by arcs (R source outermost circumference). The radius of the outermost circumference of the R source in the Y depth direction (hereinafter referred to as the first Y distance) R _Y1 is equal to the first X distance R _X1 (R _X1 = R _Y1 ). An inactive region (high withstand voltage junction termination structure) is provided outside the active region 18 on the first main surface of the semiconductor substrate.

The inactive region is provided with a first inactive region 17b and a second inactive region 17a. The second inactive region 17 a is formed so as to surround the active region 18. A first inactive region 17b is provided outside the second inactive region 17a along the outermost end of the X substrate. The second non-active region 17a and the first non-active region 17b are separated by a straight line parallel to the Y depth direction at a distance R _X2 from the outermost periphery of the X source (hereinafter referred to as a second X distance). It has been. Here, the first inactive region 17 b is a charge balance region in which the total impurity concentration of the n-type drift region 2 and the total impurity concentration of the p-type partition region 3 are equal. On the other hand, the second inactive region 17 a is a charge imbalance region in which the total impurity concentration of the p-type partition region 3 is higher than the total impurity concentration of the n-type drift region 2.

In the active region 18, the width of the n-type drift region 2 (hereinafter referred to as the first n width) W _n11 and the width of the p-type partition region 3 (hereinafter referred to as the first p width) W _p11 are equal (W _n11 = _Wp11 ). In the second non-active region 17a (hereinafter referred to as the first charge unbalance region _Sa1 ) on the parallel pn layer in which the active region 18 is provided, the outermost periphery of the Y source (hereinafter referred to as the first width change point). ) To a point (hereinafter referred to as a second width change point) L _{Y1 from} a point (hereinafter referred to as a second width change point) toward the Y substrate end portion parallel to the Y depth direction. The widths of the parallel pn layers gradually change toward the end of the Y substrate. The width (hereinafter referred to as second n width) W _n12 of the n-type drift region 2 at the second width change point is narrower than the first n width W _n11 (W _n12 <W _n11 ). . Conversely, the width of the p-type partition region 3 at the second width change point (hereinafter referred to as the second p width) W _p12 is wide (W _p12 > W _p11 ). The widths of the parallel pn layers from the second width change point to the Y substrate termination portion do not change, and the widths of the parallel pn layers at the Y substrate termination portion are the second n width W _n12 and the second width, respectively. The p width W _p12 of 2. At this time, each width of the parallel pn layer is a value satisfying the following expression (1).

W _n11 + W _p11 = W _n12 + W _p12 (1)

In a region of the second non-active region 17a other than the first charge imbalance region S _a1 (hereinafter referred to as a second charge imbalance region S _a2 ), the n-type drift region 2 adjacent to the active region 18 A width (hereinafter referred to as a fourth n width) W _n14 , a width of an n-type drift region 2 adjacent to the first charge unbalance region S _a1 (hereinafter referred to as a fifth n width) W _n15 , Other widths of the n-type drift region 2 (hereinafter referred to as a third n width) W _n13 and the width of the p-type partition region 3 (hereinafter referred to as a third p width) W _p13 are as follows: The values satisfy the expressions 2) and (3) simultaneously.

W _n15 <W _n14 <W _p13 (2)

W _n13 <W _p13 (3)

In the first inactive region 17b, the width of the n-type drift region 2 (hereinafter referred to as a sixth n width) _Wn16 and the width of the p-type partition region 3 (hereinafter referred to as a sixth p width). ) It is equal to W _p16 (W _n16 = W _p16 ).

The first Y interval L _Y1 is preferably set to a value satisfying the following expressions (4) and (5).

tan ⁻¹ ((W _n11 −W _n12 ) / (2 · L _Y1 )) ≦ 2 degrees (4)

tan ⁻¹ ((W _p12 −W _p11 ) / (2 · L _Y1 )) ≦ 2 degrees (5)

  The reason for this is that when the change in the width of the trench formed in the semiconductor substrate is large, the side surface of the trench is greatly deviated from the (100) plane, resulting in poor embeddability. Here, the (100) plane is the surface orientation of the surface of the semiconductor substrate, the side surfaces of the trench, and the bottom surface. When the width of the trench is widened in the Y depth direction, the side wall of the portion where the trench width is widened is shifted to the (1α0) plane (0 <α <1) by the inclination α from the (100) plane. The slope α is a value that satisfies the following expression (6).

α = (W _p12 −W _p11 ) / (2 · L _Y1 ) (6)

This slope α has an upper limit. When the first Y interval L _Y1 is not in a value that satisfies the expressions (4) and (5), the inclination α increases, and the first Y interval L _Y1 deviates greatly from the (100) plane.

In the first inactive region 17b (hereinafter referred to as the first charge balance region _Sb1 ), it is preferable to set a value satisfying any one of the following formulas (7) and (8). At this time, in order to avoid electric field concentration on the surface of the semiconductor substrate, it is more preferable to set the value to satisfy the formula (8).

W _n16 = W _p16 = W _n11 = W _p11 (7)

W _n16 = W _p16 <W _n11 = W _p11 (8)

  In the second non-active region 17a, it is preferable to set a value satisfying the expression (1) and the following expressions (9) to (12).

W _n14 = W _n15 + (W _p12 −W _p11 ) / 2 (9)

1.05 ≦ W _p12 / W _n12 ≦ 1.2 (10)

1.05 ≦ W _p13 / W _n13 ≦ 1.3 (11)

1.05 ≦ W _p13 / W _n15 ≦ 1.3 (12)

The reason is that, when the values of the expressions (10) to (12) are smaller than the lower limit value, the difference from the first inactive region 17b becomes small, and the p-type partition region in the second inactive region 17a. This is because the effect of increasing the relative total impurity concentration of 3 (hereinafter referred to as p-rich) is reduced. On the other hand, when the values of the expressions (10) to (12) are larger than the upper limit value, the breakdown voltage of the semiconductor substrate in the first charge unbalance region S _a1 is the second n width W _n12 and the second p width. This is because it depends on W _p12 . Also, the electric field concentrates on the surface of the semiconductor substrate at the boundary between the second charge unbalance region S _a2 and the first charge balance region S _b1 , resulting in a dense equipotential line distribution.

  Moreover, it is preferable to make it into the value which satisfy | fills following (13) Formula in R source outermost periphery.

0.05 ≦ R _X2 / R _X1 ≦ 1 (13)

The reason is that when the value of the equation (13) is smaller than the lower limit value, the p-rich region in the second charge imbalance region S _a2 becomes too narrow and the electric field concentrated on the surface of the semiconductor substrate is reduced. Because it will fade. On the other hand, when the value of the expression (13) is larger than the upper limit value, the depletion layer may spread too much in the inactive region 17 and reach the substrate termination portion. In order to avoid this, in the active region 18, the width of the semiconductor substrate in the X width direction and the width of the semiconductor substrate in the Y depth direction must be 1.5 · R _X1 or more.

The widths of the parallel pn layers may be changed from within the first charge unbalance region _Sa1 by shifting the first width change point toward the Y substrate endmost side. At this time, a distance L _Y11 for shifting the first width change point in the Y depth direction (hereinafter referred to as a width change point moving distance) L _Y11 and the depth D _{t of the} trench formed in the semiconductor substrate are as follows: A value satisfying the formula is preferable.

0 ≦ L _Y11 ≦ D _t (14)

The reason is that when the width change point moving distance L _Y11 is smaller than zero, the first width change point is formed in the active region 18. On the other hand, when the width change point moving distance L _Y11 is larger than D _t , the second width change point is too far from the outermost periphery of the R source in the first charge unbalance region S _a1 . This is because the effect of relieving the electric field concentrated on the surface of the film is diminished.

  Next, an equipotential line distribution of the semiconductor device according to the first embodiment will be described. FIG. 2 is a plan view showing equipotential line distribution generated in the superjunction layer when a breakdown voltage is applied to the semiconductor device according to the first embodiment. As shown in FIG. 2, the inactive region 17 (second region B) near the outermost periphery of the X source is less sparse than the equipotential line distribution (see FIG. 73) of the second region B in the conventional semiconductor substrate. It has a uniform equipotential line distribution. Therefore, also in the region of the inactive region 17 (third region C) in the vicinity of the outermost periphery of the R source, the curve is gentler than the equipotential distribution (see FIG. 73) of the third region C in the conventional semiconductor substrate. Equipotential line distribution with That is, in the second region B and the third region C, since the electric field concentration is relaxed, it can be seen that the breakdown voltage of the semiconductor substrate in the inactive region 17 is improved.

Next, characteristics of the semiconductor device according to the first embodiment will be described. FIG. 3 is a characteristic diagram showing the relationship between the inactive region breakdown voltage and the active region breakdown voltage of the semiconductor device according to the first embodiment. As shown in FIG. 3, W _p12 / W _n12 = 1.1 to 1.2, W _p13 / W _n13 = 1.1 to 1.2, and W _p13 / W _n15 = 1.1 to 1.2 It can be seen that the ratio η (η≡BV _e / BV: hereinafter referred to as the withstand voltage ratio) of the inactive region withstand voltage BV _{e to} the active region withstand voltage BV recovers to the maximum value or almost the maximum value. The withstand voltage ratio η at this time is about η = 1.05.

  As described above, according to the first embodiment, in the second inactive region 17a, by changing the widths of the parallel pn layers, the p-type partition is more than the total impurity concentration of the n-type drift region 2. The total impurity concentration in region 3 can be increased. Therefore, in the second region B and the third region C, the depletion layer near the surface of the semiconductor substrate can be expanded compared to the conventional semiconductor substrate, and the electric field concentration on the surface of the semiconductor substrate near the outermost periphery of the source Can be relaxed. Thereby, the breakdown voltage of the semiconductor substrate in the inactive region 17 can be improved, and the breakdown voltage of the inactive region 17 can be made higher than the breakdown voltage of the active region 18.

(Embodiment 2)
Next, a semiconductor device according to the second embodiment will be described. FIG. 4 is a plan view of the semiconductor device according to the second embodiment. As shown in FIG. 4, in the planar structure of the semiconductor device according to the second embodiment, a first inactive region that is a charge balance region is formed in a part of the first charge unbalance region S _a1 in the first embodiment. 17b (hereinafter referred to as second charge balance region _Sb2 ) is provided. The boundary between the first charge unbalance region S _a1 and the second charge balance region S _b2 is a point parallel to the X width direction from the center of the R source outermost periphery on the arc of the R source outermost periphery (hereinafter referred to as the first charge unbalance region S _a1) . 1) (P1), a point on the arc of the outermost circumference of the R source that is moved from the first position P1 by an angle θ (hereinafter referred to as a boundary angle) θ in the Y depth direction (hereinafter referred to as a boundary angle) A straight line parallel to the Y depth direction from the position of P2 to the end of the Y substrate. In the second charge balance region S _b2 , each width of the parallel pn layer is the same as that of the active region 18. Other structures are the same as those in the first embodiment.

  In the second non-active region 17a, as in the first embodiment, the expressions (1), (9), (11), and (12) are satisfied, and the following expressions (15) and (16) are satisfied. A value satisfying the formula is preferable.

1.05 ≦ W _p12 / W _n12 ≦ 1.3 (15)

    30 degrees ≦ θ ≦ 90 degrees (16)

  The reason why it is preferable to satisfy the expressions (1), (9), (11), (12) and (15) is the same as in the first embodiment. When the value of θ is smaller than 30 degrees, a point (hereinafter referred to as a third position) P3 on the outermost arc of the R source parallel to the Y depth direction from the center of the outermost arc of the R source This is because the second position P2 and the third position P3 are too far away from each other, and the effect of relaxing the electric field concentrated on the surface of the semiconductor substrate is diminished.

  The other preferable conditions for the width and distance are the same as those in the first embodiment.

  Next, the equipotential line distribution of the semiconductor device according to the second embodiment will be described. FIG. 5 is a plan view showing equipotential line distribution generated in the superjunction layer when a breakdown voltage is applied to the semiconductor device according to the second embodiment. In the second embodiment, as shown in FIG. 5, in a region D (hereinafter referred to as a fourth region) D between the first region A and the third region C, further than the first region A. Sparse equipotential line distribution. Therefore, also in the first region A and the third region C adjacent to the fourth region D, the equipotential line distribution having a gentle curve compared to the equipotential line distribution of the first embodiment (see FIG. 2). It becomes. Thereby, it can be seen that the electric field concentration is more relaxed than in the first embodiment.

Next, as an example, characteristics of the semiconductor device according to the second embodiment when the boundary angle θ = 45 degrees will be described. FIG. 6 is a characteristic diagram showing the relationship between the inactive region breakdown voltage and the active region breakdown voltage of the semiconductor device according to the second embodiment. As shown in FIG. 6, as in the first embodiment, W _p12 / W _n12 = 1.1 to 1.2, W _p13 / W _n13 = 1.1 to 1.2, and W _p13 / W _n15 = From 1.1 to 1.2, it can be seen that the withstand voltage ratio η recovers to the maximum value or almost the maximum value. At this time, the withstand voltage ratio η is about η = 1.15.

As described above, according to the second embodiment, the same effect as in the first embodiment can be obtained. Further, by providing the second charge balance region S _b2 , the depletion layer near the surface of the semiconductor substrate can be expanded in the outermost periphery of the R source as compared with the first embodiment, and the semiconductor substrate in the vicinity of the outermost source periphery. Electric field concentration on the surface of the substrate can be reduced. Thereby, the breakdown voltage of the semiconductor substrate in the inactive region 17 can be further improved as compared with the first embodiment.

(Embodiment 3)
Next, a semiconductor device according to Embodiment 3 will be described. FIG. 7 is a plan view of the semiconductor device according to the third embodiment. As shown in FIG. 7, in the planar structure of the semiconductor device according to the third embodiment, the first inactive region 17b is formed on the Y substrate peripheral end side of the first charge unbalance region S _a1 in the first embodiment. (Hereinafter referred to as a third charge balance region S _b3 ) is provided. A first inactive region 17b (hereinafter referred to as a fourth charge balance region _Sb4 ) is also provided on the Y substrate peripheral edge side of the second charge unbalance region S _a2 in the first embodiment. ing. That is, the first inactive region 17b is formed on the X substrate peripheral end side and the Y substrate peripheral end side so as to surround the second inactive region 17a.

The boundary between the first charge unbalance region S _a1 and the third charge balance region S _b3 is located at a distance R _Y2 from the outermost periphery of the Y source (hereinafter referred to as a second Y distance). In the third charge balance region S _b3 , each width of the parallel pn layer is the same as that of the active region 18.

In the first charge unbalance region S _a1 , the widths of the parallel pn layers at the first width change point and the first width change point are the same as those in the first embodiment. A distance from the boundary between the first charge unbalance region S _a1 and the third charge balance region S _b3 (hereinafter, referred to as a third width change point) toward the active region 18 in parallel with the Y depth direction. Each width of the parallel pn layer between the points of L _Y2 (hereinafter referred to as the second Y interval) (hereinafter referred to as the fourth width change point) is gradually changed toward the Y substrate termination portion. ing. Each width of the parallel pn layer at the third width change point is the same as that of the third charge balance region S _b3 . The widths of the parallel pn layers at the fourth width change point are respectively the second n width W _n12 and the second p width W _p12 .

In addition, each width of the parallel pn layer in the second charge unbalance region S _{a2 varies} depending on each width of the parallel pn layer in the first charge unbalance region S _a1 . Therefore, the width of the n-type drift region 2 of the fourth charge balance region S _b4 (hereinafter referred to as the seventh n width) W _n17 is the width of the n-type drift region 2 of the second charge unbalance region S _a2. It becomes the width corresponding to. The same applies to the width of the p-type partition region 3 in the fourth charge balance region S _b4 (hereinafter referred to as the seventh p width) W _p17 .

  Other structures are the same as those in the first embodiment.

The second Y interval L _Y2 is preferably set to a value satisfying the following expression (17).

tan ⁻¹ ((W _p12 −W _p11 ) / (2 · L _Y2 )) ≦ 2 degrees (17)

  The reason is the same as in the first embodiment.

  In the first non-active region 17b, it is preferable to set a value satisfying any one of the expressions (7) and (8) as in the first embodiment. The reason is the same as in the first embodiment. Moreover, it is preferable to make it the value which satisfy | fills following (18) Formula.

_{W n16 = W p16 ≦ W n17} = W p17 ≦ W n11 = W p11 ··· (18)

  The reason is that as the width of the parallel pn layer is reduced as the distance from the outermost periphery of the active region 18 increases, the breakdown voltage of the inactive region 17 is improved.

  In the second non-active region 17a, it is preferable to satisfy the expressions (1) and (9) and satisfy the following expressions (19) to (21) as in the first embodiment.

1.05 ≦ W _p12 / W _n12 ≦ 2.0 (19)

1.05 ≦ W _p13 / W _n13 ≦ 2.0 (20)

1.05 ≦ W _p13 / W _n15 ≦ 2.0 (21)

  The reason is the same as in the first embodiment.

  Further, in the outermost periphery of the R source, it is preferable to satisfy the following expression (13) and to satisfy the following expression (22) as in the first embodiment.

0.05 ≦ R _Y2 / R _X1 ≦ 1 (22)

  The reason is the same as in the first embodiment.

  Furthermore, it is preferable to set the value satisfying the following equation (23) at the outermost periphery of the R source.

{W _p12 · (W _p13 + W _n13 )} / {W _p13 · (W _p12 + W _n12 )} ≦ R _Y2 / R _X1 ≦ 1 (23)

The reason is that when the ratio (R _Y2 / R _X1 ) of the second Y distance R _Y2 to the first X distance R _X1 is smaller than the value on the left side, the depletion layer is difficult to spread in the third region C, This is because an equipotential line distribution is obtained. On the other hand, when the ratio (R _Y2 / R _X1 ) of the second Y distance R _Y2 to the first X distance R _X1 is larger than the value on the right side, the depletion layer expands too much in the third region C, and the substrate termination This is because there is a risk of reaching the part. Means for avoiding this are the same as those in the first embodiment.

  The other preferable conditions for the width and distance are the same as those in the first embodiment.

  Next, the equipotential line distribution of the semiconductor device according to the third embodiment will be described. FIG. 8 is a plan view showing equipotential line distribution generated in the superjunction layer when a breakdown voltage is applied to the semiconductor device according to the third embodiment. In the third embodiment, as shown in FIG. 8, it can be seen that the first region A and the second region B have a sparse equipotential line distribution. Therefore, it is understood that the electric field concentration is alleviated as a whole at the outermost periphery of the source.

Next, characteristics of the semiconductor device according to the third embodiment will be described. FIG. 9 is a characteristic diagram showing the relationship between the inactive region breakdown voltage and the active region breakdown voltage of the semiconductor device according to the third embodiment. As shown in FIG. 9, W _p12 / W _n12 = 1.1 to 1.5, W _p13 / W _n13 = 1.2 to 1.5, and W _p13 / W _n15 = 1.2 to 1.5 It can be seen that the withstand voltage ratio η is restored to the maximum value or almost the maximum value. At this time, the withstand voltage ratio η is about η = 1.1.

As described above, according to the third embodiment, the same effect as in the first embodiment can be obtained. The second inactive region 17a exhibits the same effect as the guard ring. Therefore, the electric field concentration on the surface of the semiconductor substrate in the vicinity of the outermost periphery of the source can be reduced as compared with the first and second embodiments. Further, an additional process for forming the guard ring is not required, and the manufacturing process and manufacturing cost can be reduced. Further, it is assumed that the second inactive region 17a is made to be p-rich than the first and second embodiments by forming the first charge balance region _Sb1 and the fourth charge balance region _Sb4. However, since the high breakdown voltage of the inactive region 17 can be maintained, the degree of freedom in designing the semiconductor substrate is increased.

(Embodiment 4)
Next, a semiconductor device according to Embodiment 4 will be described. FIG. 10 is a plan view of the semiconductor device according to the fourth embodiment. As shown in FIG. 10, in the planar structure of the semiconductor device according to the fourth embodiment, a part of the first charge unbalance region S _a1 in the third embodiment is a third charge balance region S _b3 . The third charge balance region S _b3 is provided so as to be in contact with the outermost periphery of the Y source and the outermost periphery of the R source that connects the second position P2 and the third position P3. At this time, the third charge balance region S _b3 is formed so as to be in contact with the active region 18 and wrap around the second inactive region 17a. Other structures are the same as those in the first embodiment.

The first Y interval L _Y1 is preferably set to a value satisfying the expression (5) as in the first embodiment. The second Y interval L _Y2 is preferably set to a value satisfying the expression (17) as in the third embodiment. In the first non-active region 17b, it is preferable to set a value satisfying any one of the expressions (7) and (8) as in the first embodiment. In the second non-active region 17a, the expressions (1) and (9) are satisfied as in the first embodiment, the expression (16) is satisfied as in the second embodiment, and the same as in the third embodiment. It is preferable that the value satisfies the expressions (19) to (21). In the outermost periphery of the R source, it is preferable to satisfy the expression (13) as in the first embodiment and to satisfy the expressions (22) and (23) as in the third embodiment. The width change point moving distance L _Y11 is preferably set to a value satisfying the expression (14) as in the first embodiment. The reason is the same as in the first to third embodiments.

  Next, an equipotential line distribution of the semiconductor device according to the fourth embodiment will be described. FIG. 11 is a plan view showing an equipotential line distribution generated in the superjunction layer when a breakdown voltage is applied to the semiconductor device according to the fourth embodiment. In the fourth embodiment, as shown in FIG. 11, in the first region C, as in the third embodiment (see FIG. 8), it can be seen that a sparse equipotential line distribution is obtained. It can also be seen that the equipotential line distribution in the fourth region D is a sparse equipotential line distribution compared to the first region A. Therefore, it can be seen that the electric field concentration is alleviated as compared with the third embodiment.

Next, characteristics of the semiconductor device according to the fourth embodiment will be described. FIG. 12 is a characteristic diagram showing the relationship between the inactive region breakdown voltage and the active region breakdown voltage of the semiconductor device according to the fourth embodiment. As shown in FIG. 12, as in the third embodiment, W _p12 / W _n12 = 1.1 to 1.5, W _p13 / W _n13 = 1.2 to 1.5, and W _p13 / W _n15 = It can be seen that when the ratio is 1.2 to 1.5, the withstand voltage ratio η recovers to the maximum value or almost the maximum value. At this time, the withstand voltage ratio η is about η = 1.2.

As described above, according to the fourth embodiment, the same effect as in the third embodiment can be obtained. Further, since the third charge balance region S _b3 is formed wider than that of the third embodiment, the equipotential line distribution of the fourth region D is less sparse than the first region A, etc. It can be a potential line distribution. Therefore, the electric field concentration can be alleviated as a whole more than in the third embodiment.

Next, a modification of the semiconductor device in Embodiment 1 will be described. FIG. 13 is a plan view showing a planar structure of a modification of the semiconductor device according to the first embodiment. As shown in FIG. 13, the second charge balance region S _b2 may be formed in the first charge unbalance region S _a1 in the first embodiment as in the second embodiment. At this time, the boundary between the first charge unbalance region S _a1 and the second charge balance region S _b2 may exist in the middle of the outer circumference of the Y source (straight line range 18a). According to such a semiconductor device, the same effect as in the first embodiment can be obtained.

Next, a modification of the semiconductor device in Embodiment 3 will be described. FIG. 14 is a plan view illustrating a planar structure of a modification of the semiconductor device according to the third embodiment. As shown in FIG. 14, a third charge balance region S _b3 may be formed in the first charge unbalance region S _a1 in the third embodiment as in the fourth embodiment. At this time, the boundary between the first charge unbalance region S _a1 and the third charge balance region S _b3 may exist in the middle of the outer periphery of the Y source. According to such a semiconductor device, the same effect as in the third embodiment can be obtained.

  Next, modified examples of the semiconductor device in the first to fourth embodiments will be described. FIGS. 15 to 46 are plan views showing the planar structure of a modification of the semiconductor device according to the first to fourth embodiments. In the semiconductor device in the first to fourth embodiments, a plurality of first inactive regions 17b and a plurality of second inactive regions 17a may be formed. As shown in FIG. 15, the second inactive region 17a may be formed in the first inactive region 17b of the first embodiment. Further, the formed second non-active region 17a and the first non-active region 17b adjacent to the second non-active region 17a are divided into the first non-active region 17b and the second non-active region 17a. It is good also as the stripe-shaped parallel layer H formed by repeating repeatedly. At this time, the substrate termination portion may be either the first inactive region 17b or the second inactive region 17a. In addition, as shown in FIG. 16, the first inactive region 17b may be formed in the second inactive region 17a on the active region 18 side of the semiconductor device shown in FIG.

  Further, as shown in FIG. 17, the first inactive region 17b and the second inactive region 17a of the first embodiment are inverted from the formation region, and the active region 18 is further formed in the first inactive region 17b. A rectangular second inactive region 17a may be formed so as to surround it. As shown in FIG. 18, the first inactive region 17 b may be formed in the second inactive region 17 a that is not in contact with the active region 18 of the semiconductor device shown in FIG. 17. At this time, the parallel layer H may be used similarly to the semiconductor device shown in FIG. Further, as shown in FIG. 19, a second inactive region 17a may be further formed in the first inactive region 17b of the semiconductor device shown in FIG. At this time, the parallel layer H may be used similarly to the semiconductor device shown in FIG. Further, as shown in FIG. 20, the semiconductor device shown in FIGS. 18 and 19 may be combined.

  As shown in FIG. 21, the region of the second inactive region 17a in contact with the active region 18 of the semiconductor device shown in FIG. 17 may be narrowed. As shown in FIG. 22, the first inactive region 17b may be formed in the second inactive region 17a not in contact with the active region 18 of the semiconductor device shown in FIG. At this time, the parallel layer H may be used similarly to the semiconductor device shown in FIG. Further, as shown in FIG. 23, the semiconductor device shown in FIG. 21 is inactivated at the end of the Y substrate at the end of the first inactive region 17b away from the second inactive region 17a in contact with the active region 18. A second inactive region 17a having the same width as the region 17a may be formed. At this time, the parallel layer H may be used similarly to the semiconductor device shown in FIG. Further, as shown in FIG. 24, the semiconductor devices shown in FIGS. 22 and 23 may be combined.

  Further, as shown in FIG. 25, the region of the second inactive region 17a may be formed so as to surround the first inactive region 17b of the semiconductor device shown in FIG. In addition, as shown in FIG. 26, a second inactive region 17a may be formed in the first inactive region 17b of the third embodiment. In addition, as shown in FIG. 27, the first inactive region 17b may be formed in the second inactive region 17a formed in the terminal portion of the X substrate of the semiconductor device shown in FIG. At this time, the parallel layer H may be used similarly to the semiconductor device shown in FIG. As shown in FIG. 28, the region of the second inactive region 17a may be formed in the first inactive region 17b of the semiconductor device shown in FIG. At this time, the parallel layer H may be used similarly to the semiconductor device shown in FIG. Further, as shown in FIG. 29, the semiconductor devices shown in FIGS. 27 and 28 may be combined.

  Further, as shown in FIG. 30, the second inactive region 17a may be formed in the first inactive region 17b of the fourth embodiment. Further, as shown in FIG. 31, the first inactive region 17b may be formed in the second inactive region 17a formed in the terminal portion of the X substrate of the semiconductor device shown in FIG. At this time, the parallel layer H may be used similarly to the semiconductor device shown in FIG. Further, as shown in FIG. 32, the semiconductor device shown in FIG. 30 is inactive at the end of the first substrate in the first inactive region 17b away from the second inactive region 17a in contact with the active region 18. A second inactive region 17a having the same width as the region 17a may be formed. At this time, the parallel layer H may be used similarly to the semiconductor device shown in FIG. Further, as shown in FIG. 33, the semiconductor device shown in FIGS. 31 and 32 may be combined. As shown in FIG. 34, the region of the second inactive region 17a in contact with the active region 18 of the semiconductor device shown in FIG. 19 may be narrowed. At this time, the first non-active region 17b adjacent to the active region 18 and the second non-active region 17a formed at the Y substrate termination portion are replaced with the first non-active region 17b and the second non-active region. A stripe-shaped parallel layer H formed by alternately and repeatedly forming the regions 17a may be used. At this time, the Y substrate termination portion may be either the first inactive region 17b or the second inactive region 17a.

  In addition, as shown in FIG. 35, the first inactive region 17b may be formed in the second inactive region 17a formed in the terminal portion of the X substrate of the semiconductor device shown in FIG. At this time, the parallel layer H may be used similarly to the semiconductor device shown in FIG. As shown in FIG. 36, the region of the second inactive region 17a formed in the Y substrate termination portion of the semiconductor device shown in FIG. 19 may be narrowed. As shown in FIG. 37, the first inactive region 17b may be formed in the second inactive region 17a formed in the terminal portion of the X substrate of the semiconductor device shown in FIG. At this time, the parallel layer H may be used similarly to the semiconductor device shown in FIG. As shown in FIG. 38, the region of the second inactive region 17a formed in the Y substrate termination portion of the semiconductor device shown in FIG. 32 may be expanded. As shown in FIG. 39, the first inactive region 17b may be formed in the second inactive region 17a formed in the terminal portion of the X substrate of the semiconductor device shown in FIG. At this time, the parallel layer H may be used similarly to the semiconductor device shown in FIG.

  As shown in FIG. 40, the region of the second inactive region 17a formed in the Y substrate termination portion of the semiconductor device shown in FIG. 28 may be narrowed. As shown in FIG. 41, the region of the second inactive region 17a formed in the Y substrate termination portion of the semiconductor device shown in FIG. 29 may be narrowed. Further, as shown in FIG. 42, the region of the Y substrate termination portion of the second inactive region 17a formed in the substrate termination portion of the semiconductor device shown in FIG. 25 may be narrowed. As shown in FIG. 43, the region of the second inactive region 17a formed in contact with the active region 18 of the semiconductor device shown in FIG. 25 may be narrowed. At this time, the parallel layer H may be used similarly to the semiconductor device shown in FIG. The parallel layer H is formed in a range not in contact with the active region 18.

Also, as shown in FIG. 44, the semiconductor device shown in FIG. 25 is formed in contact with the active region 18 and the region of the Y base termination portion of the second inactive region 17a formed at the substrate termination portion. The region of the second non-active region 17a may be narrowed. As shown in FIG. 45, the outermost circumference of the R source may be elliptical by making the second Y distance R _Y1 smaller than the first X distance R _X1 (R _X1 > R _Y1 ). In addition, as shown in FIG. 46, the outer peripheral portion of the active region 18 may have a shape including at least one straight line (straight line range 18a) and one circular arc (arc range 18b). However, in order to avoid electric field concentration, it is better to avoid a polygonal line shape and to have a smooth shape that can be differentiated to the first order. As described above, according to the semiconductor device shown in FIGS. 15 to 46, the same effect as any one or a plurality of embodiments of the first to fourth embodiments can be obtained.

(Embodiment 5)
Next, a semiconductor device according to Embodiment 5 will be described. FIG. 47 is a plan view of the semiconductor device according to the fifth embodiment. FIG. 48 is a cross-sectional view showing a cross-sectional structure taken along section line XA-XA ′ of FIG. As shown in FIG. 47, in the planar structure of the semiconductor device according to the fifth embodiment, the X source outermost periphery of the field plate electrode 14 provided on the outermost periphery (source outermost periphery) of the active region 18 in the first embodiment. And the shape of the field plate electrode 14 at the outermost periphery of the R source is a shape protruding to the second inactive region 17a. That is, as shown in FIG. 48, the field plate electrode 14 is formed to extend to the surface of the interlayer insulating film 12. At this time, the length (hereinafter referred to as the first X interval) L _X1 of the portion of the field plate electrode 14 extending in the X width direction from the outer periphery of the X source is the outermost periphery of the field plate electrode 14 in the X width direction. Has a length that is inside the outermost periphery of the second inactive region 17a. Further, the thickness of the interlayer insulating film 12 is thicker than that of the gate insulating film 13 and is, for example, substantially uniform throughout the interlayer insulating film 12. Other structures are the same as those in the first embodiment.

The first X interval L _X1 is preferably set to a value satisfying the following expression (24).

0.2 ≦ L _X1 / R _X2 ≦ 1 (24)

The expression (24) will be described with reference to FIGS. 49 and 51 are plan views showing an example of a semiconductor device in which a field plate electrode is formed. FIG. 50 is a cross-sectional view showing equipotential line distribution generated in the superjunction layer when a withstand voltage is applied to the semiconductor device according to FIG. FIG. 52 is a cross-sectional view showing equipotential line distribution generated in the superjunction layer when a breakdown voltage is applied to the semiconductor device according to FIG. In the semiconductor device shown in FIG. 49, the field plate electrode 14 is provided on the outermost periphery of the active region 18 (L _X1 = 0). In the semiconductor device shown in FIG. 51, the outermost periphery of the field plate electrode 14 near the outermost periphery of the X source and the outermost periphery of the R source is formed so as to extend to the first inactive region 17b. The reason why the first X interval L _X1 satisfies the formula (24) is that when the value of the formula (24) is smaller than 0.2, as shown in FIG. This is because the equipotential lines passing through the first main surface (hereinafter referred to as the fifth region) E of the semiconductor substrate have a dense equipotential line distribution. On the other hand, when the value of the equation (24) is larger than 1, as shown in FIG. 52, from the vicinity of the outermost periphery of the field plate electrode 14 on the outer side of the active region 18, This is because the equipotential lines passing through F (hereinafter referred to as the sixth region) have a dense equipotential line distribution. Further, the electric field concentrates on the first main surface of the semiconductor substrate in the vicinity of the boundary between the first inactive region 17b and the second inactive region 17a, and the withstand voltage decreases.

  The other preferable conditions for the width and distance are the same as those in the first embodiment.

  Next, an equipotential line distribution of the semiconductor device according to the fifth embodiment will be described. FIG. 53 is a plan view showing equipotential line distribution generated in the super-junction layer when a withstand voltage is applied to the semiconductor device according to the fifth embodiment. FIG. 54 is a cross-sectional view showing equipotential line distribution generated in the superjunction layer when a withstand voltage is applied to the semiconductor device according to the fifth embodiment. As shown in FIG. 53, it can be seen that a sparse equipotential line distribution is obtained as in the first embodiment (see FIG. 2). Furthermore, as shown in FIG. 54, it can be seen that the fifth region E and the sixth region F have a sparse equipotential line distribution.

Next, characteristics of the semiconductor device according to the fifth embodiment when L _X1 / R _X2 = 0.5 · R _X2 will be described. FIG. 55 is a characteristic diagram showing the relationship between the inactive region breakdown voltage and the active region breakdown voltage of the semiconductor device according to the fifth embodiment. As shown in FIG. 55, W _p12 / W _n12 = 1.1 to 1.2, W _p13 / W _n13 = 1.1 to 1.2, and W _p13 / W _n15 = 1.1 to 1.2 It can be seen that the withstand voltage ratio η is restored to the maximum value or almost the maximum value. The withstand voltage ratio η at this time is about η = 1.10.

FIG. 56 is a plan view showing a planar structure of a modification of the semiconductor device according to the fifth embodiment. FIG. 57 is a cross-sectional view showing a cross-sectional structure taken along section line XB-XB ′ of FIG. As shown in FIGS. 56 and 57, the outermost periphery of the field plate electrode 14 near the outermost periphery of the X source and the outermost periphery of the R source is extended to the boundary between the first inactive region 17b and the second inactive region 17a. It may be formed (L _X1 = 1).

  As described above, according to the fifth embodiment, the same effect as in the first embodiment can be obtained. Further, since the field plate electrode 14 is formed so as to extend from the outermost periphery of the X source and the outermost periphery of the R source and extend to the second inactive region 17a, the interval between the equipotential lines extending to the fifth region E is increased. be able to. Further, by forming the outermost periphery of the field plate electrode 14 extending above the second non-active region 17a so as not to extend outside the first non-active region 17a, the sixth region F is formed. The interval between the equipotential lines that pass through can be increased. Thereby, the breakdown voltage of inactive region 17 can be further improved as compared with the first embodiment.

(Embodiment 6)
Next, a semiconductor device according to Embodiment 6 will be described. FIG. 58 is a plan view of the semiconductor device according to the sixth embodiment. As shown in FIG. 58, in the planar structure of the semiconductor device according to the sixth embodiment, the outermost periphery in the Y depth direction of the field plate electrode 14 in the fifth embodiment is second non-circular from the source outermost periphery in the Y depth direction. An overhang is formed on the surface of the active region 17a. Other structures are the same as those in the fifth embodiment.

At this time, the length (hereinafter referred to as the third Y interval) L _Y3 of the portion of the field plate electrode 14 extending in the Y depth direction from the outer periphery of the Y source is set to a value satisfying the following expression (25). Is preferred.

L _Y3 ≦ L _X1 (25)

This is because the equipotential line distribution on the surface of the semiconductor substrate tends to be denser in the X width direction than in the Y depth direction, and when the third Y interval L _Y3 is larger than the value of L _X1 , This is because the curvature of the corner portion of the field plate electrode 14 is increased, and the electric field is concentrated on the outermost periphery of the R source.

  As described above, according to the sixth embodiment, the same effect as in the fifth embodiment can be obtained.

(Embodiment 7)
Next, a semiconductor device according to Embodiment 7 will be described. FIG. 59 is a sectional view of the semiconductor device according to the seventh embodiment. As shown in FIG. 59, in the semiconductor device according to the seventh embodiment, the interlayer insulating film 12 in the fifth embodiment is gradually thinned from the final end of the field plate electrode 14 in the X width direction to the active region 18. ing. That is, the shape of the bottom surface of the field plate electrode 14 protruding from the surface of the interlayer insulating film 12 is thicker on the active region 18 side than on the X terminal end side. At this time, the boundary between the field plate electrode 14 and the interlayer insulating film 12 is linear. Other structures are the same as those in the fifth embodiment.

  Next, an equipotential line distribution of the semiconductor device according to the seventh embodiment will be described. FIG. 60 is a cross-sectional view showing equipotential line distribution generated in the superjunction layer when a withstand voltage is applied to the semiconductor device according to the seventh embodiment. As shown in FIG. 60, under the outermost periphery in the X width direction of the field plate electrode 14 (hereinafter referred to as the seventh region) G, as compared with the fifth embodiment (near the sixth region in FIG. 54). It can be seen that the distribution is sparse equipotential lines. When the technique according to the seventh embodiment is adopted, the breakdown voltage of the inactive region 17 is improved by about 5 to 10% in the semiconductor device having the same configuration.

  FIG. 61 is a cross-sectional view showing a planar structure of a modification of the semiconductor device according to the seventh embodiment. As shown in FIG. 61, the boundary line between the field plate electrode 14 and the interlayer insulating film 12 may have a shape having two or more steps.

  As described above, according to the seventh embodiment, the same effect as in the fifth embodiment can be obtained. Further, the breakdown voltage of the inactive region 17 can be further improved as compared with the fifth embodiment.

(Embodiment 8)
Next, a semiconductor device according to Embodiment 8 will be described. FIG. 62 is a plan view of the semiconductor device according to the eighth embodiment. FIG. 63 is a cross-sectional view showing a cross-sectional structure taken along section line XC-XC ′ of FIG. As shown in FIGS. 62 and 63, the planar structure of the semiconductor device according to the eighth embodiment has a structure in which the field plate electrode 14 and the source electrode 15 in the fifth embodiment are provided separately. Other structures are the same as those in the fifth embodiment.

  Next, an equipotential line distribution of the semiconductor device according to the eighth embodiment will be described. FIG. 64 is a cross-sectional view showing equipotential line distribution generated in the superjunction layer when a withstand voltage is applied to the semiconductor device according to the eighth embodiment. As shown in FIG. 64, it can be seen that the seventh region G has a sparse equipotential line distribution as compared with the fifth embodiment. When the technique according to the eighth embodiment is adopted, the breakdown voltage of the inactive region 17 is improved by about 5% as compared with the fifth embodiment.

  Further, the field plate electrode 14 may be electrically connected to one of the source electrode 15 and the gate electrode 4 to have the same potential.

  FIG. 65 is a plan view showing a planar structure of a modification of the semiconductor device according to the eighth embodiment. As shown in FIG. 65, the technique of the sixth embodiment is added to the technique of the eighth embodiment to separate the field plate electrode 14 and the source electrode 15 of the field plate electrode 14 extending in the Y depth direction, The field plate electrode 14 may be provided so as to surround the outermost periphery of the source electrode 15.

  As described above, according to the eighth embodiment, the same effect as in the fifth embodiment can be obtained. Further, when the field plate electrode 14 is provided on the surface of the interlayer insulating film 12 so as to be electrically insulated, the breakdown voltage of the inactive region 17 can be further improved as compared with the fifth embodiment.

(Embodiment 9)
Next, a semiconductor device according to Embodiment 9 will be described. FIG. 66 is a plan view of the semiconductor device according to the ninth embodiment. FIG. 67 is a cross-sectional view showing a cross-sectional structure taken along section line XD-XD ′ of FIG. As shown in FIGS. 66 and 67, in the planar structure of the semiconductor device according to the ninth embodiment, the active region 18 is surrounded between the active region 18 and the second non-active region 17a in the fifth embodiment. Is provided with a third inactive region 17c. Other structures are the same as those in the fifth embodiment.

The first X interval L _X1 is set to a value satisfying the following expression (26) with respect to the width in the X width direction (hereinafter referred to as the second X interval) L _{X2 of} the third inactive region 17c. Is preferred.

L _X2 ≦ L _X1 ≦ R _X2 (26)

The reason is that, when the first X interval L _X1 is smaller than the value of L _X2 , the electric field tends to concentrate on the surface of the semiconductor substrate in the seventh region G. On the other hand, when the first X interval L _X1 is larger than the value of R _X2 , the electric field is generated near the boundary between the first inactive region 17 b and the second inactive region 17 a on the first main surface of the semiconductor substrate. This is because it concentrates and the breakdown voltage decreases.

The first X interval L _X1 is equal to the following equation (27) with respect to the width in the Y depth direction (hereinafter referred to as the fourth Y interval) L _{Y4 of} the third inactive region 17c. A value satisfying the inequality sign of equation (27) and satisfying equation (29) and L _Y4 = 0, a value satisfying equation (28), or a value satisfying equation (28) and equation (29) It is preferable to do this.

L _Y4 ≦ L _Y3 (27)

L _Y4 > L _Y3 (28)

L _Y3 = 0 (29)

FIG. 68 is a plan view showing a planar structure of a modification of the semiconductor device according to the ninth embodiment. When the equal sign of the equation (27) is satisfied, as shown in FIG. 66, the field plate electrode 14 is provided on the outermost periphery of the third inactive region 17c. Further, when the inequality sign of the expression (27) is satisfied and the expression (29) and L _Y4 = 0 are satisfied, as shown in FIG. 68, the third inactive region 17c has the X source outermost periphery and the R source outermost periphery. The field plate electrode 14 is provided so as to surround the outermost periphery of the third inactive region 17c and the outermost periphery of the Y source. According to such a semiconductor device, the same effect as in the fifth embodiment can be obtained.

  69 and 70 are plan views showing a planar structure of a modified example of the semiconductor device according to the ninth embodiment. As shown in FIG. 69, the outermost periphery in the Y depth direction of the field plate electrode 14 may be located inside the third inactive region 17c. This example is an example when the expression (28) is satisfied. As shown in FIG. 70, the third inactive region 17 c in the semiconductor device shown in FIG. 68 may be formed so as to surround the outermost periphery of the active region 18. This example is an example when the expressions (28) and (29) are satisfied. A plurality of field plate electrodes 14 may be provided on the surface of the interlayer insulating film 12 so as to be electrically insulated. Similarly to the third embodiment, the first inactive region 17b may be formed so as to surround the second inactive region 17a.

  As described above, according to the ninth embodiment, the same effect as in the fifth embodiment can be obtained.

  Note that the semiconductor devices described in Embodiments 5 to 9 can improve the breakdown voltage of the inactive region 17 regardless of the arrangement of the gate electrode 4. For example, the longitudinal direction of the gate electrodes 4 arranged in stripes on the parallel pn layers may be parallel or perpendicular to the Y depth direction of the semiconductor substrate. Further, the gate electrodes 4 may be arranged in a lattice shape on the column pn layer. The field plate electrode 14 may be at a floating potential.

In the above description of the semiconductor device, a MOSFET in which a parallel pn layer is formed on the surface of the first main surface side of the n ⁺ substrate having a low resistivity which is the n ⁺ drain region has been described. The present invention is also applicable to a structure such as an IGBT in which a parallel pn layer is formed on the surface of the low p ⁺ substrate on the first main surface side.

  In the above description of the semiconductor device, the first conductivity type is n-type and the second conductivity type is p-type. However, in the present invention, the first conductivity type is p-type and the second conductivity type is n-type. The same holds true.

  As described above, the semiconductor device according to the present invention is useful for manufacturing a high-power semiconductor element. In particular, the semiconductor device has a semiconductor substrate having a parallel pn structure and achieves both high breakdown voltage and improved on-resistance characteristics. It is suitable for a semiconductor device that can be used.

1 is a plan view showing a semiconductor device according to a first embodiment; 3 is a plan view showing equipotential line distribution generated in the superjunction layer of the semiconductor device according to the first embodiment; FIG. FIG. 6 is a characteristic diagram illustrating a relationship between a non-active region breakdown voltage and an active region breakdown voltage of the semiconductor device according to the first embodiment; FIG. 6 is a plan view showing a semiconductor device according to a second embodiment; 6 is a plan view showing equipotential line distribution generated in a superjunction layer of a semiconductor device according to a second embodiment; FIG. FIG. 6 is a characteristic diagram illustrating a relationship between a non-active region breakdown voltage and an active region breakdown voltage of the semiconductor device according to the second embodiment; FIG. 6 is a plan view showing a semiconductor device according to a third embodiment; 6 is a plan view showing equipotential line distribution generated in a superjunction layer of a semiconductor device according to a third embodiment; FIG. FIG. 10 is a characteristic diagram illustrating a relationship between the inactive region breakdown voltage and the active region breakdown voltage of the semiconductor device according to the third embodiment; FIG. 6 is a plan view showing a semiconductor device according to a fourth embodiment; FIG. 6 is a plan view showing equipotential line distribution generated in a superjunction layer of a semiconductor device according to a fourth embodiment; FIG. 10 is a characteristic diagram illustrating a relationship between a non-active region breakdown voltage and an active region breakdown voltage of the semiconductor device according to the fourth embodiment; 6 is a plan view showing a planar structure of a modification of the semiconductor device according to the first embodiment; FIG. FIG. 10 is a plan view showing a planar structure of a modification of the semiconductor device according to the third embodiment; It is a top view shown about the planar structure of the modification of the semiconductor device concerning Embodiment 1-Embodiment 4. FIG. It is a top view shown about the planar structure of the modification of the semiconductor device concerning Embodiment 1-Embodiment 4. FIG. It is a top view shown about the planar structure of the modification of the semiconductor device concerning Embodiment 1-Embodiment 4. FIG. It is a top view shown about the planar structure of the modification of the semiconductor device concerning Embodiment 1-Embodiment 4. FIG. It is a top view shown about the planar structure of the modification of the semiconductor device concerning Embodiment 1-Embodiment 4. FIG. It is a top view shown about the planar structure of the modification of the semiconductor device concerning Embodiment 1-Embodiment 4. FIG. It is a top view shown about the planar structure of the modification of the semiconductor device concerning Embodiment 1-Embodiment 4. FIG. It is a top view shown about the planar structure of the modification of the semiconductor device concerning Embodiment 1-Embodiment 4. FIG. It is a top view shown about the planar structure of the modification of the semiconductor device concerning Embodiment 1-Embodiment 4. FIG. It is a top view shown about the planar structure of the modification of the semiconductor device concerning Embodiment 1-Embodiment 4. FIG. It is a top view shown about the planar structure of the modification of the semiconductor device concerning Embodiment 1-Embodiment 4. FIG. It is a top view shown about the planar structure of the modification of the semiconductor device concerning Embodiment 1-Embodiment 4. FIG. It is a top view shown about the planar structure of the modification of the semiconductor device concerning Embodiment 1-Embodiment 4. FIG. It is a top view shown about the planar structure of the modification of the semiconductor device concerning Embodiment 1-Embodiment 4. FIG. It is a top view shown about the planar structure of the modification of the semiconductor device concerning Embodiment 1-Embodiment 4. FIG. It is a top view shown about the planar structure of the modification of the semiconductor device concerning Embodiment 1-Embodiment 4. FIG. It is a top view shown about the planar structure of the modification of the semiconductor device concerning Embodiment 1-Embodiment 4. FIG. It is a top view shown about the planar structure of the modification of the semiconductor device concerning Embodiment 1-Embodiment 4. FIG. It is a top view shown about the planar structure of the modification of the semiconductor device concerning Embodiment 1-Embodiment 4. FIG. It is a top view shown about the planar structure of the modification of the semiconductor device concerning Embodiment 1-Embodiment 4. FIG. It is a top view shown about the planar structure of the modification of the semiconductor device concerning Embodiment 1-Embodiment 4. FIG. It is a top view shown about the planar structure of the modification of the semiconductor device concerning Embodiment 1-Embodiment 4. FIG. It is a top view shown about the planar structure of the modification of the semiconductor device concerning Embodiment 1-Embodiment 4. FIG. It is a top view shown about the planar structure of the modification of the semiconductor device concerning Embodiment 1-Embodiment 4. FIG. It is a top view shown about the planar structure of the modification of the semiconductor device concerning Embodiment 1-Embodiment 4. FIG. It is a top view shown about the planar structure of the modification of the semiconductor device concerning Embodiment 1-Embodiment 4. FIG. It is a top view shown about the planar structure of the modification of the semiconductor device concerning Embodiment 1-Embodiment 4. FIG. It is a top view shown about the planar structure of the modification of the semiconductor device concerning Embodiment 1-Embodiment 4. FIG. It is a top view shown about the planar structure of the modification of the semiconductor device concerning Embodiment 1-Embodiment 4. FIG. It is a top view shown about the planar structure of the modification of the semiconductor device concerning Embodiment 1-Embodiment 4. FIG. It is a top view shown about the planar structure of the modification of the semiconductor device concerning Embodiment 1-Embodiment 4. FIG. It is a top view shown about the planar structure of the modification of the semiconductor device concerning Embodiment 1-Embodiment 4. FIG. FIG. 10 is a plan view showing a semiconductor device according to a fifth embodiment; FIG. 48 is a cross-sectional view showing a cross-sectional structure taken along section line XA-XA ′ of FIG. 47. It is a top view shown about an example of the semiconductor device in which the field plate electrode was formed. FIG. 50 is a cross-sectional view showing equipotential line distribution generated in the superjunction layer of the semiconductor device according to FIG. 49; It is a top view shown about an example of the semiconductor device in which the field plate electrode was formed. FIG. 52 is a cross-sectional view showing equipotential line distribution generated in the superjunction layer of the semiconductor device according to FIG. 51; FIG. 10 is a plan view showing equipotential line distribution generated in a superjunction layer of a semiconductor device according to a fifth embodiment; FIG. 10 is a cross-sectional view showing equipotential line distribution generated in a superjunction layer of a semiconductor device according to a fifth embodiment; FIG. 10 is a characteristic diagram showing the relationship between the inactive region breakdown voltage and the active region breakdown voltage of the semiconductor device according to the fifth embodiment; FIG. 10 is a plan view showing a planar structure of a modification of the semiconductor device according to the fifth embodiment; FIG. 57 is a cross-sectional view showing a cross-sectional structure taken along section line XB-XB ′ of FIG. 56. FIG. 10 is a plan view showing a semiconductor device according to a sixth embodiment; FIG. 10 is a sectional view showing a semiconductor device according to a seventh embodiment; FIG. 10 is a cross-sectional view showing equipotential line distribution generated in a superjunction layer of a semiconductor device according to a seventh embodiment; FIG. 10 is a cross-sectional view showing a planar structure of a modification of the semiconductor device according to the seventh embodiment; FIG. 10 is a plan view showing a semiconductor device according to an eighth embodiment; FIG. 63 is a cross sectional view showing a cross sectional structure taken along section line XC-XC ′ of FIG. 62. FIG. 10 is a cross-sectional view showing equipotential line distribution generated in a superjunction layer of a semiconductor device according to an eighth embodiment; FIG. 16 is a plan view showing a planar structure of a modification of the semiconductor device according to the eighth embodiment; FIG. 10 is a plan view showing a semiconductor device according to a ninth embodiment; FIG. 67 is a cross-sectional view showing a cross-sectional structure taken along section line XD-XD ′ of FIG. 66. FIG. 38 is a plan view showing a planar structure of a modification of the semiconductor device according to the ninth embodiment; FIG. 38 is a plan view showing a planar structure of a modification of the semiconductor device according to the ninth embodiment; FIG. 38 is a plan view showing a planar structure of a modification of the semiconductor device according to the ninth embodiment; It is sectional drawing shown about the semiconductor device concerning the 1st prior art example. It is a top view shown about the semiconductor device concerning the 1st prior art example. It is a top view which shows equipotential line distribution which arises in the super-junction layer of the semiconductor device concerning a 1st prior art example. It is a top view shown about the semiconductor device concerning the 2nd prior art example. It is sectional drawing shown about the semiconductor device concerning a 3rd prior art example. It is a top view shown about the semiconductor device concerning the 3rd prior art example. It is a top view which shows equipotential line distribution which arises in the super-junction layer of the semiconductor device concerning a 3rd prior art example. It is sectional drawing shown about the semiconductor device concerning a 4th prior art example. It is a top view shown about the semiconductor device concerning the 4th prior art example.

Explanation of symbols

2 n-type drift region (first conductivity type semiconductor region)
3 p-type partition region (second conductivity type semiconductor region)
17a Inactive region (second)
17b Inactive region (first)
18 Active region _Sa1 charge imbalance region (first)
_Sa2 charge imbalance area (second)
S _b1 charge balance area (first)
W _n11 Width of n-type drift region (first)
W _n12 Width of n-type drift region (second)
W _{n13 Width of} n-type drift region (third)
W _{n14 Width of} n-type drift region (4th)
W _n15 Width of n-type drift region (5th)
W _n16 Width of n-type drift region (6th)
W _p11 Width of the p-type partition area (first)
W _p12 Width of p-type partition region (second)
W _p13 Width of p-type partition region (third)
W _p16 Width of p-type partition area (sixth)
Y from the uppermost end of the Y depth direction radius L _Y1 active region of the corner portion of the distance R _Y1 active region of the X width direction from the top end of the X width direction radius R _X2 active region of the corner portion of R _X1 active region Distance in the depth direction

Claims (25)

A semiconductor substrate having a high impurity concentration, a parallel pn layer provided on the surface of the semiconductor substrate, in which a first conductive type semiconductor region and a second conductive type semiconductor region are alternately arranged, and the second conductive type semiconductor region A second conductivity type base region provided in the surface layer; a first conductivity type source region provided in the surface layer of the base region; and a surface of the parallel pn layer provided via a gate insulating film A gate electrode, and a source electrode electrically connected to the source region and the base region and provided apart from the gate electrode, and a current is supplied when the parallel pn layer is in an on state. In the semiconductor device disposed in both the active region that flows and the non-active region around the active region,
The parallel pn layer is formed on the first main surface of the semiconductor substrate such that the first conductive type semiconductor region and the second conductive type semiconductor region have a stripe shape,
The non-active region includes a first non-active region and a second non-active region,
Surrounding at least a portion of the active region with the second non-active region;
In the first inactive region, the total impurity amount of the first conductivity type semiconductor region and the total impurity amount of the second conductivity type semiconductor region are substantially equal,
In the second inactive region, the width of the second conductive type semiconductor region gradually increases as the distance from the boundary with the active region increases in at least a part of the parallel pn layer, and the first conductive type semiconductor A semiconductor device, wherein the total impurity amount of the second conductivity type semiconductor region is larger than the total impurity amount of the region. The width W _{n11 of} the first conductive semiconductor region at the boundary between the active region and the second inactive region, and the width W _n of the second conductive semiconductor region at the boundary between the active region and the second inactive region. _p11 , a width W _{n12 of} the first conductivity type semiconductor region at a position of a distance L _Y1 from the outermost periphery of the active region in the direction of the second inactive region in parallel with the depth direction of the semiconductor substrate, and the semiconductor Parallel to the depth direction of the substrate, the width W _p12 of the second conductivity type semiconductor region at a position of distance L _Y1 from the outermost periphery of the active region to the direction of the second inactive region is:
W _n11 > W _n12
And,
W _p11 <W _p12
And,
W _n11 + W _p11 = W _n12 + W _p12
And,
tan ⁻¹ ((W _n11 −W _n12 ) / (2 · L _Y1 )) ≦ 2 degrees and
2. The semiconductor device according to claim 1, wherein tan ⁻¹ ((W _p12 −W _p11 ) / (2 · L _Y1 )) ≦ 2 degrees is satisfied. 1.05 ≦ W _p12 / W _n12 ≦ 2.0
The semiconductor device according to claim 2, further satisfying: 1.05 ≦ W _p12 / W _n12 ≦ 1.3
The semiconductor device according to claim 2, further satisfying: 1.05 ≦ W _p12 / W _n12 ≦ 1.2
The semiconductor device according to claim 2, further satisfying:   The outermost periphery of the active region has a first straight portion that is substantially parallel to the width direction of the semiconductor substrate, a second straight portion that is substantially parallel to the depth direction of the semiconductor substrate, the first straight portion, and the The semiconductor device according to claim 1, wherein the semiconductor device is formed by an arc-shaped portion that connects the second straight portion.   The semiconductor device according to claim 6, wherein the arc-shaped portion is a part of a circumference.   The semiconductor device according to claim 6, wherein the arc-shaped portion is a part of a circumference of an ellipse.   The arcuate portion is divided into a first curved portion and a second curved portion, and further includes a third straight portion connecting the respective ends of the first curved portion and the second curved portion. 7. The semiconductor device according to claim 6, further comprising: An insulating film having a thickness greater than that of the gate insulating film on a surface of the parallel pn layer of the inactive region;
A field plate electrode provided on the surface of the parallel pn layer of the inactive region via the insulating film;
The semiconductor device according to claim 1, further comprising:   The outermost periphery of the field plate electrode in the width direction of the semiconductor substrate is in the second inactive region or on the inner periphery or the outermost periphery of the second inactive region in the width direction of the semiconductor substrate. The semiconductor device according to claim 10, wherein the semiconductor device is in any one of the above positions.   The outermost periphery of the field plate electrode in the depth direction of the semiconductor substrate is in the second inactive region or on the inner periphery or the outermost periphery of the second inactive region in the depth direction of the semiconductor substrate. The semiconductor device according to claim 10, wherein the semiconductor device is in any one of the above positions.   The semiconductor device according to claim 10, wherein a thickness of the insulating film is substantially uniform.   The semiconductor device according to claim 10, wherein a surface of the insulating film that is in contact with the field plate electrode is gradually thinned toward an end portion of the insulating film.   The surface of the insulating film in contact with the field plate electrode has two or more steps and becomes thinner toward the end of the insulating film. A semiconductor device according to 1.   The semiconductor device according to claim 10, wherein the field plate electrode has the same potential as the source electrode.   The semiconductor device according to claim 10, wherein the field plate electrode has the same potential as the gate electrode.   The semiconductor device according to claim 10, wherein the field plate electrode has a floating potential. Completely enclosing the active region with the second inactive region;
19. The semiconductor device according to claim 1, wherein a second inactive region in a depth direction of the semiconductor substrate is surrounded by the first inactive region. Surrounding the active region in the width direction of the semiconductor substrate and at least a part of the arc-shaped portion of the active region with the second inactive region,
19. The method according to claim 1, wherein the second non-active region and the active region not surrounded by the second non-active region are completely surrounded by the first non-active region. The semiconductor device as described in any one. Completely enclosing the active region with the second inactive region;
The semiconductor device according to claim 1, wherein the second inactive region is completely surrounded by the first inactive region. The non-active region further includes a third non-active region,
In the third inactive region, the total impurity amount of the first conductive type semiconductor region and the total impurity amount of the second conductive type semiconductor region are substantially equal,
Surrounding the active region in the width direction of the semiconductor substrate and at least a part of the arc-shaped portion of the active region with the third inactive region,
The semiconductor device according to claim 1, wherein the third inactive region is completely surrounded by the second inactive region.   23. The semiconductor device according to claim 22, wherein the active region is completely surrounded by the third non-active region.   24. The semiconductor device according to claim 22, wherein the first inactive region is formed outside the second inactive region along an end in the width direction of the semiconductor substrate.   24. The semiconductor device according to claim 22, wherein the second inactive region is completely surrounded by the first inactive region.

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