JP2010054364A - Drive circuit of photomultiplier tube - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a drive circuit of a photomultiplier tube capable of holding a stable dynode voltage, while suppressing power consumption and maintaining proper linearity of the output current, with respect to the quantity of incident light. <P>SOLUTION: A PMT drive circuit 1A includes a DC current source 11, having a negative electrode 11a to be connected to a cathode K; a transistor group 12, in which drain terminals of FETs 12a-12h are connected directly to the negative electrode 11a and source terminals of the FETs 12a-12h are connected to dynodes Dy1-Dy8; and a resistor-dividing circuit 13 that applies gradient potentials Va-Vh, obtained by dividing a potential difference between a positive electrode 11b and the negative electrode 11a of the DC current source 11, with the use of resistors to gate terminals of the FETs 12a-12h; and the PMT drive circuit 1A is, further, equipped with a capacitor group 14, including a plurality of serially connected capacitors 14a-14i, in which one end and the other end are respectively connected to the negative electrode 11a and the positive electrode 11b and connection points between adjacent capacitors are connected to the respective gate terminals of the FETs 12a-12h. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a photomultiplier tube driving circuit.

  In a photomultiplier tube, a plurality of dynodes are arranged between a cathode (photocathode) to which a high voltage is applied and an anode, and the plurality of dynodes are biased to a predetermined voltage. When light enters the cathode, it is converted into electrons (photoelectrons), and is multiplied at a high multiplication factor each time the electrons collide with a plurality of dynodes. The number of electrons (secondary electrons) thus increased is proportional to the amount of incident light, and the increased electrons are output from the anode as the output current of the photomultiplier tube.

  A voltage dividing circuit is used as the most basic circuit for setting the bias voltage of each dynode (hereinafter referred to as dynode voltage). The voltage dividing circuit divides a high voltage applied between the cathode and the anode by a plurality of series resistors and applies the divided voltage to each dynode. However, when such a voltage divider circuit is used, the resistance value of each resistive element is reduced to increase the amount of current flowing through the voltage divider circuit in order to ensure sufficient output current and maintain the linearity of the multiplication factor. There is a problem that power consumption increases.

  A circuit for solving such a problem in the voltage dividing circuit is disclosed in Patent Document 1, for example. FIG. 11 is a circuit diagram showing a bleeder circuit of a photomultiplier tube disclosed in Patent Document 1.

  In the bleeder circuit 100 shown in FIG. 11, the high voltage from the high-voltage power supply 101 is divided by the series resistors 102a to 102i, and the divided voltage generated by the resistors 102a to 102e is divided into the front side (cathode 104) of the photomultiplier tube 103. Are directly applied to the five dynodes 105a to 105e. The emitter voltages of the PNP transistors 107a to 107c are applied to the three dynodes 105f to 105h on the rear stage side (the anode 106 side), and the base terminals of the PNP transistors 107a to 107c are connected to the resistors 102f to 102i. Biased with the resulting split voltage. A bias resistor 102j is connected to the emitter terminal of the PNP transistor 107c. A capacitor 108 for stabilizing the bias voltage of the PNP transistors 107a to 107c is connected to the collector terminal of the PNP transistor 107a, and current is supplied from the high voltage power source 101 to the PNP transistors 107a to 107c through the resistor 102k.

In this bleeder circuit 100, by utilizing the fact that the base-emitter voltage of the PNP transistors 107a to 107c is constant, the dynode voltage of the dynodes 105f to 105h is stabilized and the linearity of the multiplication factor is improved. . Further, since the current consumed as secondary electrons in the dynodes 105f to 105h is supplied from the PNP transistors 107a to 107c, the resistance values of the series resistors 102a to 102i can be increased to reduce the current flowing through these resistors. Power consumption is reduced as compared with the case of using a voltage dividing circuit.
Japanese Patent Laid-Open No. 62-126540

  However, in the bleeder circuit 100 shown in FIG. 11, the collector current flowing through the PNP transistors 107a to 107c is supplied from the power supply 101 through the resistor 102k. Therefore, useless power loss occurs in the resistor 102k, and sufficient power consumption cannot be reduced.

  When the collector current flowing through the PNP transistors 107a to 107c is remarkably increased, the voltage across the resistor 102k increases. However, the emitter potential of the PNP transistor 107a depends only on the potential at the connection point between the resistor 102f and the resistor 102g. . Therefore, the voltage across the resistor 102k cannot be greater than the voltage value obtained by subtracting the emitter potential of the PNP transistor 107a from the voltage value of the power supply 101. By limiting the voltage value at both ends of the resistor 102k, the amount of current flowing through the resistor 102k, that is, the amount of collector current flowing through the PNP transistors 107a to 107c is limited, which causes the linearity of the multiplication factor to be impaired.

  Further, when a bipolar transistor is used as an active element that supplies current to the dynodes 105f to 105h as in the bleeder circuit 100, a current corresponding to the product of the collector current and the reciprocal of the DC current multiplication factor (hFE) It flows to the base through 102a to 102h. Therefore, the voltage distribution of the resistors 102a to 102h is likely to fluctuate, and there is a problem in the stability of the dynode voltage.

  The present invention has been made in view of the above-mentioned problems, and is a photomultiplier tube drive capable of stably maintaining the dynode voltage while maintaining power and reducing the power consumption and maintaining the linearity of the output current with respect to the amount of incident light. An object is to provide a circuit.

  In order to solve the above problems, a photomultiplier tube driving circuit according to the present invention has a cathode for emitting photoelectrons corresponding to the amount of incident light and dynodes arranged in n stages (n is an integer of 1 or more) to multiply photoelectrons. A photomultiplier tube driving circuit that is connected to a photomultiplier tube having a multiplier unit and an anode that collects electrons multiplied by the multiplier unit, and applies a predetermined potential gradient to the cathode and the n-stage dynode. A negative power source connected to the negative electrode, and m (m is an integer from 1 to n) transistors, one current terminal of each of the m transistors being connected to the other transistor Alternatively, a transistor group that is directly connected to the negative electrode of the DC power supply, and the other current terminal of each of the m transistors is connected to the corresponding dynode among the n-stage dynodes, and the positive electrode of the DC power supply A resistance dividing circuit for generating a potential gradient by dividing the potential difference with the negative electrode by resistance, and applying the gradient potential to each of the control terminals of the m transistors; and a plurality of capacitors connected in series to each other; Is connected to the negative electrode of the DC power supply, the other end is connected to the positive electrode of the DC power supply, and a connection point between adjacent capacitors is connected to a control terminal of a transistor corresponding to each connection point. It is characterized by that.

  In the photomultiplier tube driving circuit, each dynode voltage is defined by the gradient potential from the resistance dividing circuit applied to the control terminal of the transistor included in the transistor group, and the current consumed as secondary electrons in the dynode is determined by the transistor. Therefore, it is possible to increase the resistance value of the resistance dividing circuit and reduce power consumption.

  Further, the photomultiplier tube driving circuit includes a capacitor group including a plurality of capacitors connected in series with each other. One end of this capacitor group is connected to the negative electrode of the DC power supply, and the other end is connected to the positive electrode of the DC power supply. A connection point between adjacent capacitors is connected to a control terminal of a transistor corresponding to each connection point. Such a capacitor group alleviates the voltage fluctuation between the control terminals of the transistor, and hence the fluctuation of the dynode voltage, so that a rapidly changing light such as step light or pulse light is incident on the cathode. However, it is possible to keep the dynode voltage stable and maintain good linearity of the output current with respect to the amount of incident light.

  In the photomultiplier tube driving circuit, one current terminal of each of the m transistors is connected to the negative electrode of the DC power supply via the other transistor or directly. That is, the transistor and the negative electrode of the DC power supply are connected to each other without using a resistance element such as the resistor 102k in FIG. Thereby, the resistance loss when the electric charge is supplied from the DC power source to the transistor is remarkably reduced, and the power consumption can be sufficiently reduced. In addition, there is no current limitation due to the limitation of the voltage across the resistance element such as the resistor 102k in FIG. 11, and sufficient linearity of the multiplication factor is maintained even when the amount of output current is large. it can. In addition, an increase in dark current of the photomultiplier tube due to heat generated by resistance loss can be prevented.

  In the photomultiplier tube driving circuit, m transistors of the transistor group are connected in series with each other, and one current terminal of the transistor located at one end thereof is short-circuited to the negative electrode of the DC power supply. May be a feature. With such a configuration, the charge from the DC power source can be suitably supplied to one current terminal of each transistor of the transistor group.

  The photomultiplier tube driving circuit may be characterized in that the m transistors are field effect transistors (FETs). In this way, by using an FET instead of a bipolar transistor as an active element that supplies current to the dynode, when a gradient potential is applied from the resistance divider circuit to the control terminal of the FET, the resistance divider circuit is not switched to the active element. Since no current flows and fluctuations in voltage distribution in the resistance divider circuit can be more effectively suppressed, the dynode voltage can be kept more stable.

  The photomultiplier tube driving circuit may be characterized in that m transistors are P-channel FETs, one current terminal is a drain terminal, and the other current terminal is a source terminal. With such a configuration, it is possible to suitably supply the electric charge consumed in each dynode via the source terminal of each FET while defining each dynode voltage in accordance with the voltage applied to the gate terminal of each FET.

  In the photomultiplier tube driving circuit, the number m of transistors is 1/3 or more of the number n of dynodes, and the transistors are connected to the dynodes from the last stage closest to the anode to the m-th stage. This may be a feature. The dynode on the rear side near the anode has a larger amount of charge (secondary electrons) output than the dynode on the front side near the cathode, and the dynode voltage is likely to fluctuate. Therefore, by supplying charges from the transistor to the dynodes counting from the side close to the anode in this way, it is possible to effectively maintain good linearity of the output current with respect to the incident light amount.

  The photomultiplier tube driving circuit may be characterized in that the number m of transistors is equal to the number n of dynodes, and the transistors are connected to all the dynodes from the first stage to the n-th stage. Thereby, the voltage fluctuation in all the dynodes of a photomultiplier tube can be suppressed effectively, and the favorable linearity of the output current with respect to incident light quantity can be maintained more effectively.

  The photomultiplier tube driving circuit may further include a capacitor connected between the other current terminal of one transistor and the other current terminal of the other transistor included in the transistor group. Good. Thereby, the voltage fluctuation between dynodes can further be suppressed.

  The photomultiplier tube driving circuit may further include a Zener diode connected between a control terminal of the transistor included in the transistor group and the other current terminal. Thereby, a transistor can be protected suitably.

  In the present invention, when the transistor is a bipolar transistor, the control terminal means a base terminal, and the current terminal means an emitter terminal and a collector terminal. When the transistor is an FET, the control terminal means a gate terminal, and the current terminal means a source terminal and a drain terminal.

  According to the present invention, in the photomultiplier tube driving circuit connected to the photomultiplier tube, it is possible to keep the dynode voltage stable while suppressing power consumption, and to maintain good linearity of the output current with respect to the incident light amount. .

  Embodiments of a photomultiplier tube driving circuit according to the present invention will be described below in detail with reference to the accompanying drawings. In the description of the drawings, the same elements are denoted by the same reference numerals, and redundant description is omitted.

(First embodiment)
FIG. 1 is a circuit diagram showing a configuration of a PMT drive circuit 1A as a first embodiment of a photomultiplier tube (hereinafter referred to as PMT) drive circuit according to the present invention. As shown in FIG. 1, the PMT drive circuit 1A is used connected to the PMT2.

  The PMT 2 includes a cathode (photocathode) K that emits photoelectrons according to the amount of incident light L to be measured, a multiplier D that multiplies photoelectrons, and an anode that collects the electrons multiplied by the multiplier D. P is inside the vacuum tube T. The multiplication unit D has first to nth dynodes arranged in n stages (n is an integer of 1 or more). In FIG. 1, n = 8, and the first to eighth dynodes Dy1 to Dy8 are shown. The dynode Dy1 is arranged at a position for receiving photoelectrons from the cathode K, and the dynodes Dy2 to Dy8 are arranged at positions for receiving secondary electrons from the preceding dynode. The anode P is disposed at a position for receiving secondary electrons from the dynode Dy8.

  The PMT drive circuit 1A is connected to the PMT2 and applies a predetermined potential gradient to the cathode K and the dynodes Dy1 to Dy8. The PMT drive circuit 1A includes a DC power supply 11, a transistor group 12, a resistance dividing circuit 13, and a capacitor group 14. The DC power supply 11 is a high-voltage power supply device. The negative electrode 11 a of the DC power supply 11 is connected to the cathode K of the PMT 2, and the positive electrode 11 b of the DC power supply 11 is connected to a reference potential line (GND line) 15.

  The transistor group 12 includes m (m is an integer of 1 to n) P-channel FETs. In FIG. 1, m = 8, which is equal to the number of stages of dynodes Dy1 to Dy8. One current terminal (drain terminal in FIG. 1) of the eight P-channel FETs 12 a to 12 h included in the transistor group 12 is directly connected to the negative electrode 11 a of the DC power supply 11. Here, the term “directly connected” means that no resistive element or other electric element including a resistance component is used, and the short-circuit is caused by a low-resistivity wiring, terminal, or connector provided only for conduction. That means. The other current terminals (source terminals in FIG. 1) of the FETs 12a to 12h are connected to the corresponding dynodes among the dynodes Dy1 to Dy8. In this embodiment, since the number m of the FETs 12a to 12h is equal to the number n of stages of the dynodes Dy1 to Dy8, the FETs are connected to all the dynodes of the PMT2.

  The resistance dividing circuit 13 is a circuit that generates a potential gradient by dividing the potential difference between the negative electrode 11a and the positive electrode 11b of the DC power supply 11 and applies the gradient potential to each of the gate terminals of the FETs 12a to 12h. The resistive divider circuit 13 has (n + 1) resistive elements 13a to 13i, and these resistive elements 13a to 13i are connected in series in this order. One end (one end of the resistance element 13a) of the series circuit including the resistance elements 13a to 13i is connected to the negative electrode 11a of the DC power source 11, and the other end (the other end of the resistance element 13i) is the positive side of the DC power source 11. It is connected to the electrode 11b. With such a configuration, in the resistance dividing circuit 13, the potential Va is generated at the connection point between the resistance element 13a and the resistance element 13b, and the potential Vb is generated at the connection point between the resistance element 13b and the resistance element 13c. Potentials Vc to Vh are generated at connection points of the resistance elements 13c to 13i. Note that there is a relationship of Va <Vb <Vc <Vd <Ve <Vf <Vg <Vh between these potentials Va to Vh, and the resistance dividing circuit 13 uses each of the gradient potentials Va to Vh. It applies to each gate terminal of FET12a-12h.

  The capacitor group 14 includes (m + 1) capacitors 14a to 14i connected in series with each other. One end (one end of the capacitor 14a) of the series circuit including the capacitors 14a to 14i is connected to the negative electrode 11a of the DC power supply 11, and the other end (the other end of the capacitor 14i) is connected to the positive electrode 11b of the DC power supply 11. ing. A connection point between adjacent capacitors among the capacitors 14a to 14i is connected to the gate terminals of the FETs 12a to 12h corresponding to the connection points. That is, the connection point between the capacitor 14a and the capacitor 14b is connected to the gate terminal of the FET 12a, the connection point between the capacitor 14b and the capacitor 14c is connected to the gate terminal of the FET 12b, and thereafter each of the capacitors 14c to 14i. The connection points are connected to the gate terminals of the FETs 12c to 12h, respectively.

  In the PMT drive circuit 1A having the above configuration, the voltages of the dynodes Dy1 to Dy8 are defined by the gradient potentials Va to Vh from the resistance dividing circuit 13 applied to the gate terminals of the FETs 12a to 12h included in the transistor group 12. Yes. And since the electric current consumed as a secondary electron in dynodes Dy1-Dy8 is supplied from FET12a-12h, it becomes possible to enlarge the resistance value of the resistance divider circuit 13, and to reduce power consumption. Furthermore, the current supplied from the source terminals of the FETs 12a to 12h to the dynodes Dy1 to Dy8 does not flow while the light to be measured L is not incident on the PMT2, so that the power consumption is remarkably higher than that of the circuit shown in FIG. Can be reduced. Therefore, power consumption and heat generation can be greatly reduced, and the capacity of the DC power supply 11 can be reduced. And generation | occurrence | production of the dark current of PMT2 can also be suppressed by reduction of the emitted-heat amount.

  Further, the following effects can be obtained by the capacitor group 14 included in the PMT drive circuit 1A. That is, since the capacitor 14a connected between the negative electrode 11a of the DC power supply 11 and the gate terminal of the FET 12a reduces the voltage fluctuation of the gate terminal of the FET 12a with respect to the negative electrode 11a, the voltage fluctuation of the dynode Dy1 is reduced. The Rukoto. Similarly, voltage fluctuations at the gate terminals of the FETs 12b to 12h are alleviated by the capacitors 14b to 14i, and consequently voltage fluctuations at the dynodes Dy2 to Dy8 are alleviated. Therefore, even when light that changes rapidly, such as step light or pulse light, is incident on the cathode K as the light to be measured L, the voltage of the dynodes Dy1 to Dy8 is kept stable, and the output current with respect to the amount of incident light has a good straight line. Sex can be maintained.

  In the PMT drive circuit 1A, one current terminal (drain terminal) of each of the FETs 12a to 12h is directly connected to the negative electrode 11a of the DC power supply 11. That is, the drain terminals of the FETs 12a to 12h and the negative electrode 11a of the DC power supply 11 are short-circuited without using a resistance element such as the resistor 102k in FIG. Therefore, the resistance loss when the charge is transferred from the DC power supply 11 to the FETs 12a to 12h is remarkably reduced, and the power consumption can be sufficiently reduced.

  Further, as described above, if there is a resistive element such as the resistor 102k in FIG. 11, the voltage value across the resistor 102k cannot be greater than the potential difference between the negative electrode of the power supply 101 and the emitter of the transistor 107a. The current flowing through the resistor 102k is limited. On the other hand, in the PMT drive circuit 1A of the present embodiment, the drain terminals of the FETs 12a to 12h and the negative electrode 11a of the DC power supply 11 are short-circuited with each other without using a resistance element. Even when there is no limit and the amount of output current is large, sufficient linearity of the multiplication factor can be maintained.

  Further, as described above, if there is a resistive element such as the resistor 102k in FIG. 11, the dark current of the photomultiplier tube 103 increases due to the heat generated by the resistor 102k. In the PMT drive circuit 1A of the present embodiment, the drain terminals of the FETs 12a to 12h and the negative electrode 11a of the DC power supply 11 are short-circuited to each other without going through a resistance element, so that the dark current of the PMT2 due to heat generated by resistance loss Can also be prevented.

  Further, as in the present embodiment, FETs 12a to 12h are used instead of bipolar transistors as active elements for supplying current to the dynodes Dy1 to Dy8, and the gradient potential Va to the gate terminals of the FETs 12a to 12h from the resistor dividing circuit 13. It is preferable to apply Vh. As a result, no current flows from the resistor divider circuit 13 to the active element, and fluctuations in voltage distribution in the resistor divider circuit 13 can be more effectively suppressed, so that the voltages at the dynodes Dy1 to Dy8 can be kept more stable. it can. Note that bipolar transistors may be used in place of the FETs 12a to 12h as the transistors constituting the transistor group 12. In that case, one current terminal (for example, collector terminal) of each transistor included in the transistor group 12 is directly connected to the negative electrode 11 a of the DC power supply 11. The other current terminal (for example, emitter terminal) of each transistor is connected to a corresponding dynode among dynodes Dy1 to Dy8. The gradient potentials Va to Vh are applied from the resistance dividing circuit 13 to the base terminal which is the control terminal of each transistor.

  Further, as in this embodiment, in the PMT drive circuit 1A, P-channel FETs are employed as the FETs 12a to 12h, and one current terminal connected to the negative electrode 11a of the DC power supply 11 is a drain terminal. The other current terminal connected to the dynodes Dy1 to Dy8 is preferably a source terminal. With such a configuration, the charges consumed in the dynodes Dy1 to Dy8 are defined as the sources of the FETs 12a to 12h while the voltages of the dynodes Dy1 to Dy8 are defined according to the voltages applied to the gate terminals of the FETs 12a to 12h. It can supply suitably via a terminal.

  Further, as in the present embodiment, in the PMT drive circuit 1A, the number of FETs 12a to 12h is preferably equal to the number of stages of the dynodes Dy1 to Dy8, and the FETs 12a to 12h are preferably connected to all the dynodes Dy1 to Dy8. Thereby, the voltage fluctuation in all the dynodes Dy1-Dy8 of PMT2 can be suppressed effectively, and the favorable linearity of the output current with respect to incident light quantity can be maintained more effectively.

(Modification)
In the above embodiment, the PMT drive circuit 1A may further include Zener diodes 21a to 21h connected between the gate terminals and the source terminals of the FETs 12a to 12h as shown in FIG. Specifically, the cathode of the Zener diode 21a is connected to the source terminal of the FET 12a, and the anode of the Zener diode 21a is connected to the gate terminal of the FET 12a. Similarly, the cathodes of the Zener diodes 21b to 21h are connected to the source terminals of the corresponding FETs 12b to 12h, respectively, and the anodes of the Zener diodes 21b to 21h are connected to the gate terminals of the corresponding FETs 12b to 12h, respectively. By providing such Zener diodes 21a to 21h in the PMT drive circuit 1A, the FETs 12a to 12h can be suitably protected from overvoltage.

(Second Embodiment)
FIG. 3 is a circuit diagram showing a configuration of a PMT drive circuit 1B as a second embodiment of the PMT drive circuit according to the present invention. As shown in FIG. 3, the PMT drive circuit 1B is connected to the PMT2 and used. However, the configuration of the PMT2 is the same as that of the first embodiment described above, and thus the description regarding the PMT2 is omitted.

  The PMT drive circuit 1 </ b> B includes a plurality of capacitors 17 a to 17 c provided separately from the DC power supply 11, the resistor divider circuit 13, the capacitor group 14, the transistor group 16, and the capacitor group 14. Among these components, the configurations of the DC power supply 11, the resistance dividing circuit 13, and the capacitor group 14 are the same as those in the first embodiment.

  The transistor group 16 has m P-channel FETs. In FIG. 3, m = 8, which is equal to the number of stages of dynodes Dy1 to Dy8. One current terminal (drain terminal in FIG. 3) of the eight P-channel FETs 16a to 16h included in the transistor group 16 is connected to the negative electrode of the DC power supply 11 via another FET included in the transistor group 16 or directly. 11a. Specifically, m FETs 16 a to 16 h of the transistor group 16 are connected to each other in series, and the drain terminal of the FET 16 a located at one end thereof is short-circuited to the negative electrode 11 a of the DC power supply 11. The FETs 16a to 16h being connected to each other in series refers to a state in which the drain terminals of one adjacent FET and the source terminal of the other FET are connected to each other in the FETs 16a to 16h.

  The other current terminals (source terminals in FIG. 3) of the FETs 16a to 16h are connected to corresponding dynodes among the dynodes Dy1 to Dy8. Therefore, for example, the dynode Dy1 is connected to the source terminal of the FET 16a and the drain terminal of the FET 16b, and the dynode Dy2 is connected to the source terminal of the FET 16b and the drain terminal of the FET 16c. In the present embodiment, since the number of FETs 16a to 16h is equal to the number of stages of dynodes Dy1 to Dy8, the FETs are connected to all dynodes of PMT2. The source terminal of the FET 16 h located at the other end of the transistor group 16 is connected to the positive electrode 11 b (that is, the reference potential) of the DC power supply 11 through the bias resistor 18.

  Further, the gradient potentials Va to Vh generated in the resistance dividing circuit 13 are applied to the gate terminals of the FETs 16a to 16h, respectively. Furthermore, the connection point of adjacent capacitors among the capacitors 14a to 14i is connected to the gate terminals of the FETs 16a to 16h corresponding to the connection points. That is, the connection point between the capacitor 14a and the capacitor 14b is connected to the gate terminal of the FET 16a, the connection point between the capacitor 14b and the capacitor 14c is connected to the gate terminal of the FET 16b, and thereafter each of the capacitors 14c to 14i. The connection points are connected to the gate terminals of the FETs 16c to 16h, respectively.

  The capacitor 17a is connected between the source terminal of the FET 16f and the source terminal of the FET 16g among the FETs 16a to 16h included in the transistor group 16. The capacitor 17b is connected between the source terminal of the FET 16g and the source terminal of the FET 16h. The capacitor 17c is connected between the source terminal of the FET 16h and the positive electrode 11b of the DC power supply 11.

  In the PMT drive circuit 1B having the above configuration, the gradient potential Va from the resistance dividing circuit 13 applied to the gate terminals of the FETs 16a to 16h included in the transistor group 16 is the same as the PMT drive circuit 1A of the first embodiment. The voltages of dynodes Dy1 to Dy8 are defined by ~ Vh. And since the electric current consumed as a secondary electron in dynodes Dy1-Dy8 is supplied from FET16a-16h, it becomes possible to enlarge the resistance value of the resistive divider circuit 13, and to reduce power consumption. Furthermore, since the current supplied from the source terminals of the FETs 16a to 16h to the dynodes Dy1 to Dy8 does not flow while the measured light L is not incident on the PMT2, the power consumption can be significantly reduced. Therefore, power consumption and heat generation can be greatly reduced, and the capacity of the DC power supply 11 can be reduced. And generation | occurrence | production of the dark current of PMT2 can also be suppressed by reduction of the emitted-heat amount.

  In the PMT drive circuit 1B, the FETs 16a to 16h are connected in series, and one current terminal (drain terminal) of the FET 16a located at one end thereof is directly connected to the negative electrode 11a of the DC power supply 11. That is, the FETs 16a to 16h and the negative electrode 11a of the DC power source 11 are connected to each other without using a resistance element such as the resistor 102k in FIG. Therefore, the resistance loss when the charge is transferred from the DC power supply 11 to the FETs 16a to 16h is remarkably reduced, and the power consumption can be sufficiently reduced.

  Further, the voltage fluctuations of the gate terminals of the FETs 16a to 16h are alleviated by the capacitors 14a to 14i of the capacitor group 14, and the voltage fluctuations of the dynodes Dy1 to Dy8 are alleviated. Therefore, even when the rapidly changing light is incident on the cathode K as the light to be measured L, the voltage of the dynodes Dy1 to Dy8 can be kept stable, and good linearity of the output current with respect to the amount of incident light can be maintained. it can.

  Here, the effect of the capacitor group 14 will be described in more detail. As a comparison, FIG. 4 shows a PMT drive circuit 200 including one capacitor 201 instead of the capacitor group 14. One end of the capacitor 201 is connected to the negative electrode 11a of the DC power supply 11, and the other end is connected to the positive electrode 11b. Other configurations in the PMT drive circuit 200 are the same as those in the PMT drive circuit 1B.

  FIGS. 5 and 6 show the state of the output current when the pulsed light to be measured L is incident on each of the two PMT drive circuits 1B and 200. FIG. FIG. 5 shows the waveform of the measured light L in the PMT drive circuit 1B of the present embodiment and the waveform of the corresponding output current I, and FIG. 6 shows the measured light in the PMT drive circuit 200 as a comparative example. The waveform of L and the waveform of the corresponding output current I are shown. 5 and 6, the light quantity of the measured light L is larger in (b) than in (a), and the light quantity of the measured light L is larger in (c) than in (b). ing. 5 and 6, the vertical axis indicates the light amount or the current amount, and the horizontal axis indicates time.

  As shown in FIG. 6, in the PMT drive circuit 200, the potential of the dynodes Dy1 to Dy8 is swung as the light amount of the light L to be measured increases, and the waveform of the output current I is also distorted. On the other hand, as shown in FIG. 5, in the PMT drive circuit 1B of the present embodiment, the potentials of the dynodes Dy1 to Dy8 are stabilized by the capacitor group 14, so that even if the amount of the light L to be measured increases. Output current is stable. As described above, the voltage fluctuations of the dynodes Dy1 to Dy8 are alleviated by the capacitor group 14, so that the potential of the dynodes Dy1 to Dy8 is stably maintained even for the light L to be measured that changes rapidly, and the output current is good. Linearity can be maintained.

  Furthermore, the following effects are provided as effects unique to the present embodiment. That is, in the circuit shown in FIG. 11, since the magnitude of the collector current of the transistors 107a to 107c is proportional to the magnitude of the output current at the anode 106 of the PMT 103, the voltage across the resistor 102k varies greatly according to the output current. The collector voltage of the transistor 107a changes greatly. For this reason, it is necessary to use a high voltage transistor as the transistor 107a. On the other hand, in the PMT drive circuit 1B of the present embodiment, the FETs 16a to 16h are connected in series, and the drain terminal of the FET 16a located at the end and the negative electrode 11a of the DC power supply 11 are mutually connected without a resistance element. It is short-circuited. Therefore, the drain voltage of the FET 16a hardly changes, and the high voltage of the DC power supply 11 is distributed to the plurality of FETs 16a to 16h, so that the withstand voltage requirements for the FETs 16a to 16h can be relaxed.

  Further, in the PMT drive circuit 1B of the present embodiment, capacitors 17a and 17b are provided between the source terminals of the FETs 16f to 16h, and further between the source terminal of the FET 16h and the positive electrode 11b (that is, the reference potential) of the DC power supply 11. A capacitor 17c is provided. By providing these capacitors 17a to 17c, the voltage fluctuations of the dynodes Dy6 to Dy8 on the rear stage side can be further suppressed. For example, the response speed with respect to the high-speed pulse waveform is increased, and the linearity of the output current with respect to the incident light quantity is further increased. Can do.

  Further, as in this embodiment, the source terminal of the FET 16 h located at the other end of the transistor group 16 may be connected to the positive electrode 11 b of the DC power supply 11 via the bias resistor 18. The bias resistor 18 can further stabilize the potentials of the dynodes Dy1 to Dy8. In the PMT drive circuit 1B, since the necessary charge is supplied from the negative electrode 11a of the DC power supply 11 to the dynodes Dy1 to Dy8 via the FETs 16a to 16h, the bias resistor 18 can be omitted. Even if the bias resistor 18 is provided, the amount of current to each of the dynodes Dy1 to Dy8 is not limited thereby, and a high output current can be realized. When the bias resistor 18 is provided, current consumption can be suppressed by increasing the resistance value of the bias resistor 18.

  In the PMT drive circuit 1B of the present embodiment, the Zener diodes 21a to 21h shown in FIG. 2 are provided between the gate terminals and the source terminals of the FETs 16a to 16h, respectively, so that the FETs 16a to 16h can be suitably prevented from overvoltage. Can protect.

(Third embodiment)
FIG. 7 is a circuit diagram showing a configuration of a PMT driving circuit 1C as a third embodiment of the PMT driving circuit according to the present invention. Also in this embodiment, the configuration of the PMT 2 is the same as that of the first embodiment described above.

  The PMT drive circuit 1 </ b> C includes a plurality of capacitors 17 a to 17 c provided separately from the DC power supply 11, the resistance dividing circuit 13, the transistor group 19, the capacitor group 22, and the capacitor group 22. Among these components, the configurations of the DC power supply 11 and the resistance dividing circuit 13 are the same as those of the first embodiment, and the configurations of the capacitors 17a to 17c are the same as those of the second embodiment.

  The difference between the transistor group 19 of this embodiment and the transistor group 16 of the second embodiment is the number of FETs. That is, in the transistor group 19 of the present embodiment, the number m of FETs is m = 4, which is 1/3 or more of the number of stages of the dynodes Dy1 to Dy8, specifically, half of the number of stages of the dynodes Dy1 to Dy8. Yes. One current terminal (drain terminal in FIG. 7) of the four P-channel FETs 19a to 19d included in the transistor group 19 is connected to the negative electrode of the DC power supply 11 via another FET included in the transistor group 19 or directly. 11a. Specifically, the FETs 19 a to 19 d of the transistor group 19 are connected in series with each other, and the drain terminal of the FET 19 a located at one end thereof is short-circuited to the negative electrode 11 a of the DC power supply 11.

  The other current terminals (source terminals in FIG. 7) of the FETs 19a to 19d are connected to the corresponding dynodes among the dynodes Dy1 to Dy8, that is, the four dynodes Dy5 to Dy8 on the rear stage side. Therefore, for example, the dynode Dy5 is connected to the source terminal of the FET 19a and the drain terminal of the FET 19b, and the dynode Dy6 is connected to the source terminal of the FET 19b and the drain terminal of the FET 19c. Note that the source terminal of the FET 19 d located at the other end of the transistor group 19 is connected to the positive electrode 11 b (that is, the reference potential) of the DC power supply 11 via the bias resistor 18.

  The resistance dividing circuit 13 resistance-divides the potential difference between the negative electrode 11a and the positive electrode 11b of the DC power supply 11 to generate a potential gradient, and applies the gradient potential to each of the gate terminals of the FETs 19a to 19d. However, this embodiment differs from the second embodiment in the following points. In the present embodiment, among the eight gradient potentials Va to Vh generated by the resistance elements 13a to 13i, four potentials Ve to Vh are applied to the gate terminals of the FETs 19a to 19d, respectively. The remaining potentials Va to Vd are directly applied to the dynodes Dy1 to Dy4 without going through the FET.

  The capacitor group 22 has (m + 1) capacitors 22a to 22e connected in series with each other. One end of the series circuit composed of the capacitors 22a to 22e (one end of the capacitor 22a) is connected to the negative electrode 11a of the DC power supply 11, and the other end (the other end of the capacitor 22e) is connected to the positive electrode 11b of the DC power supply 11. ing. A connection point between adjacent capacitors among the capacitors 22a to 22e is connected to the gate terminals of the FETs 19a to 19d corresponding to the connection points. That is, the connection point between the capacitor 22a and the capacitor 22b is connected to the gate terminal of the FET 19a, the connection point between the capacitor 22b and the capacitor 22c is connected to the gate terminal of the FET 19b, and thereafter each of the capacitors 22c to 22e. The connection point is connected to each gate terminal of the FETs 19c and 19d.

  In the PMT drive circuit 1C having the above configuration, the voltages of the dynodes Dy4 to Dy8 are defined by the gradient potentials Ve to Vh from the resistance dividing circuit 13 applied to the gate terminals of the FETs 19a to 19d included in the transistor group 19. ing. Then, the current consumed as secondary electrons in the dynodes Dy4 to Dy8 is supplied from the FETs 19a to 19d. As described above, even when a current is supplied to some dynodes of the PMT 2 via the FET, the resistance value of the resistance dividing circuit 13 can be increased to reduce the power consumption. Compared with this embodiment, the number of FETs m can be reduced to reduce the cost and size. In addition, since the current supplied from the source terminals of the FETs 19a to 19d to the dynodes Dy5 to Dy8 does not flow while the measured light L is not incident on the PMT2, the power consumption can be significantly reduced. Therefore, power consumption and heat generation can be greatly reduced, and the capacity of the DC power supply 11 can be reduced. And generation | occurrence | production of the dark current of PMT2 can also be suppressed by reduction of the emitted-heat amount.

  Further, in the case where current is supplied to some dynodes of the PMT2 through the FET as in this embodiment, the number m of the FETs 19a to 19d is equal to or more than 1/3 of the number n of dynodes Dy1 to Dy8 (in this embodiment). It is preferable that the FETs 19a to 19d are connected to the dynodes Dy5 to Dy8 from the last stage closest to the anode P to the m-th stage. The dynodes Dy5 to Dy8 on the rear stage side near the anode P have a larger amount of charges (secondary electrons) to be output than the dynodes Dy1 to Dy4 on the front stage side near the cathode K, and the dynode voltage tends to fluctuate. Therefore, by supplying charges from the FETs 19a to 19d to the dynodes Dy5 to Dy8 that are 1/3 or more counted from the side close to the anode P, it is possible to effectively maintain good linearity of the output current with respect to the incident light amount. Can do.

  Further, the voltage fluctuations at the gate terminals of the FETs 19a to 19d are alleviated by the capacitors 22a to 22e of the capacitor group 22, and the voltage fluctuations at the dynodes Dy5 to Dy8 are alleviated. Therefore, even when the rapidly changing light is incident on the cathode K as the light to be measured L, the voltage of the dynodes Dy5 to Dy8 can be kept stable, and good linearity of the output current with respect to the amount of incident light can be maintained. it can.

  In the PMT drive circuit 1C, the FETs 19a to 19d are connected in series with each other, and one current terminal (drain terminal) of the FET 19a located at one end thereof is directly connected to the negative electrode 11a of the DC power supply 11. That is, the FETs 19a to 19d and the negative electrode 11a of the DC power supply 11 are connected to each other without using a resistive element such as the resistor 102k in FIG. Therefore, the resistance loss when charges are transferred from the DC power supply 11 to the FETs 19a to 19d is remarkably reduced, and the power consumption can be sufficiently reduced.

  Also in the PMT drive circuit 1C of the present embodiment, the Zener diodes 21a to 21h shown in FIG. 2 are provided between the gate terminals and the source terminals of the FETs 19a to 19d, respectively, so that the FETs 19a to 19d are suitably prevented from overvoltage. Can protect.

(Fourth embodiment)
FIG. 8 is a circuit diagram showing a configuration of a PMT drive circuit 1D as a fourth embodiment of the PMT drive circuit according to the present invention. Also in this embodiment, the configuration of the PMT 2 is the same as that of the first embodiment described above.

  The PMT drive circuit 1D of the present embodiment is different from the PMT drive circuit 1C (FIG. 7) of the third embodiment in the configuration of the transistor group 23 and the capacitor group 24. That is, the transistor group 23 of the present embodiment has four FETs 23a to 23d (that is, m = 4) as in the transistor group 19 shown in FIG. 7, but the other current of the FET 23a located at one end thereof. Unlike the FET 19a in FIG. 7, the terminal (source terminal) is connected to the dynode Dy3. The control terminal (gate terminal) of the FET 23a is connected to a connection point between the resistance element 13c and the resistance element 13d, and a gradient potential Vc is applied to the gate terminal of the FET 23a. Of the gradient potentials Va to Vh generated by the resistance dividing circuit 13, four potentials Vc, Vf, Vg and Vh are applied to the gate terminals of the FETs 23a to 23d, respectively, and the remaining potentials Va, Vb, Vd and Ve are applied. Are directly applied to the corresponding dynodes Dy1, Dy2, Dy4, and Dy5 without going through the FET.

  Similarly to the capacitor group 22 shown in FIG. 7, the capacitor group 24 has (m + 1), that is, five capacitors 24a to 24e. The connection point between the capacitor 24a and the capacitor 24b is the gate of the FET 23a. The connection points of the capacitors 24b and 24c are connected to the gate terminal of the FET 23b, and the connection points of the capacitors 24c to 24e are connected to the gate terminals of the FETs 23c and 23d, respectively. Yes.

  When the number m of each FET constituting the FET group is smaller than the number n of dynodes as in this embodiment, each FET can be connected to an arbitrary dynode, and the effects described in the third embodiment are preferable. Can be played. In this case, with respect to at least three dynodes continuous from the dynode Dy8 toward the previous stage, including the last dynode Dy8 closest to the anode P, that is, at least each of the dynodes Dy6, Dy7, and Dy8 in the present embodiment. It is preferable that an FET is provided.

  In the transistor group 19 shown in FIG. 7, since the FET 19a located at the end supplies current to the fifth-stage dynode Dy5, the drain terminal of the FET 19a short-circuited to the negative electrode 11a of the DC power supply 11 and the gate A large potential difference is generated between the terminal and the source terminal. For this reason, higher voltage resistance is required for the FET 19a. In contrast, in the present embodiment, the FET 23a located at the end supplies current to the third-stage dynode Dy3, and the potential difference between the adjacent FET 23b is larger than that in FIG. Thus, the potential difference between the drain terminal of the FET 23a short-circuited to the negative electrode 11a, the gate terminal, and the source terminal can be reduced.

(Fifth embodiment)
FIG. 9 is a circuit diagram showing a configuration of a PMT drive circuit 1E as the fifth embodiment of the PMT drive circuit according to the present invention. Also in this embodiment, the configuration of the PMT 2 is the same as that of the first embodiment described above.

  The PMT drive circuit 1E of the present embodiment has a configuration substantially similar to that of the PMT drive circuit 1B (see FIG. 3) of the second embodiment, but differs in the following points. That is, the PMT drive circuit 1E of the present embodiment has a so-called cathode ground configuration, and the negative electrode 11a of the DC power supply 11 connected to the cathode K is connected to the reference potential line 15. The positive electrode 11 b of the DC power supply 11 is connected to the anode P through the resistance element 25, and the anode P is connected to the output terminal 27 through the capacitor 26.

  Even with such a cathode grounding method, the same effects as those of the second embodiment can be obtained. Further, by setting the cathode K to the reference potential (GND), the electron trajectory inside the PMT 2 can be stabilized, and noise included in the output current can be reduced. However, since the anode P has a high voltage, it is necessary to extract the output signal after coupling by the capacitor 26. Therefore, since a DC signal cannot be obtained, it is suitable for an application for measuring the pulsed light to be measured L.

  In the PMT drive circuit 1E according to the present embodiment, only the output current from the anode P is allowed to flow to the FETs 16a to 16h by eliminating the bias resistor 18 between the final stage dynode Dy8 and the positive electrode 11b of the DC power supply 11. Can do. That is, as shown in FIG. 10, when the connection destination of the dynode Dy8 is only the source terminal of the FET 16h and the drain terminal of the FET 16a is connected to the output terminal 28, the output current from the anode P is changed from the dynodes Dy1 to Dy8 to the FETs 16a to 16. The DC signal can be taken out from the drain terminal of the FET 16a as a current output.

  The PMT drive circuit according to the present invention is not limited to the embodiments described so far, and various other modifications are possible. For example, in each of the above embodiments, a P-channel FET is used as a transistor constituting the transistor group, but other FETs or bipolar transistors may be used.

  In each of the above embodiments, the number n of dynodes provided in the PMT has been described as n = 8. However, the present invention can be applied to a PMT drive circuit for a PMT provided with an arbitrary number of dynodes. it can.

1 is a circuit diagram showing a configuration of a first embodiment of a PMT drive circuit according to the present invention. FIG. It is a figure which shows the Zener diode connected between the gate terminal and source terminal of FET. It is a circuit diagram which shows the structure of 2nd Embodiment of the PMT drive circuit by this invention. It is a figure which shows the PMT drive circuit provided with one capacitor | condenser instead of a capacitor group as a comparison. The waveform of the to-be-measured light in the PMT drive circuit of 2nd Embodiment and the waveform of a corresponding output current are shown. The amount of light to be measured is larger in (b) than in (a), and the amount of light in measured light is larger in (c) than in (b). The waveform of the light to be measured in the PMT drive circuit as a comparative example and the waveform of the corresponding output current are shown. The amount of light to be measured is larger in (b) than in (a), and the amount of light in measured light is larger in (c) than in (b). It is a circuit diagram which shows the structure of 3rd Embodiment of the PMT drive circuit by this invention. It is a circuit diagram which shows the structure of 4th Embodiment of the PMT drive circuit by this invention. It is a circuit diagram which shows the structure of 5th Embodiment of the PMT drive circuit by this invention. It is a circuit diagram which shows the modification of the PMT drive circuit which concerns on 5th Embodiment. FIG. 3 is a circuit diagram showing a bleeder circuit of a photomultiplier tube disclosed in Patent Document 1.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1A-1E ... Drive circuit, 2 ... PMT, 11 ... DC power supply, 11a ... Negative electrode, 11b ... Positive electrode, 12 ... Transistor group, 12a-12h, 16a-16h, 19a-19d, 23a-23d ... P channel FET , 13: resistance dividing circuit, 14, 22, 24 ... capacitor group, 15 ... reference potential line, 16, 23 ... transistor group, 19 ... transistor group, 27, 28 ... output terminal, D ... multiplication unit, Dy1-Dy8 ... Dynode, K ... Cathode, L ... Light to be measured, P ... Anode, T ... Vacuum tube, Va-Vh ... Gradient potential.

Claims (8)

A cathode that emits photoelectrons according to the amount of incident light, a dynode arranged in n stages (n is an integer of 1 or more), a multiplier that multiplies the photoelectrons, and an electron that has been multiplied by the multiplier A photomultiplier tube driving circuit that is connected to a photomultiplier tube having an anode that provides a predetermined potential gradient to the cathode and the n-stage dynode,
A direct-current power source in which a negative electrode is connected to the cathode;
Including m transistors (m is an integer from 1 to n), and one current terminal of each of the m transistors is connected to the negative electrode of the DC power supply via the other transistor or directly. A transistor group in which the other current terminal of each of the m transistors is connected to the corresponding dynode among the n stages of dynodes;
A resistance dividing circuit that generates a potential gradient by dividing a potential difference between a positive electrode and a negative electrode of the DC power source and applies the gradient potential to each of the control terminals of the m transistors;
A plurality of capacitors connected in series with each other, one end of which is connected to the negative electrode of the DC power supply, the other end is connected to the positive electrode of the DC power supply, and a connection point between adjacent capacitors is the connection point And a capacitor group connected to a control terminal of the transistor corresponding to each of the photomultiplier tube driving circuits.   The m transistors in the transistor group are connected to each other in series, and the one current terminal of the transistor located at one end thereof is short-circuited to a negative electrode of the DC power supply. Item 2. The photomultiplier tube driving circuit according to Item 1.   3. The photomultiplier tube driving circuit according to claim 1, wherein the m transistors are field effect transistors (FETs).   4. The photomultiplier tube drive according to claim 3, wherein the m transistors are P-channel FETs, the one current terminal is a drain terminal, and the other current terminal is a source terminal. 5. circuit. The number m of the transistors is 1/3 or more of the number n of stages of the dynodes;
5. The photomultiplier tube driving circuit according to claim 1, wherein the transistor is connected to the dynodes from the last stage closest to the anode to the m-th stage. 6. . The number m of the transistors is equal to the number n of stages of the dynodes;
5. The photomultiplier tube driving circuit according to claim 1, wherein the transistor is connected to all the dynodes from the first stage to the n-th stage.   The capacitor further comprising a capacitor connected between the other current terminal of one of the transistors and the other current terminal of another of the transistors included in the transistor group. The photomultiplier tube driving circuit according to any one of the above.   The photoelectron amplification according to any one of claims 1 to 7, further comprising a Zener diode connected between a control terminal of the transistor included in the transistor group and the other current terminal. Double tube drive circuit.

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