JP2010050666A - Phase comparison circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To attain lower power consumption of a phase comparison circuit in high speed operations in which internal delay of D-FF (Data Flip Flop) is not disregarded. <P>SOLUTION: To a master slave master type D-FF 11, a first M-FF (Master Flip Flop) 11-1, S-FF (Slave Flip Flop) 11-2, and a second M-FF 11-3 are cascaded, input NRZ data signal is identified in response to a clock signal, and output from the S-FF and the second M-FF. A delay circuit 4 delays the input NRZ data signal for the same time as that of the S-FF. A first EXOR circuit 7 performs an EXCLUSIVE-OR operation between output of the delay circuit and output of the S-FF, and a second EXOR 8 performs an EXCLUSIVE-OR operation between output of the S-FF and output of the second M-FF. An adder 9 adds output of the first EXOR circuit and inverse output of the second EXOR together. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a phase comparison circuit, and more particularly, to a phase comparison circuit in a PLL (phase locked loop) type clock / data identification / reproduction circuit. This phase comparison circuit is used to automatically adjust the phase of the clock signal to the optimum point (the center position of the pulse width of the data signal) when the data signal is identified by the clock signal.

  An example of this type of conventional phase comparison circuit is CRHooge, JR., “A Self Correcting Clock Recovery Circuit”, Journal of Lihtwave Tech., Vol. No. 6, 1985, p1312. The operation of this phase comparison circuit will be described with reference to a circuit diagram (FIG. 4) and a time chart (FIG. 5). Here, it is assumed that the high-speed operation is such that the internal delay of the D-FF cannot be ignored.

  First, in the D-FF 5, the NRZ data signal input from the input terminal 1 is identified and output at the rising edge of the clock input signal from the clock amplifier 10. The delay circuit 4 outputs the NRZ data signal input from the input terminal 1 with the same delay time as the internal delay time of the D-FF 5. The D-FF5 output signal and the delay circuit 4 output signal are input to an EXOR (exclusive OR circuit) 7, and the phase difference between them, that is, the rise and fall of the NRZ data signal and the rise of the D-FF5 clock input signal. A comparison pulse signal corresponding to the phase difference is output from the EXOR 7.

  Here, the reason why the delay circuit 4 is inserted is that the width of the comparison pulse signal which is the output of the EXOR7 at the optimum phase (1 in FIG. 5) in which the rising edge of the D-FF5 clock input signal matches the center position of the NRZ data signal. Is a half cycle of the clock, and the change in the comparison pulse signal width can be centered on the optimum phase point. At the optimum phase, the pulse width of the comparison pulse signal is equal to the pulse width of the reference pulse signal.

  On the other hand, in the state where the phase of the D-FF5 clock input signal is advanced with respect to the NRZ data signal (2 in FIG. 5), the pulse width of the comparison pulse signal is narrowed as shown in the EXOR7 output. In a state where the phase of the D-FF5 clock input signal is delayed (3 in FIG. 5), the pulse width of the comparison pulse signal is wide as shown by the EXOR7 output.

  Next, the D-FF5 output signal is input to the D-FF6 and identified by the rising edge of the D-FF6 clock input signal. Then, the D-FF6 output signal is output to EXOR8. Since the phase difference between the D-FF5 output signal and the D-FF6 output signal is always a half cycle of the clock regardless of the phase state of the D-FF5 clock input, EXOR8 has the same width as the comparison pulse signal at the optimum phase point. The reference pulse signal is always output from the EXOR 8 (1 to 3 in FIG. 5).

  Then, the adder 9 adds the comparison pulse signal and the inverted reference pulse signal, and outputs the adder 9 output to the output terminal 3. The phase difference between the data and the clock is detected by taking the average value of the adder 9 output. The average value of the adder 9 output is lower than the average value at the optimum phase (1 in FIG. 5) when the phase of the D-FF5 clock input signal is advanced (2 in FIG. 5). It can be seen that in the state where the phase is delayed (3 in FIG. 5), it is higher than the average value at the optimum phase (1 in FIG. 5).

JP 2000-68991 A (page 2 to page 3, FIG. 7)

  As shown in FIG. 6, the D-FF circuit is usually an MS type in which two flip-flop circuits having the same configuration are cascade-connected, and the former stage is designated as a master and the latter stage is designated as a slave. A D-FF (master-slave data flip-flop) is used. The master flip-flop is composed of a Gilbert cell circuit composed of transistors 30 to 36, resistors 20, 21 and resistor 24, and a two-stage emitter follower circuit composed of transistors 37, 38 and resistors 25, 26, and is a slave flip-flop. The circuit comprises a Gilbert cell circuit composed of transistors 39 to 47, resistors 22, 23 and a resistor 27, and a two-stage emitter follower circuit composed of transistors 46, 47 and resistors 28, 29.

  The input terminal 12 connected to the base of the transistor 30 and the input terminal 13 connected to the base of the transistor 31 are the data input terminal D, the input terminal 14 connected to the bases of the transistors 34 and 44, and the transistors 35 and 43, respectively. The input terminal 15 connected to the base corresponds to the clock input terminal C, the output terminal 17 connected to the base of the transistor 42 and the output terminal 17 connected to the base of the transistor 41 correspond to the data output terminal Q.

  As described above, since the conventional phase comparison circuit employs a configuration that requires two D-FF circuits, four Gilbert cell circuits and eight emitter follower circuits are necessary, and four Gilbert cell circuits. Therefore, it is difficult to reduce the power consumption.

  Therefore, an object of the present invention is to provide a phase comparison circuit that realizes lower power consumption than a conventional circuit during high-speed operation in which the internal delay of the D-FF cannot be ignored.

  In the phase comparison circuit of the present invention, the first input terminal is connected to the data input of the MSM type D-FF (master slave master type data flip-flop) and the input of the delay circuit, and the output of the delay circuit is the first EXOR Connected to the first input. The second input terminal is connected to the input of the clock amplifier, and the output of the clock amplifier is connected to the clock input of the MSM type D-FF. The second output of the first EXOR and the first input of the second EXOR are connected to the first output of the MSM type D-FF, and the second output of the first MSM type D-FF is connected to the first output of the MSM type D-FF. , The second input of the second EXOR is connected. The outputs of the first and second EXORs are respectively connected to the input of the adder, and the output terminal is connected to the output of the first adder.

In the phase comparison circuit in the PLL clock / data identification / reproduction circuit,
In the MSM type D-FF, a first master flip-flop, a slave flip-flop, and a second master flip-flop are connected in cascade, and an input NRZ data signal is identified in response to a clock signal. Output from flip-flop. The delay circuit delays the input NRZ data signal by the same time as the slave flip-flop.

  The first EXOR circuit performs an exclusive OR operation on the output of the delay circuit and the output of the slave flip-flop, and the second EXOR performs an exclusive OR operation on the output of the slave flip-flop and the output of the second master flip-flop. Do. The adder adds the output of the first EXOR circuit and the inverted output of the second EXOR.

  More specifically, the clock supplied to the first master flip-flop and the second master flip-flop and the clock supplied to the slave flip-flop are in a reverse phase relationship.

  Further, when the rising edge of the clock is at the center position of the minimum pulse width of the input NRZ data signal, the output of the adder is configured to be zero.

  The effect of the present invention is that the power consumption of the phase comparator can be reduced. The reason for this is that by using one MSM type D-FF instead of two MS type D-FFs in the conventional phase comparison circuit, one Gilbert cell circuit and two emitter follower circuits are reduced, and at the same time This is because one Gilbert cell circuit serving as a load of the clock amplifier is reduced.

  An embodiment of the phase comparison circuit of the present invention will be described below with reference to the drawings.

[Description of configuration]
FIG. 1 is a circuit diagram showing an embodiment of a phase comparison circuit of the present invention. As can be seen from comparison with FIG. 4, the MSM type D-FF 11 is employed instead of the MS type D-FFs 5 and 6. In the MSM type D-FF 11, a first master flip-flop (M-FF) 11-1, a slave flip-flop (S-FF) 11-2, and a second master flip-flop (M-FF) 11-3 are connected in cascade. The output Q1 is extracted from the S-FF 11-2 and the output Q2 is extracted from the second M-FF 11-3.

  In FIG. 1, the input terminal 1 is connected to the data input of the MSM type D-FF 11 and the input of the delay circuit 4, and the output of the delay circuit 4 is connected to the first input of the EXOR 7. The input terminal 2 is connected to the input of the clock amplifier 10, and the output of the clock amplifier 10 is connected to the clock input of the MSM type D-FF 11. The second input of EXOR7 and the first input of EXOR8 are connected to the output Q1 of the MSM type D-FF11, and the second input of EXOR8 is connected to the output Q2 of the MSM type D-FF11. The output of the EXOR 7 and the inverted output of the EXOR 8 are connected to the input of the adder 9, and the output terminal 3 is connected to the output of the adder 9. The output of the clock amplifier 10 is directly connected to the clock inputs of the M-FF 11-1 and M-FF 11-3, but the inverted output of the clock amplifier 10 is connected to the clock input of the S-FF 11-2. .

  FIG. 2 is a detailed circuit diagram of the MSM type D-FF 11. As can be seen from a comparison between FIG. 2 and FIG. 6, the MSM type D-FF 11 has the second M-FF 11-3 connected to the output terminals 17 and 16 in FIG. 6, and the base of the transistor 55 in the second M-FF 11-3. Are connected to the output terminal 17, and the base of the transistor 56 is connected to the output terminal 16. The second M-FF 11-3 has the same configuration as the first M-FF 11-1, and is driven by the same clock as the first M-FF 11-1 and the S-FF 11-2. 2, the first M-FF 11-1 and the second M-FF 11-3 correspond to the master flip-flop in FIG. 6, and the S-FF 11-2 corresponds to the slave flip-flop in FIG. It can be seen that the clock drive of the S-FF 11-2 is in a reverse phase relationship with the clock drive of the first M-FF 11-1 and the second M-FF 11-3 because the input terminals 14 and 15 are interchanged.

  In the conventional phase comparison circuit, the MS type D-FF shown in FIG. 6 is connected in two stages, whereas in the phase comparison circuit of the present invention, only the MSM type D-FF 11 shown in FIG. 2 is provided. . Therefore, the conventional phase comparison circuit requires four Gilbert cell circuits and eight emitter follower circuits, whereas the phase comparison circuit of the present invention requires three Gilbert cell circuits and six emitter follower circuits. . One Gilbert cell circuit as a load of the clock amplifier 10 is also reduced.

[Description of operation]
Next, the operation of the phase comparison circuit will be described with reference to a circuit diagram (FIG. 1) and a time chart (FIG. 3). First, in the first M-FF 11-1 of the MSM type D-FF 11, the NRZ data signal input from the input terminal 1 is identified at the rising edge of the clock input signal from the clock amplifier 10 and output to the S-FF 11-2. In the S-FF 11-2, this input is identified by the rising edge of the inverted output of the clock input signal from the clock amplifier 10 and used as an MSM D-FF 11Q1 output signal. Since the output signal of the MSM type D-FF11Q1 is a result from the slave output in the master-slave master configuration, the same result as that of the MS type D-FF is obtained.

  This MSM type D-FF11Q1 output signal and the NRZ data signal input from the input terminal 1 are input to the EXOR 7 by the delay circuit 4 and the delay circuit 4 output signal having the same delay as the internal delay time of the S-FF 11-2. The comparison pulse signal corresponding to the phase difference between the delay circuit 4 output signal and the MSM type D-FF11Q1 output signal, that is, the phase difference between the rise and fall of the NRZ data signal and the rise of the MSM type D-FF11 clock input signal Is output from EXOR7.

  Here, the reason why the delay amount of the delay circuit 4 is the same as the internal delay time of the S-FF 11-2 is that the clock is supplied to the S-FF 11-2 separately from the first M-FF 11-1. This is because the delay amount from the rise of the MSM type D-FF11 clock input signal to the output of the MSM type D-FF11Q1 is determined only by the S-FF11-2. On the other hand, in the above-described prior art, since the clock is supplied to the D-FF 5, the delay amount of the delay circuit 4 is made the same as the internal delay time of the D-FF 5.

  The reason for inserting the delay circuit 4 is that the width of the comparison pulse signal that is the output of the EXOR7 is set at the optimum phase (1 in FIG. 3) in which the rising edge of the D-FF5 clock input signal is aligned with the center position of the NRZ data signal. This is for the half cycle of the clock, so that the change of the comparison pulse signal width can be centered on the optimum phase point. At the optimum phase, the pulse width of the comparison pulse signal is equal to the pulse width of the reference pulse signal.

  On the other hand, when the phase of the D-FF5 clock input signal is advanced with respect to the NRZ data signal (2 in FIG. 3), the comparison pulse signal is narrowed as shown by the EXOR7 output, and the D-FF5 is compared with the NRZ data signal. In the state where the phase of the clock input signal is delayed (3 in FIG. 3), the comparison pulse signal becomes wide as shown by the EXOR7 output.

  Next, the output of the MSM type D-FF 11Q1 is input to the second M-FF 11-3 and identified by the rising edge of the clock input signal from the clock amplifier 10. Then, the MSM type D-FF 11Q2 output is output to EXOR8. The EXOR8 receives the MSM D-FF11Q1 output signal and the MSM D-FF11Q2 output, and generates an EXOR8 output signal that is a reference pulse output. The MSM type D-FF11Q2 output signal (reference pulse signal) is defined as a data acquisition when the clock is at the Lo level in the second M-FF 11-3 and a holding operation when the clock is at the Hi level. Data is output in synchronization with the falling edge. For this reason, the MSM type D-FF11Q2 output signal is a signal having a delay of a half cycle of the clock with respect to the MSM type D-FF11Q1 output signal.

  As a result, the pulse width of the EXOR8 output signal, which is the reference pulse output, is equivalent to a half clock cycle. The EXOR8 output, which is the reference pulse, has a width of the comparison pulse signal at the optimum phase point even when the clock phase is advanced (2 in FIG. 3) or delayed (3 in FIG. 3) with respect to the input data. It has a width corresponding to a half cycle of the clock (1 to 3 in FIG. 3).

  Then, the adder 9 adds the comparison pulse signal and the inverted reference pulse signal, and outputs the adder 9 output to the output terminal 3. The phase difference between the data and the clock is detected by taking the average value of the adder 9 output. The average value of the adder 9 output is lower than the average value at the optimum phase (1 in FIG. 3) in the state where the phase of the MSM type D-FF11 clock input signal has advanced (2 in FIG. 3), and the MSM type D-FF11. It can be seen that when the phase of the clock input signal is delayed (3 in FIG. 3), it is higher than the average value at the optimum phase (1 in FIG. 3). This average value is used for feedback control of phase control.

  As described above, the phase comparison circuit of the present invention is capable of performing phase comparison in the same manner as the conventional circuit at the time of high-speed operation in which the internal delay of the D-FF cannot be ignored. This reduces the power consumption by one Gilbert cell circuit and two emitter follower circuits, and at the same time reduces one Gilbert cell circuit as a load of the clock amplifier. Furthermore, power consumption can be reduced.

The circuit diagram which showed one Example of the phase comparison circuit of this invention Detailed circuit diagram of MSM type D-FF11 adopted in the present invention The flowchart which shows operation | movement of the phase comparison circuit of this invention. Circuit diagram showing an example of a conventional phase comparison circuit A flowchart showing the operation of a conventional phase comparison circuit Detailed circuit diagram of MS type D-FF in conventional phase comparator

Explanation of symbols

1, 2 Input terminal 3 Output terminal 4 Delay circuit 5, 6 D-FF
7,8 EXOR
9 Adder 10 Clock amplifier 11 MSM type D-FF
12 to 15 Input terminal 16, 17 Output terminal 18, 19 Voltage source 20 to 29 Resistor 30 to 47 Bipolar transistor 48 to 52 Resistor 53 to 61 Bipolar transistor

Claims (4)

An input terminal for inputting an NRZ data signal;
A delay circuit for delaying the NRZ data signal;
A second master-slave master type data flip-flop (MSM type D-FF) connected to the input terminal and the input clock and having a first output and a second output;
A first exclusive OR circuit that inputs the output of the delay circuit and the first output of the MSM type D-FF;
A second exclusive OR circuit that inputs a first output of the MSM type D-FF and a second output of the MSM type D-FF;
An adder for adding the output of the first exclusive OR circuit and the inverted output of the second exclusive OR circuit;
A phase comparison circuit comprising an output terminal to which an output of the adder is connected. In the phase comparison circuit in the PLL clock / data identification / reproduction circuit,
A first master flip-flop, a slave flip-flop, and a second master flip-flop are connected in cascade, and an input NRZ data signal is identified in response to a clock signal and output from the slave flip-flop and the second master flip-flop. Master-slave master type data flip-flop,
A delay circuit for delaying the input NRZ data signal by the same time as the slave flip-flop;
A first EXOR circuit that performs an exclusive OR operation on the output of the delay circuit and the output of the slave flip-flop;
A second EXOR that performs an exclusive OR operation on the output of the slave flip-flop and the output of the second master flip-flop;
A phase comparison circuit comprising an adder for adding the output of the first EXOR circuit and the inverted output of the second EXOR.   3. The phase comparison circuit according to claim 2, wherein the clock supplied to the first master flip-flop and the second master flip-flop and the clock supplied to the slave flip-flop are in a reverse phase relationship. .   4. The phase comparison circuit according to claim 1, wherein when the rising edge of the clock is at the center position of the minimum pulse width of the input NRZ data signal, the output of the adder becomes zero. .

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