JP2010050242A - Method of manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve the positional accuracy of a mark that is given to a semiconductor device. <P>SOLUTION: While a dicing tape 9 is adhered to the rear surface 1b of a wafer 1d, green light 2 is applied from the rear surface 1b thereof with the dicing tape 9 interposed to give a mark. Thus, the positioning accuracy between the wafer 1d and the green light 2 becomes high because the green light 2 is applied to the wafer 1d as it is, and the deviation of irradiation position of the green light 2 to the wafer 1d is hard to occur, thereby improving the positional accuracy of the mark. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor device manufacturing technique, and more particularly to a semiconductor device manufacturing technique including a laser marking process.

  In a method for manufacturing a semiconductor device, a semiconductor wafer is attached to the upper surface of a dicing sheet via a protective film having a high infrared (laser) absorption rate, and a laser beam that passes through the dicing sheet is irradiated onto the upper surface of the protective film. A technique for imprinting a predetermined recognition mark is disclosed (for example, see Patent Document 1).

A semiconductor device includes a semiconductor substrate, a first coating layer that covers a side surface of the semiconductor substrate, and a wiring formed on a lower surface of the semiconductor substrate, and the first coating layer has an insulating property such as a resin material. It is made of a material and covers the side surface of the semiconductor substrate. Further, the first coating layer is formed so as to cover at least the entire side surface of the semiconductor substrate, its lower end is located up to the insulating layer, and its upper end extends to the upper surface of the semiconductor substrate. The existing structure is disclosed (for example, refer to Patent Document 2).
JP 2007-266420 A JP 2007-266421 A

  In the manufacturing process of a semiconductor device (semiconductor device), there is a step of marking a back surface of a chip in order to recognize the type and function of a semiconductor chip (hereinafter also simply referred to as a chip) to be used. As the marking method, for example, a process on the chip main surface side is processed at the stage of a semiconductor wafer (hereinafter also referred to simply as a wafer), the wafer is separated into individual pieces, and each separated chip is stored in a tray. In this state, a mark is formed on the back surface of the chip with a laser.

  However, as shown in the comparative example of FIG. 44, the tray 31 for storing the chips 30 suppresses the occurrence of chip cracks due to the edge portions 30a of the chips 30 coming into contact with the tray 31 when the chips 30 are stored. For this purpose, the storage portion 31a is formed larger than the chip size. Therefore, the chip 30 is likely to be displaced at the stage of the mark process using the laser beam 32, and it is difficult to improve the mark alignment accuracy. Further, the inventor of the present application states that the tray 31 is often made of a resin material, for example, and the tray itself is likely to warp, and even if chip cracks can be prevented, the accuracy of alignment is limited. discovered.

  Then, as shown in the said patent documents 1 and 2, after sticking a wafer on the upper surface of a dicing sheet and dividing a wafer, the method of irradiating an infrared light through a dicing sheet can be considered.

  However, as a result of examination by the inventors of the present application, when laser light having a wavelength as long as infrared light is irradiated onto a semiconductor wafer made of silicon, the inside of the semiconductor wafer is also transmitted and a circuit formed on the main surface side of the semiconductor wafer There is a problem that the element may be damaged (decrease in reliability of the semiconductor device).

  Therefore, as shown in Patent Documents 1 and 2, it is also conceivable to form an insulating layer on the back surface of the semiconductor wafer in order to easily absorb infrared light on the back surface of the semiconductor wafer.

  However, the formation of the insulating layer has a problem that the manufacturing cost of the semiconductor device increases as the material cost to be added and the number of steps for forming the insulating layer increase.

  An object of the present invention is to provide a technique capable of improving the positional accuracy of a mark attached to a semiconductor device.

  Another object of the present invention is to provide a technique capable of suppressing a decrease in reliability of a semiconductor device.

  Furthermore, another object of the present invention is to provide a technique capable of suppressing an increase in manufacturing cost of a semiconductor device.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in this application, the outline of typical ones will be briefly described as follows.

  That is, the present invention includes the following steps. (A) preparing a wafer having a plurality of device forming regions having a main surface on which circuit elements and a plurality of pads are formed, and a back surface opposite to the main surface; (b) the main surface of the wafer Attaching a first holding tape for holding the wafer to the substrate and grinding the back surface of the wafer. And (c) attaching a second holding tape for holding the wafer to the back surface of the wafer and peeling the first holding tape from the main surface of the wafer; (d) the plurality of device forming regions A step of connecting a plurality of bump electrodes to each of the plurality of pads; (e) irradiating the back surface of the wafer with the first light from the second holding tape side; A step of applying a mark to the back surface.

  Moreover, this invention includes the following processes. (A) preparing a wafer having a plurality of device forming regions having a main surface on which circuit elements and a plurality of pads are formed, and a back surface opposite to the main surface; (b) the main surface of the wafer Attaching a first holding tape for holding the wafer to the surface and grinding the back surface of the wafer; (c) attaching a second holding tape for holding the wafer to the back surface of the wafer; A step of peeling the first holding tape from the main surface. And (d) connecting a plurality of bump electrodes to the plurality of pads in each of the plurality of device formation regions; and (e) between adjacent device formation regions among the plurality of device formation regions. Cutting and dividing the semiconductor device into a plurality of semiconductor devices; (f) irradiating the back surface of the wafer with the first light from the second holding tape side to mark each back surface of the plurality of device formation regions; Process.

  Of the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  With the holding tape affixed to the back side of the semiconductor wafer, the laser is irradiated from the back side through the holding tape to mark it, and the laser is irradiated in the wafer state to align the semiconductor wafer and the laser. The accuracy is good and the position accuracy of the mark can be improved.

  In addition, laser light with a wavelength shorter than that of infrared light is used as a laser for marking, and this laser light is irradiated from the back side of the semiconductor wafer, thereby damaging circuit elements formed on the main surface side of the semiconductor wafer. As a result, a decrease in reliability of the semiconductor device can be suppressed.

  In addition, by adopting a dicing tape as the holding tape to be attached to the back surface of the semiconductor wafer, it is possible to eliminate the need for additional material costs, and a process for forming an insulating layer on the back surface is not necessary. An increase in manufacturing cost can be suppressed.

  In the following embodiments, the description of the same or similar parts will not be repeated in principle unless particularly necessary.

  Further, in the following embodiment, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments, but they are not irrelevant to each other unless otherwise specified. The other part or all of the modifications, details, supplementary explanations, and the like are related.

  Also, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), particularly when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and it may be more or less than the specific number.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof will be omitted.

(Embodiment 1)
1 is a plan view showing an example of the structure of a semiconductor wafer used in the method of manufacturing a semiconductor device according to the first embodiment of the present invention, and FIG. 2 is a cross-sectional view showing the structure cut along the line AA in FIG. FIG. 3 is a partially enlarged plan view showing an enlarged structure of the B part in FIG. 1, and FIG. 4 is a partially enlarged sectional view showing an enlarged structure of the B part in FIG. 5 is a plan view showing an example of the structure before back grinding in the back grinding process of the manufacturing method of the semiconductor device according to the first embodiment of the present invention, and FIG. 6 is cut along the line AA in FIG. FIG. 7 is a cross-sectional view showing the structure, FIG. 7 is a plan view showing an example of the structure at the time of back grinding in the back grinding process of the semiconductor device manufacturing method according to the first embodiment of the present invention, and FIG. It is sectional drawing which shows the structure cut | disconnected along. Further, FIG. 9 is a plan view showing an example of a structure at the time of tape replacement in the method of manufacturing a semiconductor device according to the first embodiment of the present invention, and FIG. 10 shows a structure cut along the line AA in FIG. FIG. 11 is a cross-sectional view, FIG. 11 is a plan view showing an example of a structure after bump formation in the method of manufacturing a semiconductor device according to the first embodiment of the present invention, and FIG. 12 shows a structure cut along line AA in FIG. FIG. 13 is a partially enlarged sectional view showing the structure of the B part in FIG.

  14 is a cross-sectional view showing an example of the structure at the time of laser irradiation in the laser marking step of the manufacturing method of the semiconductor device according to the first embodiment of the present invention, and FIG. 15 is an example of the detailed structure at the time of laser irradiation shown in FIG. FIG. 16 is a partially enlarged plan view showing an example of a mark formed by laser irradiation shown in FIG. Further, FIG. 17 is a cross-sectional view showing an example of the structure before dicing in the dicing process of the manufacturing method of the semiconductor device according to the first embodiment of the present invention, and FIG. 18 shows an example of the structure after dicing in the dicing process shown in FIG. FIG. 19 is a plan view showing an example of the structure of a semiconductor device assembled by the method of manufacturing a semiconductor device according to the first embodiment of the present invention, and FIG. 20 is cut along the line AA in FIG. It is sectional drawing which shows a structure.

  The semiconductor device according to the first embodiment is as small as the chip size as shown in FIGS. 19 and 20, and in the first embodiment, as an example of the semiconductor device, a wafer level CSP (Chip Size) is used. Package) 7 is taken up and explained.

  The configuration of the wafer level CSP 7 shown in FIG. 19 and FIG. 20 will be described. The main surface 1a has a main surface 1a and a back surface 1b provided on the opposite side of the main surface 1a. Semiconductor chip (semiconductor device) 1 provided, lead wiring (rewiring, rearrangement wiring) 1i for replacing the arrangement of a plurality of pads 1c with an arrangement of a plurality of external terminals corresponding to these pads 1c, a plurality of And solder balls (bump electrodes) 5 which are a plurality of external terminals electrically connected to the lead wiring 1i.

  An insulating film 1g is formed on the main surface 1a of the semiconductor chip 1, and the lead-out wiring 1i is formed on the insulating film 1g. Further, a protective film 1h is formed on the insulating film 1g, and each lead-out wiring 1i is covered and protected by this protective film 1h so as to expose a region to which each of the plurality of external terminals is connected. Yes.

  A part of each lead-out wiring 1i is exposed through the opening of the protective film 1h, and a solder ball (bump electrode) 5 as an external terminal is disposed at the opening. As a result, as shown in FIG. 19, the arrangement of the plurality of pads 1c is replaced with the arrangement of the plurality of solder balls 5 by the lead wires 1i.

  The semiconductor chip 1 is made of, for example, silicon, and the planar shape of the main surface 1a and the back surface 1b intersecting with the thickness thereof is a square shape. On the main surface 1a of the semiconductor chip 1, a plurality of pads 1c are provided in a line along the peripheral edge along each of the four sides. The solder balls 5 drawn from the pad 1c by the lead wiring 1i are arranged side by side so as to form a square inside the pad row.

  A circuit element 1f is formed on the main surface 1a side of the semiconductor chip 1 as shown in FIG.

  Note that the back surface 1b of the semiconductor chip 1 of the wafer level CSP 7 and the side surface 1j serving as a cut surface are exposed.

  Next, assembly of the wafer level CSP 7 which is the semiconductor device of the first embodiment will be described.

  First, as shown in FIG. 1 to FIG. 4, a device element region 1e having a main surface 1a having a circuit element 1f and a plurality of pads 1c formed around the circuit element 1f and a back surface 1b opposite to the main surface 1a. A wafer (semiconductor wafer) 1d made of silicon is prepared. As shown in FIGS. 3 and 4, in each device formation region 1e, a plurality of pads 1c are formed along the dicing lines (regions between adjacent device formation regions 1e) at the peripheral portion, A circuit element 1f is formed inside the pad row. The planar shape of each device formation region 1e is a quadrangle, and is partitioned and formed on the main surface 1a of the wafer by a dicing line.

  Thereafter, as shown in FIGS. 5 and 6, a BG (Back Grinding) tape (first holding tape) 8 for holding the wafer 1d is attached to the main surface 1a of the wafer 1d. Here, the main surface 1a of the wafer 1d is attached to the BG tape 8 attached to the ring member 10 so that the wafer 1d is positioned inside the ring member 10.

  Thereafter, as shown in FIGS. 7 and 8, the back surface 1b of the wafer 1d having the main surface 1a attached to the BG tape 8 is ground. Here, the back surface 1b of the wafer 1d is ground by the grinding pad 11 to reduce the thickness of the wafer 1d (wafer back grinding).

  After the BG process, the back surface 1b of the wafer 1d is finish-polished by polishing to make the wafer 1d thinner.

  After the polishing process is completed, as shown in FIGS. 9 and 10, a dicing tape (second holding tape) 9 for holding the wafer 1d is attached to the back surface 1b of the wafer 1d. At this time, as shown in FIG. 10, the dicing tape 9 is affixed to the back surface 1b of the wafer 1d and one surface of the ring member 10 (the surface opposite to the surface on which the BG tape 8 is affixed). Thereafter, the BG tape 8 is peeled off from the main surface 1 a of the wafer 1 d and the other surface of the ring member 10.

  Since the semiconductor device is the wafer level CSP 7, after the BG tape 8 is peeled off, the insulating film 1g, the lead wiring 1i and the protection shown in FIG. 20 are formed on the main surface 1a in each device formation region 1e of the wafer 1d. A film 1h is formed, and each pad 1c is drawn out by the lead wiring 1i. That is, the arrangement of the pads 1c is converted by the lead wiring 1i. In the first embodiment, the pitch between the external terminals 5 that are part of the lead-out wiring 1i and adjacent to each other (or the region to which the external terminals are connected) is larger than the pitch between the adjacent pads 1c. The arrangement of the pads 1c is changed so that becomes larger.

  Thereafter, bump formation shown in FIGS. 11 and 12 is performed. Here, a plurality of solder balls (bump electrodes) are provided on the lead wirings 1i drawn from the plurality of pads 1c in the plurality of device forming regions 1e in a state where the dicing tape 9 is attached to the back surface 1b of the wafer 1d. ) 5 are electrically connected to each other. That is, as shown in FIG. 13, the solder balls 5 are mounted on the main surface 1a of the wafer 1d with the dicing tape 9 attached to the back surface 1b of the wafer 1d.

  As shown in FIG. 13, the dicing tape 9 is composed of a base material 9a and an adhesive layer 9b. The base material 9a is composed of, for example, polyolefin and has a thickness of, for example, 100 μm. The adhesive layer 9b is, for example, an acrylic adhesive, and has a thickness of 10 μm, for example. That is, the dicing tape 9 is transparent so that both the base material 9a and the adhesive layer 9b can transmit at least laser light (the back surface 1b of the wafer 1d can be visually observed from the dicing tape 9 side). Needless to say, it may be made of other materials as long as it is transparent.

  In addition, the dicing tape 9 is attached to the back surface 1b side before the bump formation step, and the BG tape 8 attached to the main surface 1a side is peeled off to replace the tape. When the thickness is as thick as 100 μm or more, it is possible to perform bump formation without attaching the dicing tape 9 to the back surface 1b side in the bump formation step.

  Thereafter, as shown in FIGS. 14 and 15, marking using laser irradiation is performed. Here, green light (first light) 2 as an example of laser light is irradiated from the dicing tape 9 side to the back surface 1b of the wafer 1d, and a plurality of devices are formed on the wafer 1d by the laser light transmitted through the dicing tape 9. A mark 3 as shown in FIG. 16 is applied to each back surface 1b of the region 1e. That is, as shown in FIG. 15, the dicing tape 9 is attached to the back surface 1b side, and the outer periphery of the wafer 1d on which the solder balls 5 are mounted on the main surface 1a side is supported by the ring member 10, and these are The dicing tape 9 is supported by the wafer support block 4 in this state, and in this state, the dicing tape 9 is applied to the back surface 1b of the wafer 1d using the hollow portion 4a formed at the center of the wafer support block 4 from the back surface 1b side of the wafer 1d. The mark 3 is applied to the back surface 1b of the wafer 1d.

  Here, the conditions of the laser beam applied to the back surface 1b of the wafer 1d used in the marking process of the first embodiment will be described.

  The laser beam is, for example, green light 2 and its wavelength is 532 nm. This wavelength is longer than the wavelength (150 nm to 300 nm) of the ultraviolet light (second light) 13 irradiated from, for example, a UV lamp in the pickup process in which the semiconductor chip 1 is picked up. This is because the semiconductor chip 1 is picked up by curing the adhesive layer 9b of the dicing tape 9 by irradiating the ultraviolet light 13 in the pick-up process after the marking process. This is to prevent the adhesive layer 9b from being cured.

  The wavelength of the laser beam is from the wavelength (1064 nm to 10600 nm) of infrared light (third light) 18 that is a laser beam imprinted on a surface 17a of a resin sealing body 17 (see FIG. 40) described later. short. This is because the circuit element 1f is formed on the main surface 1a side of the wafer 1d (semiconductor chip 1), and when the infrared light 18 is irradiated from the back surface 1b side in the marking process, the wavelength of the infrared light is relative to silicon. Therefore, since the transmittance is good, it penetrates through silicon and damages the element surface. Therefore, in the marking process, it is possible to prevent the circuit element 1f from being damaged by irradiating the wafer 1d with the green light 2 having a wavelength shorter than that of the infrared light 18 from the back surface 1b side.

  Therefore, the wavelength of the mark light used in the marking step is [wavelength of infrared light 18 (third light)> wavelength of green light 2 (first light)> wavelength of ultraviolet light 13 (second light)]. It is a condition to satisfy. By using light of such a wavelength, the irradiated light can pass through the dicing tape 9. Moreover, in this marking process, it can suppress that hardening of the contact bonding layer 9b of the dicing tape 9 is accelerated | stimulated. Furthermore, in this marking process, it can suppress that light reaches | attains the circuit element 1f.

  After the marking, the wafer 1d is diced as shown in FIGS. That is, the wafer 1d is separated into pieces by dicing. First, as shown in FIG. 17, a wafer 1d having a dicing tape 9 attached to the back surface 1b and an outer peripheral portion held by a ring member 10 is placed on a dicing stage 12 with the main surface 1a facing upward. In this state, among the plurality of device formation regions 1e on the wafer 1d, the adjacent device formation regions 1e are cut by the blade 6, and a plurality of wafer level CSPs (semiconductor devices) are obtained as shown in FIG. ) Divide into 7.

  Thereafter, an area between each of the separated semiconductor devices is expanded by an expanding process, and further, ultraviolet light 13 (second light) having a wavelength different from that of the green light 2 (first light) is dicing tape 9 (second holding). The adhesive layer 9b of the dicing tape 9 is cured by irradiating the tape), and after the curing, the wafer level CSP 7 is picked up. That is, the wavelength of the green light 2 that is the first laser light used in the marking process is different from the wavelength of the ultraviolet light 13 used in the dicing process, and the wavelength of the green light 2 is more than the wavelength of the ultraviolet light 13. Also long.

  With this pickup, the wafer level CSP 7 shown in FIGS. 19 and 20 is acquired.

  According to the manufacturing method of wafer level CSP 7 (semiconductor device) of the first embodiment, green light 2 is emitted from the back surface 1b side through the dicing tape 9 with the dicing tape 9 attached to the back surface 1b of the wafer 1d. By irradiating the mark 3 by irradiating the green light 2 in the wafer state, the alignment accuracy of the wafer 1d and the green light 2 is good, and the deviation of the irradiation position of the green light 2 with respect to the wafer 1d hardly occurs. .

  That is, if the irradiation of the green light 2 at the time of marking is after the wafer 1d is singulated, there is an expanding process of the dicing tape 9, so that the device forming area 1e to be marked 3 is likely to be displaced. Further, when the dicing blade 6 is used in the dicing process, fine irregularities are formed on the cut surface of the wafer 1d due to the stress of the rotating blade 6, so that the outer shape of the device forming region 1e to which the mark 3 is to be applied is formed. It becomes difficult to specify, and there is a possibility that the mark 3 may be applied to a place deviated from the original position where the mark 3 is to be applied. Therefore, as in the first embodiment, if the wafer 1d before the irradiating control of the green light 2 is singulated, the misalignment hardly occurs, and the green light 2 is irradiated in a state where the alignment accuracy is improved. be able to.

  Thereby, the position accuracy of the mark 3 can be improved.

  Further, as the laser for applying the mark 3, laser light such as green light 2 having a wavelength shorter than that of the infrared light 18 is adopted, and this green light 2 is irradiated from the back surface 1b side of the wafer 1d, whereby the main surface of the wafer 1d. Damage to the circuit element 1f formed on the 1a side can be suppressed, and as a result, a decrease in reliability of the wafer level CSP 7 can be suppressed.

  Further, by using the dicing tape 9 as the holding tape to be attached to the back surface 1b of the wafer 1d, it is possible to eliminate the need for additional material costs, and the process of forming an insulating layer on the back surface 1b is unnecessary. As a result, an increase in the manufacturing cost of the wafer level CSP 7 can be suppressed.

  Further, in the assembly of the wafer level CSP 7 according to the first embodiment, even if the thickness of the wafer 1d is reduced by the back grinding of the wafer 1d, the dicing tape 9 is attached to the back surface 1b of the wafer 1d in each step after the back grinding. Therefore, the wafer 1d can be easily transferred between the processes.

  In the assembly of the wafer level CSP 7 according to the first embodiment, the appearance inspection of the wafer 1d is performed after the solder ball forming process shown in FIGS. 11 and 12 and before the marking process.

  As a result, it is possible to recognize a joint failure location of the solder ball 5 in the appearance inspection process, and it is possible to mark a failure mark with a laser beam at the joint failure location in the subsequent marking process.

  Next, a modification of the method for manufacturing the semiconductor device according to the first embodiment will be described.

  That is, in the assembly flow of FIGS. 1 to 20 described above, the case where marking is performed with a laser beam such as green light 2 after the formation of the solder balls and before the wafer 1d is singulated has been described. The marking on the wafer 1d may be performed after the solder balls are formed and after the wafer 1d is separated.

  That is, as shown in FIGS. 11, 12, and 13, after mounting the solder balls 5 on the main surface 1a of the wafer 1d with the dicing tape 9 attached to the back surface 1b of the wafer 1d, FIG. The wafer 1d shown in FIG. 18 is first singulated, and marking is performed on the wafer 1d shown in FIGS.

  At the time of marking, the wafer 1d (wafer level CSP 7) fixed to the dicing tape 9 after dicing shown in FIG. 18 is placed on the wafer support block 4 shown in FIG. Marking is performed by irradiating laser light such as green light 2.

  After marking, after the ultraviolet light 13 (second light) having a wavelength different from that of the green light 2 (first light) is irradiated to the dicing tape 9 (second holding tape), the adhesive layer 9b of the dicing tape 9 is cured. The wafer level CSP 7 is picked up.

  By marking with laser light after dicing in this way, marking is performed after the four sides of the semiconductor chip 1 are formed. Therefore, the outline of the chip can be clearly recognized at the time of marking, and the wafer 1d (semiconductor chip 1 ) And the laser beam can be easily aligned.

(Embodiment 2)
21 is a plan view showing an example of the structure of a semiconductor wafer used in the method of manufacturing a semiconductor device according to the second embodiment of the present invention, and FIG. 22 is a cross-sectional view showing the structure cut along the line AA in FIG. FIG. 23 is a partially enlarged plan view showing the structure of the B part in FIG. 21 in an enlarged manner, and FIG. 24 is a partially enlarged sectional view showing the structure of the B part in FIG. FIG. 25 is a plan view showing an example of the structure before back grinding in the back grinding process of the semiconductor device manufacturing method according to the second embodiment of the present invention, and FIG. 26 is cut along the line AA in FIG. 27 is a cross-sectional view showing the structure, FIG. 27 is a plan view showing an example of the structure during back grinding in the back grinding process of the method of manufacturing a semiconductor device according to the second embodiment of the present invention, and FIG. 28 is taken along line AA in FIG. It is sectional drawing which shows the structure cut | disconnected along. Further, FIG. 29 is a plan view showing an example of a structure at the time of tape reattachment in the method of manufacturing a semiconductor device according to the second embodiment of the present invention, and FIG. 30 shows a structure cut along the line AA in FIG. FIG. 31 is a sectional view showing an example of the structure during laser irradiation in the laser marking step of the semiconductor device manufacturing method according to the second embodiment of the present invention.

  FIG. 32 is a cross-sectional view showing an example of the structure before dicing in the dicing process of the method of manufacturing a semiconductor device according to the second embodiment of the present invention, and FIG. 33 shows an example of the structure after dicing in the dicing process shown in FIG. FIG. 34 is a sectional view showing an example of the structure of a wiring board used in the method for manufacturing a semiconductor device according to the second embodiment of the present invention. FIG. 35 is a method for manufacturing the semiconductor device according to the second embodiment of the present invention. It is sectional drawing which shows an example of the structure after the chip mounting in this chip mounting process. FIG. 36 is a cross-sectional view showing an example of the structure after wire bonding in the wire bonding step of the method of manufacturing a semiconductor device according to the second embodiment of the present invention. FIG. 37 shows the manufacturing of the semiconductor device according to the second embodiment of the present invention. 38 is a cross-sectional view showing an example of the structure after resin molding in the molding step of the method, and FIG. 38 is a cross-sectional view showing an example of the structure after ball attachment in the ball supply step of the semiconductor device manufacturing method according to the second embodiment of the present invention. is there. 39 is a cross-sectional view showing an example of the structure during dicing in the package dicing step of the semiconductor device manufacturing method according to the second embodiment of the present invention, and FIG. 40 is a method for manufacturing the semiconductor device according to the second embodiment of the present invention. It is sectional drawing which shows an example of the structure at the time of marking in the package marking process. 41 is a plan view showing an example of the structure of the semiconductor device assembled by the method of manufacturing a semiconductor device according to the second embodiment of the present invention. FIG. 42 is a back view showing an example of the structure of the semiconductor device shown in FIG. 43 is a cross-sectional view showing the structure cut along the line AA in FIG.

  In the semiconductor device according to the second embodiment, as shown in FIGS. 41 to 43, the semiconductor chip (semiconductor device) 1 is mounted on the main surface 14a of the wiring board 14, and the semiconductor chip 1 and the wiring board 14 are made of gold. A resin-sealed package that is electrically connected by a conductive wire 15 such as a wire, and is further provided with solder balls 5 that are a plurality of external terminals arranged in a grid pattern on the back surface 14b of the wiring board 14. There is a BGA (Ball Grid Array) 19 as an example.

  As shown in FIG. 43, the semiconductor chip 1 is fixed onto the main surface 14a of the wiring board 14 via the die bonding material 16, and a plurality of wires 15 and the semiconductor chip are further formed on the main surface 14a of the wiring board 14. A resin-made sealing body 17 for sealing 1 is formed. As shown in FIG. 41, a mark 3 is engraved on the surface 17a of the sealing body 17. The sealing resin forming the sealing body 17 is, for example, a thermosetting epoxy resin.

  In addition, a circuit element 1f is formed on the main surface 1a side of the semiconductor chip 1, and pads 1c, which are a plurality of surface electrodes, are formed on the peripheral portion. The pad 1c and a wiring board corresponding to the pad 1c are formed. 14 bonding leads 14 c are electrically connected by wires 15.

  Further, in the wiring board 14, the bonding lead 14c on the main surface 14a side and the land 14d on the back surface 14b side are electrically connected by an internal wiring or the like of the board (not shown), and each land 14d is solder which becomes an external terminal. A ball 5 is connected.

  Next, assembly of the BGA 19 that is the semiconductor device of the second embodiment will be described.

  As shown in FIGS. 21 to 24, a plurality of device formation regions 1e having a main surface 1a having a plurality of pads 1c formed around the circuit element 1f and its periphery and a back surface 1b opposite to the main surface 1a are provided. A wafer (semiconductor wafer) 1d made of silicon is prepared. As shown in FIGS. 23 and 24, in each device forming region 1e, a plurality of pads 1c are formed at the peripheral portion, and a circuit element 1f is formed inside the pad row.

  Thereafter, as shown in FIGS. 25 and 26, a BG (Back Grinding) tape (first holding tape) 8 for holding the wafer 1d is attached to the main surface 1a of the wafer 1d. Here, the main surface 1 a of the wafer 1 d is attached to the BG tape 8 attached to the ring member 10 so as to be positioned inside the ring member 10.

  Thereafter, as shown in FIGS. 27 and 28, the back surface 1b of the wafer 1d having the main surface 1a attached to the BG tape 8 is ground. Here, the back surface 1b of the wafer 1d is ground by the grinding pad 11 to reduce the thickness of the wafer 1d (wafer back grinding).

  After the BG process, the back surface 1b of the wafer 1d is finish-polished by polishing to make the wafer 1d thinner.

  After completion of the polishing process, as shown in FIGS. 29 and 30, a dicing tape (second holding tape) 9 for holding the wafer 1d is attached to the back surface 1b of the wafer 1d. Thereafter, the BG tape 8 is peeled from the main surface 1a of the wafer 1d.

  As shown in FIG. 13 of the first embodiment, the dicing tape 9 is composed of a base material 9a and an adhesive layer 9b. The base material 9a is composed of, for example, polyolefin and has a thickness of, for example, 100 μm. The adhesive layer 9b is, for example, an acrylic adhesive, and has a thickness of 10 μm, for example. That is, it goes without saying that the dicing tape 9 is transparent so that both the base material 9a and the adhesive layer 9b can transmit at least laser light, and may be made of other materials as long as it is transparent. Yes.

  Thereafter, as shown in FIG. 31, marking using laser irradiation is performed. Here, green light 2, which is an example of laser light, is irradiated from the dicing tape 9 side to the back surface 1b of the wafer 1d, and each of the plurality of device formation regions 1e of the wafer 1d is transmitted by the laser light transmitted through the dicing tape 9. A mark 3 as shown in FIG. 16 of the first embodiment is applied to the back surface 1b. That is, the outer periphery of the wafer 1d with the dicing tape 9 attached to the back surface 1b side is supported by the ring member 10, and these are supported by the wafer support block 4 together with the dicing tape 9, and in this state, the back surface of the wafer 1d. By irradiating the back surface 1b of the wafer 1d with the green light 2 through the dicing tape 9 using the hollow portion 4a formed at the center of the wafer support block 4 from the 1b side, the back surface 1b of the wafer 1d is shown in FIG. A mark 3 as shown in FIG.

  Note that the conditions of the first laser light applied to the back surface 1b of the wafer 1d used in the marking process of the second embodiment are the same as those described in the first embodiment.

  That is, the laser beam is, for example, green light 2 and the wavelength thereof is 532 nm. This wavelength is longer than the wavelength (150 nm to 300 nm) of the ultraviolet light (second light) 13 irradiated from, for example, a UV lamp in the pickup process in which the semiconductor chip 1 is picked up. This is because the semiconductor chip 1 is picked up by curing the adhesive layer 9b of the dicing tape 9 by irradiating the ultraviolet light 13 in the pick-up process after the marking process. This is to prevent the adhesive layer 9b from being cured.

  The wavelength of the laser beam is from the wavelength (1064 nm to 10600 nm) of infrared light (third light) 18 that is a laser beam imprinted on a surface 17a of a resin sealing body 17 (see FIG. 40) described later. short. This is because the circuit element 1f is formed on the main surface 1a side of the wafer 1d (semiconductor chip 1), and when the infrared light 18 is irradiated from the back surface 1b side in the marking process, the wavelength of the infrared light is relative to silicon. Therefore, since the transmittance is good, it penetrates through silicon and damages the element surface. Therefore, in the marking process, it is possible to prevent the circuit element 1f from being damaged by irradiating the wafer 1d with the green light 2 having a wavelength shorter than that of the infrared light 18 from the back surface 1b side.

  Therefore, the wavelength of the first laser beam for marks used in the marking process is the same as in the first embodiment: [wavelength of infrared light 18 (third light)> wavelength of green light 2 (first light)> The condition is that the wavelength of the ultraviolet light 13 (second light) is satisfied. By using light of such a wavelength, the irradiated light can pass through the dicing tape 9. Moreover, in this marking process, it can suppress that hardening of the contact bonding layer 9b of the dicing tape 9 is accelerated | stimulated. Furthermore, in this marking process, it can suppress that light reaches | attains the circuit element 1f.

  After the marking, the wafer 1d is diced as shown in FIGS. That is, the wafer 1d is separated into pieces by dicing. First, as shown in FIG. 32, a wafer 1d having a dicing tape 9 attached to the back surface 1b and an outer peripheral portion held by a ring member 10 is placed on the dicing stage 12 with the main surface 1a facing upward. In this state, among the plurality of device forming regions 1e on the wafer 1d, the adjacent device forming regions 1e are cut by the blade 6, and a plurality of semiconductor chips (semiconductor devices) are formed as shown in FIG. Divide into 1.

  Thereafter, the region between each of the separated semiconductor devices is expanded by expansion, and further, ultraviolet light 13 (second light) having a wavelength different from that of the green light 2 (first light) is applied to the dicing tape 9 (second holding tape). ) To cure the adhesive layer 9b of the dicing tape 9, and after curing, the semiconductor chip 1 is picked up. That is, the wavelength of the green light 2 used in the marking process and the wavelength of the ultraviolet light 13 that is the second laser light used in the dicing process are different, and the wavelength of the green light 2 is more than the wavelength of the ultraviolet light 13. Also long.

  With this pickup, individual semiconductor chips (semiconductor devices) 1 can be obtained.

  On the other hand, a multi-piece wiring board 14 as shown in FIG. 34 is prepared. The main surface 14a of the wiring board 14 is provided with a plurality of bonding leads 14c, and the back surface 14b is provided with a plurality of lands 14d.

  Thereafter, a desired semiconductor chip 1 is picked up, and the picked-up semiconductor chip 1 is mounted on the wiring board 14. That is, die bonding is performed. Here, as shown in FIG. 35, the semiconductor chip 1 is mounted on the main surface 14 a of the wiring substrate 14 via the die bonding material 16. At that time, the semiconductor chip 1 is mounted by face-up mounting. That is, the main surface 14a of the wiring substrate 14 and the back surface 1b of the semiconductor chip 1 are joined via the die bond material 16 such as a paste material.

  Note that flip chip bonding may be employed as the die bonding. In this case, the semiconductor chip 1 is mounted on the wiring substrate 14 by face-down mounting. That is, the semiconductor chip 1 is mounted with the main surface 1 a facing the main surface 14 a of the wiring substrate 14.

  Thereafter, wire bonding shown in FIG. 36 is performed. That is, the pad 1c of the semiconductor chip 1 and the bonding lead 14c of the wiring substrate 14 are connected by the wire 15 such as a gold wire to electrically connect the semiconductor chip 1 and the wiring substrate 14.

  Thereafter, resin sealing shown in FIG. 37 is performed. Here, the sealing body 17 is formed by resin sealing in a state where a plurality of semiconductor chips 1 are covered with one cavity of a resin molding die. That is, the sealing body 17 is formed by performing batch molding that covers the plurality of semiconductor chips 1 with one sealing body 17.

  Thereafter, solder ball attachment shown in FIG. 38 is performed. Here, the solder balls 5 that are external terminals of the BGA 19 are connected to the lands 14d of the back surface 14b with the back surface 14b of the wiring board 14 facing upward.

  After the solder balls are attached, package dicing (separation) shown in FIG. 39 is performed. Here, the wiring board 14 and the sealing body 17 are cut together with the blade 6 along the package region, and separated into individual BGAs 19.

  Thereafter, the marking shown in FIG. 40 is performed. Here, marking is performed on the surface 17 a of the sealing body 17. At that time, the surface 17a of the sealing body 17 is irradiated with laser light having a wavelength different from that of the green light 2 that is the first laser light to form an inscription. The wavelength of the green light (first light) 2 that marks the back surface 1b of the wafer 1d is shorter than the wavelength of the laser light used in the marking process on the sealing body 17, and is, for example, infrared light 18. .

  That is, the marking applied to the sealing body 17 uses infrared light 18 having a wavelength longer than that of the green light 2 used when applied to the wafer 1d. This is because the marking device for infrared light 18 is cheaper than the marking device for green light 2. However, the marking applied to the sealing body 17 is not limited to the infrared light 18 but may be the green light 2.

  When the infrared light 18 is used as the marking laser light applied to the sealing body 17, the relationship between the wavelengths of the respective lights used in the assembly of the semiconductor device of the second embodiment is the same as that of the first embodiment. The wavelength of the infrared light 18 (third light)> the wavelength of the green light 2 (first light)> the wavelength of the ultraviolet light 13 (second light)].

  By irradiating the surface 17a of the sealing body 17 with the infrared light 18 in this way, the mark 3 can be formed as shown in FIG.

  Note that when marking is performed on the sealing body 17, since the marking area is wider than that of a single chip, the positional accuracy can be ensured even in the marking process after singulation. However, if attention is paid to improving the positional accuracy, it is preferable to perform marking before the singulation step of FIG.

  When the marking is completed, the assembly of the BGA 19 is completed as shown in FIGS.

  Other effects obtained by the method of manufacturing the semiconductor device (BGA 19) according to the second embodiment are the same as those described in the first embodiment, and thus redundant description thereof is omitted.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiments of the invention. However, the present invention is not limited to the embodiments of the invention, and various modifications can be made without departing from the scope of the invention. It goes without saying that it is possible.

  For example, in the second embodiment, the semiconductor device is a package, and the BGA is taken as an example. However, the semiconductor device is not limited to the BGA, but is a QFP (Quad Flat Package) or QFN (QuadFlatNon-). leaded Package) or the like. Further, it may be an MCM (Multi-Chip Module) on which a plurality of chips are mounted.

  The present invention is suitable for a manufacturing technique of an electronic device for applying a mark.

It is a top view which shows an example of the structure of the semiconductor wafer used with the manufacturing method of the semiconductor device of Embodiment 1 of this invention. It is sectional drawing which shows the structure cut | disconnected along the AA line of FIG. FIG. 2 is a partially enlarged plan view showing an enlarged structure of a portion B in FIG. 1. It is a partial expanded sectional view which expands and shows the structure of the B section of FIG. It is a top view which shows an example of the structure before the back grinding in the back grinding process of the manufacturing method of the semiconductor device of Embodiment 1 of this invention. It is sectional drawing which shows the structure cut | disconnected along the AA line of FIG. It is a top view which shows an example of the structure at the time of the back grinding in the back grinding process of the manufacturing method of the semiconductor device of Embodiment 1 of this invention. It is sectional drawing which shows the structure cut | disconnected along the AA line of FIG. It is a top view which shows an example of the structure at the time of tape replacement in the manufacturing method of the semiconductor device of Embodiment 1 of this invention. It is sectional drawing which shows the structure cut | disconnected along the AA line of FIG. It is a top view which shows an example of the structure after bump formation in the manufacturing method of the semiconductor device of Embodiment 1 of this invention. It is sectional drawing which shows the structure cut | disconnected along the AA line of FIG. It is a partial expanded sectional view which expands and shows the structure of the B section of FIG. It is sectional drawing which shows an example of the structure at the time of the laser irradiation in the laser marking process of the manufacturing method of the semiconductor device of Embodiment 1 of this invention. It is sectional drawing which shows an example of the detailed structure at the time of the laser irradiation shown in FIG. FIG. 16 is a partially enlarged plan view showing an example of a mark formed by laser irradiation shown in FIG. 15. It is sectional drawing which shows an example of the structure before dicing in the dicing process of the manufacturing method of the semiconductor device of Embodiment 1 of this invention. It is sectional drawing which shows an example of the structure after the dicing in the dicing process shown in FIG. It is a top view which shows an example of the structure of the semiconductor device assembled by the manufacturing method of the semiconductor device of Embodiment 1 of this invention. It is sectional drawing which shows the structure cut | disconnected along the AA line of FIG. It is a top view which shows an example of the structure of the semiconductor wafer used with the manufacturing method of the semiconductor device of Embodiment 2 of this invention. It is sectional drawing which shows the structure cut | disconnected along the AA line of FIG. It is the elements on larger scale which expand and show the structure of the B section of FIG. It is a partial expanded sectional view which expands and shows the structure of the B section of FIG. It is a top view which shows an example of the structure before the back grinding in the back grinding process of the manufacturing method of the semiconductor device of Embodiment 2 of this invention. It is sectional drawing which shows the structure cut | disconnected along the AA line of FIG. It is a top view which shows an example of the structure at the time of the back grinding in the back grinding process of the manufacturing method of the semiconductor device of Embodiment 2 of this invention. It is sectional drawing which shows the structure cut | disconnected along the AA line of FIG. It is a top view which shows an example of the structure at the time of tape replacement in the manufacturing method of the semiconductor device of Embodiment 2 of this invention. It is sectional drawing which shows the structure cut | disconnected along the AA line of FIG. It is sectional drawing which shows an example of the structure at the time of the laser irradiation in the laser marking process of the manufacturing method of the semiconductor device of Embodiment 2 of this invention. It is sectional drawing which shows an example of the structure before dicing in the dicing process of the manufacturing method of the semiconductor device of Embodiment 2 of this invention. It is sectional drawing which shows an example of the structure after the dicing in the dicing process shown in FIG. It is sectional drawing which shows an example of the structure of the wiring board used with the manufacturing method of the semiconductor device of Embodiment 2 of this invention. It is sectional drawing which shows an example of the structure after the chip mounting in the chip mounting process of the manufacturing method of the semiconductor device of Embodiment 2 of this invention. It is sectional drawing which shows an example of the structure after the wire bonding in the wire bonding process of the manufacturing method of the semiconductor device of Embodiment 2 of this invention. It is sectional drawing which shows an example of the structure after the resin molding in the mold process of the manufacturing method of the semiconductor device of Embodiment 2 of this invention. It is sectional drawing which shows an example of the structure after ball attachment in the ball supply process of the manufacturing method of the semiconductor device of Embodiment 2 of this invention. It is sectional drawing which shows an example of the structure at the time of the dicing in the package dicing process of the manufacturing method of the semiconductor device of Embodiment 2 of this invention. It is sectional drawing which shows an example of the structure at the time of the marking in the package marking process of the manufacturing method of the semiconductor device of Embodiment 2 of this invention. It is a top view which shows an example of the structure of the semiconductor device assembled by the manufacturing method of the semiconductor device of Embodiment 2 of this invention. 42 is a back view showing an example of the structure of the semiconductor device shown in FIG. 41. FIG. It is sectional drawing which shows the structure cut | disconnected along the AA line of FIG. It is a fragmentary sectional view which shows the storage structure of the semiconductor device of a comparative example.

Explanation of symbols

1 Semiconductor chip (semiconductor device)
DESCRIPTION OF SYMBOLS 1a Main surface 1b Back surface 1c Pad 1d Wafer 1e Device formation area 1f Circuit element 1g Insulating film 1h Protective film 1i Lead-out wiring 1j Side surface 2 Green light (first light)
3 Mark 4 Wafer Support Block 4a Hollow Part 5 Solder Ball (Bump Electrode)
6 Blade 7 Wafer level CSP (semiconductor device)
8 BG tape (first holding tape)
9 Dicing tape (second holding tape)
9a Base material 9b Adhesive layer 10 Ring member 11 Grinding pad 12 Dicing stage 13 Ultraviolet light (second light)
14 Wiring board 14a Main surface 14b Back surface 14c Bonding lead 14d Land 15 Wire 16 Die bond material 17 Sealed body 17a Surface 18 Infrared light (third light)
19 BGA (semiconductor device)
30 Chip 30a Edge part 31 Tray 31a Storage part 32 Laser light

Claims (17)

A method for manufacturing a semiconductor device comprising the following steps:
(A) a step of preparing a wafer having a plurality of device forming regions each having a main surface on which circuit elements and a plurality of pads are formed, and a back surface opposite to the main surface;
(B) attaching a first holding tape for holding the wafer to the main surface of the wafer and grinding the back surface of the wafer;
(C) attaching a second holding tape for holding the wafer to the back surface of the wafer and peeling the first holding tape from the main surface of the wafer;
(D) connecting a plurality of bump electrodes to the plurality of pads in each of the plurality of device formation regions;
(E) A step of irradiating the back surface of the wafer with the first light from the second holding tape side to mark each back surface of the plurality of device forming regions. 2. The method of manufacturing a semiconductor device according to claim 1, wherein after the step (e),
(F) a step of cutting between adjacent device formation regions among the plurality of device formation regions and dividing the device formation regions into a plurality of semiconductor devices;
A method for manufacturing a semiconductor device, comprising: 3. The method of manufacturing a semiconductor device according to claim 2, wherein after the step (f),
(G) irradiating the second holding tape with second light having a wavelength different from that of the first light to pick up the semiconductor device;
Including
The method of manufacturing a semiconductor device, wherein the wavelength of the first light in the step (e) is longer than the wavelength of the second light in the step (g).   4. The method of manufacturing a semiconductor device according to claim 3, wherein the second light is ultraviolet light. 2. The method of manufacturing a semiconductor device according to claim 1, wherein after the step (e),
(F) A step of cutting between adjacent device formation regions among the plurality of device formation regions and dividing into a plurality of semiconductor devices;
(G) irradiating the second holding tape with second light having a wavelength different from that of the first light to pick up the semiconductor device;
(H) mounting the picked-up semiconductor device on a substrate;
(I) electrically connecting the semiconductor device and the substrate;
(J) forming a sealing body by resin-sealing the semiconductor device;
(K) irradiating the surface of the sealing body with third light having a wavelength different from that of the first light to form a mark;
Including
The method of manufacturing a semiconductor device, wherein the wavelength of the first light in the step (e) is shorter than the wavelength of the third light in the step (k).   6. The method of manufacturing a semiconductor device according to claim 5, wherein the third light is infrared light.   7. The method of manufacturing a semiconductor device according to claim 6, wherein the first light is green light.   2. The method of manufacturing a semiconductor device according to claim 1, wherein the second holding tape is transparent.   2. The method of manufacturing a semiconductor device according to claim 1, wherein the circuit element is formed on the main surface of the wafer.   2. The method of manufacturing a semiconductor device according to claim 1, wherein the wafer is made of silicon.   2. The method of manufacturing a semiconductor device according to claim 1, further comprising an appearance inspection step of inspecting the appearance of the wafer between the step (d) and the step (e). A method for manufacturing a semiconductor device comprising the following steps:
(A) a step of preparing a wafer having a plurality of device forming regions each having a main surface on which circuit elements and a plurality of pads are formed, and a back surface opposite to the main surface;
(B) attaching a first holding tape for holding the wafer to the main surface of the wafer and grinding the back surface of the wafer;
(C) a step of attaching a second holding tape for holding the wafer to the back surface of the wafer, and peeling the first holding tape from the main surface of the wafer;
(D) connecting a plurality of bump electrodes to the plurality of pads in each of the plurality of device formation regions;
(E) a step of cutting between adjacent device formation regions among the plurality of device formation regions and dividing the device formation regions into a plurality of semiconductor devices;
(F) A step of irradiating the back surface of the wafer with the first light from the second holding tape side to mark each back surface of the plurality of device formation regions. 13. The method of manufacturing a semiconductor device according to claim 12, wherein after the step (f),
(G) irradiating the second holding tape with second light having a wavelength different from that of the first light to pick up the semiconductor device;
Including
The method of manufacturing a semiconductor device, wherein the wavelength of the first light in the step (f) is longer than the wavelength of the second light in the step (g).   14. The method of manufacturing a semiconductor device according to claim 13, wherein the first light is green light.   13. The method of manufacturing a semiconductor device according to claim 12, wherein the second holding tape is transparent.   13. The method of manufacturing a semiconductor device according to claim 12, wherein the circuit element is formed on the main surface of the wafer.   13. The method of manufacturing a semiconductor device according to claim 12, wherein the wafer is made of silicon.

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