JP2010045943A - Voltage booster circuit and power supply apparatus using it - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a voltage booster circuit which can get high voltage boosting capacity, without increasing the element withstand voltage of a DC/DC converter section or the responsiveness of a feedback control section more than necessary. <P>SOLUTION: This voltage boosting circuit has the DC/DC converter section A1, which generates a boosted voltage Va from an input voltage Vin by switching on or switching off a transistor N1 that is connected to the other end of an inductor L1 to one end of which the input voltage Vin is applied thereby rectifying and smoothing a pulsated switch voltage Vsw drawn out of the other end of the inductor L1, charge pump sections A31-A3n on n stages (but, n is an integer of one or over), which is connected to the rear stage of the DC/DC converter section A1 and generates the final output voltage Vout by boosting the boosted voltage Va more, using the switch voltage Vsw, and the feedback control section A2, which switches on or switches off the transistor N1 so that the feedback voltage Vfb geared to the output voltage Vout and the specified reference voltage Vref may accord with each other. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a booster circuit that boosts an input voltage to generate a desired output voltage, and a power supply device using the booster circuit.

  FIG. 6 is a circuit diagram showing a conventional example of a step-up switching regulator. As shown in FIG. 6, the conventional step-up switching regulator includes a DC / DC conversion unit including a transistor N1, an inductor L1, a diode D1, and a capacitor C1, and an input voltage Vin is applied to one end. The transistor N1 connected to the other end of the inductor L1 is turned on / off, and the pulsed switch voltage Vsw drawn from the other end of the inductor L1 is rectified and smoothed to boost the input voltage Vin to obtain the output voltage Vout. It was supposed to be generated.

  The conventional step-up switching regulator includes a feedback control unit including resistors R1 and R2, an error amplifier ERR, a DC voltage source E1, an oscillator OSC, a comparator CMP, and a driver DRV, and depends on the output voltage Vout. The on-duty of the transistor N1 is controlled by PWM [Pulse Width Modulation] so that the feedback voltage Vfb (divided voltage of the output voltage Vout) matches a predetermined reference voltage Vref, so that the output voltage Vout is set to the target value. Therefore, the feedback control is performed so as to maintain the current.

Patent document 1 can be mentioned as an example of the related art related to the above.
JP 2001-69749 A

  Certainly, with the conventional step-up switching regulator, it is possible to boost the input voltage Vin and generate the desired output voltage Vout.

  However, in the conventional step-up switching regulator, the switch voltage Vsw rises to a voltage level (Vout + Vf) that is higher than the output voltage Vout by the forward drop voltage Vf of the diode D1, so that the output voltage Vout is a high voltage. In some cases, the breakdown voltage between the source and drain of the transistor N1 must be designed to be sufficiently high, resulting in an increase in element size.

  In the conventional step-up switching regulator, when the high output voltage Vout is to be obtained from the low input voltage Vin, the on-duty of the transistor N1 must be PWM controlled near 100%. In order to control the off period with high accuracy, the responsiveness of the error amplifier ERR, the comparator CMP, and the driver DRV that form the feedback control unit must be improved, and the circuit design is very difficult.

  In view of the above problems, the present invention provides a booster circuit capable of obtaining a high boosting capability without unnecessarily increasing the element breakdown voltage of the DC / DC converter and the responsiveness of the feedback controller, and An object is to provide a power supply device used.

  In order to achieve the above object, a booster circuit according to the present invention turns on / off an output switch element connected to the other end of an energy storage element to which an input voltage is applied at one end, and A DC / DC converter that generates a boosted voltage from the input voltage by rectifying and smoothing a pulsed switch voltage drawn from an end; and connected to a subsequent stage of the DC / DC converter, and using the switch voltage A charge pump unit of m stages (where m is an integer of 1 or more) that generates a final output voltage by further boosting the boosted voltage by repeating the charge storage operation and charge transfer operation performed; A feedback control unit that performs on / off control of the output switch element so that a feedback voltage corresponding to the voltage matches a predetermined reference voltage (first configuration); It has been.

  In the booster circuit having the first configuration, each of the n-stage charge pump units includes a first capacitor having one end connected to the switch voltage application terminal; and one end of the DC / DC conversion unit. A first diode or a first switch connected to the output terminal or the output terminal of the immediately preceding charge pump unit, the other end connected to the other end of the first capacitor; one end connected to the other end of the first capacitor A second diode or a second switch connected to the input terminal of the charge pump unit at the next stage or the output terminal of the output voltage; one end connected to the other end of the second diode or the second switch. And a second capacitor having the other end connected to the ground terminal (second configuration).

  In the booster circuit having the first or second configuration, the feedback control unit divides the output voltage to generate the feedback voltage; and a reference voltage to generate the reference voltage A generation circuit; an error amplifier that amplifies a difference between the feedback voltage and the reference voltage to generate an error voltage; an oscillation circuit that generates a triangular or sawtooth slope voltage; and the error voltage and the slope voltage And a comparator that generates a PWM signal based on the PWM signal; and a driver that generates a drive signal for the output switch element based on the PWM signal.

  Further, in the booster circuit having the third configuration, the reference voltage generation circuit includes a digital / analog conversion circuit that generates the reference voltage by converting the input digital data into analog (first). 4 configuration).

  Further, in the booster circuit having the third configuration, the feedback voltage generation circuit includes a resistance divider circuit that divides the output voltage using a digital potentiometer in which a resistance value is set according to input digital data. (5th configuration).

  According to another aspect of the present invention, there is provided a power supply device that boosts an input voltage to generate a desired output voltage, the booster circuit having the fourth or fifth configuration, and control information related to output settings of the booster circuit as the digital data. And a register unit for volatile storage as a configuration (sixth configuration).

  The power supply device having the sixth configuration includes a memory unit that stores digital data in a nonvolatile manner, and automatically reads out the digital data stored in the memory unit when the power supply device is activated. A configuration (seventh configuration) in which the auto-read function unit that outputs to the register unit is integrated may be used.

  Further, the power supply device having the sixth or seventh configuration described above has a configuration (eighth configuration) in which an interface unit that outputs digital data input from the outside of the power supply device to the register unit is integrated. Good.

  With the booster circuit and the power supply device using the same according to the present invention, a high boosting capability can be obtained without unnecessarily increasing the element breakdown voltage of the DC / DC converter and the responsiveness of the feedback controller.

  FIG. 1 is a block diagram showing an embodiment of a system power supply IC according to the present invention. As shown in FIG. 1, the system power IC 10 of this embodiment includes a plurality of power supply units (first power supply unit 1-1 to n-th power supply unit 1-n), a protection circuit unit 2, and a sequence control unit 3. And a register unit 4, a power-on reset unit 5, a serial interface unit 6 (hereinafter referred to as a serial I / F unit 6), and a memory unit 7, and a liquid crystal panel 20 as a load. In contrast, the semiconductor device supplies n output voltages V1 to Vn.

  The first power supply unit 1-1 to the nth power supply unit 1-n are means for generating desired output voltages V1 to Vn from the input voltage Vin and supplying them to the liquid crystal panel 20, respectively. A series regulator or a step-down or step-up switching regulator can be used. The output voltages V1 to Vn are used for applications such as a logic power source, a source driver power source, and a gate driver power source for the liquid crystal panel 20, respectively.

  The protection circuit unit 2 is means for detecting an abnormality in the system power supply IC 10 and generating a predetermined protection signal. The protection circuit unit 2 includes an overcurrent protection circuit (OCP [Over Current Protection] circuit) and an overvoltage protection circuit (OVP [Over Voltage Protection]). Circuit), an undervoltage lockout circuit (UVLO [Under Voltage Lock-Out] circuit), a thermal shutdown circuit (TSD [Thermal ShutDown] circuit), and the like. Of the various protection circuits listed above, the OCP circuit and the OVP circuit are preferably provided in each of the first power supply unit 1-1 to the nth power supply unit 1-n.

  The sequence control unit 3 performs sequence control related to the startup sequence and the shutdown sequence of the first power supply unit 1-1 to the nth power supply unit 1-n, and performs the first control based on the protection signal input from the protection circuit unit 2. It is means for performing abnormality protection control (shutdown control or the like) of the 1 power supply unit 1-1 to the nth power supply unit 1-n. As an example of the above sequence control, for example, it is conceivable to set a startup sequence in which the logic power supply of the liquid crystal panel 20 is started, the source driver power supply is started, and then the gate driver power supply is started. .

  The register 4 stores digital data input from the serial I / F unit 6 in a volatile manner, and stores the digital data in the first power supply unit 1-1 to the nth power supply unit 1-n, the protection circuit unit 2, and the sequence control. Volatile temporary storage means for outputting to the unit 3.

  The power-on reset unit 5 generates a power-on reset signal when the system power supply IC 10 is activated, and resets each unit of the system power supply IC 10 (serial I / F unit 6 in the example of FIG. 1) to an initial state. It is.

The serial I / F unit 6 is means for outputting digital data read from the memory unit 7 and digital data input from the outside of the IC to the register unit 4. The serial I / F unit 6 includes a 3-wire serial bus, an I ² C bus, and the like as a signal transmission path (bus) to the outside of the IC. The serial I / F unit 6 also has a digital data read / write function with respect to the memory unit 7. In particular, the system power supply IC 10 is activated when the serial I / F unit 6 is reset to an initial state upon receiving a power-on reset signal. And has a function of automatically reading out the digital data stored in the memory unit 7 (auto-read function).

  The memory unit 7 stores, as digital data, control information related to output settings of the first power supply unit 1-1 to the nth power supply unit, a protection value of the protection circuit unit 2, and sequence control of the sequence control unit 3. This means includes a flash memory and an EEPROM (Electrically Erasable and Programmable Read Only Memory). The digital data stored in the memory unit 7 may be written in advance by the manufacturer before shipment of the system power supply IC 10, or may be arbitrarily written by the user via the serial I / F unit 6. .

  Next, the startup operation of the system power supply IC 10 having the above configuration will be described in detail. When the system power supply IC 10 is turned on, the power-on reset unit 5 detects the activation of the system power supply IC 10, generates a power-on reset signal, and resets each unit of the system power supply IC 10 to an initial state. At this time, the serial I / F unit 6 automatically reads the digital data stored in the memory unit 7 and outputs it to the register unit 4. The register unit 4 stores the digital data input from the serial I / F unit 6 in a volatile manner, and stores the digital data in the first power supply unit 1-1 to the nth power supply unit 1-n, the protection circuit unit 2, and the sequence. Each is output to the control unit 3.

  The first power supply unit 1-1 to the n-th power supply unit 1-n set voltage values of the output voltages V <b> 1 to Vn based on the digital data input from the register unit 4, respectively. By adopting such a configuration, it is possible to take in a resistance element that has been conventionally externally attached to the system power supply IC 10, and (1) fine adjustment of the output voltages V1 to Vn is facilitated. (2) system The number of parts externally attached to the power supply IC 10 is reduced, and (3) the resistance element built in the system power supply IC 10 can enjoy the effect that the relative accuracy is higher than that of the resistance element conventionally attached externally. It becomes possible.

  Based on the digital data input from the register unit 4, the protection circuit unit 2 uses protection values (OCP circuit overcurrent detection threshold, OVP circuit overvoltage detection threshold, UVLO circuit low voltage) used when an abnormality is detected in the system power supply IC 10. Detection threshold, TSD circuit upper limit temperature threshold, etc.). With such a configuration, not only the output setting of the first power supply unit 1-1 to the nth power supply unit 1-n but also the protection value of the protection circuit unit 2 is high without requiring external components. Fine adjustments can be made to the accuracy.

  The sequence control unit 3 sets the startup sequence and the shutdown sequence of the first power supply unit 1-1 to the nth power supply unit 1-n based on the digital data input from the register unit 4. By adopting such a configuration, not only the output setting of the first power supply unit 1-1 to the nth power supply unit 1-n, but also the startup order and the shutdown order without requiring external parts, It becomes possible to adjust arbitrarily.

  As described above, with the system power supply IC 10 according to the present embodiment, the setting change of the system power supply IC 10 can be easily realized by arbitrarily rewriting the digital data stored in the memory unit 7. Therefore, it is possible to realize a common substrate on which the system power supply IC 10 is mounted.

  Note that the rewriting of the digital data stored in the memory unit 7 can be realized very easily because it is sufficient to change the data writing software as appropriate.

  Also, with the system power supply IC 10 of the present embodiment, the set values of the output voltages V1 to Vn can be arbitrarily changed after mounting on the board, so the module can easily perform a voltage drop test and an overvoltage test. It becomes possible to do.

  The system power supply IC 10 according to the present embodiment automatically reads out digital data stored in the memory unit 7 to the register unit 4 when the system power supply IC 10 is activated as a function of the serial I / F unit 6. Since the automatic read function for outputting is provided, the above-described various setting operations can be completed by the system power supply IC 10 alone without requiring control from outside the IC.

  In addition, the system power supply IC 10 of the present embodiment includes the serial I / F unit 6 that outputs digital data input from outside the IC to the register unit 4, so that not only when the system power supply IC 10 is started, Even during operation, it is possible to arbitrarily change the setting of the system power supply IC 10. In that case, digital data input from the outside of the IC may be directly written to the register unit 4, or digital data input from the outside of the IC is once written in the memory unit 7 and then stored in the memory unit 7. The stored digital data may be read and written to the register unit 4.

  1 illustrates the configuration in which the memory unit 7 is incorporated in the system power supply IC 10, the configuration of the present invention is not limited to this, and the memory unit 7 may be provided outside the IC. . Further, when various setting operations in the system power supply IC 10 do not need to be completed by the IC alone, except for the memory unit 7, the digital data is received from the outside of the IC via the serial I / F unit 6 one by one. Also good. Conversely, when it is not necessary to control various setting operations in the system power supply IC 10 from outside the IC, the digital data may be read from only the memory unit 7 except for the serial I / F unit 6.

  FIG. 2 is a circuit diagram illustrating a configuration example of a booster circuit used as at least one of the first power supply unit 1-1 to the nth power supply unit 1-n. As shown in FIG. 2, the booster circuit of this configuration example includes a DC / DC converter A1, a feedback controller A2, and m stages (where m is an integer of 1 or more) of charge pump units A31 to A3m. Have. Note that the booster circuit of this configuration example generates an output voltage Vout (for example, a gate voltage of the liquid crystal panel 20) higher than the input voltage Vin among the first power supply unit 1-1 to the nth power supply unit 1-n. As a power supply part, it can use suitably.

  The DC / DC converter A1 includes an inductor L1 as an energy storage element, an N-channel MOS [Metal Oxide Semiconductor] field effect transistor N1 as an output switch element, a diode D1 as a rectifier element, and a capacitor as a smoothing element. C1. One end of the inductor L1 is connected to the application end of the input voltage Vin. The drain of the transistor N1 is connected to the other end of the inductor L1. The source of the transistor N1 is connected to the ground terminal. The gate of the transistor N1 is connected to the drive signal output terminal (output terminal of the driver DRV) of the feedback control unit A2. The anode of the diode D1 is connected to the other end of the inductor L1. The cathode of the diode D1 is connected to the input terminal of the charge pump unit A31 at the next stage (first stage) as the output terminal of the DC / DC converter A1. One end of the capacitor C1 is connected to the cathode of the diode D1. The other end of the capacitor C1 is connected to the ground terminal.

  The DC / DC converter A1 having the above-described configuration turns on / off the transistor N1 connected to the other end of the inductor L1 to which the input voltage Vin is applied at one end, and is in a pulse shape drawn from the other end of the inductor L1 ( The boosted voltage Va is generated from the input voltage Vin by rectifying and smoothing the switch voltage Vsw having a rectangular wave shape with the diode D1 and the capacitor C1.

  The feedback control unit A2 includes a feedback voltage Vfb and a predetermined reference voltage Vref according to the output voltage Vout (at least one of the voltages V1 to Vn shown in FIG. 1) that is finally output via the charge pump units A31 to A3m. Is a means for performing on / off control of the transistor N1, so that the output voltage Vout is divided to generate a feedback voltage Vfb, and a reference voltage Vref is generated. A reference voltage generation circuit (DC voltage source E1), an error amplifier ERR that amplifies the difference between the feedback voltage Vfb and the reference voltage Vref to generate an error voltage Verr, and an oscillation that generates a triangular or sawtooth slope voltage Vslope Comparator for generating PWM signal by comparing circuit OSC with error voltage Verr and slope voltage Vslope And MP, comprising a, a driver DRV for generating a drive signal of the transistor N1 based on the PWM signal.

  In the feedback control unit A2 configured as described above, the error amplifier ERR amplifies the difference between the feedback voltage Vfb drawn from the connection node of the resistors R1 and R2 and the reference voltage Vref generated by the DC voltage source E1 to generate an error voltage. Generate Verr. That is, the voltage level of the error voltage Verr becomes higher as the output voltage Vout is lower than the target value.

  The comparator CMP compares the error voltage Verr and the slope voltage Vslope to generate a PWM signal. At this time, as the output voltage Vout is lower than the target value, the error voltage Verr becomes higher. Therefore, the high level period of the PWM signal becomes longer, and the error voltage Verr becomes lower as the output voltage Vout approaches the target value. Therefore, the high level period of the PWM signal is shortened.

  The driver DRV performs on / off control of the transistor N1 so that the transistor N1 is turned on when the PWM signal is at a high level and the transistor N1 is turned off when the PWM signal is at a low level. Accordingly, the on-duty of the transistor N1 (ratio of the on-period of the transistor N1 to the unit period) is sequentially changed according to the relative level of the error voltage Verr and the slope voltage Vslope. Specifically, as the output voltage Vout is lower than its target value, the high level period of the PWM signal becomes longer, so that the on-duty of the transistor N1 increases and as the output voltage Vout approaches its target value, the PWM Since the high level period of the signal is shortened, the on-duty of the transistor N1 is decreased.

  As described above, in the booster circuit of this configuration example, the output voltage Vout can be adjusted to the target value by the output feedback control using the feedback control unit A2.

  The charge pump units A31 to A3m are connected in series to the subsequent stage of the DC / DC converter A1, and repeat the charge accumulation operation and the charge transfer operation using the switch voltage Vsw, thereby further boosting the boosted voltage Va. This is a means for generating a typical output voltage Vout.

  The first-stage charge pump unit A31 includes capacitors C11 and C12 and diodes D11 and D12. One end of the capacitor C11 is connected to the application terminal of the switch voltage Vsw. The anode of the diode D11 is connected to the output terminal of the DC / DC converter A1 as the input terminal of the charge pump unit A31. The cathode of the diode D11 is connected to the other end of the capacitor C11. The anode of the diode D12 is connected to the other end of the capacitor C11. The cathode of the diode D12 is connected to the input terminal of the charge pump unit A32 at the next stage (second stage) as the output terminal of the charge pump unit A31. One end of the capacitor C12 is connected to the cathode of the diode D12. The other end of the capacitor C12 is connected to the ground terminal.

  The charge pump units A32 to A3m on and after the second stage basically have the same configuration as that of the charge pump part A31 on the first stage. However, for the charge pump units A32 to A3m in the second and subsequent stages, the anodes of the diodes D21 to Dm1 corresponding to the respective input terminals are connected to the output terminals of the immediately preceding charge pump unit. For the m-th stage charge pump unit A3m, the cathode of the diode Dm2 corresponding to the output terminal is connected to the output terminal of the final output voltage Vout.

  In the charge pump unit A31 configured as described above, when the switch voltage Vsw is at a low level, the diode D11 is in a conductive state and the diode D12 is in a non-conductive state, so that one end of the capacitor C11 has a low switch voltage Vsw. A level potential (ground voltage GND) is applied, and a voltage (Va−Vf) obtained by subtracting the forward drop voltage Vf of the diode D11 from the boosted voltage Va is applied to the other end. As a result, the capacitor C11 is charged until the voltage between both ends becomes (Va−Vf).

  When the switch voltage Vsw is set to the high level after the charging of the capacitor C11 is completed, the one-end voltage of the capacitor C11 is raised from the low level potential (ground voltage GND) of the switch voltage Vsw to the high level potential (Va + Vf) of the switch voltage Vsw. It is done. Here, since a potential difference equal to (Va−Vf) is given between both ends of the capacitor C11 by the previous charge, when the one end voltage of the capacitor C11 is raised to (Va + Vf), the capacitor C11 The other end voltage is also raised to 2Va (= one end voltage of C11 (Va + Vf) + a voltage across C11 (Va−Vf)).

  At this time, the diode D11 becomes non-conductive and the diode D12 becomes conductive. Therefore, the forward voltage drop Vf of the diode D12 is subtracted from the other end voltage (2Va) of the capacitor C11 at one end of the capacitor C12. Voltage (2Va-Vf) is applied. The ground voltage GND is applied to the other end of the capacitor C12. As a result, the capacitor C12 is charged until the voltage between both ends reaches (2Va−Vf), and this is applied to the input terminal of the charge pump unit A32 at the immediately subsequent stage (second stage). That is, in the charge pump unit A31, the boosted voltage Va generated by the DC / DC conversion unit A1 is boosted approximately twice and output.

  For the charge pump units A32 to A3m in the second and subsequent stages, the same charge / discharge operation as described above is periodically repeated based on the switch voltage Vsw, and finally the m-th charge pump part A3m is formed. An output voltage Vout (= (m + 1) × Va−m × Vf) obtained by boosting the boosted voltage Va approximately (m + 1) times is extracted from one end of the capacitor Cm2.

  In the booster circuit configured as described above, the high level potential of the switch voltage Vsw applied to the drain of the transistor N1 can be obtained by the following equation (1).

  As described above, in the booster circuit of this configuration example, the output voltage Vout is generated by combining the DC / DC conversion unit A1 and the charge pump units A31 to A3m. Therefore, the output voltage Vout is obtained using only the DC / DC conversion unit A1. Compared with the conventional configuration in which is generated, the high level potential of the switch voltage Vsw can be greatly reduced.

  Therefore, with the booster circuit of this configuration example, it is not necessary to design the source-drain breakdown voltage of the transistor N1 unnecessarily high, and the element size can be reduced. In addition, the booster circuit of this configuration example can also enjoy the effect that the efficiency is higher than that of the conventional configuration in which the output voltage Vout is generated using only the charge pump unit.

  Further, in the booster circuit of this configuration example, the charge / discharge operation of the charge pump units A31 to A3m (capacitors C11 to Cm1 and capacitors C12 to Cm2) is performed using the switch voltage Vsw generated by the DC / DC conversion unit A1. Charge storage operation and charge transfer operation) are controlled, it is not necessary to separately prepare a clock signal for charge / discharge control, and the circuit scale is not increased unnecessarily.

  Further, with the booster circuit of this configuration example, even when trying to obtain a high output voltage Vout from a low input voltage Vin, it is not necessary to perform PWM control with the on-duty of the transistor N1 near 100%. It is not necessary to unnecessarily increase the responsiveness of the error amplifier ERR, the comparator CMP, and the driver DRV that form the feedback control unit A2.

  The clock signal applied to each end of the capacitors C11 to Cm1 is not a switch voltage Vsw generated by the DC / DC converter A1, but, for example, a pulse between the ground voltage (GND) and the input voltage (Vin). Even if the configuration using a separate clock signal to be driven, in other words, the DC / DC conversion unit A1 and the charge pump units A31 to A3m are not linked to each other but simply connected in series, the switch voltage Vsw It is possible to lower the high-level potential.

  However, in such a configuration, the output voltage Vout (= Va + m × Vin−) obtained by simply adding the boosted voltage Va obtained by the DC / DC conversion unit A1 and the input voltage Vin boosted approximately m times. 2m × Vf) is obtained, and the effect of lowering the high level potential of the switch voltage Vsw is weakened. Therefore, it is desirable to adopt this configuration example.

  FIG. 3 is a circuit diagram showing another configuration example of the booster circuit used as at least one of the first power supply unit 1-1 to the nth power supply unit 1-n. Note that the booster circuit of this configuration example is substantially the same as the configuration example shown in FIG. 2, and instead of the diode D1, a P-channel MOS field effect transistor P1 is used as a rectifying element that forms the DC / DC converter A1. By using the switch SW11 to SWm1 instead of the point that the DC / DC conversion unit A1 is changed to the synchronous rectification method, the diodes D11 to Dm1 and the diodes D12 to Dm2 that form the charge pump units A31 to A3m, and The switches SW12 to SWm2 are characterized in that they are used.

  In the booster circuit of this configuration example, the transistors N1 and P1 forming the DC / DC converter A1 are both turned on / off exclusively based on the drive signal from the driver DRV. Further, the switches SW11 to SWm1 forming the charge pump units A31 to A3m receive a switch drive signal from the driver DRV and are turned on when the switch voltage Vsw is at a low level, so that the switch voltage Vsw is at a high level. When turned off. On the other hand, a logical inversion signal of the switch drive signal is input to the switches SW12 to SWm2 via the inverter INV, and is turned off when the switch voltage Vsw is set to the low level, and the switch voltage Vsw is set to the high level. It is turned on when

  As described above, in the booster circuit of this configuration example, the DC / DC conversion unit A1 and the charge pump units A31 to A3m are combined by using the transistor P1 and the switches SW11 to SWm1 and SW12 to SWm2 having a lower voltage drop than the diode. It is possible to further reduce the switch voltage Vsw by further increasing the boosting magnification at that time.

  FIG. 4 is a circuit diagram showing a configuration example of the output variable mechanism in the booster circuit, and particularly shows an input portion of the error amplifier ERR forming the feedback control unit A2. As shown in FIG. 4, in the booster circuit of this configuration example, the digital data DD read from the register unit 4 is converted into an analog signal as a reference voltage generation circuit connected to the non-inverting input terminal (+) of the error amplifier ERR. Thus, the digital / analog conversion circuit E1a that generates the reference voltage Vref is used. By adopting such a configuration, the voltage value of the reference voltage Vref can be flexibly adjusted based on the digital data DD input from the register unit 4, and the target value of the output voltage Vout can be arbitrarily set. It becomes possible to set to.

  FIG. 5 is a circuit diagram showing another configuration example of the output variable mechanism in the booster circuit, and particularly shows an input portion of the error amplifier ERR forming the feedback control unit A2. As shown in FIG. 5, in the booster circuit of this configuration example, a resistance value corresponding to digital data DD input from the register unit 4 is used as a feedback voltage generation circuit connected to the inverting input terminal (−) of the error amplifier ERR. Is used to generate a divided voltage (feedback voltage Vfb) of the output voltage Vout using digital potentiometers R1a and R1b. With such a configuration, the voltage dividing ratio of the resistor divider circuit can be flexibly adjusted based on the digital data DD input from the register unit 4, and the target value of the output voltage Vout can be arbitrarily set. It becomes possible to set to.

  In the above embodiment, the configuration in which the present invention is applied to the system power supply IC that supplies a plurality of power supply voltages to the liquid crystal panel has been described as an example, but the scope of application of the present invention is limited to this. However, the present invention can be widely applied to other power supply devices.

  The configuration of the present invention can be variously modified within the scope of the present invention in addition to the above embodiment.

  The present invention is a technique that can be used in general boosting circuits that boost the input voltage to generate a desired output voltage. For example, the technique is suitable for a system power supply IC that supplies a plurality of power supply voltages to a liquid crystal panel. is there.

These are block diagrams which show one Embodiment of the system power supply IC which concerns on this invention. These are circuit diagrams which show the example of 1 structure of the booster circuit used as at least any one of a 1st power supply part-an nth power supply part. These are circuit diagrams which show another structural example of the booster circuit used as at least any one of the 1st power supply part-the nth power supply part. These are circuit diagrams which show one structural example of the output variable mechanism in a booster circuit. These are circuit diagrams which show another example of a structure of the output variable mechanism in a booster circuit. These are the circuit diagrams which show one prior art example of a step-up type switching regulator.

Explanation of symbols

10 System power IC
DESCRIPTION OF SYMBOLS 20 Liquid crystal panel 1-1 to 1-n 1st power supply part-nth power supply part 2 Protection circuit part 3 Sequence control part 4 Register part 5 Power-on reset part 6 Serial interface part (serial I / F part)
7 Memory part A1 DC / DC conversion part A2 Feedback control part A31, A32, ..., A3m Charge pump part L1 Inductor (energy storage element)
N1 N-channel MOS field effect transistor (output switch element)
D1 Diode (rectifier element)
C1 capacitor R1, R2 resistance ERR error amplifier E1 DC voltage source OSC oscillation circuit CMP comparator DRV driver C11, C21, ..., Cm1 first capacitor C12, C22, ..., Cm2 second capacitor D11, D21, ..., Dm1 first diode D12, D22,..., Dm2 Second diode P1 P-channel MOS field effect transistor (synchronous rectifier)
SW11, SW21,..., SWm1 first switch SW12, SW22,..., SWm2 second switch INV inverter E1a Digital / analog conversion circuit (DAC)
R1a, R2a Digital potentiometer

Claims (8)

By turning on / off the output switch element connected to the other end of the energy storage element to which the input voltage is applied to one end, rectifying and smoothing the pulsed switch voltage drawn from the other end of the energy storage element, A DC / DC converter for generating a boosted voltage from the input voltage;
M stages connected to the subsequent stage of the DC / DC converter and generating a final output voltage by further boosting the boosted voltage by repeating a charge storage operation and a charge transfer operation using the switch voltage. (Where m is an integer greater than or equal to 1) charge pump unit;
A feedback control unit that performs on / off control of the output switch element so that a feedback voltage corresponding to the output voltage matches a predetermined reference voltage;
A booster circuit comprising: The n-stage charge pump units are respectively
A first capacitor having one end connected to the switch voltage application end;
A first diode or a first switch, one end of which is connected to the output terminal of the DC / DC conversion unit or the output terminal of the immediately preceding charge pump unit and the other end connected to the other end of the first capacitor;
A second diode or a second switch having one end connected to the other end of the first capacitor and the other end connected to the input end of the charge pump unit at the next stage or the output end of the output voltage;
A second capacitor having one end connected to the other end of the second diode or the second switch and the other end connected to the ground;
The booster circuit according to claim 1, comprising: The feedback control unit
A feedback voltage generation circuit that divides the output voltage to generate the feedback voltage;
A reference voltage generating circuit for generating the reference voltage;
An error amplifier that amplifies a difference between the feedback voltage and the reference voltage to generate an error voltage;
An oscillation circuit that generates a triangular or sawtooth slope voltage;
A comparator that compares the error voltage with the slope voltage to generate a PWM signal;
A driver that generates a drive signal for the output switch element based on the PWM signal;
The booster circuit according to claim 1, wherein the booster circuit comprises:   4. The booster circuit according to claim 3, wherein the reference voltage generation circuit includes a digital / analog conversion circuit that generates the reference voltage by performing analog conversion on input digital data.   4. The feedback voltage generation circuit includes a resistance dividing circuit that divides the output voltage using a digital potentiometer in which a resistance value is set according to input digital data. Booster circuit.   The booster circuit according to claim 4 or 5, which boosts an input voltage to generate a desired output voltage, and a register unit that volatilely stores control information regarding output setting of the booster circuit as the digital data, A power supply device characterized by being integrated.   A memory unit that stores digital data in a nonvolatile manner and an auto-read function unit that automatically reads the digital data stored in the memory unit and outputs the digital data to the register unit when the power supply device is activated are integrated. The power supply device according to claim 6, wherein the power supply device is formed.   8. The power supply apparatus according to claim 6, wherein an interface unit that outputs digital data input from outside the power supply apparatus to the register unit is integrated.

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