JP2010045391A - Method of manufacturing layered structure, semiconductor substrate, method of manufacturing element circuit, and serial connection circuit of solar cell element - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To manufacture a plurality of layered structures of the same structures by using a surface structure of a semiconductor substrate, and to manufacture an element at low cost by increasing an operation speed, reducing a used amount of a material, and reusing the semiconductor substrate. <P>SOLUTION: In the method of manufacturing the layered structure 28 formed of a semiconductor material, a porous layer 18 is formed on the semiconductor substrate 10, and the layered structure 28 is formed on the porous layer. The layered structure is formed by being separated from the semiconductor substrate while utilizing the porous layer as a target separation position and constituting a surface of the semiconductor substrate before the porous layer is generated, or i formed by constituting a surface of the porous layer. The layered structure is formed on a porus surface by at least partial epitaxial growth, and at least one semiconductor layer belonging to the layered structure is formed on the surface of the porous layer by epitaxial growth. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  In the present invention, a porous material layer (including a material layer having a hollow cavity) is formed on a substrate made of, for example, single-crystal p-type or n-type Si, and a layered structure or a part thereof is a porous material layer ( The porous layer is used as a target crushing position while mechanical strain is generated, for example, in the porous layer or at the interface between the porous layer and the layered structure. The present invention also relates to a method for manufacturing a layered structure sequentially separated from a substrate, a semiconductor substrate, an element circuit manufacturing method, and a series connection circuit of solar cell elements.

  The first type of method is known from documents.

European Patent Publication No. 0528229A1 European Patent Publication No. 0536788A1 European Patent Publication No. 0449589A1 European Patent Publication No. 0767486

January 20, 1997 Appl. Phys. Lett. 70 (3), 390, Rolf Brendel, Ralf B. et al. Bergmann, Peter L tgen, Michael Wolf and J rgen H. Werner's paper "Ultrathin crystalline silicon solar cell on glass substrate" S. Oelting, Dr. Martini and D.M. The Bonnet publication “Crystalline Thin Film Silicon Solar Cell Device by Ion Assisted Deposition” (this publication was published in Solar Energy Conference (“12th European Photovoltaic Solar Energy Conference (April 11-15, 1994, Amsterdam, It is also described on pages 1815 to 1818 of the minutes at "

  A method for manufacturing a semiconductor body is described in Patent Document 1 by way of example, in which a silicon substrate is generated porous, and a non-porous single crystal silicon layer is formed on the porous silicon substrate at a first temperature. The non-porous single crystal silicon layer is bonded to a second substrate having an insulator on the surface thereof. Thereafter, the porous silicon layer is removed by a chemical etching process, and another single crystal silicon layer is grown on the first non-porous single crystal silicon layer listed by epitaxial process at a second temperature.

  The significance of this method is that single crystal silicon can be grown on a desired substrate. However, this method is relatively complex because the porous silicon layer must be etched away. A similar method is apparent from Patent Document 2 and Patent Document 3.

  In Patent Document 4, a method as mentioned at the beginning is described. In this method, the porous layer has a portion in which more pores are formed. By performing the separation, the layered structure is separated from the substrate. Porous regions are created by iron implantation or altered current density during the production of the porous layer. Even if the separation method is improved by this, the method becomes more complicated and the risk of undesired separation before or during the production of the layered structure increases. To be honest, the first substrate can be used multiple times, but if used multiple times, the single crystal substrate becomes expensive in a relatively wasteful state.

  A similar proposal is also disclosed in non-priority European Patent Publication No. 799258.

  When manufacturing silicon solar cell elements at a modest cost, high quality silicon, single crystal silicon for high photovoltage, and thin Si layer for material storage are necessary, but still for proper absorption and energy saving. Low manufacturing temperatures and inexpensive foreign materials such as glass to obtain mechanical stability are also required.

  As far as we know, there is no way to meet all these criteria. For example, in the above-mentioned several European patent applications, a method is described in which CVD epitaxy is performed on porous silicon at a temperature of 800 ° C. or more, and the epitaxial layer thus formed is transferred to a glass substrate. The silicon layer is not structured. When performing the separation, a wet chemical process or a method of breaking the substrate wafer is used. There is no mention of applications in the photovoltaic field.

  Non-Patent Document 1 describes the possibility of manufacturing a structured polycrystalline silicon layer suitable for use as a photoelectric cell. However, this paper is not related to a single crystal material, and a complicated structuring of the glass substrate and complicated contact of the p and n layers are required to realize a photoelectric cell.

  In addition, another document related to porous silicon is a publication from Research Center J-Lich, which describes the fabrication of lateral diffraction gratings based on porous silicon and porous silicon interference filters.

  A method for texturing a substrate surface of crystalline silicon is known from JP-A-030833939, in which a porous layer is first formed and then etched. The pores of the porous layer are used as a starting point for the etching process, and in this way a very uniform texture is obtained.

  The thin-layer silicon solar cell element is described in Non-Patent Document 2.

  The object of the present invention is to solve the above-mentioned problems, not only parts, particularly inexpensive silicon solar cell elements, but also high-quality silicon, single crystal silicon for high photovoltage as much as possible, and thin silicon that does not waste material The object is to propose a method of the kind mentioned above which allows the production of layers and at the same time improves the light absorption while using low production temperatures and inexpensive foreign substances. In particular, the method aims to allow reuse of a substrate to be used or to allow a plurality of similar structures to be manufactured at low cost.

  Another object of the present invention is to propose a method for manufacturing a different new structure which is a starting point for manufacturing a plurality of structures with an epitaxial layer. It is a further object of the present invention to provide photocells and other semiconductor components by the method of the present invention that can be inexpensively manufactured and have excellent technical characteristics.

  To achieve this objective method, according to the present invention, the surface of the substrate is structured before the porous layer is formed, or the surface of the porous layer is structured. Here, structuring the surface means forming a hollow cavity or a depression on the surface of the layer.

  Since the porous layer is structured, mechanical separation is clearly improved at the interface with the layered structure without the need to purify a porous layer having two types of pores. However, not only is mechanical separation a problem, but other methods described in detail below are also described.

  Of particular importance are time savings, effort and material, which can be achieved by using structured layers, especially when structuring in the final product. Since the corresponding surface of the porous layer is structured, the layered structure can have the same structure.

  The manufacture of a thin part having a structured surface requires the manufacture of only a thin layered structure. However, when performing operations based on the prior art for flat surfaces, a thick layer that must be structured in a complex manner by removing material must first be produced.

  That is, when the method of the present invention is used, it is possible to produce a plurality of layered structures having the same structure, particularly using the surface structure of the substrate once produced, so that the porous layer is relatively thin, more preferably about It can be generated in the range of 100 nm to 10 μm, and the working speed can be increased without losing much material.

  When separating the layered structure from the substrate using mechanical stress, only the porous layer is damaged by the method of the present invention, but this separation takes place on the structured surface without damaging the substrate or the layered structure. In many cases, the porous layer remains protected because the separation can take place at the upper interface of the porous layer away from the substrate. Therefore, the substrate can be easily reused. Therefore, since the porous layer is usually damaged, the porous layer is removed first. After separation from the remainder of the porous layer, a new porous layer is created on the substrate so that the substrate can be reused.

  When the porous layer is removed from the layered structure by etching or mechanical removal, such reuse is not possible in the prior art.

  By the way, in this regard, a desired crushing position and a desired crushing surface can be obtained by using a layer having a hollow cavity instead of a porous layer, thereby generating a hollow cavity by, for example, photo-etching, and A hollow cavity can be opened in the free surface of the substrate. In this application, only the porous layer will be briefly described. However, it will be apparent that layers that have hollow cavities and that form the desired fracture location are also included in such porous layers.

  When the surface of the porous layer is flattened, the layered structure can be separated from the substrate as described above. This is particularly preferable when manufacturing photoelectric cells and various other components, and when the surface of the porous layer that is separated from the substrate is structured, the growth of the layered structure is proceeding on the porous layer. The layered structure reflects the structuring of the porous layer. For example, in the case of a solar cell element, light trapping is performed with substantially high efficiency.

  Since the structured surface of the substrate is protected and can be reused, multiple identical layered structures can be manufactured from one substrate after any cleaning process or after a structured refresh. In particular, the method can be made substantially cheaper since there is no need to restructure the substrate each time.

  In principle, the production of the structured surface of the porous layer takes place in two ways. In one method, the surface of the single crystal substrate is structured and then made porous by a known method. The porous layer manufacturing process automatically creates a porous layer with the same structure as the structured substrate itself, along with the thin layer, on the upper boundary surface away from the substrate and the lower (complementary) boundary surface facing the substrate. Is done. In another method, the flat surface of the single crystal semiconductor substrate is made porous, and then the surface of the porous layer is structured. Various possible ways of doing this structuring are set forth in claims 2 and 3.

  The substrate is not necessarily a single crystal, and may be a polycrystal. In this case, the particle size of the single crystal material is larger than the width and thickness dimensions of the structure and the thickness of the porous layer, for example, a particle size of 100 μm to centimeter.

  The difference in thickness and width of typical structures considered for solar cell elements is in the range of 0.5 μ to 00 μ, respectively. When a thin porous layer is used in the range of about 100 nm to 10 μm, even if the same substrate is used a plurality of times, that is, even if a plurality of porous layers are generated on the same substrate, The shape of the porous surface remains faithful to the structured shape of the substrate.

  The layered structure is at least partially pressed against the porous surface by an epitaxial method. That is, the porous layer has the same crystal structure as that of the original substrate, and becomes suitable for the growth of the layered structure by the epitaxial method, and the grown layered structure has the same crystal structure. That is, the layered structure is also a single crystal.

  The epitaxial method can be executed as a homogeneous epitaxial method or a heterogeneous epitaxial method. Heterogeneous epitaxial methods are preferred because some porous layers are produced, and there is no need to worry about significant distortion in the boundary surface region.

  In the epitaxial method, at least one semiconductor layer belonging to the layered structure is pressure-bonded to the surface of the porous layer. Depending on the purpose of the layered structure, other layers can then be pressure bonded to the generated semiconductor layer, but these multiple layers need not have a single crystal structure as well. However, there are many structures in which the layered structure includes a plurality of single crystal semiconductor layers, for example, there are two layers forming a pn junction.

  However, according to claims 4 and 5 of the present invention, a metal layer is attached to the layered structure and / or a dielectric, for example a transparent or transmissive window layer, is crimped, for example by a sol-gel treatment or an adhesive. Can be made.

  This is because, for example, the carrier layer is formed as a part of the layered structure by contacting the layered structure by bonding, wafer bonding or diffusion soldering (diffusion soldering method), or by continuously performing the epitaxial processing, for example. Is particularly preferable. When the carrier layer is pressure-bonded to the surface of the layered structure by bonding, wafer bonding, or diffusion treatment, the carrier layer can be made of glass or aluminum, for example. The carrier layer of the carrier is usually composed of an inexpensive and stable material such as glass. The mechanical separation of the layered structure from the substrate can be achieved, for example, by peeling on the carrier layer or on the carrier, so that the carrier layer or carrier having the layered structure is separated from the substrate. The carrier layer or carrier forms another substrate on which the layered structure is provided. Thus, the following treatment can be performed on the free surface of the layered structure. For example, when the layered structure is a processed semiconductor element, it can be easily covered or provided with a film or a surface contact. According to the present invention, contacts, gates or electrodes can be created on both sides of the layered structure, which provide various advantages for both the technical manufacturing viewpoint and the physical characteristics of the manufactured semiconductor components. This is very important.

  If the layered structure has not yet been processed, another semiconductor layer is formed by epitaxial method on the free surface of the layered structure, and another structure is formed by photo-etching or other methods as necessary. It can be done arbitrarily. The single crystal of the layered structure is held during the epitaxial process.

  As mentioned at the beginning, after separating the layered structure from the substrate at the target crushing position, it is possible to newly use a substrate having the remaining porous layer as a substrate to be crimped to another layered structure. is there.

  This method is particularly preferably developed according to claim 11. That is, before or after separating the layered structure from the substrate, another porous layer is generated on the surface of the layered structure separated from the substrate, and another layered structure is provided on the porous layer. By optionally repeating this method a plurality of times, a plurality of layered structures, particularly structured layered structures, overlap each other, which are each separated from adjacent layered structures by a porous layer forming the desired fracture location, After manufacturing such multiple structures, each layered structure can be separated from each other by the generation of mechanical stress within or at the boundary surface of each porous layer.

  During the generation of the multiple structure, each layered structure can be manufactured very reasonably, and then the layered structure can be separated from the multiple structure one by one. That is, exactly as in the case where a single layered structure is formed on the substrate, each layered structure has a carrier layer or carrier before separating each layered structure from the multiple structure. This is as described in detail above.

  In this variant of the method according to the invention, other structures can optionally be grown on the layered structure thus formed by an epitaxial method.

  Another variant of the invention produces or crimps a porous material layer outside or on the first substrate, and the layer optionally has structured free surfaces, e.g. grooves arranged to be parallel to each other. Further, the second substrate is pressure-bonded to an optionally structured free surface of the porous material layer, and then a layer or section with the porous material layer remains or remains attached to the second substrate. By generating such mechanical strain, the second substrate is sequentially separated from the first substrate by using a porous layer as a target crushing position, whereby the second substrate can be used by an epitaxial method.

  When the remaining porous layer is removed from the first substrate after separating the second substrate from the first substrate, it is particularly preferable to newly form a porous layer on the substrate and repeat this process. This process can optionally be repeated multiple times to produce a plurality of second substrates based on one substrate.

  Since the sections of the porous layer remain bonded to each second substrate, the desired layered structure can be grown on these substrates by epitaxial methods. Since the arrangement of the crystal structures in each section of the porous material layer is the same, the structures grown on the second substrate by the epitaxial method have a single crystal structure as well, so that the epitaxial method is based on an expensive substrate. It is possible to manufacture a plurality of substrates to be used at low cost.

  There are various methods for crimping the second substrate onto the first substrate. One method uses an adhesive, and another method deposits a metal layer on the porous surface of the first substrate and bonds the metal layer to the carrier material in another way. The carrier material can also be bonded to the porous layer of the first substrate by a diffusion brazing process. After separating the second substrate, it is very important that the porous substrate sections of the first substrate are present dispersed on the surface of the second substrate.

  There are many ways to generate mechanical stresses in a porous layer that separate the entire layered structure or a portion thereof from the substrate. These methods are described in claim 15.

  The substrate produced by the method according to the invention is an intermediate product and is itself valuable and is exactly as described in claims 19-24.

  Preferred embodiments of the subject matter of the present invention are set forth in the dependent claims.

  According to the present invention, since a plurality of layered structures having the same structure can be manufactured using the surface structure of a semiconductor substrate that has been manufactured once, the porous layer is relatively thin, more preferably in the range of about 100 nm to 10 μm. It is possible to increase the working speed without losing much material. In addition, the element can be manufactured at low cost by reducing the amount of material used and reusing the semiconductor substrate.

It is a series of schematic diagrams showing a first modification of the manufacturing method of the present invention. It is a recording by the electron microscope of the layered structure without a carrier layer corresponding to FIG. 1B. FIG. 3 is a recording by an electron microscope on the upper side of the substrate after the removal of the layered structure of FIG. 2 and before execution of a cleaning process. FIG. 2 is an electron microscope recording of the layered structure of FIG. 1 viewed from a different angle in order to prove the lower quality of the layered structure. Figure 2 is a schematic view of a possible multiple structure produced by the method of the present invention. It is the schematic which shows the modification of the method of this invention. It is another modification of the method of the present invention. It is a schematic sectional drawing of the solar cell element manufactured by the method of this invention. It is a top view of the structure of FIG. 8 which passes along an IX-IX plane. It is a schematic sectional drawing of a radiation detector. FIG. 11 shows the detector of FIG. 10 viewed from the free direction XI. It is the same schematic as FIG. 6 which added correction. It is the schematic which shows manufacture of the semiconductor layer which is a single crystal in a predetermined area | region, and becomes amorphous in another area | region. 3 is an X-ray diffraction spectrum of the silicon “waffle” of FIG. 2 and a single crystal substrate. FIG. 2 shows the temporary microwave reflectivity ΔR of Si “waffle” with Wf = 5.8 μm thickness in FIG. 2 after optical excitation with a 20 ns laser pulse. This is the measured hemispherical reflectivity of the encapsulated waffle structure. It is the theoretical energy conversion efficiency (solid line) and ideal element thickness (broken line) of the solar cell element which has the waffle structure of FIG. FIG. 10 is a schematic view similar to FIGS. 8 and 9, but showing a modified embodiment. FIG. 10 is a schematic view similar to FIGS. 8 and 9, but showing a modified embodiment. This is a series connection of solar cell elements in the module. In Ψ processing, it is a schematic diagram of an integrated connection using a shadow mask that moves from position 1 to position 3 while moving the shadow mask or sample in the horizontal direction. 1 is a schematic diagram illustrating a method according to the present invention for separating a layered structure from a substrate at a boundary surface region for a porous layer. FIG. 1 is a schematic diagram illustrating a method according to the present invention for separating a layered structure from a substrate at a boundary surface region for a porous layer. FIG.

  Hereinafter, the present invention will be described in detail with reference to examples and drawings.

  FIG. 1A shows a p-Si silicon substrate (semiconductor substrate) 10, for example, and an n-Si substrate will be described in the same manner. The Si substrate 10 has, on one surface thereof, a structure 12 that can be considered as a matrix of pyramidal depressions 14 and base surfaces that are placed directly parallel to each other, so that the upper boundary of the surface is a square lattice. Very similar.

  Next, the substrate 10 is processed in a known manner to produce a porous silicon layer 18 (FIG. 1B). The upper side of the porous silicon layer 18 has the same shape as the structured surface of the Si substrate 10. The interface between the porous silicon layer 18 and the substrate has the same shape.

  Next, the substrate 10 is coated by an epitaxial method. Thus, an epitaxial silicon layer 22 is formed on the surface of the porous layer 18. In principle, this layer 22 can be formed using any known epitaxial method, in particular vapor phase epitaxy (CVD), ion assisted epitaxy, plasma assisted epitaxy, liquid phase epitaxy and molecular beam epitaxy. .

  As can be seen from FIG. 1C, the free surface of layer 22 also has the same shape as the structured surface 12 of the silicon substrate of FIG. 1A and the porous silicon layer of FIG. 1B. Similarly, the interface between the layer 22 and the porous layer 18 has the same shape. This applies especially when the porous layer 18 is thin. In this figure, the thickness of the layer is indicated by “w”.

  Furthermore, the crystal orientation of the layer 22 is the same as that of the substrate 10 and the porous layer 18 formed from the substrate 10. The layer 22 is composed of single crystal silicon.

  Although not specifically illustrated, in the next step, the grid electrode 24 is applied to the layer 22 such that the grid electrode 24 extends along only part of the lines forming the grid 16. A layer structure is then formed by the layer 22 and the lattice 24 comprises a glass layer 26. This glass layer 26 can be produced by a so-called sol-gel process. Brendel, A.M. Gier, M .; Menning, H.M. Schmidt, J. et al. H. The publication by Werner, “Sol-gel coating for light traps in crystalline thin-film silicon solar cell devices” (Journal of non-crystalline solids, 218 (1997), 391-394). According to this, as shown in FIG. 1E, for example, a mechanical stress that “peels” the glass cover disk 26 from the substrate 10 is generated in the porous layer. In this way, the layered structure is separated from the porous layer 18, and in this example, the layered structure is composed of the epitaxial silicon layer 22, the lattice electrode 24, and the glass cover 26. In this regard, this boundary serves as the intended break location because separation is advantageously performed at the interface between the porous layer 18 and the epitaxial layer 22 and is easily superior to mechanical bonding. Thereafter, as shown in FIG. 1F, the layered structure 28 is pressed against the metal plate 30 to form the solar cell element in this way. The metal plate 30 on the one hand serves as a contact portion for the pyramidal tip 32 of the single crystal silicon layer 22 and on the other hand also functions as a reflector, so that light that has not yet been absorbed by the silicon passes through the layer 22 again, It becomes possible to be absorbed.

  Incidentally, since the grating 24 is made of gold and silver wire, there is no significant loss of light due to the reflection of the incident light 34.

  The structure of such a photoelectric cell will be described in more detail with reference to FIGS.

  To assure the quality of the method of the present invention, reference is first made to FIGS. Each figure shows an electron microscope record, FIG. 2 shows the top surface of the epitaxial Si layer 22 of FIG. 1, and FIG. 3 shows the free surface of the porous layer formed after the epitaxial Si layer 22 is removed. ing. FIG. 4 shows another recording of the epitaxial layer 22, which is shown from another viewpoint, and it can be seen that there is no problem with the boundary surface of the porous layer 18.

  The record of FIG. 3 shows the surface of the substrate 18 after separation of the epitaxial layer 22 and before cleaning to remove the residue of the porous layer 18 from the free surface. After cleaning by etching and / or sonication, the same free surface of the substrate 10 appears as the porous layer 18 is produced and the epitaxial silicon layer 22 is grown. Thus, just like layer 22 in FIG. IC, a new porous layer 18 may be provided on substrate 10 and reused for growth of another layered structure or semiconductor layer.

  Therefore, this is the first method that allows the substrate 10 to be used multiple times.

  In the example of FIG. 5, a p- or p-Si-like substrate 10 is similarly prepared, and the structured porous layer 18 is also disposed thereon. The structure of the first free surface of the porous layer 18 applies exactly to the cross-sectional shape of the relevant interface, for example in the embodiment shown in FIG. That is, 19 represents the uppermost interface of the porous layer 18 (that is, the interface of the porous layer 18 away from the substrate 10).

  Two successive layers of n-Si and p-Si, i.e. layers 22A and 22B, are grown on the structured surface of substrate 10, i.e. porous layer 18, by an epitaxial method. After producing the two layers 22A and 22B, the free surface of the p-Si layer 22B first extends to a height of 40 and has the same cross-sectional shape as the interface 19. Thereafter, layer 22B is processed for formation in another porous layer 18A in the upper region, which corresponds to the shape of porous layer 18 of FIG. 1, for example. Next, when this process is repeated a plurality of times, the other layers 22A ′, 22B ′, 22A ″, 22B ″, 22A ″ ′, 22B ′ ″ and the like are generated, and the porous Si layer 18A ′. , 18A ″, 18A ′ ″, the free surface treatment of the upper layer 22B (B ′, B ″, B ′ ″, etc.) is performed each time.

  Next, the multiple structure of FIG. 5 includes each layered structure 22A and 22B (22A "", 22B ""), (22A "", 22B "),. . . (The order of 22A and 22B) is divided so as to be separated from the multiple structure. The layer bundle of FIG. 5 to each structure comprising n-layer and p-layer, ie 22A, 22B, layers 22A ′, 22B ′, 22A ″, 22B ″, 22A ′ ″, 22B ′ ″, respectively. This division is also possible by putting the layer bundle in an etching bath for a relatively long time, for example, several hours to several days. Although the porous material is etched more rapidly, there is a problem that the surfaces of the useful layers 22A and 22B and the layers 22A 'and 22B' are also etched.

  In another separation method, the carrier in each case can be bound to the free surface of a set of layers that are then separated, and the separation can be performed, for example, while the temperature is changing. . After washing, the electrodes can be provided in a set of layers if desired.

  It is clearly understood that the several sets of layers 22A, 22B, etc. described in the example with reference to FIG. 5 form an n− / p− junction. After adding the necessary electrodes, it is possible to bond one surface of several sets of layers to a carrier material comprising a glass layer, for example as shown in FIG. Next, several sets of layers that have undergone such treatment can be flipped over and another structure can be pressed against the free surface of each lower layer 22A (22A ', 22A ", etc.) by an epitaxial method. In some cases, the substrate 10 with the structured porous layer 18 can be reused.

  In this regard, it is emphasized that the porous Si layer is not limited to the above pyramid shape. In practice, a wide variety of structures can be selected as needed.

  This also becomes clear, for example, in the embodiment of FIG. That is, FIG. 6A also shows the Si substrate 10 having the porous Si layer 18. In this case, the porous Si layer 18 has a groove-like cross-section 50 that is arranged in parallel to each other and is constituted by longitudinal grooves 52 that are separated from each other by a web 54 of porous silicon material. These grooves 52, or the corresponding webs, are formed in the desired manner, for example by mechanical grinding or by locally grinding the porous layer 18 using a casting tool or a profile roll.

  Next, an outline of a method of applying the adhesive 56 to the surface of the porous layer is shown in FIG. 6A. The adhesive 56 adheres the second substrate 58 made of a desired material to the first substrate 10, and a finished structure shown in FIG. 6B is obtained. Next, when the mechanical separation process is performed, the second substrate 58 is separated from the first substrate 10 and the web residue 54B together with the adhesive layer 56 and the portion 54A of the web 54 as shown in FIG. 6C.

  As a result of the manufacturing method, the crystal orientation of the porous layer 18 is the same as that of the substrate 10, and this crystal orientation is also included in the web 54. Furthermore, the orientation of this crystal is the same for all webs 54 and is compatible with the section 54A secured to the second substrate 58. The substrate 58 having the section 54A can then be used to grow another structure on the free surface having the section 54A by epitaxial methods. Thus, a single crystal semiconductor material is produced on the substrate 58, ie, single crystal silicon on the web 54A.

  Next, the first substrate 10 is reused to completely remove the residue of the porous layer 18, and the method of FIG. 6 is performed again. This method can be repeated multiple times.

  In the embodiment of FIGS. 6A to 6C, even if this structure is preferably realized by using a smoothed or structured surface, separation at the boundary surface with respect to the porous substrate is performed by the method described in FIGS. When doing so, it is possible to work with an unstructured porous layer according to the invention, although this is not the only case.

  FIG. 7 is a schematic diagram showing another embodiment of the method according to the present invention.

  Here, a cylindrical portion of single crystal silicon is continuously processed to produce a porous silicon surface. For this reason, the lower part of the cylindrical rod 60 is lightly immersed in the HF tank, and a voltage is generated between the grid electrode 62 and the cylindrical rod 60. By using this voltage and the HF tank, a current is generated and a porous Si layer is generated.

  While the cylindrical rod 60 is rotated, the flexible substrate material is pressed against the exposed surface of the porous Si layer, and then, for example, a curing agent is sprayed thereon, and further this is used to peel the porous Si layer from the surface of the cylindrical rod 60. To do. The porous Si layer 18 is originally curved, but has a permanent stress that can be used for manufacturing a predetermined component because it is linearly stretched by peeling off by the substrate 10. This variant has the advantage that a band-like substrate, ie a band-like substrate 10 having a band-like porous layer 18 that can be used for many different purposes, can be produced.

  For example, the porous layer 18 can be structured and used to carry out any of the methods described above. That is, first, a semiconductor layer is formed on the free surface of the porous Si layer 18 by an epitaxial method, and this is optionally structured, and then corresponding single or plural semiconductor layers made of a single crystal material are sequentially formed.

  When the flexible substrate is later formed into a tubular shape and epitaxy is performed, a single crystal Si tube is generated. This is important as a silane supply line for epitaxial reactors because silicon tubes are mechanically very stable and do not contain foreign atoms. It is also flexible and can be used, for example, in the production of foils that are spread on arbitrarily curved glass surfaces of vehicles operating on solar energy.

  Next, another method of use will be described in detail.

A. Method for structuring a substrate with an inverted pyramid:
a) 45 min oxidation (1% trans LC) at 1000 ° C. of (100) oriented and polished Si wafer. A 100 nm thick SiO ₂ layer is produced.
b) Photoresist exposed by photoetching using a reticulated mask. Depending on the mask configuration, only the photoresist after development on the web of about 2 μm width remains, and a free surface of 11 × 11 μm ² is formed on the web.
c) Remove oxide with buffered HF in about 2 minutes. The photoresist is removed.
d) The RCA1 and RCA2 cleaning is completed by immersing in HF.
e) The inverted pyramid portion is etched with 8% KOH solution at a temperature of 80 ° C. for 10 minutes. After the etching process, the sample is rinsed with high purity water and dried. Remove the oxidized web to a visible extent. This anisotropic etching technique produces an oriented crystal surface (111). Since hydrogen can be stably infiltrated into the free bonding portion of the surface (111), generation of SiO _{2 on} the surface can be surely prevented. Thus, even in the next epitaxial process, the method and reactant are considered not to cause thermal conduction of the oxide.
f) Other methods:
f1) Pyramids randomly arranged by anisotropic etching with KOH (not photoetching)
f2) Mechanical grinding with specially shaped saw blades (typical structure size is 100 μm) f3) Deeply ground porous silicon is generated with non-uniform illumination (n-type Si) and later removed again f4 ) The starting wafer may be single crystal Si, such as a block casting material.

  B. Method for creating a porous layer on the surface of a structured wafer:

a) The wafer is B-doped with a receptor concentration between 50 × 10 ¹⁸ cm ^{−3 and} 2 × 10 ¹⁹ cm ⁻³ . RCA1 and RCA2. Removal of residual oxide with HF.
b) The etching apparatus corresponds to that disclosed in FIG. 2b of EP-A-0536788. Porous silicon is produced by anodic corrosion with HF, H ₂ O and ethanol. Note that HF: H ₂ O: ethanol = 1: 1: 2 (at room temperature). The structured side of the substrate faces the cathode. The porosity of the layer is adjusted by the current concentration, and a typical current concentration is 1 to 100 mA / cm ² .
c) Producing a first porous layer of about 150 nm thickness with low porosity (about 35%), followed by a second porous layer of about 10 μm thickness with high porosity (50%).
d) A silicon disc having a structured porous surface is oxidized at 400 ° C. for 30 minutes in a dry O 2 atmosphere and stored in an inert gas (N 2) prior to epitaxy.

C. Epitaxial method of ion-assisted deposition:
This process is described in S.A. Oelting, D.C. Martini, D.M. It is described in detail in a paper by Bonnet, “Crystalline Thin Film Silicon Solar Cell Device by Ion-Assisted Deposition”. As shown in FIGS. 2 to 4, the sample on which the SEM is recorded is subjected to an epitaxy process as follows.
a) Dip in HF for RCA1 and RCA2 clean (30% with 5% HF, then rinse with deionized water).
b) Feed into the reactor and remove gas at 400-500 ° C.
c) Heat to 850 ° C. for 10 minutes to remove residual oxide.
d) With a Ga doping of 5 × 10 ¹⁷ cm ⁻³ , a 10 μm thick silicon layer (measured parallel to the macroscopic surface normal of the substrate wafer) was grown. The temperature of the Ga pool is 670 ° C., and the substrate temperature is 700 ° C. The deposition rate is 4 μm / h. Coating is performed under high vacuum (<10 ⁻⁵ Pa). The continuously doped layer, in particular the pn junction produced during epitaxy, likewise separated without problems.
e) Other epitaxy methods e1) Liquid phase epitaxy (LPE). LPE is interesting because it is possible at temperatures below 850 ° C.
e2) Solid phase crystallization (SPC) of amorphous Si (a-Si). Deposition plants that perform large-area a-Si deposition are interesting because they are prior art. The disadvantage is the slow SPC rate (5-10 hours for recrystallization).
e3) Vapor phase epitaxy (CVD) as disclosed in the Canon patent. CVD requires a deposition temperature exceeding 900 ° C., and the disadvantage is that the porous material is sintered. Mechanical separation is difficult or impossible.
e4) Plasma assisted vapor phase epitaxy (LPCVD). Interesting because it is possible at low temperatures.
e5) Hot wire epitaxy because a high deposition rate (> 1 nm / s) is possible at low temperatures (<600 ° C.).
e6) Laser crystallization of amorphous Si because it is rapid and only low temperature loading of the substrate and porous Si is performed.

E. Separation process a) A 10 μm thick epitaxial layer on a porous layer of a substrate wafer is placed on a heating plate at a temperature of 125 °. The epitaxial layer is on top.
b) A glycol phthalate is placed on the heated epitaxial layer, and a cover glass having a size of ² cm × 2 cm = 4 cm ² is further placed thereon. This transparent polymer softens and flows under the weight of the glass plate, and after 10 minutes, completely removes the air between the epitaxial layer and the glass. After cooling, the glass is bonded to the structured epitaxial layer.
b1) Adhesives different from glycol phthalates, eg plastics customary in the photovoltaic field.
b2) Use of mechanical carriers other than glass, such as plastic foil. Such flexible carriers take advantage of the fact that thin structured epitaxial layers are also very flexible (elastic solar cell elements).
b3) on the epitaxial layer. "B3) Use of a sol-gel glass that can be molded and cured on an epitaxial layer. For more information on the sol-gel technique, see the article" Sol-gel coating for light trapping in crystalline thin films "( R. Brendel et al., Journal of non-crystalline solids, 218 (1997), 391-394).
b4) Anodic bonding of structured epitaxial layer to glass or “direct wafer bonding” of epitaxial layer to Si.
c) The glass is easily separated with the epitaxial layer. The porous layer is partially broken at the central portion, part remains on the substrate, and another part adheres to the epitaxial layer. All porous Si residues are removed by sonication for 2 minutes. The epitaxial layer is firmly bonded to the glass. When sonication is performed prior to peeling, a weak mechanical force is required to peel the glass from the substrate along with the epitaxial layer.

Alternative methods for performing mechanical separation c1) When the epitaxial layer is heated (for example) shockously with light vibrations, a large temperature gradient is created in the porous layer, thereby breaking the porous layer.
c2) Filling the hollow cavity of the porous layer with liquid or gas. The liquid or gas expands and destroys the epitaxial layer.
c3) A large mechanical pressure is applied to the epitaxial layer.
c4) Since resonance radiation coupling to the porous layer functions as a waveguide, radiation concentrates on the porous material.

  Next, semiconductor components realized by the present invention will be described.

  First, FIGS. 8 and 9 show a photoelectric cell which is a solar cell element here, and a layered structure 22 made of an n-type Si layer and having the same shape as the layer 22 of FIG. 1 is provided in the core.

  The aluminum plate or foil 30 is disposed below the layered structure 22 and is in contact with the pyramidal tip 32 of the layered structure 22. By the heat treatment, as shown at 70, aluminum atoms are diffused to the tip of the layered structure 22, and p-type Si is generated instead of n-type Si. That is, the pn bond necessary for the photoelectric cell is obtained in this way.

  Instead of the above, as shown in FIG. 5, for example, the layered structure 22 may be composed of a first layer 22A of n-type Si and a second layer 22B of p-type Si. It shows with. The structure of the lower reflector that also functions as an electrode is the same as described above.

  In this example, finger-like lattice electrodes 24 are provided on the layered structure 22 as shown in FIG.

  In a practical embodiment, the area is somewhat different from that shown in FIG. Each finger 25 of the grid electrode has a width of about 20 μm, that is, about twice the width of each pyramid of the layered structure 22. Further, as shown in the figure, the lattice fingers 25 are not provided for every fifth lattice line, and the number of exposed lattice cells provided between the fingers is very large, for example, 1000. is there.

  It is also possible to manufacture the grid electrode 25 from a transparent material such as indium tin oxide. The grid electrode 25 may be provided on the entire lower region of the plate 26 or on the upper surface of the layered structure 22.

  As described below, the installation of the glass plate is started.

  In the case of a solar cell or the like, the structure of the Si layer is very important because a large amount of sunlight can be absorbed by the thin layer only by this method. In contrast to known methods (direct silicon deposition on flat or stamped glass), the front and rear sides can be freely touched as described herein.

  Complex contact tissue is not necessary (for example, as described on Jan. 20, 1997, Appl. Phys. Letters Vol. 70, No. 3, pages 390-392). Epitaxy, i.e., pn transitions have been created in layers 22A and 22B, for example between a metal mirror surface (e.g. aluminum sheet 30 above) on a carrier material such as glass and a transparent conductor (e.g. indium tin oxide or zinc oxide) If the layered structure, that is, the waffle is easily fixed, the production of the solar cell element becomes very simple. Therefore, vapor deposition of the finger is not necessary. Mechanical pressing is sufficient.

  In solar cell device applications, the reuse of structured substrate wafers is an important feature.

  It is possible to reduce the thickness of the porous layer 18 from the previously used experimental value of 10 μm to less than 1 μm. When the porous layer is reduced, the frequency of reuse of the substrate wafer can be increased.

  18 and 19 are schematic views similar to FIGS. 8 and 9, but showing a modification.

  Here, the structure of the layered structure exhibits somewhat different efficacy, so that the predetermined pyramid tip 22D of the upper layer 22A faces upward. That is, this tip is higher than the other pyramid tips. This embodiment shows a method of controlling the contact frequency to the layered structure independently from the grating period P by carefully selecting the substrate structure.

  FIG. 20 shows a method of forming a module by connecting various solar cell elements shown in FIGS. 8 and 9 in series, for example. As shown here, a spring 80 is used to electrically connect the upper and lower electrodes or conductors to each other. The triple voltage of the solar cell source can be obtained between the points A and B.

  10 and 11 are schematic diagrams illustrating possible embodiments of radiation detectors.

  The structured Si epitaxial layer 22 bonded to the glass substrate forms a number of chambers 72 that are closed and filled with a predetermined amount of gas. The chamber thus formed is closed by the upper glass plate 26. As the radiation passes through the glass and enters each chamber 72, the gas is heated and expands, causing the film formed of the layered structure 22 to bend. This expansion can be detected by the piezoelectric element 74. When different regions of the detector are used for different wavelengths of radiation to be detected, for example, a filter is provided on the upper glass plate 26 that passes only each radiation to be detected.

  10 and 11, only four chambers 72 are shown. There are actually more rooms than this.

  It is also possible to use the structure of FIGS. 10 and 11 for a pressure sensor. A plurality of closed chambers are shown in which a structured Si epitaxial layer bonded to glass is filled with a predetermined amount of gas. As the external pressure changes (pneumatic or mechanical pressure), the chamber walls bend. Such bending can be detected by a piezoelectric element in each chamber.

  Another possible application of the layered structure is the use of special mirrors (micromirrors with special characteristics) made by special structuring of the reflective surface of the layered structure.

  12A to 12D show a structure similar to that shown in FIG. 6, but the special outer shape of the porous layer is not formed.

  Specifically, FIGS. 12A to 12D show a method for manufacturing a substrate on which a single crystal semiconductor layer is pressure-bonded by epitaxy.

  As a first step, a substrate 10 of semiconductor material, preferably silicon, is treated to produce a plate-like porous layer having a flat interface.

  Next, if possible, an adhesive 56 already provided with a carrier 58 is applied to the porous layer so that at least a portion of the adhesive penetrates into the porous layer 18. Thereafter, the adhesive is mechanically separated from the substrate. If the adhesive is a compound having sufficient mechanical strength, the carrier may be omitted. That is, the adhesive itself forms a carrier. However, the adhesive can be reinforced with a carrier 58 as needed.

  If possible, the adhesive having a carrier is separated from the substrate 10 so that the porous semiconductor material having a desired orientation permeates the surface formed by the separation. An adhesive having a coating of porous material and possibly having a carrier 58 on the side away from the porous material forms a substrate for subsequent epitaxial processing.

  The substrate 10, which would normally have porous material residues, is first cleaned to remove these residues. As a result, a porous layer is newly formed, and the substrate 10 can be reused.

  13A to 13H show a method for manufacturing a semiconductor layer in which a predetermined portion is a single crystal and the other portions are amorphous.

  According to FIG. 13A, a flat substrate made of a monocrystalline or polycrystalline semiconductor material such as Si is first provided.

  FIG. 13B very simply shows that one side of the substrate is structured to provide a structure depth h by providing grooves or holes or a desired pattern by grinding or etching.

  According to FIG. 13C, a porous layer having a thickness of WPS is produced by known methods such as anodic corrosion with HF.

  Thereafter, an adhesive, such as sol-gel glass, is applied to the structured surface of the structure and all or part of it penetrates into the porous layer. Thereby, as shown in FIG. 13D, the porous layer 18 into which the adhesive has penetrated is formed.

  Thereafter, as shown in FIG. 13E, the adhesive is mechanically separated from the substrate, and a part of the porous layer into which the adhesive 56 penetrates is bonded to the adhesive. And after an appropriate surface treatment (removal of porous layer residues and optional new structuring), the substrate 10 can be used.

  A second substrate made of an adhesive (possibly with a carrier) and a porous processing material into which the adhesive has penetrated is subjected to a process such as polishing, and partially with a determined crystal orientation as shown in FIG. 13F. A layered structure is formed that includes a porous material but does not include a porous material in another portion.

  Thereafter, as shown in FIG. 13G, an amorphous layer 76 is deposited over the entire surface 78 in the stage 13F.

  Thereafter, as shown in FIG. 13H, for example, heat treatment is performed, solid-phase crystallization of the amorphous material occurs, and an oriented nucleation seed in which the porous material in the adhesive is determined is obtained. The material remains amorphous where there is no porous layer. According to FIG. 13B, the corresponding position is the position where the recess 14 was formed while the substrate 10 was being structured. The structure shown in FIG. 13H forms the starting point for manufacturing a product such as a flat screen. That is, it becomes possible to form a control transistor with a single crystal portion that controls the light emission state at the amorphous portion while structuring the product of FIG. 13H to emit light at the amorphous portion.

  Another interesting possibility according to the invention is that, as described above, the substrate is first made porous near the surface and the crystalline Si layer is not deposited on the porous layer by epitaxy, but by rapid dissolution followed by solidification. Is converted into a single crystal porous layer by a method different from the above. That is, the top layer of the porous layer is first melted at least locally and then solidified again.

  This can also be understood as a type of porous substrate epitaxy. However, the epitaxy material originates from the porous layer itself. After forming the single crystal non-porous layer by melting the porous layer and subsequent solidification, the solidified layer is separated from the substrate once or the layered structure is grown on the solidified layer and then the solidified layer is removed from the substrate. Can be separated.

  By generating mechanical strain in the porous layer or at the interface with the porous layer, or by using the method described with reference to FIGS. 22 and 23, the porous layer can be used as the target crushing position. Separation is performed in advance using a layer having the same.

  Preferably, melting is performed by emitting laser light pulses from an excimer or copper vapor laser. This is described, for example, in Ishihara and M. et al., October 26, 1995, Electronic Letters Vol. 31, No. 22, pp. 1956-1957. It can be carried out according to the method described in the publication by Matsumura “Growth of giant grains of Si films on glassy substrates”.

  The difference from the method described in this publication is that the porous silicon is changed to single crystal Si. Short light pulses are possible as well, and only the portion close to the surface can be melted in this way, and the porous material existing underneath is not changed, which is advantageous compared to long-term radiation. There is also a technical problem that the crystal layer is torn due to the generated thermal gradient. This problem can be prevented by appropriately adjusting the porous Si or by generating and separating layers at once, which is possible according to the invention.

  As an alternative to laser treatment, zone drawing can be considered as one method of rapid heating. In this way, the porous layer is guided under a linear bundle of electron or light beams, resulting in a partially crystalline layer. A corresponding method is described in the solar energy material and solar cell element 41/42 (1996), pages 119-126. Pauli, T .; Reindl, W.M. Kr hler, F.M. Homberg and J.H. Mller, described in a publication entitled “A Novel Method for Fabricating a Polycrystalline Silicon Layer on a Graphite Substrate Suitable for Low-Cost Thin-Film Solar Cell Devices”, which was published by Elsevier Science B. Published by V.

  Next, the present invention will be described from another viewpoint.

Hereinafter, processing of porous silicon (Ψ processing) for generating an ultrathin silicon layer that efficiently performs light trapping will be described. For this purpose, a silicon layer is grown epitaxially on the porous surface of the structured single crystal silicon substrate. Since the porous layer is broken by the mechanical stress, the epitaxial layer is separated from the substrate. According to X-ray diffraction analysis, the silicon layer with a thickness of Wf = 5.8 μm is a single crystal. If the layers are waffle-shaped, and these layers are fixed to glass, the maximum short-circuit current of jSC * is predicted to be 36.5 mA / cm ² by reflectance measurements and ray tracing simulation. For a film thickness of Wf = 2 to 3 μm, it is predicted that the efficiency η = 16 to 19% in the transport simulation.

1. Introduction Crystalline silicon thin-layer solar cell elements are known, for example, from the literature [1]. This document and the following documents are numbered in square brackets and are listed at the end of the list for summary purposes. There are essentially three requirements for crystalline silicon thin film solar cell elements.

  (I) Growth of high quality and large grain crystalline silicon layers on inexpensive substrates; (ii) Realization of a light trap method to correct intrinsically weak and nearly infrared absorption in crystalline silicon; (iii) Effective film protection on grain boundaries and surfaces.

  A structured single crystal silicon layer on float glass can meet the following three requirements: (I) Single crystal material has high capacity quality, and float glass is an inexpensive substrate. (Ii) Light traps can be efficiently performed by innovative layer structures [2-4] such as pyramid-type layer structures [4]. (Iii) The single crystal structure can prevent recombination of grain boundaries and enables effective surface coating protection at low temperature [5]. The production of such a thin structured single crystal silicon layer has not been described so far in the literature.

  In the following, a novel treatment of porous silicon for producing a structured single crystal thin layer on float glass will be described. In this respect, the light trapping effect of such a layer is investigated experimentally. Theoretically analyze the potential of the new layer structure that can be considered.

2. Porous silicon treatment The epitaxy of porous silicon was investigated in detail in the production of this single crystal silicon layer on an insulating substrate [6]. In this process, the epitaxial layer is grown on a flat single crystal silicon wafer having a porous surface by a CVD process at a temperature T> 1000 ° C. The epitaxial layer is then crimped onto the insulator by wafer bonding. Then, the substrate wafer is removed by mechanical grinding. The process is completed by chemical etching of the remaining porous layer. Due to the lack of light trap characteristics, bonding processing, and substrate wafer consumption, this technology cannot be used for photovoltaic technology because of its cost.

  In contrast, the processes listed below can be used in photovoltaic technology because they facilitate light trapping, do not perform the bonding process, and do not consume the substrate wafer. 1A-F show processing steps for producing a structured single crystal silicon layer on glass.

a) The single crystal silicon substrate wafer receives the surface structure by any kind of etching or mechanical grinding. In this regard, the structure can be made more complex than the normal inverted pyramid with periodicity p in FIG. 1A.
b) The surface of the substrate is changed to a porous silicon layer (porous Si layer, PSL) having a thickness of WPS. The orientation of the silicon within the PSL conveys information regarding the orientation of the substrate.
c) Silicon grows epitaxially sequentially on the PSL. Since the surface mobility of silicon atoms on the inner surface of the PLS leads to a sintering process at a temperature [7] exceeding 850 ° C., the low temperature epitaxial technique is beneficial.
At this point, the outer surface of the epitaxial layer can be freely touched. Each treatment performed at a temperature below about 850 ° C. can form the emitter of the cell. In addition to epitaxial emitters, inversion layers and heterojunction emitters are possible. For surface coating protection and grid formation, for example, the innovative techniques described in [5, 8, 9] may be used.
d) The overlying substrate (eg glass) is fixed to the front surface with a transparent adhesive. The temperature stability of the overlying substrate and adhesive determines the maximum processing temperature for all subsequent processing steps.
e) Use low PSL mechanical strength compared to substrate silicon to separate the cells from the substrate. A plurality of different processing methods are possible. For example, heating to create large internal stresses, filling in expanding liquid or gas holes, pulling PSL with compressive or tensile stress, or sonication. In any case, PSL functions as a silicon perforation (Psi) and is therefore called (.
f) The back side of the cell can be touched for surface coating protection and reflector formation. Offset reflectors can also form point contacts that withstand low recombination of minority charge carriers.

  The rear and front free accessibility is an inherent advantage of the process φ over the process of depositing silicon directly on the insulating substrate.

  The formation of PSL consumes the thickness WPS / Cos (α) of the substrate wafer that is structured such that the crystal surface forms an angle α with the macroscopic cell surface. After removing all residual porous silicon, assuming WPS / p << 1, the substrate retains the underlying surface morphology (FIG. 1A). Otherwise, as shown in FIG. 1E, the end face and the tip are rounded with a radius of curvature WPS / p. Thus, the substrate can be reused multiple times at a sufficiently small ratio WPS / p until a new structuring of the substrate is required.

3. Experimental Investigation 3.1 Sample Preparation A p + type single crystal silicon wafer doped with boron to 10 ¹⁹ cm ⁻³ and oriented in (100) direction and having a 4 inch diameter is subjected to photo-etching and KOH. The anisotropic etching used gives an inverted pyramid structure with periodicity p = 13 μm. The anodic corrosion method with diluted HF produces a porous silicon layer with a thickness of WPS = 6 μm in about 2 minutes. Prior to epitaxy, the sample is heated to 850 ° C. for about 10 minutes to remove the naturally occurring oxide from the PSL surface. The Ga doped epitaxial silicon layer with WPS = 5,8 μm thickness is grown by ion assisted deposition technique (IAD) [10] at 700 ° C. The growth rate is 4 μm / h on a plane. Transparent poly (ethylene-phthalic hydrochloric acid) fixes the 2 × 2 cm ² size glass surface to the epitaxial layer. Sonication for about 2 minutes destabilizes the PSL layer and provides for mechanical removal of the epitaxial layer without chemical etching. It is also possible to separate the epitaxial layer and the substrate from each other without performing ultrasonic treatment.

3.2 Characterization of the Samples FIGS. 2 and 4 show a free-standing silicon waffle structure produced by the φ process recorded with a scanning electron microscope. Aside from sonication, no cleaning is performed prior to investigation using a scanning electron microscope. The perspective plan view of FIG. 2 shows a regular inverted pyramid that is a copy of the original surface structure of the substrate wafer. FIG. 4 shows an oblique cross section of the waffle structure. The tip of the pyramid faces downward. There are no cracks. The layer thickness perpendicular to the pyramid crystal plane is Wf = 5.8 μm. There are invisible depressions in FIGS. 2 and 4 on the upper surface side, and the depth and diameter of the depressions are each less than 0.1 μm, which represents a kind of minimal roughness. These cavities also occur in flat epitaxial layers grown on unstructured substrate silicon and therefore correspond to IAD technology.

Measuring the hole in the layer deposited on the unstructured single crystal substrate with high resistivity, the concentration of 2 × 10 ¹⁷ cm ⁻³ of the electrically active trace substance additive Ga and the hole of 186 cm ² / Vs You can see the mobility.

  FIG. 14 shows the CuKα X-ray diffraction spectrum of a silicon waffle on glass compared to the spectrum of a single crystal silicon substrate. Intensity is shown on a logarithmic scale. All peaks occur at the same angle. Therefore, the silicon waffle structure is a single crystal and has the same orientation as the substrate wafer. Only the large (400) peak is based on silicon. All other peaks are smaller by two or more steps and are produced by the X-ray apparatus. The background strength of the epitaxial layer is generated by the amorphous glass substrate. As a result, the IAD technique [10] enables epitaxial growth on the porous substrate.

  The lifetime of substrate minority charge carriers is a critical material parameter of any solar cell element. In order to evaluate the lifetime of the substrate, the surface must be sufficiently protected. Thus, the free stationary silicon waffle is oxidized on both sides at a temperature of 1000 ° C. To repel minority charge carriers from the surface recombination centers, the surface is charged by a corona discharge chamber [11].

FIG. 15 shows the arrangement of the microwave reflectivity after excitation with a 20 ns light pulse. To obtain optimum sensitivity [12], the sample is placed above the metal reflector by a quarter microwave wavelength. Strict decline is not strictly a single index. However, the lifetime is estimated at τ = 0.27 μs ± 0.08 μs. The slow decline for time t> 0.6 μs is caused by softening (release) of charge carriers at a flat level. Electron mobility was not measured. However, considering the measured hole mobility μ = 186 cm ² / Vs, the minority charge carrier diffusion length L> 11 μm is obtained as the lower limit of the electron mobility, and this is from the film thickness Wf = 5.8 μm. Is also big.

  For thin film cells, light traps are important. Unfortunately, the ideal action of an adhesively bonded waffle structure with an aluminum mirror behind the sample as shown in the schematic diagram of FIG. 1F cannot be measured without contacting the sample. Therefore, the short current potential of the sample was estimated from a comparison with the measured hemispheric reflectivity and a ray tracing simulation with the program SUNRAYS [13]. It has been found that the offset reflector substantially reduces optical loss at A1.

FIG. 16 shows the measured hemispherical reflectance (continuous line) and calculated (circle). The ray tracing simulation can almost reproduce the measured value without adapting the optical parameters. The small deviation between the measured value and the simulation is qualitatively explained by the microroughness of the pyramidal crystal plane that was not considered in the simulation [2]. SUNRAYS has a maximum short-circuit current jSC * = 36.5 mA / cm, from a pseudo absorption (triangle) of Wf = 5.8 μm thickness waffle with a structural period p = 13 μm of radiation having an AM1.5G spectrum of 1000 W / m ^{2. 2} Calculate ± 0.5 mA / cm ² . As a result of the Monte Carlo simulation statistics, an error band occurs.

4). Possible efficiency The possible efficiency of the crystalline silicon layer having the shape shown in FIGS. 2 and 4 is investigated by theoretical modeling. In the optical model, ray tracing by vapor SUNRAYS is performed. The rate of generation of fractional charge carriers is made spatially uniform in the silicon layer and is calculated from jSC * and the cell volume. In addition to the optical model, an electron transfer model is also required. The complex three-dimensional charge carrier diffusion in a silicon waffle is approximated by pure one-dimensional transmission perpendicular to the pyramidal crystal plane. The efficiency of the cell depends on the fractional charge carrier diffusion length L and (mirror recombination rate SRV) S. It is very important to optimize the cell thickness Wf in order to correctly estimate the possible efficiency of the fixed L and S [14]. Therefore, the film thickness W with an ideal cell efficiency varies depending on the simulation. The silicon cell has an emitter that is p-doped to 10 ¹⁹ cm ⁻³ and 0.5 μm thickness and has a base that is B-doped to 10 ¹⁸ cm ⁻³ . For W <1 μm thickness, the base and emitter thickness are the same. In order to reduce the number of free parameters, the diffusion length L and the surface recombination rate S are considered equivalent for the base and emitter. Recombination in the space charge zone is described in [15]. The mobility values and parameters for band gap reduction of c-silicon are taken from document [14].

  FIG. 17 represents the efficiency (continuous line) of the optimum cell thickness (dashed line) for a wide range of parameters S and L. When the diffusion length L = 11 μm, the energy conversion efficiency of 16 to 19% is obtained based on the surface recombination speed S of an ideal seven-thickness of 2 to 3 μm (point). For a 2 μm thick crystalline silicon solar cell element on glass, an efficiency of 16% corresponding to SRVS = 104 cm / s is sufficient. The deposition of a thin layer of Wf = 2 μm takes 50 minutes with the currently used IAD technology.

A new treatment (φ treatment) for perforated silicon has been described. When epitaxy is performed on a structured single crystal silicon substrate and the epitaxial layer is mechanically separated from the substrate, an ultrathin single crystal structured silicon layer is formed on any type of glass. The measured value of the reflection ability revealed an optical absorption corresponding to the maximum short-circuit current jSC * = 36.5 mA / cm ² . Theoretically, the quality of the material is sufficient for 16-19% efficiency with an ideal cell thickness in the range of Wf = 2-3 μm.

Another possible φ treatment is to reduce the material consumption by setting the thickness of the porous layer to WPS <1 μm to allow repeated reuse of the substrate wafer. An increase in deposition rate is possible as well. An ultra-thin layer with a size of 100 cm ² can be produced without problems.

  Also, a particularly preferred embodiment of the present invention will be described below, which relates to the manufacture of solar cell elements. The method described here is not limited to photocells, but should be understood as a general manufacturing process. The motivation of the present embodiment is that electric power can be obtained from the solar cell element model with high voltage and small current by connecting the solar cell elements in series. Small current reduces ohm loss. The front and rear tentacles of the solar cell element are also designed to reduce ohmic loss. Therefore, the contact mark can be erased by appropriate series connection of the bases.

  Such series connection is realized by using a shadow mask. Here, the series connection of the solar cell elements has already taken place during the production of the layers, that is to say when the layers are selectively grown (only at predetermined positions). The position of the layer growth is controlled by a shadow mask. The shadow mask is preferably realized with a wire in a pulled state.

  An example of series connection using φ processing will be described below with reference to FIG. One possible method of layer deposition of porous materials is ion-assisted deposition technology (IAD). In IAD technology, transmission of silicon atoms is very directional, as is vapor deposition technology. The present invention takes advantage of this to achieve an integrated series connection while manufacturing layers using a shadow mask.

  FIG. 21 is a schematic diagram showing a simple process sequence. The embossed porous substrate 18 manufactured as described above, that is, the structured substrate, will be described without an embossing structure for convenience. When the shadow mask 301 is installed at the position 1, each region 300 of the p + Si layer that is separated from each other by the groove 302 is grown. Thereafter, the same mask moves in the horizontal direction by a predetermined distance, and each region of the pSi layer 304 grows. In the third position, each region of the n + Si layer 306 is finally generated, and the series circuit is completed by overlapping the exposed regions of the first p + si layer. The groove of each layer 300, 304, 306, for example, the surface area of each layer in a direction transverse to the groove 302, can be defined by another shadow mask that need not be moved but can be optionally moved.

The advantages of this type of series connection are as follows.
・ No need to use metal contacts. It is not necessary to etch the groove. These can save processing costs.
-Only one mask is required, and the accuracy of its shape is not important.
-It is not necessary to use a wire grid.
• If the wire is fixed outside the heating area of the reactor, the wire spacing does not change during heating. This avoids unknown problems associated with large mask thermal expansion.
• Shadow masks are covered during deposition and become unusable over time.
The wire mask can be easily regenerated by winding the reactor wire again on the reel.

For example, the following very different modifications are possible.
1. The order of dope can be changed. For example, n + is at the bottom and p + is at the top.
2. For example, a metal layer or a semi-transparent metal oxide or layer system of conductive and non-conductive layers is provided on the emitter to increase the mutual conductivity of the emitter. All these layers can be provided by a shadow mask.
3. Wire diameter and wire spacing can be varied from layer to layer.
4). The relative position of the wire mask and the sample or substrate can be changed continuously during layer deposition.
5). The shadow mask is made of metal pieces as well as wires.
6). A semiconductor layer having a desired outer shape can be generated by using the principle of the shadow mask. For example, when a mask having a circular opening is held in front of the porous Si layer, a circular single crystal semiconductor layer that can be used as a solar cell element of a wristwatch is generated. Thereafter, it is not necessary to cut the semiconductor layer into a desired shape.

  As explained from the introduction to the specification, in the mass production of electronic components using a porous layer, it is difficult to achieve a clean mechanical separation as in a laboratory. This is because porous silicon has two functions. One function allows epitaxial, i.e., non-porous, growth with sufficient orientation. When the porosity is lowered, this first function is sufficiently exhibited. On the other hand, silicon functions as a crushing position for the purpose of mechanical separation. When the porosity is increased, this second function is sufficiently exhibited. Therefore, a high quality, simultaneously peelable epitaxial layer must balance high and low porosity. Experiments have shown that this balance adjustment is often difficult to achieve. Therefore, undesirable and uncontrolled epitaxial layer separation was frequently observed in subsequent epitaxial processes. The methodology of EP-A-0 767 486 attempts to solve this problem by implanting ions into the porous layer at a specific level or while changing the current concentration during anodization of the porous layer production. In either case, a highly porous porous layer region is generated, where mechanical separation is preferably performed. However, these method variants are relatively complex and inconvenient.

  Ion implantation is another stage of processing. If the porosity is increased in both variants of the invention, the substrate may be crushed or separated during subsequent epitaxial processing, for example, when this is not desirable.

  Variations of the method of the present invention described below in connection with FIGS. 22A through 23E play an auxiliary role.

  1) Make the reusable silicon substrate wafer generally or near surface porous. When an n-type wafer is used, another illuminance is required when obtaining porosity by the anodic corrosion method. In the following, it is assumed that the substrate wafer is completely porous. To provide high mechanical stability to the substrate wafer, the porosity is reduced (greater than 0% but less than 50%, preferably 10-20%).

  2) Although the mechanically stable low porosity substrate wafer 18 of FIG. 22A is illustrated with a flat surface for convenience, the structured surface shown in FIG. 1, for example, is preferred. Epitaxy is performed on the embossed or flat surface of the substrate wafer 18 (for example, the n-type Si layer 400 is formed thereon in FIG. 22B). The porous substrate provides mechanical stability to the thin epitaxial layer, thereby enabling solar cell element processing without causing undesired separation. The solar cell element can also deposit a p-type epitaxial layer 402 on an n-type epitaxial layer 400 as shown in FIG. 22C, for example.

  3) The solar cell element is preferably adhesively bonded to a transparent carrier 404 as shown in FIG. 23D. The porous substrate and the epitaxial layer or solar cell element firmly bonded together are then bonded to carriers. Due to the low porosity, mechanical separation from the porous substrate and the epitaxial layer is not possible.

  4) Immerse the entire structure once more in an etching solution containing HF in order to separate the porous substrate from the epitaxial layers and carriers. The solution penetrates the porous substrate without being corroded. This allows the holes to pass through the transparent carrier by illumination means or by applying an appropriate magnitude of voltage from between the electrolyte and the epitaxial layer to the interface between the porous substrate and the epitaxial layer. If the hole concentration is large enough, the boundary region is mechanically unstable by generating further perforations according to claim 1 and subsequently the epitaxial layer together with the carriers is separated from the substrate by mechanical loading, or Since silicon is completely dissolved (electropolishing) by a particularly high hole concentration, the epitaxial layers 400, 402 and carriers are separated from the porous substrate 18 (FIG. 23E). A carrier 404 comprising two epitaxial layers, preferably having the structure according to FIG. 8 or FIG. 18 or FIG. 20 or FIG. 21, is incorporated into the solar cell element through the reactor, or is subjected to another process for producing other components. It is possible.

Concentration of holes by recombination at porous substrate depths of 0.1-10 μm due to high doping of porous substrate wafers, for example in the range of 10 ¹⁸ -10 ¹⁹ cm ^-3 doping concentration and large surface recombination in porous Si As the degree decreases, the bulk of the porous substrate is preserved and can be reused. When using a p-type epitaxial layer on a p-type porous substrate, the separation technique described here provides for the porosity of the porous material at which the current concentration selected during the anodic corrosion process is newly generated at the interface. It uses known research results that affect sex. Selecting a porosity close to 100% separates the epitaxial layer and leaves most of the porous substrate for reuse.

Literature list (1) H Werner, R. Bergman and R.C. Brendel, "Solid Problem No Solid State (Solid) Physics Advancement," Volume 34. R. Issue 15 by Herbig (1994, Braunschweig city).
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(8) R.M. Heel, 24th Electrical and Electronic Engineers Association, Photovoltaic Experts Meeting, Minutes, New York City, Electrical and Electronic Engineers Association, 1995, 1466.
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DESCRIPTION OF SYMBOLS 10 Substrate 12 Structure 14 Pyramid depression 16 Lattice 18 Porous substrate, porous layer 18A Porous layer 19 Interface 22 Epitaxial silicon layer 22 Layered structure 22D Pyramid tip 24 Lattice electrode 25 Lattice electrode 26 Glass layer 28 Layered structure 30 Aluminum sheet 30 Metal plate 32 Pyramid tip 50 Grooved cross section 52 Vertical groove 54 Web 54A Web 54A Section 54B Web residue 56 Adhesive layer 58 Carrier 58 Second substrate 60 Cylindrical rod 62 Grid electrode 72 Chamber 74 Piezoelectric element 76 Amorphous Material layer 78 surface 80 spring 300 region 301 shadow mask 302 groove 304 layer 306 n + Si layer 400 n-type epitaxial layer 402 p-type epitaxial layer 404 carrier

Claims (28)

In a layered structure manufacturing method for manufacturing a layered structure (28) made of a semiconductor material,
A porous layer (18) is formed on the semiconductor substrate (10);
A layered structure (28) is provided on the porous layer,
The layered structure is separated from the semiconductor substrate using the porous layer as a target separation position,
The surface of the semiconductor substrate is structured before the formation of the porous layer, or the surface of the porous layer is structured,
The layered structure is provided at least partially on the porous surface by epitaxial growth, and at least one semiconductor layer belonging to the layered structure is provided on the surface of the porous layer by epitaxial growth;
A layered structure manufacturing method characterized by the above. The surface of the semiconductor substrate is
2) Structured by one or more of the following: a) light etching b) etching c) chemical method d) mechanical milling e) laser processing The layered structure manufacturing method. The surface of the porous layer is
a) Light etching b) Etching c) Chemical methods d) Mechanical milling e) Laser processing f) Structured by one or more of the mechanical coining methods The method for producing a layered structure according to claim 1.   4. The layered structure according to claim 1, wherein the layered structure is formed at least partly by the deposition of a metal layer (30), the metal layer being applied to the adjacent material of the layered structure by heating and surface diffusion. The method for producing a layered structure according to any one of the above items.   The layered structure according to any one of claims 1 to 4, wherein the forming process of the layered structure includes a process of providing a dielectric in the formation of the transparent or light transmissive window layer (26). Body manufacturing method.   6. A carrier layer that is bonded to a layered structure by adhesive bonding, wafer bonding, or diffusion brazing, or provided as part of the layered structure is provided. The method for producing a layered structure according to item.   7. After separating the layered structure from the semiconductor substrate, another layered structure is provided on an optionally structured surface of the layered structure that forms the target crushing position. The method for producing a layered structure according to any one of the above items.   8. The layered structure according to claim 7, wherein the surface of the layered structure is cleaned and / or partially removed and / or newly structured or made porous before providing the another layered structure. Production method.   After separating the layered structure from the semiconductor substrate at the desired crushing position, the semiconductor substrate is used again as a semiconductor substrate for providing the layered structure with or without removing the porous layer residue. The method for producing a layered structure according to any one of claims 1 to 8, wherein:   When a semiconductor substrate having a structured porous layer, that is, a non-flat parallel plate-shaped porous layer is newly used, the semiconductor substrate used last is subjected to a cleaning process performed by etching or ultrasonic cleaning process. The layered structure manufacturing method according to claim 9, wherein the layered structure is manufactured.   Before or after separating the layered structure from the semiconductor substrate, another porous layer is formed on the surface of the layered structure separated from the semiconductor substrate, and another layered structure is formed thereon. The method for producing a layered structure according to any one of claims 1 to 10, wherein the layered structure is produced.   The method for producing a layered structure according to claim 11, wherein each of the other layered structures is grown on the surface of the layered structure formed so as to face the semiconductor substrate by epitaxial growth.   The layered structure manufacturing method according to any one of claims 1 to 12, wherein the semiconductor substrate is made of single crystal p-type Si or single crystal n-type Si.   14. The layered structure or a part thereof is separated from a semiconductor substrate during generation of mechanical stress in the porous layer or at the interface with the porous layer. 2. A method for producing a layered structure according to item 1. Generation of mechanical stress that acts in the porous layer and separates the layered structure or a part thereof from the semiconductor substrate,
a) Separation of a layered semiconductor substrate from a semiconductor substrate b) Ultrasonic treatment c) Generation of an ignition gradient d) Expansion or state change (liquid) of fluid (gas or liquid) or solvent filled in the pores of the porous layer Phase to gas phase, liquid phase to solid phase)
The method for producing a layered structure according to any one of claims 1 to 14, wherein the layered structure is produced by any one of the methods. In a layered structure manufacturing method for manufacturing a layered structure (28) made of a semiconductor material,
A porous layer (18) is formed on the semiconductor substrate (10);
A layered structure (28) is provided on the porous layer,
The layered structure is separated from the semiconductor substrate using the porous layer as a target separation position,
The surface of the semiconductor substrate is structured before the formation of the porous layer, or the surface of the porous layer is structured,
The layered structure is provided at least partially on the porous surface by epitaxial growth, and at least one semiconductor layer belonging to the layered structure is provided on the surface of the porous layer by epitaxial growth;
Before or after separating the layered structure from the semiconductor substrate, another porous layer is formed on the surface of the layered structure separated from the semiconductor substrate, and another layered structure is formed on the porous layer. Repeating the process multiple times, the structured layered structures separated from each other from the adjacent layered structures are generated by the porous layer forming the desired crushing position, overlapping each other, creating this multiple layered structure Then, the respective layered structures are separated from each other by generating mechanical strain in each porous layer or by anodizing treatment at the interface with each porous layer.
A layered structure manufacturing method characterized by the above.   The method for producing a layered structure according to claim 16, wherein after the separation of each layered structure, another layered structure is generated on one and / or the other free surface of each layered structure.   Before each layered structure is separated from the multiple layered structure, each layered structure has a carrier layer (404) or is fixed to the carrier layer (404). Item 17. The method for producing a layered structure according to Item 16. A semiconductor substrate (10) having a porous layer (18) on its surface,
A semiconductor substrate (10), characterized in that the free surface of the porous layer (18) is structured.   The semiconductor substrate according to claim 19, wherein the semiconductor substrate is made of a single crystal.   20. A semiconductor substrate according to claim 19, characterized in that it is combined with a layered structure (28) of semiconductor material which grows on the surface of the porous layer by epitaxial growth.   20. The semiconductor substrate of claim 19, wherein the semiconductor substrate is bonded to a second substrate attached to the structured surface of the porous layer.   The semiconductor substrate according to claim 22, wherein the bonding between the second substrate and the porous layer is realized by an adhesive, a bonding process, a diffusion brazing process, or an epitaxial process.   The layered structure is made of a single crystal semiconductor material, and the surface of the layered structure away from the semiconductor substrate has the same surface structure as the free surface of the porous layer of the semiconductor substrate. 22. The semiconductor substrate according to claim 21, characterized in that it is realized as a porous layer having another layered structure arranged on the structured layer in the same manner. . Use of a semiconductor substrate (10, 18) according to any one of claims 19 to 24, each comprising a plurality of layers (300, 304, 306) of different conductivity types and / or different conductivity types In an element circuit manufacturing method for manufacturing a series connection circuit of solar cell elements,
During deposition of each layer (300, 304, 306) on the porous layer of the semiconductor substrate, a shadow mask (301) is placed in front of the semiconductor substrate and intersects the direction of movement of the deposited atoms, An element circuit manufacturing method, which is used for selective growth control.   During the growth of the layers or between the growth of each layer (300, 304, 306), the shadow mask (301) and the semiconductor substrate (10) are arranged in parallel to each other, and the first conductivity type of the first position of the shadow mask. A trench (302) is created between the layer regions of the layer (300), and an end region of the layer (306) of the second conductivity type at another position of the shadow mask and the second region adjacent to the trench (302). An overlapping portion is formed between the exposed end region of the layer of one conductivity type (300), and thereby, between the two end regions, that is, between the two semiconductor elements formed by the layers on both sides of the trench. The device circuit manufacturing method according to claim 25, wherein the device circuits are connected in series.   27. The element circuit manufacturing method according to claim 25, wherein the shadow mask is formed of a wire having a desired cross-sectional shape. A series connection circuit of solar cell elements manufactured by the method according to any one of claims 25 to 27,
First and second regions of a first conductivity type layer (300) separated from each other by a trench (302);
A second conductivity type layer (306), which is deposited directly on top of the first conductivity type layer or separated from the first conductivity type layer by another layer; First and second regions of the layer (306) of
An end region of the first region of the second conductivity type (306) traversing over the trench (302) and directly overlapping the end region of the second region of the first conductivity type layer (300); ,
A series connection circuit of solar cell elements, comprising:

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