JP2010045312A - Semiconductor device, electronic component, and method of manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device that is increased in threshold voltage while suppressing a decrease in ON current, to provide an electronic component, and to provide a method of manufacturing the semiconductor device. <P>SOLUTION: The semiconductor device includes an HV transistor 10 formed on a semiconductor substrate 1, and the HV transistor 10 includes a gate electrode 19 formed on the semiconductor substrate 1 with an insulating film interposed, and a source 15 and a drain 13, the inside of the gate electrode 19 being depleted when a voltage is applied to the gate electrode 19 and a current flows between the source 15 and drain 13. With this configuration, the gate electrode 19 has capacity through the depletion and the capacity is connected to the capacity of a gate insulating film in series. Consequently, the capacity of the gate insulating film substantially decreases and then the threshold voltage of the HV transistor 10 is therefore raised. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor device, an electronic component, and a method for manufacturing a semiconductor device, and more particularly to a technique that makes it possible to increase a threshold voltage while suppressing a decrease in on-current.

As this type of prior art, for example, there is one disclosed in Patent Document 1, which includes a high breakdown voltage MOS transistor having a LOCOS (local oxidation of silicon) offset structure, and a low breakdown voltage MOS transistor. Manufacturing on the same semiconductor substrate is described. In the LOCOS offset structure, a large distance between the source and the drain can be secured. Thereby, the concentration of carriers at the drain end can be suppressed and the withstand voltage between the source and the drain can be increased, so that a high voltage can be applied between them.
JP 2007-255102 A

  By the way, a high breakdown voltage MOS transistor (hereinafter also referred to as HV transistor) having a high breakdown voltage between the source and drain and a low breakdown voltage MOS transistor (hereinafter also referred to as LV transistor) having a low breakdown voltage between the source and drain. .)), The operation speed of the LV transistor is desired to be improved, but the operation of the HV transistor is sometimes desired to be delayed in order to suppress a surge or the like. In such a case, a method of increasing the threshold voltage by doping a region which becomes a channel of the HV transistor with an impurity having a conductivity type opposite to that of the source and drain can be considered. This method is also called channel doping.

However, with this method, the on-current of the HV transistor is significantly reduced, and there is a possibility that desired performance cannot be obtained in a circuit combining the HV transistor and the LV transistor.
Therefore, the present invention has been made in view of such circumstances, and a semiconductor device capable of increasing a threshold voltage while suppressing a decrease in on-current, and an electronic component and a method for manufacturing the semiconductor device The purpose is to provide.

  [Invention 1] In order to achieve the above object, a semiconductor device of Invention 1 includes a first MOS transistor formed on a semiconductor substrate, and the first MOS transistor is formed on the semiconductor substrate via an insulating film. A first gate electrode; and a first source and a first drain formed on the semiconductor substrate. The first gate electrode includes a first voltage applied to the first gate electrode and the first gate electrode. When current flows between the first source and the first drain, depletion occurs. Here, the “first voltage” means the threshold voltage of the first MOS transistor. In addition, “current” that flows between the first source and the first drain when the first voltage is applied to the first gate electrode is also referred to as ON current.

  In such a configuration, a capacity is generated in the first gate electrode due to depletion of the interior of the first gate electrode, and this capacity is an insulating film sandwiched between the first gate electrode and the semiconductor substrate (that is, The gate insulating film) is connected in series. As a result, the capacitance of the gate insulating film is substantially reduced, so that the threshold voltage of the first MOS transistor can be increased. Compared with the case where the threshold voltage is adjusted using only channel dope, a decrease in on-current (ie, an increase in on-resistance) can be suppressed.

[Invention 2, 3] The semiconductor device of Invention 2 further includes a second MOS transistor formed on the semiconductor substrate in the semiconductor device of Invention 1, and the second MOS transistor is interposed on the semiconductor substrate via an insulating film. A second gate electrode formed on the semiconductor substrate, and a second source and a second drain formed on the semiconductor substrate, and a second voltage is applied to the second gate electrode inside the second gate electrode. It is not depleted when a current flows between the second source and the second drain when applied.
A semiconductor device according to a third aspect of the invention is the semiconductor device according to the second aspect, wherein the first voltage and the second voltage have the same voltage value.
According to the second and third aspects of the semiconductor device, a desired circuit (that is, an IC) can be configured by combining the first MOS transistor having a high threshold voltage and the second MOS transistor having a low threshold voltage.

[Invention 4] The semiconductor device according to Invention 4 is the semiconductor device according to any one of Inventions 1 to 3, wherein the first MOS transistor has a LOCOS offset structure.
With such a configuration, the electric field effect of the gate potential can be relaxed and the carrier concentration can be suppressed at the first drain end, so that the breakdown voltage between the first source and the first drain can be reduced. Can be increased.

[Invention 5] An electronic component of Invention 5 includes the semiconductor device according to any one of Inventions 1 to 4, and a heating resistor, wherein the heating resistor is the first source or the first of the semiconductor device. 1 drain is connected in series.
With such a configuration, the first MOS transistor has a high threshold voltage, and the operation (ie, response) from when the first voltage is applied to the first gate electrode until the on-current begins to flow is slow. As shown in FIG. 8B, the surge can be reduced. Thereby, the fluctuation of the voltage applied to the heating resistor can be reduced, and the temperature controllability of the heating resistor can be improved.
Also, since the on-resistance of the first MOS transistor connected in series with the heating resistor is small, a high voltage can be applied to the heating resistor. That is, it is possible to perform resistance division so that the heating resistor can efficiently generate heat. Such an electronic component is extremely suitable when applied to a thermal head such as a printer.

[Invention 6] A method of manufacturing a semiconductor device according to Invention 6 includes a step of forming a first gate electrode on an insulating film through a first gate electrode when forming a first MOS transistor on a semiconductor substrate. Forming a first source and a first drain on the semiconductor substrate below both sides of the semiconductor substrate, wherein in the step of forming the first gate electrode, a first voltage is applied to the first gate electrode, The amount of impurities introduced into the first gate electrode is adjusted so that the inside of the first gate electrode is depleted when a current flows between the first source and the first drain. It is.
With such a method, a capacitance is generated inside the first gate electrode due to depletion, and this capacitance is the capacitance of the insulating film (that is, the gate insulating film) sandwiched between the first gate electrode and the semiconductor substrate. A semiconductor device connected in series can be provided. In such a semiconductor device, the capacitance of the gate insulating film is substantially reduced due to capacitive coupling, so that the threshold voltage of the first MOS transistor can be increased. Compared with the case where the threshold voltage is adjusted using only channel dope, a decrease in on-current (ie, an increase in on-resistance) can be suppressed.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. Note that, in each drawing described below, parts having the same configuration are denoted by the same reference numerals, and redundant description thereof is omitted.
(1) HV Transistor FIG. 1 is a cross-sectional view showing a configuration example of an HV transistor 10 according to an embodiment of the present invention. As shown in FIG. 1, the HV transistor 10 is an NMOS transistor having a LOCOS offset structure, and includes a semiconductor substrate 1, an N well layer 3, a P well layer 5, an offset layer 7, a stopper layer 9, A field oxide film 11, a source 15, a drain 13, an insulating film 17, a gate electrode 19, and spacers (that is, sidewalls) 21 are included.

  Among these, the semiconductor substrate 1 is a P-type silicon semiconductor substrate 1 (P-sub) made of, for example, single crystal silicon and containing a P-type impurity such as boron. The N well layer 3, the offset layer 7, the source 15 and the drain 13 are impurity diffusion layers containing N-type impurities such as phosphorus or arsenic. The source 15 and the drain 13 are respectively formed on the semiconductor substrate 1 below both sides of the gate electrode 19, the source 15 is formed near the surface of the P well layer 5, and the drain 13 is formed near the surface of the N well layer 3. Has been. Further, the source 15 has a so-called LDD structure, and includes a low concentration layer 15a containing an N-type impurity at a low concentration and a high concentration layer 15b containing an N-type impurity layer at a high concentration. The offset layer 7 is formed so as to straddle the N well layer 3 and the P well layer 5.

The field oxide film 11 is formed right above the offset layer 7 and right above the stopper layer 9. When the semiconductor substrate 1 is made of, for example, silicon, the field oxide film 11 is made of a silicon oxide film. Further, in this HV transistor 10, a gate insulating film is constituted by a part of the field oxide film 11 and the insulating film 17, and the gate electrode 19 is formed on the semiconductor substrate 1 through such a gate insulating film. ing.
By adopting such a structure in which a part of the field oxide film 11 is a gate insulating film (that is, a LOCOS offset structure), a large distance between the source 15 and the drain 13 can be secured. Carrier concentration at the end of the drain 13 can be suppressed. In addition, the breakdown voltage between the source 15 and the drain 13 can be increased, and a high voltage can be applied therebetween. The insulating film 17 is made of, for example, a silicon oxide (SiO ₂ ) film or a silicon oxynitride film (SiON). The gate electrode 19 is made of polysilicon (poly-Si) containing an N-type impurity such as phosphorus or arsenic.

In the HV transistor 10, when a threshold voltage is applied to the gate electrode 19, the inside of the gate electrode 19 is depleted. Such depletion is achieved by adjusting the impurity dose with respect to the gate electrode 19 to an extremely low level of about 10 ¹³ to 10 ¹² [cm ⁻² ] instead of the general 10 ¹⁵ [cm ⁻² ]. Has been. By this depletion, the HV transistor 10 can increase the threshold voltage while suppressing a decrease in on-current (that is, an increase in on-resistance). Hereinafter, this point will be described in detail based on the results of simulation and measurement performed by the present inventors.

(2) Results of Simulation and Measurement FIG. 2 is a diagram showing the result of simulating the state of depletion inside the gate electrode, and FIG. 2A shows the impurity dose amount (G-dose) with respect to the gate electrode. FIG. 2B shows a cross section of an NMOS transistor with 4 * 10 ⁻¹⁵ [cm ⁻² ], and FIG. 2B shows a cross section of the NMOS transistor with a dose (G-dose) of 4 * 10 ⁻¹³ [cm ⁻² ]. FIG. 2C shows a cross section of an NMOS transistor having a dose amount (G-dose) of 4 * 10 ⁻¹² [cm ⁻² ].

2A to 2C, the voltage (Vg) applied to the gate electrode is set to 5 [V], the voltage (Vd) applied to the drain is set to 0 [V], and the source is applied. The voltage (Vs) to be applied is set to 0 [V], and the voltage (Vsub) applied to the semiconductor substrate is set to 0 [V]. At this time, in the transistor in FIG. 2A, depletion does not occur inside the gate electrode, but in each of the transistors in FIGS. 2B and 2C, depletion occurs in the gate electrode. Further, comparing FIG. 2B and FIG. 2C, the transistor of FIG. 2C has a larger depletion layer.
From these simulation results, “there is a correlation between the dose of impurities to the gate electrode and the extent of the depletion layer inside the gate electrode, and the smaller the dose, the greater the extent of the depletion layer” I understand that. Further, when the dose is about 10 ¹⁵ [cm ⁻² ], no depletion layer is formed inside the gate electrode, but when the dose is about 10 ¹³ to 10 ¹² [cm ⁻² ], the depletion layer is formed inside the gate electrode. "Is formed."

FIG. 3 is a diagram showing the result of simulating the relationship between the Id-Vg characteristics of the NMOS transistor and the impurity dose with respect to the gate electrode. A curve a in FIG. 3 shows the Id-Vg characteristic when the impurity dose with respect to the gate electrode is set to 4 * 10 ⁻¹⁵ [cm ⁻² ], and a curve b shows the dose amount 4 * 10 ⁻¹³ [ The Id-Vg characteristic when set to cm ^-2 ] is shown, and the curve c shows the Id-Vg characteristic when the dose is set to 4 * 10 ^-12 [cm ^-2 ]. Note that Id is a current flowing between a source and a drain (that is, a drain current).
Here, the simulation conditions are set to Vd = 0.1 [V], Vs = 0 [V], Vsub = 0 [V], and Vg is in the range of 0.0 to 2.5 [V]. Set to move. As shown in FIG. 3, in the curve a, the rise of Id from 0 (zero) is seen when Vg = 0.4 to 0.5 [V]. On the other hand, rising of the Id from 0 (zero) is seen in the curves b and c when vg = 1.2 to 1.4 [V]. From such a simulation result, it can be said that “the threshold voltage (Vth) can be shifted in the direction of increasing by reducing the dose of impurities to the gate electrode and depleting the inside of the gate electrode”. Recognize.

FIG. 4 is a diagram showing a result of simulating the relationship between the Id-Vd characteristics of the NMOS transistor and the impurity dose with respect to the gate electrode. A curve a in FIG. 4 shows Id-Vd characteristics when the impurity dose to the gate electrode is set to 4 * 10 ⁻¹⁵ [cm ⁻² ], and a curve b shows the dose to 4 * 10 ⁻¹³ [ The Id-Vd characteristic when set to cm ^-2 ] is shown, and the curve c shows the Id-Vd characteristic when the dose is set to 4 * 10 ^-12 [cm ^-2 ]. Here, the simulation conditions are set to Vg = 5.0 [V], Vs = 0 [V], Vsub = 0 [V], and Vd is in the range of 0.0 to 2.0 [V]. Set to move.
As shown in FIG. 4, the curves a to c increase upward with a similar inclination with Id = 0 (zero) and Vd = 0 (zero) as the origin. In addition, a region surrounded by a broken line in FIG. 4 (that is, about vd = 1.0 [V], about Vg = 5.0 [V]) is a general operation region in which the NMOS transistor is turned on. The Id in this region has a small difference between the curve a and the curves b and c, and the Id of the curves b and c is about 10% lower than the Id of the curve a. From these simulation results, it can be seen that “the depletion of the gate electrode hardly reduces the on-current (ie, the on-resistance hardly increases)”.

FIG. 5 is a diagram showing Id-Vth characteristics when channel doping is used for an NMOS transistor. In FIG. 5, the channel voltage is used to adjust the threshold voltage of the NMOS transistor to a different value, and Vd = 1.0 [V] and Vg = 5.0 [V] in each transistor in which Vth is adjusted. It is the figure obtained by setting and actually measuring the Id-Vth characteristic under this setting. A plurality of plots in FIG. 5 are measured values.
As shown in FIG. 5, in a transistor in which Vth is adjusted by channel doping, when Vth is in the range of 0.25 to 0.55 [V], Id is about 2.3 * 10 ^{−3 to} 1.8. * Decreased to the right in the range of 10 ^-3 [mA]. Further, from a straight line obtained by connecting a plurality of plots, Id when Vth = 1.2 V is calculated as about 0.9 * 10 ⁻³ [mA]. From these results, it can be seen that “on-current is significantly reduced (that is, on-resistance is remarkably increased when the threshold voltage is shifted in the direction of increasing using channel dope”). For example, when Vth is increased from about 0.55V to about 1.2V using channel doping, the decrease in on-current is calculated to be about 50%.

Thus, from the simulation and measurement results shown in FIG. 2 to FIG. 5, in order to increase the threshold voltage of the transistor while suppressing the decrease in on-current (that is, increase in on-resistance), It is clear that it is effective to deplete the inside. “This depletion causes the impurity dose to the gate electrode to be reduced from the usual 1/100 (= 10 ¹³ [cm ⁻² ] / 10 ¹⁵ [cm ⁻² ]) to 1/1000 (= 10 ^{12 [cm -2] / 10 15} [cm -2]) can be achieved by setting the "that can be seen.
That is, in a general operation region (for example, Vd = 1.0 [V], Vg = 5.0 [V]), when the threshold voltage is adjusted using only channel dope, the ON current is reduced. Is remarkable. For example, as shown in FIG. 5, when only Vth is used to shift Vth from 0.55V to 1.2V, the decrease in on-current is about 50%. On the other hand, when the threshold voltage is adjusted by depleting the inside of the gate electrode, as shown in FIG. 4, the on-current can be reduced by about 10%.

(3) Mixed mounting of HV transistor and LV transistor Next, a configuration example of a semiconductor device in which the HV transistor 10 and the LV transistor are mounted together and a manufacturing method thereof will be described.
FIG. 6 is a cross-sectional view showing a configuration example of the semiconductor device 100 according to the embodiment of the present invention. As shown in FIG. 6, the semiconductor device 100 includes an HV-Nch (channel) region, an LV-Nch region, and an LV-Pch region in the semiconductor substrate 1. Here, the above-described HV transistor 10 is formed in the HV-Nch region. In the LV-Nch region, an NMOS transistor 20 having a low low breakdown voltage between the source and the drain is formed. Further, a low breakdown voltage PMOS transistor 30 having a low breakdown voltage between the source and the drain is formed in the LV-Pch region. Hereinafter, for convenience of explanation, the low breakdown voltage NMOS transistor is referred to as an LV-Nch transistor 20, and the low breakdown voltage PMOS transistor is referred to as an LV-Pch transistor 30. The HV transistor 10 is referred to as an HV-Nch transistor 10.

  As shown in FIG. 6, the LV-Nch transistor 20 includes a P well layer 5, a field oxide film 11, a P-type stopper layer 9, a source 23, a drain 25, and an insulating layer formed on the semiconductor substrate 1. The film 17, the gate electrode 27, and the spacer 21 are included. Among these, the source 23 and the drain 25 are impurity diffusion layers containing an N-type impurity such as phosphorus or arsenic. The source 23 and the drain 25 are formed near the surface of the P well layer 5 under both sides of the gate electrode 27, and each of them has a so-called LDD structure. That is, the source 23 includes a low concentration layer 23a containing an N-type impurity at a low concentration and a high concentration layer 23b containing an N-type impurity layer at a high concentration. The drain 25 includes a low concentration layer 25a containing an N-type impurity at a low concentration and a high concentration layer 25b containing an N-type impurity layer at a high concentration. Further, the gate electrode 27 is formed on the P well layer 5 with the insulating film 17 interposed therebetween. The gate electrode 27 is made of poly-Si containing an N-type impurity such as phosphorus or arsenic. The LV-Nch transistor 20 is separated from other elements by the field oxide film 11 and the P-type stopper layer 9.

  On the other hand, the LV-Pch transistor 30 includes an N well layer 3 formed on the semiconductor substrate 1, a field oxide film 11, a source 31, a drain 33, an insulating film 17, and a gate electrode 35. Has been. Among these, the source 31 and the drain 33 are impurity diffusion layers containing a P-type impurity such as boron, and are formed near the surface of the N well layer 3 under both sides of the gate electrode 35. The gate electrode 35 is formed on the N well layer 3 via the insulating film 17. The gate electrode 35 is made of poly-Si containing a P-type impurity such as boron. The LV-Pch transistor 30 is separated from other elements by the field oxide film 11.

FIG. 7 is a diagram illustrating an example of the electronic component 200 according to the embodiment of the present invention.
As shown in FIG. 7, the electronic component 200 includes the semiconductor device 100 and the heating resistor R described above. In the electronic component 200, the semiconductor device 100 includes, for example, a LV-Nch transistor 20 and an LV-Pch transistor 30 to form a CMOS inverter 40, and the output of the CMOS inverter 40 is applied to the gate electrode 19 of the HV-Nch transistor 10. The circuit configuration is as follows. In this example, the semiconductor device 100 is externally attached to the heating resistor R, and the drain terminal DO of the HV-Nch transistor 10 is connected in series to one end of the heating resistor R. Further, in the electronic component 200, a high voltage (for example, 40 [V]) is always applied to the terminal VH, and a low voltage (for example, 3.5 to 5.5 [V]) is always applied to the terminal VL. Is set to The terminal STR is set so that a signal of H (High: for example, 3.5 to 5.5 [V]) and a signal of L (Low: for example, 0 [V]) are selected and input. ing.

In such an electronic component 200, an inverted signal of the signal input to the terminal STR is output from the CMOS inverter 40. When the signal output from the CMOS inverter 40 is H (that is, when the input signal to the CMOS inverter is L), the HV-Nch transistor 10 is turned on. From this moment, current begins to flow between the heating resistor R and the source and drain of the HV-Nch transistor 10, and the voltage at the terminal VH (for example, 40 [V]) is turned on to the heating resistor R and the HV-Nch transistor 10. Divided by resistance. That is, the divided voltages are applied to the heating resistor R and the drain terminal DO of the HV-Nch transistor 10, respectively.
Here, when the response of the HV-Nch transistor is fast, surge (that is, fluctuation of the waveform of the voltage Vd) increases as shown in FIG.

However, in the electronic component 200 according to the embodiment of the present invention, when the signal H is applied to the gate electrode 19 of the HV-Nch transistor 10, the inside of the gate electrode 19 is depleted. Is also high. For this reason, the response of the HV-Nch transistor 10 is slower than that of the CMOS inverter 40, and the surge can be reduced as shown in FIG. 8B. Therefore, also in the heating resistor R, the fluctuation of the voltage waveform can be reduced, and the fluctuation of the heating temperature can be reduced. Thereby, the temperature controllability of the heating resistor R can be improved.
Further, since the on-resistance of the HV-Nch transistor 10 is small, a high voltage can be applied by the heating resistor R. That is, resistance division can be performed so that the heating resistor R generates heat efficiently. Such an electronic component 200 is extremely suitable when applied to a thermal head such as a printer.

Next, a method for manufacturing the semiconductor device 100 shown in FIG. 6 will be described.
FIG. 9A to FIG. 10C are cross-sectional views illustrating a method for manufacturing the semiconductor device 100 according to the embodiment of the present invention.
In FIG. 9A, first, an N well layer 3 and a P well layer 5 are formed on a semiconductor substrate 1, respectively. Here, the N well layer 3 partially introduces an N-type impurity such as phosphorus into the semiconductor substrate 1 by, for example, photolithography and ion implantation technology, and then thermally diffuses the introduced impurity into the semiconductor substrate 1. To form. Further, the P well layer 5 partially introduces a P-type impurity such as boron into the semiconductor substrate 1 by, for example, photolithography and ion implantation technology, and then thermally diffuses the introduced impurity into the semiconductor substrate 1. To form.

  Next, an N-type offset layer 7 and a P-type stopper layer 9 are respectively formed on the semiconductor substrate 1. Here, the N-type offset layer 7 is formed by, for example, partially introducing N-type impurities such as phosphorus into the semiconductor substrate 1 by photolithography and ion implantation techniques, and subsequently introducing the introduced impurities into the semiconductor substrate 1. It is formed by thermal diffusion. The P-type stopper layer 9 partially introduces a P-type impurity such as boron into the semiconductor substrate 1 by photolithography and ion implantation techniques, for example, and then introduces the introduced impurity into the semiconductor substrate 1 by heat. It is formed by diffusing. The thermal diffusion process for forming the offset layer 7 and the P-type stopper layer 9 may be performed in combination with a process for forming a field oxide film 11 which will be described later, or may be performed with another process for thermal diffusion which will be described later. You can go there.

Next, as shown in FIG. 9B, a field oxide film 11 is formed on the semiconductor substrate 1 by, eg, LOCOS. After the field oxide film 11 is formed, although not shown, an oxidation resistant mask made of a silicon nitride (Si ₃ N ₄ ) film or the like is removed from the semiconductor substrate 1. Then, an insulating film 17 is formed on the semiconductor substrate 1. The insulating film 17 is formed, for example, by thermally oxidizing the semiconductor substrate 1. Next, for example, a poly-Si film is formed on the entire upper surface of the semiconductor substrate 1 on which the insulating film 17 is formed. The formation of the poly-Si film is performed by, for example, CVD (chemical vapor deposition). Then, this poly-Si film is patterned to form gate electrodes 19, 27, and 35. This patterning is performed by photolithography and etching techniques.

  Next, as illustrated in FIG. 9C, a resist pattern 41 that covers the HV-Nch region and the LV-Nch region and exposes the LV-Pch region is formed on the semiconductor substrate 1. Then, using this resist pattern 41 as a mask, a P-type impurity such as boron is ion-implanted into the LV-Pch region. Next, the resist pattern 41 is removed, and then the P-type impurity is thermally diffused. Thereby, as shown in FIG. 10A, the P-type source 31 and drain 33 are formed in the N well layer 3 in the LV-Pch region, and the gate electrode 35 is made to have P-type conductivity. The thermal diffusion process for forming the source 31 and the drain 33 may be performed in combination with other thermal diffusion processes described later.

Next, as shown in FIG. 10A, a resist pattern 43 that covers the LV-Pch region and exposes the HV-Nch region and the LV-Nch region is formed on the semiconductor substrate 1. Then, N-type impurities such as phosphorus are ion-implanted into the HV-Nch region and the LV-Nch region using the resist pattern 43 as a mask. Here, the dose of the N-type impurity is set to about 10 ¹² to 10 ¹³ [cm ⁻² ]. Next, the resist pattern 43 is removed, and then the N-type impurity is thermally diffused. Thereby, N-type low concentration layers 13a and 15a are formed in the HV-Nch region, and N-type low concentration layers 23a and 25a are formed in the LV-Nch region. The gate electrodes 19 and 27 are made to have N-type conductivity. The thermal diffusion process for forming the low concentration layers 13a, 15a, 23a, 25a, etc. may be performed in combination with other thermal diffusion processes described later.

Next, as shown in FIG. 10B, spacers 21 are formed on the side surfaces of the gate electrodes 19, 27, and 35. The spacer 21 is formed by, for example, forming an insulating film (SiO ₂ film or Si ₃ N ₄ film or the like) on the entire surface of the semiconductor substrate 1 by CVD, and then etching back the insulating film. Next, a cap layer 37 is formed on the gate electrodes 19, 27 and 35. The cap layer 37 is formed by, for example, forming an insulating film (for example, SiO ₂ film or Si ₃ N ₄ film) on the entire surface of the semiconductor substrate 1 by CVD, and subsequently patterning the insulating film. .

Next, as shown in FIG. 10C, a resist pattern 45 is formed on the semiconductor substrate 1 so as to cover the LV-Pch region and expose the other region on the gate electrode 19 of the HV-Nch transistor 10. . Then, N-type impurities such as phosphorus or arsenic are ion-implanted using the resist pattern 45 as a mask. Here, the dose amount of the N-type impurity is set to about 10 ¹⁵ [cm ⁻² ], for example. Next, the resist pattern 45 is removed, and then the N-type impurity is thermally diffused. Thus, as shown in FIG. 6, the N-type high concentration layer 15b and the drain 13 are formed in the HV-Nch region, and the N-type high concentration layers 23b and 25b are formed in the LV-Nch region. Simultaneously with these formations, the N-type impurity concentration of the gate electrode 27 is further increased. In this N-type impurity introduction step, since the N-type impurity is not introduced into the gate electrode 19 in the HV-Nch region, the N-type impurity concentration of the gate electrode 19 is kept low, and the above-described depletion inside the gate electrode 19 is prevented. Achieved.

As described above, according to the embodiment of the present invention, in the HV-Nch transistor 10, the gate electrode 19 is depleted to generate a capacitance, and this capacitance is in series with the capacitance of the gate insulating film. Connected. As a result, the capacitance of the gate insulating film is substantially reduced, so that the threshold voltage of the HV-Nch transistor 10 can be increased. Compared with the case where the threshold voltage is adjusted using only channel dope, a decrease in on-current (ie, an increase in on-resistance) can be suppressed.
In this embodiment, the HV-Nch transistor 10 corresponds to the “first MOS transistor” of the present invention, and the gate electrode 19 corresponds to the “first gate electrode” of the present invention. The source 15 corresponds to the “first source” of the present invention, and the drain 13 corresponds to the “first drain” of the present invention. Further, the LV-Nch transistor 20 corresponds to the “second MOS transistor” of the present invention, and the gate electrode 27 corresponds to the “second gate electrode” of the present invention. The source 23 corresponds to the “second source” of the present invention, and the drain 25 corresponds to the “second drain” of the present invention. Furthermore, the voltage of 3.5 to 5.5 [V] corresponds to the “first voltage” and the “second voltage” of the present invention.

The figure which shows the structural example of the HV transistor 10 which concerns on embodiment of this invention. The figure which shows the result of having simulated the mode of the depletion inside a gate electrode. The figure which shows the result of having simulated the relationship between Id-Vg characteristic and a dose. The figure which shows the result of having simulated the relationship between Id-Vd characteristic and a dose. The figure which shows the Id-Vth characteristic at the time of using channel dope. 1 is a diagram illustrating a configuration example of a semiconductor device 100 according to an embodiment of the present invention. The figure which shows an example of the electronic component 200 which concerns on embodiment of this invention. The figure which compares the magnitude of the surge. The figure which shows the manufacturing method of the semiconductor device 100 which concerns on embodiment of this invention. The figure which shows the manufacturing method of the semiconductor device 100 which concerns on embodiment of this invention.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 Semiconductor substrate, 3 N well layer, 5 P well layer, 7 Offset layer, 9 Stopper layer, 10 HV-Nch transistor (HV-transistor), 11 Field oxide film, 15, 23, 31 Source, 13, 25, 33 Drain, 17 Insulating film, 19, 27, 35 Gate electrode, 20 LV-Nch transistor, 30 LV-Pch transistor, 37 Cap layer, 41, 43, 45 Resist pattern, 100 Semiconductor device, 200 Electronic component, DO drain terminal, R Heating resistor

Claims (6)

A first MOS transistor formed on a semiconductor substrate;
The first MOS transistor is
A first gate electrode formed on the semiconductor substrate via an insulating film;
A first source and a first drain formed on the semiconductor substrate;
The semiconductor is characterized in that the inside of the first gate electrode is depleted when a first voltage is applied to the first gate electrode and a current flows between the first source and the first drain. apparatus. A second MOS transistor formed on the semiconductor substrate;
The second MOS transistor is
A second gate electrode formed on the semiconductor substrate via an insulating film;
A second source and a second drain formed on the semiconductor substrate;
The inside of the second gate electrode is not depleted when a second voltage is applied to the second gate electrode and a current flows between the second source and the second drain. Item 14. The semiconductor device according to Item 1.   The semiconductor device according to claim 2, wherein the first voltage and the second voltage have the same voltage value.   4. The semiconductor device according to claim 1, wherein the first MOS transistor has a LOCOS offset structure. 5. A semiconductor device according to any one of claims 1 to 4,
A heating resistor, and
The electronic component, wherein the heating resistor is connected in series to the first source or the first drain of the semiconductor device. When forming the first MOS transistor on the semiconductor substrate,
Forming a first gate electrode on a semiconductor substrate via an insulating film;
Forming a first source and a first drain on the semiconductor substrate,
In the step of forming the first gate electrode,
The first gate is depleted when the first voltage is applied to the first gate electrode and a current flows between the first source and the first drain. A method for manufacturing a semiconductor device, comprising adjusting an amount of impurities introduced into an electrode.

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