JP2010045272A - Method of manufacturing laminated soi (silicon on insulator) wafer and laminated soi wafer obtained by this method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce the occurrence of void or blister after joint annealing, and to improve a yield of a laminated substrate. <P>SOLUTION: The method of manufacturing an SOI layer is improved so that a first silicon substrate forming the SOI layer is bonded to a supporting substrate, i.e., a second silicon substrate through an oxide film and then the first silicon substrate is thinned, wherein its laminate includes a structure that the SOI layer is formed on the supporting substrate through a BOX layer is improved. The characteristic constitution of this improvement exists in the decision wherein a faulty size and a faulty number which are permitted for the first silicon substrate and the second silicon substrate are set in accordance with the thicknesses of the BOX layer and the SOI layer in the SOI wafer scheduled for manufacturing to determine whether the first silicon substrate and the second silicon substrate are suitable based on the set value. <P>COPYRIGHT: (C)2010,JPO&amp;INPIT

Description

  The present invention relates to a method for producing a bonded SOI (Silicon On Insulater) wafer and a bonded SOI wafer obtained by the method.

  In the case of manufacturing a device using a silicon single crystal wafer, one of the causes of lowering the yield in the device manufacturing process is the presence of COP (Crystal Organized Particle). COP is a pit-like defect generated on the surface of a silicon wafer by heat treatment or etching.

  As a method of improving the yield reduction in the device manufacturing process caused by COP, for example, a defect-free silicon single crystal ingot having no COP or OSF (Oxidation-induced Stacking Fault) is grown, cut out from this ingot, and processed A method using a defect-free silicon wafer has been proposed (for example, see Patent Document 1). By using a defect-free silicon wafer as a device fabrication wafer, it is possible to suppress a decrease in yield due to COP and OSF.

  On the other hand, an SOI wafer is employed as one of the types of wafers used when manufacturing devices. The SOI wafer has a structure in which a single crystal silicon layer (hereinafter referred to as an SOI layer) serving as an active layer is formed through a buried oxide film (hereinafter referred to as BOX) layer using a silicon single crystal as a supporting substrate. Have As a method for manufacturing an SOI wafer, a bonding method and a SIMOX (Separation by Implanted Oxygen) method are known. In the bonding method, for example, techniques such as an ion implantation separation method or a hydrogen ion separation method (smart cut method) have been developed (see, for example, Patent Document 2).

  However, when manufacturing an SOI wafer by this bonding method, when two wafers are stacked and bonded, bubbles are included in the bonding interface, as shown in FIG. However, there was a problem that a bonding defect called void or blister occurred. The SOI wafer 1 is obtained by repelling the BOX layer 3 and the SOI layer 4 where the organic matter and particles contained in the bonding interface are vaporized by receiving a high-temperature bonding heat treatment, and the organic matter is contained by the generated vaporized gas. The dent generated on the surface of the wafer is a void 5, and the generated vaporized gas is confined as a bubble at the bonding interface (between the support substrate 2 and the BOX layer 3 in FIG. 7), and the swelling generated on the surface of the SOI wafer 1 Is the blister 6. Voids and blisters are also called killer defects in the device manufacturing process, and are one of the causes of reducing the yield of the device manufacturing process.

  As a cause of the generation of voids and blisters in the bonded SOI wafer, for example, in the ion implantation separation method, it has become clear that foreign substances such as organic substances adhering during the ion implantation process performed before the bonding are affected. Yes. As a measure to solve this cause, by removing the foreign substances and organic substances present on the main surface of the bonding, which is the bonding interface, using a technique such as cleaning and polishing, and performing the bonding so as not to pass the foreign substances, A technique for suppressing voids and blisters is known (for example, see Patent Document 3).

  However, it is difficult to obtain a bonded SOI wafer in which the generation of voids and blisters is completely suppressed even when a method for removing foreign matters by a technique such as cleaning or polishing as shown in Patent Document 3 is used. An SOI wafer with a very thin BOX layer (hereinafter referred to as a thin BOX-SOI wafer) or a directly bonded bonded wafer, such as a BOX layer with a bonded SOI wafer thickness of 5 nm or less, is manufactured. In some cases, voids and blisters are easily generated, and it is difficult to suppress the generation of voids and blisters.

  In thin BOX-SOI wafers and directly bonded wafers, one of the reasons why voids and blisters are likely to occur is that the void extinction effect using the viscosity of the oxide film due to the thinning of the BOX layer is reduced. It can be considered that the trapping effect of organic matter and foreign matter is reduced. By thinning or eliminating the BOX layer that alleviated these effects, the void disappearance effect is significantly reduced, the effects of organic substances and foreign substances are not only emphasized, but the effects of other disturbance factors are also manifested. Have been doing.

  As problems that have become apparent in thin BOX-SOI wafers and directly bonded wafers, the influence of COP, which has been a problem during device design, has become clear, other than the influence of organic substances and foreign substances. Even when the thickness of the BOX layer of the bonded SOI wafer is 100 nm or more, there is no influence of COP, but the influence of organic substances and foreign matters is more dominant as the cause of voids and blisters than the effect of COP. It was the target.

  As a method for reducing the COP existing on the wafer surface as the main bonding surface, for example, a single crystal ingot in which a single crystal is pulled at a high speed and a small size COP is present at a high density at a low oxygen concentration is produced. In addition, it has been proposed to use a wafer having a COP density significantly reduced by heat-treating the wafer obtained from the above in a reducing atmosphere as the active wafer of the SOI wafer (see, for example, Patent Document 4).

  On the other hand, by controlling the boron addition concentration, the OSF ring is completely contracted to produce a silicon single crystal ingot having no COP, and a defect-free crystal wafer cut and processed from the ingot is used as a support wafer. Thus, a method of manufacturing an SOI wafer by an ion implantation separation method in which a microvoid is not formed between a buried oxide film and a supporting wafer is disclosed (for example, refer to Patent Document 5).

However, a method of using a wafer in which COP has been extinguished before bonding as shown in Patent Document 4 as an active wafer of an SOI wafer, or a wafer having a COP controlled as shown in Patent Document 5 is a supporting wafer. However, the effect of suppressing voids and blisters is not enough, especially in bonded SOI wafers that require ultra-precise bonding, such as thin BOX-SOI wafers and direct bonded wafers. The yield of voids and blisters was not satisfactory.
Japanese Patent Application Laid-Open No. 11-1393 JP 05-211128 A (paragraphs [0033] to [0036], FIGS. 2 to 4) JP 2000-30992 A (paragraphs [0012] to [0019]) JP 2000-49063 A (Claims 1 to 3, paragraph [0026]) International Publication No. 2005/027217 (claims [1] to [2], paragraphs [0011] and [0041])

  The object of the present invention is to reduce the generation of voids and blisters after bonding heat treatment at the time of bonding, and to improve the yield of the bonded substrate, and to a bonded SOI wafer obtained by the method. Is to provide.

  According to the first aspect of the present invention, the first silicon substrate for forming the SOI layer and the second silicon substrate to be the support substrate are bonded together through an oxide film, and then the first silicon substrate is thinned. This is an improvement of a method for manufacturing a bonded SOI wafer having a structure in which an SOI layer is formed on a substrate via a BOX layer. The characteristic configuration is the thickness of each of the BOX layer and the SOI layer in the SOI wafer to be manufactured. Accordingly, the defect size and the number of defects allowed for the first silicon substrate and the second silicon substrate are set, and the suitability of the first silicon substrate and the second silicon substrate is determined based on the set values. It is in.

  The invention according to claim 2 is the invention according to claim 1, wherein in the SOI wafer manufactured by the ion implantation separation method, the thickness of the buried oxide layer immediately after the separation heat treatment is 2 to 5 nm, and the thickness of the SOI layer. Is 400 nm to 800 nm, the defect size Ds allowed for the first silicon substrate and the second silicon substrate is 90 nm, which is larger than the defect size Ds allowed for the first silicon substrate and the second silicon substrate. This is a method for manufacturing a bonded SOI wafer having 10 or fewer defects.

  The invention according to claim 3 is a bonded SOI wafer obtained by the manufacturing method according to claim 1 or 2.

  The manufacturing method of the bonded SOI wafer according to the present invention includes a thin BOX-SOI wafer and a directly bonded bonded wafer which are difficult to suppress the occurrence of voids and blisters which are currently bonded defects. For the production of bonded wafers, the defect size that tends to form voids and the number of defects larger than the defect size are set according to the SOI layer thickness and BOX layer thickness of the SOI wafer to be manufactured. By determining the suitability of the wafer used for bonding, there is an advantage that generation of voids and blisters after bonding heat treatment at the time of bonding can be reduced, and a high yield can be secured.

  By using the above method to bond wafers of SOI structure or silicon wafers with different characteristics, and bonding silicon wafers and heterogeneous crystal substrates, defects before bonding can be inevitably suppressed and used. There are few defects in a silicon single crystal wafer, and it is possible to sufficiently suppress bonding defects, voids and blisters that occur during bonding.

  Next, the best mode for carrying out the present invention will be described with reference to the drawings.

  As shown in FIG. 1J, the SOI wafer 11 includes a second silicon substrate 12 serving as a support substrate, and an SOI layer 13 bonded to the second silicon substrate 12 via an oxide film 21.

  A method for manufacturing such an SOI wafer 11 in the present invention will be described.

First, an oxide film (SiO ₂ film) 21 is formed on the first silicon substrate 14 on which the SOI layer is to be formed (FIG. 1A). When the oxide film 21 is formed by a thermal oxidation method, an insulating film is formed not only on the surface of the substrate 14 but also on the entire surface including the back surface and side surfaces (not shown). The oxide film 21 is formed to have a thickness of 2 to 5 nm when a thin BOX-SOI wafer is obtained. Here, the thickness of the oxide film 21 is set to 2 to 5 nm because the oxide film below the lower limit value is bonded to the first silicon substrate and the second silicon substrate without the natural oxide film, and is protected by the natural oxide film. If the exposed silicon surface is exposed to the process, particles are likely to adhere to the surface, and if the upper limit is exceeded, direct bonded wafers are oxidized by outward diffusion when manufactured using outward diffusion. This is because it is difficult to remove the film. Note that the oxide film may be formed only on the surface of the first silicon substrate 14 by CVD instead of thermal oxidation.

Next, hydrogen ions are implanted from the surface of the first silicon substrate 14 on which the oxide film is formed. Thereby, an ion implantation region 16 is formed inside the first silicon substrate 14 (FIG. 1B). This ion implantation region 16 becomes a release layer. Hydrogen ion implantation is preferably performed at a dose of 5 × 10 ¹⁶ atoms / cm ^{2 to} 1.2 × 10 ¹⁷ atoms / cm ² and an acceleration energy of 30 to 80 keV. Here, the dose of hydrogen ions is set within the above range because if the amount is less than the lower limit value, it cannot be cleaved by heat treatment. It is because it becomes easy to generate | occur | produce. The reason why the acceleration energy is within the above range is that the SOI layer 13 becomes too thin if the acceleration energy is less than the lower limit value, and a special ion implantation device is required if the acceleration energy exceeds the upper limit value.

At this time, foreign matters and organic substances generated during hydrogen ion implantation cause voids and blisters. Therefore, in order to remove these foreign substances and organic substances, the first silicon substrate 14 after ion implantation is subjected to RCA cleaning or It is preferable to perform single wafer cleaning using HF / O ₃ .

  On the other hand, a second silicon substrate 12 made of a silicon single crystal having the same surface area as the first silicon substrate 14 is prepared (FIG. 1C). Then, the first silicon substrate 14 is overlaid on the second silicon substrate 12 via the oxide film 21 to form a laminated body 15 (FIG. 1D). The stacked body 15 is formed by superimposing the first silicon substrate 14 on the second silicon substrate 12 and aligning the first silicon substrate 14 with the first silicon substrate 14 in the center of the second silicon substrate 12 superimposed on the first silicon substrate 14. This is performed by applying a load toward the silicon substrate 14.

  Thereafter, the laminate 15 is heat-treated in an oxygen atmosphere or a reducing atmosphere such as Ar at 300 to 700 ° C., preferably 400 to 500 ° C., for 5 to 30 minutes, preferably 5 to 15 minutes. As a result, the first silicon substrate 14 is broken at the ion implantation region 16 corresponding to the hydrogen ion implantation peak position, and is separated into an upper thick portion 17 and a lower thin SOI layer 13 (FIG. 1E). Then, the lower SOI layer 13 is in close contact with the second silicon substrate 12 through the oxide film 21 to become a bonded substrate 18 (FIG. 1F).

  Next, the bonded substrate 18 is flattened and thinned by a general method until the final film thickness is obtained. For example, after removing a region where damage has occurred during separation by CMP processing, oxidation treatment, or the like, heat treatment for improving the bonding strength is performed. The lamination may be performed while performing a plasma treatment using an inert gas plasma for increasing the bonding strength or a heat treatment for increasing the bonding strength. Further, planarization is performed by CMP processing and high-temperature heat treatment in an atmosphere such as hydrogen or argon gas (FIG. 1 (h)), and then thinning is performed by CMP processing or oxidation processing until a predetermined SOI layer 13 thickness is obtained. Then, an SOI wafer 11 is obtained (FIG. 1 (j)).

  As shown in FIG. 1 (g), the thick portion 17 separated by the peeling process is subjected to a process such as surface polishing (FIG. 1 (i)) and reused as a wafer for bonding. For other uses.

  The characteristic structure in the manufacturing method of the bonded SOI wafer of the present invention is allowed as the first silicon substrate and the second silicon substrate depending on the thicknesses of the BOX layer 21 and the SOI layer 13 in the SOI wafer to be manufactured. The defect size and the number of defects are set, and the suitability of the first silicon substrate and the second silicon substrate is determined based on the set values.

The present inventor has a relationship between the defect size existing on the wafer surface before bonding and the number of voids generated in the SOI wafer after bonding, and the thickness of the SOI layer in the SOI wafer to be manufactured. And the thickness of the BOX layer is the most dominant factor that determines the defect size at which voids are likely to occur. Further, the thickness of the BOX layer affects the void disappearance effect and the trap effect. Therefore, in order to judge the suitability of the first silicon substrate and the second silicon substrate used for the bonded SOI wafer, the SOI layer thickness T _SOI (nm) and the BOX layer thickness T _BOX (nm) The following equation (1) showing the relationship between the defect size and the allowable defect size Ds (nm) was derived.

Ds = α × (βT _SOI + T _BOX ) γ (1)
(However, in the formula, α = 60, β = 0.008, and γ = 0.24.)
The above formula (1) was derived based on the following knowledge.

The generation of voids is considered to strongly depend on the thickness of the SOI layer and the BOX layer due to the void structure. Against the force F _V intend to become void, thicker the total film thickness of the SOI layer and the BOX layer, the stronger the total rigidity of the SOI layer and the BOX layer is easily to hardly become void I can imagine.

Therefore, when it is assumed that the force F _V (D) at which a certain defect size D becomes a void and the total rigidity of the SOI layer and the BOX layer are equal, that is, a state where no void is formed,
F _V (D) ≦ α ′ × (βT _SOI + T _BOX ) (A)
It turns out that it becomes. Β is a physical property that relaxes differences in rigidity and thermal expansion coefficient between Si and SiO ₂ considering that the SOI layer and the BOX layer have different physical property values from Si and SiO ₂ , respectively. The constant α ′ is a constant that relates the rigidity of the SOI layer and the BOX layer to the force to become a void.

In the formula (A), when the force F _V (D) for a certain defect size D to become a void is proportional to the defect size D, the left side in the formula (A) is
F _V (D) = α ″ × D (B)
Can be considered. Here, α ″ is a constant taking into account the physical constant of D and the like. Considering the above formula (A) and the above formula (B), the relationship between the defect size and the film thickness, which are likely to become voids, is
D = α ′ × (βT _SOI + T _BOX ) / α ″
= Α × (βT _SOI + T _BOX ) (C)
Can be considered. However, the defect size that occurs during the process does not necessarily have an infinite value, and it is necessary to manage the clean room and cleanliness and consider that the process is designed to have a finite value. As the thickness increases, it is considered that the defect size, which is likely to become a void, gradually becomes less influential as the film thickness increases.

Therefore, the relationship between the defect size that tends to cause voids and the film thickness of the SOI layer and the BOX layer is
D = α × (βT _SOI + T _BOX ) γ (D)
it is conceivable that. When fitting with experimental data based on this relational expression, the constants in the formula (D) show good agreement when α = 60, β = 0.008, and γ = 0.24, respectively. I was able to derive.

  Then, the allowable defect size Ds is calculated from the thicknesses of the SOI layer and the BOX layer in the SOI wafer to be manufactured by the above formula (1), and the number of defects equal to or larger than this defect size Ds is 10 per wafer. A wafer that satisfies the following conditions is determined as a wafer suitable for a bonded SOI wafer to be manufactured. By producing a bonded SOI wafer using a wafer that has been determined to be suitable, the generation of voids and blisters after bonding heat treatment during bonding is reduced, thus improving the yield of bonded SOI wafers. be able to. In addition, it can be expected to realize a thin BOX-SOI wafer and a directly bonded bonded wafer with high yield.

  For example, in an SOI wafer manufactured by an ion implantation separation method, when the thickness of the buried oxide film layer immediately after the separation heat treatment is 2 to 5 nm and the thickness of the SOI layer is 400 to 800 nm, the first silicon substrate and the second silicon substrate It is preferable that the defect size Ds allowed as a substrate is 90 nm, and the number of defects equal to or larger than the defect size Ds allowed as the first silicon substrate and the second silicon substrate is 10 or less.

  As a method for measuring defects existing on the wafer before bonding, for example, a generally used particle counter or surface detector can be sufficiently managed. Bonding may be performed after classifying the types and sizes of defects using a high-sensitivity SEM. However, considering the cost and throughput, it is possible to obtain a sufficient effect even with an inspection similar to a particle counter or a surface inspection machine.

  Further, as a wafer suitable for bonding, a perfect crystal wafer without COP can be used to suppress the defect size and the number of defects. Therefore, the bonding may be performed using the complete crystal wafer.

  Further, the COP existing on the wafer bonding surface may be reduced by using a method such as heat treatment in an inert gas, RTA treatment, or activation by plasma, and a wafer suitable for bonding may be obtained.

  In this way, by managing the first silicon substrate and the second silicon substrate used for the bonded SOI wafer, it is possible to control the defects of the size that affects the voids and blisters generated in the bonded SOI wafer. In addition, since organic substances, foreign substances, COPs, and the like that are thought to affect the generation of voids and blisters can be managed at the same time, it can be expected to reduce the probability of occurrence of voids and blisters.

  Further, in the method of determining the suitability of the first silicon substrate and the second silicon substrate used for the bonded SOI wafer using the above formula (1), the thickness of the desired SOI layer and the thickness of the BOX layer are determined. Since the defect size that tends to become voids is taken into consideration, it is very effective for a thin BOX-SOI wafer or a directly bonded wafer.

  Next, embodiments of the present invention will be described in detail.

<Example 1>
Defects existing on the wafer before bonding are measured with a surface inspection machine (SP1), the size of the detected LPD (Light Point Defect), and the generation of voids generated on the bonded SOI wafer obtained using the wafer The correlation with the number was investigated.

Here, the SOI layer thickness T _SOI of the SOI wafer to be manufactured is fixed to 550 nm, the thickness T _BOX of the BOX layer is set to four levels of 100 nm, 50 nm, 20 nm, and 2 nm, respectively, to generate voids. The relationship between the size and the number of voids was determined. The result is shown in FIG. Note that the oxide film to be the BOX layer was formed by thermal oxidation.

As apparent from FIG. 2, the thickness T _BOX of the BOX layer, have different easy LPD size voids are generated, the thickness T _BOX is 100nm each BOX layer, 50 nm, 20 nm, in the case of 2 nm, LPD It was found that voids are most likely to occur at a size of 170 nm, 150 nm, 130 nm, and 90 nm.

The SOI layer thickness T _SOI was fixed at 780 nm, and the BOX layer thickness T _BOX was set to 50 nm, 20 nm, and 2 nm, respectively, and the relationship between the LPD size for generating voids and the number of voids generated was obtained. In some cases, when the thickness T _BOX of the BOX layer was 50 nm, 20 nm, and 2 nm, the LPD sizes were 170 nm, 140 nm, and 100 nm, respectively.

The above results confirm that the void disappearance effect due to the viscous flow of the oxide film is reduced, and the effect of trapping foreign substances and organic substances is reduced. The thinner the BOX layer thickness T _BOX , the easier it is to generate voids. There is a tendency for the LPD size to decrease.

From this result, the thickness T _BOX of the SOI layer thickness T _SOI and BOX layer, is inferred that the most dominant factor that voids determine the likely defect size occurs.

Relationship between BOX layer thickness T _BOX and LPD size in defect size Ds value (fitting value) calculated from equation (1) and LPD size (experimental value) where voids are most likely to occur in the actual measurement. Are shown in FIGS. 3 and 4, respectively.

  As is clear from FIG. 3 and FIG. 4, the fitting value and the experimental value are very close to each other, and there is a correlation between the defect size that tends to become a void and the thickness of the BOX layer. It can be seen that voids are generated from the large defect size.

For example, as shown in FIG. 3, when the SOI layer thickness T _SOI is 550 nm and the BOX layer thickness T _BOX is 20 nm, the defect size Ds that tends to form a void is 130 nm. If it is 130 nm or less, voids are less likely to occur after bonding. Therefore, in FIG. 3 and FIG. 4, it can be said that a defect size larger than the fitting value and the experimental value is a void generation region, and a small defect size is a void free region.

  From the above, when manufacturing a bonded SOI wafer, the defect size that is likely to become void, that is, the allowable defect size is calculated in advance from the thicknesses of the BOX layer and the SOI layer in the SOI wafer to be manufactured. To determine the suitability of the first silicon substrate and the second silicon substrate to be used for bonding based on the set value, and to selectively bond the wafers with such management of suitability. Therefore, generation of voids can be prevented in advance.

<Example 2>
Using the above equation (1) showing the relationship between the SOI layer thickness T _SOI and the BOX layer thickness T _BOX and the defect size Ds, an attempt was made to fabricate a directly bonded bonded wafer in which the generation of voids was suppressed. . Specifically, in the SOI wafer to be manufactured, the SOI layer thickness T _{SOI is set} to 780 nm, the BOX layer thickness T _BOX is set to 2 nm, the number of defects larger than the allowable defect size Ds, and the actual void The number of occurrences was verified. The value of the thickness T _SOI of the SOI layer to be manufactured and the value of the thickness T _BOX of the BOX layer were respectively substituted into the above formula (1), and the defect size Ds was determined to be about 100 nm.

  Therefore, an LPD having a size of 100 nm or more is measured with a surface inspection machine, and a wafer in which a large number of defects are detected as about 13 LPDs of this size or more is used as a first silicon substrate for forming an SOI layer. A bonded SOI wafer was produced according to the process shown in FIG. FIG. 5 shows the LPD measurement result by the surface detector on the bonding surface of the first silicon substrate before bonding.

  In addition, with respect to the SOI layer of the SOI wafer obtained by peeling treatment and separation in the ion implantation region, an LPD having a size of 10 μm or more was measured by a surface inspection machine, and the presence or absence of voids and blisters was confirmed. . The result is shown in FIG.

  As is clear from FIG. 6, only one bonded SOI wafer was confirmed as a void in the direct bonding, and the defect size calculated from the above equation (1) when producing the bonded SOI wafer. Even when the first silicon substrate in which the number of defects equal to or greater than Ds is detected is about 13, it can be seen that 1 in-plane void / wf is achieved.

  Further, comparing FIG. 5 and FIG. 6, the position of the void generated in the SOI wafer is the same as that of one of the LPDs detected from the first silicon substrate before bonding, and is generated in the SOI wafer. It was confirmed that the void was generated from LPD. The LPD size was 100 nm.

  In the second embodiment, the number of defects larger than the allowable defect size Ds is 10 or more, and a wafer with a large number of defects detected is used as the first silicon substrate. Therefore, the number of defects is suppressed to 10 or less. It can be judged that further improvement can be made by using a new wafer.

It is a figure which shows the manufacturing method of the SOI wafer of this invention embodiment in process order. It is a figure which shows the relationship between the LPD size of Example 1, and the number of void generation | occurrence | production. It is a figure which shows the relationship (thickness of SOI layer 550 nm) of LPD size and the thickness of a BOX layer which are easy to generate the void of Example 1. FIG. It is a figure which shows the relationship (thickness of an SOI layer of 780 nm) of LPD size and the thickness of a BOX layer which are easy to generate the void of Example 1. FIG. It is a figure which shows the 100 nm or more LPD map in the bonding surface of the 1st silicon substrate before bonding of Example 2. FIG. 10 is a diagram showing an LPD map of 10 μm or more in the SOI layer of the SOI wafer just after peeling in Example 2. FIG. It is a schematic cross section which shows the void and blister which are bonding defects.

Explanation of symbols

DESCRIPTION OF SYMBOLS 11 SOI wafer 12 2nd silicon substrate 13 SOI layer 14 1st silicon substrate 15 Laminated body 16 Ion implantation area | region 17 Peeling wafer 21 Oxide film

Claims (3)

A first silicon substrate for forming an SOI layer and a second silicon substrate to be a support substrate are bonded via an oxide film, and then the first silicon substrate is thinned to form an embedded oxide film layer on the support substrate. In a manufacturing method of a bonded SOI wafer having a structure in which an SOI layer is formed through
In accordance with the thicknesses of the buried oxide film layer and the SOI layer in the SOI wafer to be manufactured, the defect size and the number of defects allowed for the first silicon substrate and the second silicon substrate are set, and the set values are set. A method for manufacturing a bonded SOI wafer, wherein the suitability of the first silicon substrate and the second silicon substrate is determined based on the determination. In an SOI wafer manufactured by an ion implantation delamination method, when the thickness of the buried oxide film layer immediately after delamination heat treatment is 2 to 5 nm and the thickness of the SOI layer is 400 to 800 nm,
The defect size Ds allowed as the first silicon substrate and the second silicon substrate is 90 nm, and the number of defects larger than the defect size Ds allowed as the first silicon substrate and the second silicon substrate is 10 or less. The manufacturing method of the bonding SOI wafer of Claim 1.   A bonded SOI wafer obtained by the production method according to claim 1.

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