JP2010039632A - Bus arbitration system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To make it possible to perform bus arbitration depending on desired priority order even if a bus master of low priority issues a bus transfer request prior to a bus master of high priority. <P>SOLUTION: A bus arbitration system includes a plurality of bus masters, a plurality of memory controllers, and a bus arbiter for arbitrating access conflict when accessing the memory controller via a system bus, notifies the bus arbiter of a queue state storing bus transfer requests of the plurality of bus masters, compares the notified queue state with a preset condition for determination, and then decides timing for arbitrating the access conflict based on the determination result. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a bus arbitration system including a bus arbiter in which at least one or more bus masters and a memory controller are connected by a system bus and arbitrate bus transfer of the bus master.

  As a conventional means of arbitrating access to the memory controller, the bus arbiter monitors only the transfer on the system bus. Each time the bus transfer of each bus master ends, arbitration between the bus masters issuing the bus transfer request at that time I do. A method of giving an access right to the memory controller to a bus master having a high priority at that time is generally known.

  However, in this conventional arbitration method, the timing at which each bus master issues a transfer request is different, so that a bus master transfer request with a higher priority necessarily obtains an access right before a bus master transfer request with a lower priority. Not always.

FIG. 8 is a diagram illustrating an example in which bus arbitration is performed by a conventional arbitration method when a plurality of bus masters issue a bus transfer request at each timing.
As shown in FIG. 8, there is an embedded system in which bus transfer requests are issued in order from a bus master with a low priority, and bus transfer requests of a bus master with a high priority are issued only infrequently. In this case, at the time when the bus transfer is completed and the next arbitration is performed, another bus master having a higher priority has not yet issued a transfer request. For this reason, a situation occurs in which a bus master having a low priority is assigned an access right first, performs bus transfer, and is stored in the queue of the memory controller. Therefore, even if the priority of each bus master is set in advance, the bus transfer requests are stored in the queue of the memory controller in an order different from the priority depending on the bus transfer request timing of each bus master. Thereby, bus arbitration according to a desired priority order cannot be performed.

  Therefore, in order to solve this problem, a reordering technique in which a plurality of bus transfer requests once stored in the queue of the memory controller are changed in order within the queue, so that a bus transfer request with a higher priority is made first. There is. There is also known a technique in which a queue dedicated to each bus master is provided in the memory controller, and the memory access processing is performed first from the queue of the bus master having a high priority.

  However, the method of performing reordering inside the queue requires a relatively complicated control circuit that rearranges the bus transfer requests stored in the queue by the bus arbitration in a desired order once again. Further, in the method having the dedicated queue, it is necessary to prepare queues as many as the number of bus masters to be given priority, which increases the circuit scale. Furthermore, neither of these methods is a solution to the problem that the bus arbitration according to the desired priority, which is a fundamental problem, cannot be performed.

  In view of the above-described problems, the present invention performs bus arbitration according to a desired priority even when a low priority bus master issues a bus transfer request before a high priority bus master. The purpose is to be able to.

  In the bus arbitration system of the present invention, a plurality of bus masters, a plurality of memory controllers, and the plurality of bus masters access the memory controller via a system bus connecting the plurality of bus masters and the plurality of memory controllers. A bus arbitration system including a bus arbiter for arbitrating access contention, a queue status notification means for notifying the bus arbiter of a queue status for storing bus transfer requests of the plurality of bus masters, and a notification by the queue status notification means Determining means for comparing the queue state with a preset condition, and arbitration timing control means for determining a timing for arbitrating access competition based on a result of the determination means. .

  According to the present invention, since the bus arbitration timing can be made longer than in the prior art, it is possible to perform bus arbitration according to a desired priority order.

(First embodiment)
Hereinafter, embodiments of the present invention will be described with reference to FIGS. In the present embodiment, the bus arbitration timing is configured to perform arbitration when the number of queues in the memory controller is two or more. It is assumed that the number of competing bus masters that perform arbitration is four.

FIG. 1 is a diagram illustrating an example of a bus arbitration system according to the present embodiment.
In FIG. 1, in this embodiment, the bus arbiter 107 detects bus transfer contention when four master devices 101 to 104 connected to the system bus 106 perform bus transfer to the memory controller 105 connected to the system bus 106. Mediate at.

  Further, the memory controller 105 of this embodiment stores therein a plurality of bus transfer requests of each bus master in advance. And it has a queue for this. The bus arbiter 107 is configured to control the timing of bus arbitration by detecting and monitoring the number of empty queues notified from the memory controller 105.

FIG. 2 is a block diagram illustrating a detailed configuration example of the bus arbitration system according to the present embodiment.
In FIG. 2, the bus arbiter 200 includes an arbitration determination unit 201, an arbitration timing control unit 202, an arbitration unit 203, and an arbitration timing setting unit 204 that performs initial setting of the bus arbitration system. In addition, the memory controller 220 includes a queue state notification unit 221.

  The arbitration determination unit 201 is a block that receives the queue state notification signal 250 from the memory controller 220 and determines whether the condition is satisfied by comparing with a preset arbitration condition. It is determined whether a condition for performing bus arbitration is satisfied, a determination flag indicating the result is generated, and based on this, it is determined whether or not to perform arbitration. In the present embodiment, when the number of empty queues of the memory controller 220 notified by the queue state notification signal 250 is two or more, the bus arbitration condition is satisfied, and the determination flag is set to 1.

  The arbitration timing control unit 202 is a block that receives the determination flag from the arbitration determination unit 201 and controls the bus transfer request of each bus master based on the determination flag, the number of empty queues, and the number of bus masters that are issuing bus transfer requests. . While the determination flag is 0, all bus transfer requests of each bus master are masked to 0, and the bus arbitration in the arbitration unit 203 is stopped.

  On the other hand, when the determination flag becomes 1 and the condition for performing the bus arbitration is satisfied in the arbitration determination unit 201, the bus transfer request mask of each bus master is canceled by the number of empty queues at that time. To continuously arbitrate the bus transfer requests for the number of empty. At this time, if the number of bus masters issuing bus transfer requests is less than the number of free queues, the mask is continuously released by the number of bus masters issuing bus transfer requests. Arbitrate bus transfer requests.

  Note that the determination flag is not taken into consideration until the transfer for the empty number of queues or the bus arbitration for the number of bus masters that have issued the bus transfer request is completed. As soon as the bus arbitration for a predetermined number of times is completed, the determination flag is monitored again and the next arbitration timing is awaited. In this embodiment, when the number of empty queues in the memory controller 220 is 1 or less, the bus transfer request of each bus master is masked to 0 and bus arbitration is stopped.

  When the number of vacant queues becomes two and the determination flag is set to 1, if the number of bus masters issuing bus transfer requests is two or more, until two bus arbitrations are performed The bus transfer request mask of each bus master is canceled and the bus arbitration is performed continuously. If the number of bus masters issuing a bus transfer request is 1, the bus transfer request mask is canceled until the bus master performs bus arbitration. As soon as the bus arbitration is completed twice or once, the state of the determination flag is monitored again, and the bus transfer request of each bus master is masked until the next arbitration timing.

  FIG. 3 is a diagram illustrating a state in which there are two or more bus masters issuing bus transfer requests when the determination flag is set to 1. Here, although details will be described later, the value of Que_Vac is set to 2 which is a threshold when performing the bus arbitration of the present embodiment, and the queue status notification signal 250 is the number of free queues in the memory controller 220. Is shown.

  The gnt signal is a signal for the arbitration unit 203 to perform bus arbitration and give an access right to any bus master. The condition flag flg is set to 1 when the value of the queue state notification signal 250 becomes 2 and the preset condition for bus arbitration is satisfied. When flg is set to 1, the bus transfer request mask of each bus master is canceled and bus arbitration is performed.

  When the arbitration unit 203 performs bus arbitration and a bus access right is given to one of the bus masters (gnt = 1), bus transfer is performed. Then, the bus transfer request is stored in the queue of the memory controller 220, and the number of empty queues notified by the queue state notification signal 250 is reduced by one. Since there are two or more bus masters that have issued a bus transfer request when flg is set to 1, the arbitration timing control unit 202 continuously cancels the mask and causes the next bus arbitration to be performed. When the bus arbitration is completed twice, the flg signal is monitored again, and the bus arbitration is stopped by masking the bus transfer requests of all the bus masters to 0 until the flg signal is set to 1 again.

  The arbitration unit 203 is the same as conventional arbitration means, and is a block that performs bus arbitration by a fixed priority method, a round robin method, or the like, and continuously changes access right assignment to any bus master. The arbitration timing setting unit 204 is a register group that performs operation settings of the bus arbitration system of the present embodiment, and is set by a CPU or the like.

  Reference numeral 210 denotes a queue empty number setting register for setting a threshold value for determining the number of empty queues in the memory controller 220 when the bus arbitration is performed. The output Que_Vac is connected to the arbitration determination unit 201.

FIG. 4 is a diagram showing specifications of the queue empty number setting register.
In FIG. 4, Bits indicates a bit configuration, and Name indicates a register name. Access is a register attribute, R indicates read, and W indicates write. Function indicates a register function. Note that although Que_Vac has a 4-bit configuration, the bit width may be increased or decreased according to the total number of queues that the memory controller 220 has.

  The queue status notification unit 221 is a block that notifies the bus arbiter 200 of the status of the queue in the memory controller 220 by a queue status notification signal 250. In the case of this embodiment, the number of empty queues is counted and notified.

Next, the operation of this embodiment will be described with reference to the flowchart of FIG.
First, the CPU or the like sets the queue empty number 0x2, which is a condition for performing bus arbitration, in the queue empty number setting register 410 (step S1). Here, when the number of empty queues is 2 or more, a setting is made to perform bus arbitration.

  When initialization is performed, the bus arbiter 200 starts monitoring the queue state notification signal 250 notified from the memory controller 220 (step S2). Next, it is determined whether or not the value of the queue state notification signal 250 is 2 or more (step S3). If the result of this determination is 1 or less, the process returns to step S2. On the other hand, if the result of determination in step S3 is 2 or more, the process proceeds to step S4 to start bus arbitration. Then, it is determined whether or not the number of bus masters issuing a bus transfer request is larger than the number of empty queues (step S4).

  If the result of this determination is that there are more queues than available, bus arbitration is performed for the number of available queues and an access right is assigned to each bus master (step S5). On the other hand, if the number of bus masters issuing a bus transfer request is equal to or less than the number of empty queues as a result of the determination in step S4, bus arbitration is performed for the number of bus masters issuing a transfer request. An access right is assigned to the bus master (step S6). When the predetermined number of bus arbitrations are completed, monitoring of the value of the queue state notification signal is started again (step S2).

  As described above, according to the present embodiment, the bus arbitration timing can be set longer than that in the prior art, so that bus arbitration according to a desired priority order can be performed.

  FIG. 9 is a diagram illustrating a case where bus arbitration is set when the number of empty queues is two or more. FIG. 9 shows a bus arbitration operation when the bus arbitration system of this embodiment is applied when each bus master issues a bus transfer request at exactly the same timing and interval as in the example shown in FIG.

  As shown in FIG. 9, by using the bus arbitration system of the present embodiment, it is possible to increase the number of bus masters that issue bus transfer requests during bus arbitration. Thereby, the bus transfer request of each bus master can be stored in the queue of the memory controller in the order according to the desired priority. In addition, since it is not necessary to adjust the bus transfer request once the bus arbitration is performed by the memory controller according to the priority order as in the prior art, it is possible to perform memory access according to the desired priority order with an easy circuit configuration. Make it possible.

(Second Embodiment)
In the first embodiment, the condition for performing the bus arbitration is set by the threshold value of the number of empty queues. However, in this case, the contents of each bus transfer request stored in the queue are not taken into consideration at all, and are not necessarily optimal. It was not always possible to achieve the correct bus arbitration timing.

  For example, in a memory controller having a four-stage queue, it may be set to start bus arbitration when two or more stages of queues are available. In this case, when the two bus transfer requests that are still stored in the queue are two 8-beat transfer requests and two 4-beat transfer requests, the memory access of these transfer requests is completed. The latency required to do this is quite different.

  Normally, if the memory controller queues at least one bus transfer request to prepare for the next memory access after the current memory access, the memory controller does not need extra latency. Can be done. Therefore, if the transfer amount for a total of 8 beats remains in the queue with two 4-beat transfer requests and the next bus arbitration is started, a new bus transfer request can be stored. There is no need to start bus arbitration with two requests stored. It is possible to start the bus arbitration after another bus transfer request leaves the queue and the number of empty queues becomes three. In this case, an extra timing for starting bus arbitration can be obtained, so that more effective bus arbitration can be performed.

  Thus, it is not a uniform value that the next bus arbitration is appropriate when the number of queues is empty, but depends on the total transfer amount of bus transfer requests stored in the memory controller queue. Fluctuates. Therefore, in view of the above problem, in this embodiment, by setting a threshold value for the total transfer amount of each bus transfer request stored in the queue, the total transfer amount can be set without fixing the number of empty queues uniformly. In response, the timing of mediation is dynamically changed. As a result, more effective bus arbitration can be performed.

  FIG. 6 is a block diagram illustrating a detailed configuration example of the bus arbitration system according to the present embodiment. In this embodiment, a condition for performing bus arbitration is set based on the total transfer amount of each bus transfer request stored in the queue. The configuration shown in FIG. 6 is almost the same as the configuration of the first embodiment shown in FIG. 2, but in this embodiment, the contents set by the arbitration timing setting unit 604 and the queue state in the memory controller 620 The content notified by the notification unit 621 is different.

  Reference numeral 610 denotes a register that is set by the arbitration timing setting unit 604, and is a queue that sets a threshold value for determining how many bytes or less the bus transfer request stored in the queue of the memory controller 620 is to perform bus arbitration. This is a total transfer amount setting register. The output Que_Amo is connected to the arbitration determination unit 601.

  FIG. 7 is a diagram showing the specifications of the queue total transfer amount setting register 710. In FIG. 7, Que_Amo has a 4-bit configuration, but the bit width may be increased or decreased according to the value of the total transfer amount to be set. In the present embodiment, the queue status notification unit 621 notifies the bus arbiter 600 of the total transfer amount of bus transfer requests stored in the queue using the queue status notification signal 650 in addition to the number of empty queues.

  The arbitration determination unit 601 compares the value set by the queue total transfer amount setting register 610 with the total transfer amount information notified by the queue state notification signal 650, and determines the timing for starting bus arbitration. The queue status notification signal 650 notifies the number of empty queues in addition to the total transfer amount information, thereby controlling how many times the bus arbitration is performed at the time of bus arbitration.

  FIG. 10 is a diagram showing the operation timing of the present embodiment. In this embodiment, the bus arbitration is started when the total transfer amount of each bus transfer request stored in the queue becomes 4 bytes or less.

  It is assumed that the memory controller 620 has a four-stage queue, and bus transfer requests are already stored in the queue in the order of 8 bytes, 1 byte, 1 byte, and 4 bytes. In this case, the value of Que_Amo is set to 4, which is a threshold value for bus arbitration, and the number of empty queues and the total transfer amount stored in the queue are notified by the queue state notification signal 650. The gnt signal is a signal for the arbitration unit 603 to perform bus arbitration and give an access right to any bus master.

  The queue initially stores a total transfer amount of 14 bytes, and when the three bus transfer requests leave the queue, the total transfer amount inside the queue becomes 4 bytes, which is the condition for starting bus arbitration. Flg is set to 1 and bus arbitration is started. In the present embodiment, the condition for performing the bus arbitration is not limited to the number of empty queues or the total transfer amount of the queue. Furthermore, a more effective bus arbitration system can be easily expanded by taking into account read / write attributes and page hit / miss conditions.

  As described above, according to the present embodiment, the bus arbitration timing can be set longer than in the prior art, so that the bus arbitration according to the desired priority order can be performed.

(Other embodiments according to the present invention)
Each means constituting the bus arbitration system and each step of the bus arbitration method in the embodiment of the present invention described above can be realized by operating a program stored in a RAM or ROM of a computer. This program and a computer-readable recording medium recording the program are included in the present invention.

  Further, the present invention can be implemented as, for example, a system, apparatus, method, program, or recording medium. Specifically, the present invention may be applied to a system including a plurality of devices. The present invention may be applied to an apparatus composed of a single device.

  Note that the present invention includes a case where a software program for realizing the functions of the above-described embodiments (in the embodiment, a program corresponding to the flowchart shown in FIG. 5) is directly or remotely supplied to a system or apparatus. This includes the case where the system or the computer of the apparatus is also achieved by reading and executing the supplied program code.

  Accordingly, since the functions of the present invention are implemented by computer, the program code installed in the computer also implements the present invention. In other words, the present invention includes a computer program itself for realizing the functional processing of the present invention.

  In that case, as long as it has the function of a program, it may be in the form of object code, a program executed by an interpreter, script data supplied to the OS, and the like.

  Examples of the recording medium for supplying the program include a flexible disk, a hard disk, an optical disk, and a magneto-optical disk. Further, there are MO, CD-ROM, CD-R, CD-RW, magnetic tape, nonvolatile memory card, ROM, DVD (DVD-ROM, DVD-R) and the like.

  As another program supply method, there is a method of connecting to a homepage on the Internet using a browser of a client computer. The computer program itself of the present invention or a compressed file including an automatic installation function can be downloaded from the homepage by downloading it to a recording medium such as a hard disk.

  It can also be realized by dividing the program code constituting the program of the present invention into a plurality of files and downloading each file from a different homepage. That is, a WWW server that allows a plurality of users to download a program file for realizing the functional processing of the present invention on a computer is also included in the present invention.

  As another method, the program of the present invention is encrypted, stored in a recording medium such as a CD-ROM, distributed to users, and encrypted from a homepage via the Internet to users who have cleared predetermined conditions. Download the key information to be solved. It is also possible to execute the encrypted program by using the key information and install the program on a computer.

  Further, the functions of the above-described embodiments are realized by the computer executing the read program. Furthermore, based on the instructions of the program, an OS or the like running on the computer performs part or all of the actual processing, and the functions of the above-described embodiments can be realized by the processing.

  As another method, the program read from the recording medium is first written in a memory provided in a function expansion board inserted into the computer or a function expansion unit connected to the computer. Then, based on the instructions of the program, the CPU or the like provided in the function expansion board or function expansion unit performs part or all of the actual processing, and the functions of the above-described embodiments are also realized by the processing.

It is a figure which shows an example of the bus arbitration system which concerns on the 1st Embodiment of this invention. It is a block diagram which shows the detailed structural example of the bus arbitration system which concerns on the 1st Embodiment of this invention. It is a figure which shows a state when there are two or more bus masters which have issued the bus transfer request when the determination flag is set to 1. It is a figure which shows the specification of the queue empty number setting register | resistor in the 1st Embodiment of this invention. It is a flowchart which shows an example of the operation | movement procedure in the 1st Embodiment of this invention. It is a block diagram which shows the detailed structural example of the bus arbitration system which concerns on the 2nd Embodiment of this invention. It is a figure which shows the specification of the queue total transfer amount setting register | resistor in the 2nd Embodiment of this invention. It is a figure which shows the example of mediation in the conventional mediation system. It is a figure which shows the example of arbitration at the time of using the arbitration system in the 1st Embodiment of this invention. It is a figure which shows the operation | movement timing of the 2nd Embodiment of this invention.

Explanation of symbols

200 Bus Arbiter 201 Arbitration Determination Unit 202 Arbitration Timing Control Unit 203 Arbitration Unit 204 Arbitration Timing Setting Unit 220 Memory Controller 221 Queue State Notification Unit 250 Queue State Notification Signal

Claims (4)

A plurality of bus masters, a plurality of memory controllers, and a bus arbiter that arbitrates access contention when the plurality of bus masters accesses the memory controller via a system bus connecting the plurality of bus masters and the plurality of memory controllers. A bus arbitration system comprising:
A queue status notification means for notifying the bus arbiter of a queue status for storing bus transfer requests of the plurality of bus masters;
A determination unit that determines the state of the queue notified by the queue state notification unit by comparing with a preset condition;
A bus arbitration system comprising: an arbitration timing control unit that determines a timing for arbitrating access competition based on a result of the determination unit. The determination means determines whether the number of empty queues has reached a preset value,
2. The bus arbitration system according to claim 1, wherein the arbitration timing control means determines whether to perform bus arbitration according to a result of determination of the number of empty queues by the determination means. The determination means determines the combination of attributes of all bus transfer requests stored in the queue by comparing with a preset condition,
2. The bus arbitration system according to claim 1, wherein the arbitration timing control means dynamically changes a timing for performing bus arbitration according to a result of determination of the attribute combination by the determination means.   4. The arbitration timing control means, when detecting the number of empty queues and performing bus arbitration, continuously assigns bus access rights for the number of empty queues. The bus arbitration system according to claim 1.

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