JP2007280253A - Information processor and information processing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To guarantee the real time property of a master and to improve memory bus transfer efficiency. <P>SOLUTION: This information processing method or the like is provided, which comprises: a comparison result receiving step for performing an operation in which a remaining time until a determined time and the amount of data until a determined data amount are used to perform the operation and receiving a comparison result of each operation result; a memory access request receiving step for receiving a memory access request; and a processing urgency determining step for determining the processing urgency of the memory access request on the basis of information including the operation result, and processes the memory access request preferentially when urgency is determined to be high in the processing urgency determining step. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to an information processing apparatus, an information processing method, and a program thereof, and relates to a technique suitable for use in, for example, a memory controller.

  The master needs to complete the transfer of the requested amount of data within the requested time. When the amount of data to be transferred with respect to the requested time is large, the real-time property of the master becomes severe. Conversely, when the amount of data to be transferred with respect to time is small, the real-time property can be afforded.

  Conventionally, a real-time guarantee arbiter such as [SOC idea number] P204024 has been proposed to guarantee real-time performance. As shown in FIG. 5, the real-time guarantee arbiter sets the amount of data to be transferred for each master and the time until data transfer is completed. The real-time guarantee arbiter calculates the requested transfer rate (= remaining data amount ÷ remaining time) for each master, and gives the bus right in preference to the master that needs the bus right most in order to guarantee real-time performance.

  In the example of FIG. 5, the requested transfer rates A1, B1, and C1 at time t1 are A1> C1> B1, and at time t1, the bus right is given with the priority of master a> master c> master b. Become. As a result of master A having priority over other masters and acquiring the bus right by time t2, the requested transfer rates A2, B2, and C2 at time t2 are B2> A2> C2, and at time t2, master b> master a> master The bus right is assigned with the priority of c.

  As described above, the real-time guarantee arbiter shortens the time to acquire the bus right and guarantees the real-time property of the master by causing the master having the strictest real-time property to use the bus preferentially at a certain time.

  Some memory controllers have attempted to guarantee the real-time property of the master. The memory controller holds a reordering queue as shown in FIG. 6, and prioritizes stored memory access requests in consideration of the occurrence of bank conflicts, page hit misses, and real-time characteristics.

  Whether the real-time property is severe is determined based on a fixed priority assigned to each master. Taking FIG. 5 as an example, a high priority is assigned to the master b having the largest average transfer rate (= data amount / time). A memory access request with a high priority is issued to the memory.

  In FIG. 6, the memory access requests stored in the reordering queue are prioritized by algorithms of (1) presence / absence of bank conflict and page hit miss, (2) real-time property, and (3) arrival order. Then, the memory access request request3 having the highest priority is processed. As described above, the memory controller uses the reordering queue to guarantee real-time performance and improve memory bus utilization efficiency.

  As described above, conventionally, in order to guarantee the real-time property of the master, either or both of the real-time guarantee arbiter and the memory controller performing reordering are used in combination. The real-time guarantee arbiter reduces the time from when the master issues the memory access request until the bus is acquired until the memory controller that performs reordering stores the memory access request in the reordering queue until it is processed in memory. can do.

  However, in order to guarantee the real-time property of the master, it is necessary to consider the time from when the master issues a memory access request until it is processed by the memory. Sex cannot be fully guaranteed. Therefore, there is a need for a means for guaranteeing the real-time property of the master by combining a real-time guarantee arbiter and a reorderable memory controller.

  However, there is no dependency between the reordering of the real-time guarantee arbiter and the memory controller, and each guarantees the real-time property of the master independently. The real-time guarantee arbiter gives the bus right to the master having the highest real-time property at a certain time, whereas the memory controller uses the real-time property of the master as a judgment material for prioritization for reordering.

  Therefore, even when the real-time guarantee arbiter gives the bus right to the memory access request that is really strict in real-time and is stored in the reordering queue in the memory controller, the prioritization algorithm that emphasizes the occurrence of bank conflicts, etc. There is a possibility that the processing priority may be lowered due to the influence of other factors such as occurrence of conflict and page hit. Therefore, a memory access request that arrives later is processed first like request 1 in FIG. 6, and there is a possibility that the result request 1 may not satisfy the real-time property.

  Also consider the case where the importance of real-time performance is increased in the reordering prioritization algorithm. In this case, the real-time property that is fixedly set is strict as in the master b in FIG. 5B, but even if the memory access request is from a master that has sufficient real-time property because the bus right is sufficiently acquired. The memory controller is preferentially processed. As a result, the occurrence of bank conflicts and page misses may reduce the memory bus transfer efficiency and reduce the system performance.

  As described above, in order to actually guarantee the real-time property of the master and improve the memory bus transfer efficiency, an information processing apparatus in which the real-time guarantee arbiter and the memory controller operate in cooperation is necessary. That is, there is a need for a method in which the memory controller performs reordering by selecting whether to prioritize real-time performance or memory bus transfer efficiency in accordance with dynamic changes in the real-time performance of the master.

  The present invention has been made in view of the above-mentioned problems, and has as its object to ensure the real-time property of the master and improve the memory bus transfer efficiency.

  In order to solve the above-mentioned problem, the present invention performs an operation using the remaining time until the determined time is reached and the remaining data amount until the determined amount of data is reached, and compares the results of the calculation results. A comparison result receiving step for receiving, a memory access request receiving step for receiving a memory access request, a processing urgency level determining step for determining a processing urgency level of the memory access request based on information including the calculation result, and the processing There is provided an information processing method or the like characterized by preferentially processing the memory access request when the urgency level is determined to be high in the urgency level determination step.

  According to the present invention, the memory controller receives the memory access request from the real-time guarantee arbiter, the transfer rate requested by the master, the set data amount and time, determines the urgency of the memory access request, and improves the real-time property. Switching between priority reordering and memory bus utilization efficiency priority. Thereby, the memory bus transfer efficiency can be improved while guaranteeing the real-time property of the master.

(First embodiment)
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
FIG. 1 is a block diagram illustrating an example of a system configuration in the present embodiment.
This system includes masters 10, 11, 12 and 13, a real-time guarantee arbiter 15, a memory controller 16 and a memory (SDRAM) 17.

  Each of the masters 10 to 13 has real-time characteristics. The real-time guarantee arbiter 15 includes data amount setting registers 158, 162, 166, and 170 for setting the data transfer amount for each of the masters 10 to 13, and time setting registers 159, 163, 167, and 171 for setting the data transfer time. Have

  The real-time guarantee arbiter 15 also includes data transfer amount counters 156, 160, 164, and 168 that decrement the data amount transferred by each master from the value of the data amount setting register and output the remaining data amount. The real-time guarantee arbiter 15 also has timers 157, 161, 165, and 169 that start counting down from the value of the time setting register time after the first memory access request of the masters 10 to 13 arrives and output the remaining time.

  The requested transfer rate calculation means 152 to calculate the requested transfer rate by dividing the remaining data amount output from the data transfer amount counters 156, 160, 164, 168 by the remaining time output from the timers 157, 161, 165, 169. 155. Further, the real-time guarantee arbiter 15 has arbitration means 151 that gives priority to the master having the highest required transfer speed by comparing the required transfer speeds calculated by the required transfer speed calculating means 152 to 155.

  The memory controller 16 includes a memory access request storage unit 180 that stores the memory access request acquired by the arbitration unit 151 and the emergency flag notified by the processing urgency determination signal 203.

  Further, the memory controller 16 determines the requested transfer rate of the master that has issued the memory access request that has arrived at the memory controller 16 by the request transfer rate signal 201, the data amount signal 202, and the time signal 203, and the set data amount and time. The information is received from the arbitration unit 151, the average transfer rate (= data amount / time) is calculated, it is determined whether the requested transfer rate is greater than the average transfer rate, and if it is greater, the memory access request is urgent. It has processing urgency determining means 181 for storing the indicated flag in the memory access request storing means 180.

  Further, the memory controller 16 monitors the emergency flag of the memory access request stored in the memory access request storage unit 180 by the emergency flag signal 204, and if at least one emergency flag is set, the algorithm is sent to the priority determination unit 182. Algorithm change means 182 for asserting the change signal 205 and notifying the algorithm change is provided.

  Further, the memory controller 16 switches the algorithm for prioritizing the memory access request stored in the memory access request storage unit 180 by the algorithm change signal 205 and sends the memory access request selected by the algorithm to the memory 17 Degree determining means 183.

  14 is a bus. 201 is a request transfer rate signal for the arbitration unit 151 to notify the processing urgency determination unit 181 of the request transfer rate of the master that has issued the memory access request that has acquired the bus right. Reference numeral 202 denotes a data amount signal for the arbitrating unit 151 to notify the processing urgency determining unit 181 of the data amount to be transferred set in the master that has issued the memory access request that has acquired the bus right.

  203 is a time signal for the arbitration unit 151 to notify the processing urgency level determination unit 181 of the transfer time set for the master that has issued the memory access request that has acquired the bus right. Reference numeral 204 denotes a processing urgency determination signal that is asserted by the processing urgency determination means 181 when the memory access request that has acquired the bus right is urgent.

  205 is an emergency flag signal for the algorithm changing unit 182 to monitor all emergency flags stored in the memory access request storage unit 180. An algorithm change signal 206 is asserted when the algorithm change unit 182 notifies the priority determination unit 183 of the algorithm change. Reference numeral 18 denotes a memory bus signal.

Next, the operation of this embodiment will be described with reference to FIG. The case where the data amount and time of each master 10-13 are set as shown in FIG. 2A will be described as an example.
Assume that the master 10 issues a memory access request request10 at time t1. At t1, since the master having the highest request transfer rate is the master 10, the real-time guarantee arbiter 15 gives the bus right to the memory access request request 10 issued by the master 10.

  At the same time as giving the bus right, the real-time guarantee arbiter 15 uses the requested transfer rate of the master 10, the amount of data set in the master 10, and the time using the requested transfer rate signal 201, the data amount signal 202, and the time signal 203. Is notified to the processing urgency determination means 181. The processing urgency determining unit 181 calculates the average transfer rate by dividing the amount of data received from the real-time guarantee arbiter 15 by time, and determines whether the request transfer rate received from the real-time guarantee arbiter 15 is larger than the calculated average transfer rate. Determine.

  If the requested transfer rate is greater than the average transfer rate based on the determination result, the processing urgency level determination unit 181 asserts the processing urgency level determination signal 204. The memory access request storage unit 180 stores request10 which is a memory access request from the master 10 and a processing urgency determination signal 204 output from the processing urgency determination unit 181 as shown in FIG. The state of the memory access request storage means 180 at this time is as shown in FIG.

FIG. 3 is a flowchart showing the processing of a conventional prioritization algorithm.
In step S301 in FIG. 3, the most efficient memory access request is selected based on the bank conflict and page hit information.

  Next, in step S302, it is determined whether or not the number of selected memory access requests is one. If the result of this determination is that the selected memory access request number is not 1, memory access with high real-time characteristics is selected in step S303.

  Next, in step S304, it is determined whether or not the number of selected memory access requests is one. If the result of this determination is that the number of selected memory access requests is not 1, the memory access request stored first in the memory access request storage means is selected in step S305. Next, in step S306, the selected memory access request is issued to the memory, and the process returns to step S301.

  On the other hand, if the number of selected memory access requests is 1 as a result of the determination in step S302 or step S304, the process jumps to step S306.

  In the conventional memory controller adopting the prioritization algorithm as shown in FIG. 3, when the memory access request storage means is as shown in FIG. 2C, the priority is given in the order of request12> request11> request13> request10. Attached. As described above, processing of request 10 having the highest degree of urgency may be postponed. In addition, while the memory controller is processing request12, request11, and request13 in order, a new memory access request arrives by another master, and the memory access request storage means at time t2 as shown in FIG. Suppose that it becomes a state.

  The priority of each memory access request in this state is request11> request12> request13> request10, and the processing of the memory access request request10 issued by the master with strict real-time property is further postponed. As a result, the real-time property of the master may not be satisfied.

FIG. 4 is a flowchart showing processing of the prioritization algorithm in the present embodiment.
In step S401 in FIG. 4, it is determined whether or not the algorithm change signal 206 is “1”. If the result of this determination is that the algorithm change signal 206 is not 1, in step S402, the most efficient memory access request is selected based on the bank conflict and page hit information.

  Next, in step S403, it is determined whether or not the number of selected memory access requests is one. If the result of this determination is that the number of selected memory access requests is not 1, the memory access request stored first in the memory access request storage means 180 is selected. On the other hand, if the number of selected memory access requests is 1 as a result of the determination in step S403, the process jumps to step S405. Next, in step S405, the selected memory access request is issued to the memory 17, and the process returns to step S401.

  On the other hand, if the algorithm change signal 206 is 1 as a result of the determination in step S401, a memory access request with the urgency flag = 1 is selected in step S406. Next, in step S407, it is determined whether or not the number of selected memory access requests is one.

  If the result of this determination is that the number of selected memory access requests is not 1, the memory access request first stored in the memory access request storage means 180 is selected in step S408, and the process proceeds to step S405. On the other hand, if the result of determination in step S407 is that the number of selected memory access requests is 1, processing proceeds directly to step S405.

  In the present embodiment, the algorithm change unit 182 monitors the emergency flag signal 205 of the memory access request stored in the memory access request storage unit 180, and when one or more emergency flag signals are 1, the algorithm change signal 206 Is asserted.

  The priority determination means 183 prioritizes the memory access requests stored in the memory access request storage means 180 according to the algorithm of FIG. 4 and issues the memory access request with the highest priority to the memory 17.

  When there is no memory access request from a master with a high degree of urgency and the algorithm change signal 206 is negated, the priority determination means 183 issues a memory access request so that the transfer efficiency of the memory bus is improved as before. Prioritize and improve system performance. However, when a memory access request from a master with high urgency is stored in the memory access request storage unit 180 and the algorithm change signal 206 is asserted, the priority determination unit 183 gives priority to the memory access request with high urgency. To process.

  Although the present invention has been described above using the embodiments, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present invention.

(Other embodiments according to the present invention)
Each unit constituting the information processing apparatus and each step of the information processing method in the embodiment of the present invention described above can be realized by operating a program stored in a RAM or a ROM of a computer. This program and a computer-readable recording medium recording the program are included in the present invention.

  Further, the present invention can be implemented as, for example, a system, apparatus, method, program, or recording medium. Specifically, the present invention may be applied to a system including a plurality of devices. The present invention may be applied to an apparatus composed of a single device.

  In the present invention, a software program (in the embodiment, a program corresponding to the flowcharts shown in FIGS. 3 and 4) for realizing the functions of the above-described embodiments is directly or remotely supplied to the system or apparatus. This includes the case where the system or the computer of the apparatus is also achieved by reading and executing the supplied program code.

  Accordingly, since the functions of the present invention are implemented by computer, the program code installed in the computer also implements the present invention. In other words, the present invention includes a computer program itself for realizing the functional processing of the present invention.

  In that case, as long as it has the function of a program, it may be in the form of object code, a program executed by an interpreter, script data supplied to the OS, and the like.

  Examples of the recording medium for supplying the program include a floppy (registered trademark) disk, a hard disk, an optical disk, and a magneto-optical disk. Further, there are MO, CD-ROM, CD-R, CD-RW, magnetic tape, nonvolatile memory card, ROM, DVD (DVD-ROM, DVD-R) and the like.

  As another program supply method, there is a method of connecting to a homepage on the Internet using a browser of a client computer. The computer program itself of the present invention or a compressed file including an automatic installation function can be downloaded from the homepage by downloading it to a recording medium such as a hard disk.

  It can also be realized by dividing the program code constituting the program of the present invention into a plurality of files and downloading each file from a different homepage. That is, a WWW server that allows a plurality of users to download a program file for realizing the functional processing of the present invention on a computer is also included in the present invention.

  As another method, the program of the present invention is encrypted, stored in a recording medium such as a CD-ROM, distributed to users, and encrypted from a homepage via the Internet to users who have cleared predetermined conditions. Download the key information to be solved. It is also possible to execute the encrypted program by using the key information and install the program on a computer.

  Further, the functions of the above-described embodiments are realized by the computer executing the read program. Furthermore, based on the instructions of the program, an OS or the like running on the computer performs part or all of the actual processing, and the functions of the above-described embodiments can be realized by the processing.

  As another method, the program read from the recording medium is first written in a memory provided in a function expansion board inserted into the computer or a function expansion unit connected to the computer. Then, based on the instructions of the program, the CPU or the like provided in the function expansion board or function expansion unit performs part or all of the actual processing, and the functions of the above-described embodiments are also realized by the processing.

It is a block diagram which shows an example of the system configuration | structure in embodiment of this invention. It is a figure which shows operation | movement of the memory controller in embodiment of this invention. It is a flowchart which shows the process of the prioritization algorithm in the past. It is a flowchart which shows the process of the prioritization algorithm in embodiment of this invention. It is a figure which shows an example of operation | movement in a real-time guarantee arbiter. It is a figure which shows an example of operation | movement in the conventional memory controller.

Explanation of symbols

10-13 Master 14 Bus 15 Real-time guarantee arbiter 16 Memory controller 17 Memory 18 Memory bus 151 Arbitration means 152-155 Request transfer rate calculation means 156, 160 164 168 Data transfer amount counters 157, 161, 165, 169 Timer 158, 162, 166, 170 Data amount setting registers 159, 163, 167, 171 Time setting registers 168-171 Timer 180 Memory access storage means 181 Processing urgency judgment means 182 Algorithm change means 183 Priority determination means 201 Requested transfer rate signal 202 Data Quantity signal 203 Time signal 204 Processing urgency determination signal 205 Emergency flag signal 206 Algorithm change signal

Claims (5)

An information processing device comprising a bus arbitration device and a memory controller,
The bus arbitration device arbitrates a bus usage right so that each master can complete data transfer of a determined amount of data within a determined time, and the bus arbitration device further includes the bus arbitration device, Time setting means for setting the time, data amount setting means for setting the data amount, remaining time measuring means for measuring the remaining time until the time is reached, and measuring the remaining data amount until the data amount is reached A data amount measuring means for performing the calculation using the remaining time and the remaining data amount, comparing the calculation results calculated by the calculation circuit for each master, and using the bus according to the comparison result Right assignment,
The memory controller temporarily stores memory access requests issued by individual masters, and prioritizes memory access requests stored in the memory access request storage means according to a first algorithm. A priority determination means for processing, and processes from a memory access request having a high priority,
The memory controller further receives information including at least the calculation result together with a memory access request from the bus arbitration device, and includes a processing urgency determination unit that determines a processing urgency level of the memory access request, and a processing urgency determination unit. When it is determined that the urgency level is high, regardless of the first algorithm, the priority determination unit includes an algorithm change unit that preferentially processes a memory access request with a high urgency level. Information processing device. A computing means for computing using the remaining time until reaching the determined time and the remaining data amount until reaching the determined data amount;
An information processing apparatus comprising: assignment means for assigning a bus use right according to a comparison result of calculation results for each master. Comparison result receiving means for calculating using the remaining time until reaching the determined time and the remaining data amount until reaching the determined data amount, and receiving a comparison result of each calculation result;
Memory access request receiving means for receiving a memory access request;
A process urgency determining means for determining a process urgency of the memory access request based on information including the calculation result;
An information processing apparatus comprising: an algorithm changing unit that preferentially processes the memory access request when the processing urgency level determination unit determines that the urgency level is high. A comparison result receiving step for calculating using the remaining time until reaching the determined time and the remaining data amount until reaching the determined data amount, and receiving a comparison result of each calculation result;
A memory access request receiving step for receiving a memory access request;
A process urgency determining step of determining a process urgency of the memory access request based on information including the calculation result;
An information processing method comprising: preferentially processing the memory access request when it is determined that the urgency level is high in the processing urgency level determination step.   A program for causing each step of the method according to claim 4 to be executed by a computer.

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