JP2010034303A - Method of manufacturing semiconductor wafer - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor wafer in which a material wafer obtained by slicing a single-crystal ingot is processed into the semiconductor wafer having small variance in material characteristics. <P>SOLUTION: The method of manufacturing the semiconductor wafer in which the semiconductor wafer for semiconductor device manufacture is manufactured using the material wafer obtained by slicing the single-crystal ingot, includes: a detection process S42 of detecting a lengthwise position of the material wafer in the single-crystal ingot; and a working process S50 of working the material wafer according to working contents corresponding to the lengthwise position detected in the detection process, as one of working processes upon the manufacturing. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor wafer, in which a material wafer obtained by slicing a single crystal ingot is processed into a semiconductor wafer.

A wafer (semiconductor wafer) for manufacturing a semiconductor device such as a silicon wafer is manufactured by manufacturing a single crystal ingot such as silicon and slicing the ingot to a material wafer through a grinding process, an etching process, and a polishing process. It is manufactured by flattening its surface with high accuracy.
Furthermore, an annealed wafer with reduced defect density on the wafer surface can be produced by further heat-treating (annealing) the semiconductor wafer thus produced.

Moreover, an epitaxial wafer having an epitaxial layer on the wafer surface can be manufactured by vapor-phase-growing a single crystal on the mirror-finished surface of the manufactured semiconductor wafer.
In addition, since an annealed wafer and an epitaxial wafer are wafers for manufacturing semiconductor devices, they are referred to as a semiconductor wafer together with a semiconductor wafer that is not subjected to an annealing process or an epitaxial layer formation.

When processing a raw material wafer obtained by slicing such an ingot into a semiconductor wafer, or when performing an annealing process or epitaxial layer formation process on a semiconductor wafer, most commonly, a large number of wafers are batched. (See Patent Documents 1 and 2), but for etching processes that process semiconductor wafers, single wafer processing that processes wafers in units of one sheet has also been developed (Patent Documents). 3).
JP 2006-108151 A Japanese Patent Laid-Open No. 10-261555 JP 2007-207811 A

By the way, the Czochralski method (CZ method) is widely used for the production of silicon single crystal ingots. Polycrystalline silicon is filled into a crucible and melted and heated to form a silicon melt on the surface of the melt. A silicon single crystal ingot is formed by bringing the seed crystal into contact and solidifying and growing the melt.
However, it has been found that, for example, when a raw material wafer obtained from a single single crystal ingot is batch-processed under the same conditions in batch processing, the material characteristics vary among the wafers.

  As a measure of the material properties of the wafer, for example, the density of COP (Crystal Originated Particles, so-called void defects) detected using LSTD (Laser Scattering Topography Defect) and the BMD (Bulk Micro Defect) which is oxygen precipitates Although the density and width of the DZ (Denuded Zone, defect-free layer) can be used, batch processing is performed under the same conditions in batch, ignoring from which position in the longitudinal direction of the single crystal ingot the material wafer is sliced. As a result, the LSTD density (COP density), BMD density, and DZ width of the processed semiconductor wafer vary from one wafer to another.

  For example, the LSTD density and the DZ width are larger on the top side of the single crystal ingot than the tail side (bottom side), and the BMD density is smaller on the top side than on the tail side. The top side is an upper part at the time of manufacturing including the growth start part of the single crystal ingot, and the tail side (bottom side) is a lower part at the time of manufacturing including the final growth part of the single crystal ingot. FIG. 6 is a diagram showing the detection result of the LSTD density of the wafer according to the longitudinal position (crystal position) of the single crystal ingot, and the top side (crystal position 0 mm side) is the tail side (crystal position 2000 mm). It can be seen that the LSTD density is larger than the LSTD density.

As described above, the material characteristics of the single crystal ingot slightly change in the longitudinal position because the single crystal ingot grows into a substantially cylindrical shape over time and is exposed to a high temperature in the pulling apparatus. This can be attributed to the difference in the time taken by the top and tail sides.
In order to pull up a single crystal ingot with a low resistivity, dopants such as boron and phosphorus are added to the polycrystalline silicon melt in the crucible. At this time, the added dopant is the pulling direction of the single crystal (longitudinal direction). As a result, segregation occurs along the axis, and the resistivity varies in the longitudinal direction of the single crystal ingot. If it is such a cause, it is difficult to eliminate such a change in the material direction of the single crystal ingot in the longitudinal direction.

  SUMMARY OF THE INVENTION The present invention has been made in view of such a problem, and is capable of processing from a material wafer obtained by slicing a single crystal ingot into a semiconductor wafer having little variation in material characteristics. It aims to provide a method.

  In order to achieve the above object, a semiconductor wafer manufacturing method of the present invention is a method for manufacturing a semiconductor wafer for manufacturing semiconductor devices from a material wafer obtained by slicing a single crystal ingot. A detection step of detecting a longitudinal position in the single crystal ingot, and at least one processing step at the time of manufacturing, wherein the material wafer is processed with processing details corresponding to the longitudinal position detected by the detection step And a processing step.

The material wafer includes not only a non-processed wafer obtained by slicing a single crystal ingot but also a wafer before heat treatment when an annealed wafer is manufactured, for example.
In the detection step, it is preferable to detect a longitudinal position of the material wafer in the single crystal ingot using a laser mark ID which is given to the material wafer and can be used for product management.

In the processing step, it is preferable to batch process the material wafers.
In the processing step, it is preferable to divide the material wafer into a plurality of groups according to the position in the longitudinal direction of the single crystal ingot, and to change the processing content in units of each group. In this case, the plurality of groups may be three groups: a group on the top side of the single crystal ingot, a group on the tail side of the single crystal ingot, and a group in the middle portion located between these groups. preferable.

In the processing step, the material wafer may be subjected to single wafer processing.
The processing step is preferably an annealing step for annealing the material wafer using a wafer whose surface has been flattened with high accuracy through a grinding step and a polishing step as a material wafer.
Alternatively, the processing step may be a polishing step in which the wafer that has undergone the grinding step is used as a material wafer, and the surface of the material wafer is planarized with high accuracy after annealing.

  In any of the above cases, in the annealing step, the amount of heat applied to the material wafer corresponding to the top side of the single crystal ingot is larger than the amount of heat applied to the material wafer corresponding to the tail side of the single crystal ingot. It is preferable to enlarge it.

  According to the method for manufacturing a semiconductor wafer of the present invention, when manufacturing a semiconductor wafer for manufacturing a semiconductor device from a material wafer, the longitudinal position in the single crystal ingot of the material wafer is detected, and the detected longitudinal direction position is determined. Since the material wafer is processed according to the processing contents, it is possible to appropriately process each material wafer having different material characteristics according to the position in the longitudinal direction.

If the laser mark ID given to the material wafer and used for product management is used to detect the longitudinal position of the material wafer, the position of the material wafer can be reliably and easily detected.
When batch processing of material wafers in the processing process, if the material wafers are divided into multiple groups according to the position in the longitudinal direction of the single crystal ingot and the processing content is changed for each group, batch processing will be performed efficiently. However, it becomes possible to process each material wafer appropriately.

Moreover, if the material wafer is processed into single wafers in the processing step, each material wafer having different characteristics depending on the position in the longitudinal direction of the single crystal ingot can be processed more appropriately.
When the processing step is an annealing step, the annealing process is performed if the amount of heat applied to the material wafer corresponding to the top side of the single crystal ingot is set larger than the amount of heat applied to the material wafer corresponding to the tail side. Thus, the variation in the quality of the annealed wafer manufactured can be reduced.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[First Embodiment]
1 to 4 illustrate a semiconductor wafer manufacturing method according to the first embodiment of the present invention. FIG. 1 is a flowchart showing the manufacturing method, and FIG. 2 is a block diagram showing a heat treatment furnace used in the manufacturing method. 3 and 4 are diagrams for explaining grouping during batch processing.

  The semiconductor wafer manufacturing method according to the present embodiment is configured as shown in FIG. 1, and includes a slicing step (step S10), a grinding step (step S20), a laser mark processing step (step S30), and a polishing step (step). S40), a crystal position detection step (step S42), a lot configuration step (step S50), a heat treatment (argon annealing treatment, also simply referred to as annealing treatment) step (step S60), an inspection step (step S70), Are carried out in this order and shipped (step S80).

  In the slicing step S10, a single crystal ingot such as silicon is sliced to obtain a material wafer. In this step, wafer IDs are given to the sliced wafers sequentially from the top (top side), for example, according to the crystal position (longitudinal position of the single crystal ingot). The wafer ID is not stamped on the wafer itself, but is used for identification on the processing system.

In the grinding step S20, the front and back surfaces of the material wafer are ground.
In the next laser mark processing step S30, a laser mark ID corresponding to the wafer ID is imprinted on the ground wafer. Therefore, it is possible to specify from which crystal position the wafer is sliced from this laser mark ID.
In the polishing step S40, the surface of the wafer is mirror-polished.

  Then, in the crystal position detection step S42, the crystal position before slicing the wafer is detected from the laser mark ID, and in the lot configuration step S50, the wafers are grouped according to the crystal position for argon annealing. Perform lot configuration. Here, the lot structure is divided into three groups, that is, in a relatively simple manner, a group on the top side of the single crystal ingot, a group on the tail side (bottom side), and an intermediate group located between these groups. For example, the use area of the single crystal ingot is divided into three in the longitudinal direction: top side, middle part, and tail side (may be divided into three equal parts), and the wafer is allocated to one of these groups according to the crystal position. Thus, a predetermined number in the same group is configured as one lot.

In the heat treatment step S60, a heat treatment (argon annealing treatment) is performed on each lot configured in this manner by a batch processing method to manufacture an annealed wafer.
In this heat treatment step S60, a heat treatment furnace is used. For example, as shown in FIG. 2, the heat treatment furnace 1 includes a furnace body 1A at the top and a transfer chamber 1B at the bottom. Is equipped with a heat insulating table 3 via an elevator 2, and a boat (heat treatment jig) 4 on which a large number of wafers 10 are transferred is placed on the heat insulating table 3. In the furnace main body 1 </ b> A, a core tube 5 is disposed at the center, and a heater 6 is disposed around the core tube 5.

  At the time of heat treatment, a predetermined number (for example, 125) of wafers 10 are transferred to the boat 4 and the elevator 2 is raised, so that the heat insulating table 3 and the boat 4 mounted thereon are arranged in the core tube 5. Then, the heater 6 is operated and heated to perform heat treatment. When the heat treatment is completed, the elevator 2 is lowered, the boat 4 is taken out from the furnace core tube 5, and the wafers 10 are collected from the boat 4.

In this heat treatment step, the heat treatment conditions are changed in units of crystal positions in each lot. That is, the amount of heat applied to the wafer increases as the crystal position of the wafer increases toward the top.
In other words, in the heat treatment process, the wafer is heated at a high temperature to reduce the LSTD density (COP density, also referred to as the LSTD value). It is effective to increase the amount of heat applied to the wafer as the LSTD density increases. is there. Thereby, the BMD density and the DZ width can be made uniform over the entire length of the single crystal ingot in the longitudinal direction.

The trend of LSTD density, BMD density, and DZ width when a single crystal ingot is divided into three parts, the top side (Top part), the middle part (Middle part), and the tail side (Tail part) in the longitudinal direction, is shown below. Table 1 shows.
As shown in Table 1, the LSTD density tends to be higher on the top side and lower on the tail side, and the DZ width tends to be larger on the top side and smaller on the tail side. Conversely, the BMD density is lower on the top side and lower on the tail side. There is a high tendency.

  Therefore, it is effective to perform processing so that the amount of heat applied to the material wafer corresponding to the top side is larger than the amount of heat applied to the material wafer corresponding to the tail side.

  To increase the amount of heat, if the top side, middle part, and tail side are heat-treated at the same temperature, the top side has a longer heat treatment time, the tail side has a shorter heat treatment time, and the middle part has a heat treatment time. Is processed to an intermediate length between them. Alternatively, if heat treatment is performed on the top side, the middle part, and the tail side in the same treatment time, the heat treatment temperature is increased on the top side, the heat treatment temperature is lowered on the tail side, and the heat treatment temperature is intermediate between these. The processing is performed at a high height (see Table 1 above). Of course, the top side has a long heat treatment time and a high heat treatment temperature, the tail side has a short heat treatment time and a low heat treatment temperature, and the intermediate portion has both the heat treatment time and the heat treatment temperature. An intermediate process may be performed.

Specifically, it becomes possible to make all the quality equal regardless of the crystal position by processing according to each part as follows.
(A) If the time is constant-Top site: 1250 ° C x 1 hour-Middle site: 1225 ° C x 1 hour-Tail site: 1200 ° C x 1 hour (b) If the temperature is constant-Top site: 1200 ° C x 2 hours-Middle Site: 1200 ° C. × 1.5 hours Tail site: 1200 ° C. × 1 hour Then, the annealed wafer thus manufactured is shipped after passing through the inspection step S70.

  Since the semiconductor wafer manufacturing method according to the first embodiment of the present invention is configured as described above, when manufacturing an annealed wafer that is a semiconductor wafer for manufacturing semiconductor devices, the material wafer (up to the polishing step S40). The crystal position (longitudinal position in the single crystal ingot) of the processed wafer) is detected from the laser mark ID (crystal position detection step S42), and the wafers are grouped according to the crystal position (here, the top 3) (side, middle, tail)), and heat treatment (argon annealing) by changing the heat treatment conditions so that the amount of heat applied to the wafer is larger in the top group than in the tail group. , Manufacture annealed wafers.

Therefore, while processing efficiently by batch processing, wafers with different characteristics according to the crystal position are heat-treated according to the characteristics, so that many annealed wafers that are products have uniform characteristics with little variation in quality. Can be a wafer.
In particular, since the laser mark ID given to the material wafer and used for product management is used to detect the longitudinal position of the material wafer, the position of the material wafer can be detected reliably and easily. it can.

  In this embodiment, the material wafers are grouped into three groups, ie, the top side, the intermediate part, and the tail side, and heat treatment is performed by batch processing. It can be done. However, when the distribution of the LSTD density of FIG. 3 measured based on the sample of FIG. 6 is seen, the case where it is divided into three groups [FIG. 3A] and the case where it is divided into 15 groups [FIG. (B)] and the difference in characteristics is small, and the range of the LSTD density in FIG. 4 created based on FIG. 3 is also divided into three groups [FIG. 4 (a)], When the small group is divided into 15 groups, the difference in the characteristic range is small compared to that in FIG. 4B. Therefore, it is considered that appropriate processing according to each material wafer can be performed even in rough grouping such as three groups.

  In this embodiment, after the laser mark processing step (step S30), the polishing step (step S40), the crystal position detection step (step S42), the lot configuration step (step S50), and the heat treatment step (step S60) are performed in this order. After the laser mark processing step (step S30), the crystal position detection step (step S42), the lot configuration step (step S50), the heat treatment step (step S60), and the polishing step (step S40) are performed in this order. You may process with.

[Second Embodiment]
FIG. 5 is a flowchart showing a semiconductor wafer manufacturing method according to the second embodiment of the present invention.
The semiconductor wafer manufacturing method according to the present embodiment employs a single wafer processing method in which each wafer is individually processed instead of batch processing. As shown in FIG. ), Grinding step (step S20), laser mark processing step (step S30), polishing step (step S40), crystal position detection step (step S42), and heat treatment (argon annealing treatment, single wafer processing method). The process (also referred to simply as annealing) (step S62) and the inspection process (step S70) are performed in this order, and are shipped (step S80). That is, in this embodiment in which each wafer is individually processed, the lot configuration process S50 of the first embodiment is omitted.

  Since the semiconductor wafer manufacturing method according to the second embodiment of the present invention is configured as described above, when manufacturing an annealed wafer, which is a semiconductor wafer for manufacturing semiconductor devices, the material wafer (until the polishing step S40). The crystal position (longitudinal position in the single crystal ingot) of the processed wafer) is detected from the laser mark ID (crystal position detection step S42), and each wafer is changed to the optimum heat treatment condition according to the crystal position, An annealing wafer is manufactured by performing a heat treatment (argon annealing process) by a single wafer processing method.

Therefore, by heat-treating wafers having different characteristics according to crystal positions according to the characteristics, a large number of annealed wafers as products can be made into wafers with more uniform characteristics with less quality variation.
Also in this embodiment, since the laser mark ID given to the material wafer and used for product management is used to detect the longitudinal position of the material wafer, the position of the material wafer is surely and easily detected. Can be detected.

  In this embodiment, the laser mark processing step (step S30) is followed by the polishing step (step S40), the crystal position detection step (step S42), and the heat treatment step (step S62). After the mark processing step (step S30), the crystal position detection step (step S42), the heat treatment step (step S62), and the polishing step (step S40) may be processed in this order.

[Others]
As mentioned above, although embodiment of this invention was described, this invention is not limited to the said embodiment, A various deformation | transformation is possible in the range which does not deviate from the meaning of this invention.

For example, in the lot configuration in the first embodiment, the simplest is that the crystal position may be divided into only two of the top side and the tail side, and may be divided into any number.
In each of the above embodiments, the manufacture of the annealed wafer has been described as an example. However, the processing according to the crystal position of the material wafer of the present invention is performed after the manufacture of the epitaxial wafer, the annealing process, the epitaxial layer forming process, and the like. You may apply to the process (grinding, etching, polishing, etc.) of the semiconductor wafer which does not process.

It is a flowchart which shows the manufacturing method of the semiconductor wafer as 1st Embodiment of this invention. It is a block diagram which shows the heat processing furnace used for the manufacturing method of the semiconductor wafer as 1st Embodiment of this invention. It is a graph which shows distribution of the LSTD density for each group at the time of grouping at the time of batch processing by the manufacturing method of a semiconductor wafer as a 1st embodiment of the present invention, and (a) shows the case where it is divided into large groups, (B) shows the case of dividing into small groups. It is a graph which shows the range of the LSTD density for each group at the time of grouping at the time of batch processing by the manufacturing method of a semiconductor wafer as a 1st embodiment of the present invention, and (a) shows the case where it is divided into large groups, (B) shows the case of dividing into small groups. It is a flowchart which shows the manufacturing method of the semiconductor wafer as 2nd Embodiment of this invention. It is a graph explaining the subject of this invention, and is a figure which shows the example of the LSTD density according to the longitudinal direction position (crystal position) of a single crystal ingot.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Heat treatment furnace 1A Furnace main body 1B Transfer chamber 2 Elevator 3 Heat insulation table 4 Boat (heat treatment jig)
5 Core tube 6 Heater 10 Wafer

Claims (8)

A method of manufacturing a semiconductor wafer for manufacturing semiconductor devices from a material wafer obtained by slicing a single crystal ingot,
A detection step of detecting a longitudinal position of the single wafer in the single crystal ingot;
A semiconductor wafer characterized by comprising at least one processing step at the time of manufacturing, and processing the raw wafer with a processing content corresponding to the longitudinal position detected by the detection step. Production method. The said detection process detects the longitudinal direction position in the said single-crystal ingot of the raw material wafer using laser mark ID provided to the said raw material wafer and can be used for product management of Claim 1 characterized by the above-mentioned. Semiconductor wafer manufacturing method. The semiconductor wafer manufacturing method according to claim 1, wherein in the processing step, the material wafer is batch-processed. 4. The process according to claim 1, wherein in the processing step, the material wafer is divided into a plurality of groups according to the longitudinal position in the single crystal ingot, and the processing content is changed in units of each group. 2. A method for producing a semiconductor wafer according to item 1. The method for manufacturing a semiconductor wafer according to claim 1, wherein in the processing step, the material wafer is subjected to single wafer processing. The processing step is an annealing treatment step of annealing the material wafer using a wafer whose surface has been flattened with high precision through a grinding step and a polishing step as a material wafer. 6. The method for producing a semiconductor wafer according to any one of 5 above. The processing step is a polishing step in which a wafer subjected to a grinding step is used as a material wafer, and the surface of the material wafer is flattened with high accuracy after annealing. 2. A method for producing a semiconductor wafer according to item 1. In the annealing step, the amount of heat applied to the material wafer corresponding to the top side of the single crystal ingot is made larger than the amount of heat applied to the material wafer corresponding to the tail side of the single crystal ingot, The manufacturing method of the semiconductor wafer of Claim 6 or 7.

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