JP2010034101A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve heat dissipation performance, reliability and reduction in manufacturing cost in a semiconductor device. <P>SOLUTION: In a BGA (ball grid array) 8 in which an SOC (system on chip) 1 is mounted on a wiring board 3, the SOC 1 includes an operation circuit 1g having at least one part of a region on the center portion of the SOC 1, a second pad 1i is provided on the operation circuit 1g of the main surface of the SOC 1, and the second pad 1i is directly connected to a bonding lead 3c of the wiring board 3 by a second wire 4b. With this configuration, the heat generated from the operation circuit 1g is dissipated to the wiring board 3 through the second wire 4b, and the heat dissipation performance of the BGA 8 is improved. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device on which a system-on-chip is mounted.

In a BGA type semiconductor device, a package substrate having a plurality of lands, a through hole formed on each of the plurality of lands by laser processing, and a plating film disposed in the through hole, and a semiconductor mounted on the package substrate There is a configuration including a chip, a conductive wire that connects the semiconductor chip and the package substrate, and a plurality of solder bumps provided on the land of the package substrate (see, for example, Patent Document 1).
JP 2006-190771 A

  In recent years, with the enhancement of functions of semiconductor devices, the main surface (circuit formation surface) of a semiconductor chip (hereinafter also simply referred to as a chip) is not limited to a circuit element that performs arithmetic processing such as a CPU (Central Processing Unit). In addition, various types of circuits such as analog, digital, or macro circuit elements are provided as input / output circuits for inputting signals from external devices (or for outputting signals to external devices). Yes. Among these, the input / output circuit frequently inputs and outputs signals to / from an external device, so that noise resistance and high transmission speed are required.

  In consideration of such problems, an input / output circuit is arranged in the vicinity of a pad (electrode) for inputting and outputting signals.

  However, for example, as in Patent Document 1 (FIG. 1), pads for supplying signals and power from the outside to the circuit are formed at the peripheral edge along each side of the chip. For this reason, in consideration of the above problems, it is preferable that the input / output circuit is also arranged at the peripheral portion of the chip. As a result, most arithmetic circuits that perform arithmetic processing on signals input to these input / output circuits are often provided on the center side of the chip, which is an empty area.

  Here, since the arithmetic circuit performs arithmetic processing on each input / output circuit as described above, the power consumption is higher than that of the input / output circuit. As a result, the heat generation amount is also higher than that of the input / output circuit. When the amount of heat generation increases, the operation of the input / output circuit becomes unstable due to the influence of this heat, so that there is a problem that the reliability of the semiconductor device is lowered.

  Therefore, it is conceivable that the arithmetic circuit is also arranged in the vicinity of the pad and radiates heat through a wire which is a conductive member connected to the pad.

  However, as described above, since a plurality of input / output circuits are preferentially arranged in the peripheral portion, it is difficult to arrange the entire arithmetic circuit close to the vicinity of the pad. In other words, it is difficult to take measures against IR drop and heat generation in a part of the arithmetic circuit located at the center of the chip. That is, how to dissipate a part of the arithmetic circuit arranged at the center of the chip is a problem.

  Also, mounting is performed by a so-called flip chip connection method in which the main surface (circuit forming surface) of the semiconductor chip is mounted facing the upper surface of the wiring board, and the heat radiation is improved by exposing the back surface of the semiconductor chip. Can be considered.

  However, in the flip chip connection method, it is necessary to form the pitch of the electrodes of the substrate in accordance with the pitch of the pads of the semiconductor chip, and it is necessary to apply a technique for forming the electrodes at a narrow pitch. Also, in order to improve the bondability between the bump electrode and the substrate electrode, it is necessary to form a plating layer or a solder material on the substrate electrode, or to fill an underfill resin between the substrate and the semiconductor chip. . For these reasons, the flip chip connection method has a higher technical fee than the wire bonding method, and there is a problem that the cost of the manufactured semiconductor device also increases.

  Furthermore, as one of the techniques for improving the heat dissipation of the semiconductor device, the mounting of a heat sink is generally raised. However, since the cost of the heat sink is high, an increase in the cost of the semiconductor device becomes a problem.

  The objective of this invention is providing the technique which can aim at the improvement of the heat dissipation in a semiconductor device.

  Another object of the present invention is to provide a technique capable of improving the reliability of a semiconductor device.

  Furthermore, another object of the present invention is to provide a technique capable of reducing the manufacturing cost of a semiconductor device.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in this application, the outline of typical ones will be briefly described as follows.

  That is, the present invention provides a wiring substrate having an upper surface on which a plurality of bonding leads are formed and a lower surface on which a plurality of lands are formed, and a plurality of circuit elements and a plurality of circuit elements via the wirings. And a semiconductor chip mounted on a region inside the plurality of bonding leads on the upper surface of the wiring board. A plurality of wires for electrically connecting the plurality of pads of the semiconductor chip and the plurality of bonding leads of the wiring substrate; a sealing body for sealing the semiconductor chip and the plurality of wires; And an external terminal connected to each of the plurality of lands of the wiring board. Further, the plurality of circuit elements are formed closer to a central portion side of the main surface of the semiconductor chip than the plurality of pads, and the plurality of circuit elements include an input / output circuit that inputs / outputs signals to / from an external device; And an arithmetic circuit for arithmetically processing a signal input from the external device to the input / output circuit. Furthermore, the frequency of the arithmetic circuit is higher than the frequency of the input / output circuit, and the arithmetic circuit has more regions arranged on the central portion side of the main surface than the input / output circuit, and the plurality of pads Is a first pad formed along each side of the semiconductor chip having a rectangular planar shape, and a second pad located closer to the central portion of the main surface of the semiconductor chip than the first pad. It has. Further, the plurality of wires include a first wire that is electrically connected to the first pad and a second wire that is electrically connected to the second pad.

  Of the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  In a semiconductor device mounted with a semiconductor chip having an arithmetic circuit that is a heating element, at least a part of which is disposed on the central portion side of the semiconductor chip, a pad corresponding to the arithmetic circuit is provided on the main surface of the semiconductor chip, and this pad By directly connecting the bonding lead of the wiring board to the wiring board, the heat generated from the arithmetic circuit can be released to the wiring board through the wire, thereby improving the heat dissipation in the semiconductor device. .

  In addition, since heat dissipation can be improved in the semiconductor device, the input / output circuit can be prevented from becoming unstable due to heat, and as a result, reliability of the semiconductor device can be improved.

  In addition, since the connection between the semiconductor chip and the wiring board is not a flip chip connection but a wire, the manufacturing cost of the semiconductor device can be reduced as compared with the flip chip connection. Furthermore, since heat dissipation is improved via a wire without mounting a heat sink, an increase in the manufacturing cost of the semiconductor device can be suppressed, and the manufacturing cost of the semiconductor device can be reduced.

  In the following embodiments, the description of the same or similar parts will not be repeated in principle unless particularly necessary.

  Further, in the following embodiment, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments, but they are not irrelevant to each other unless otherwise specified. The other part or all of the modifications, details, supplementary explanations, and the like are related.

  Also, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), particularly when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and it may be more or less than the specific number.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof will be omitted.

(Embodiment)
FIG. 1 is a plan view showing an example of the structure of a semiconductor device according to an embodiment of the present invention through a sealing body, and FIG. 2 is a cross-sectional view showing the structure cut along the line AA in FIG. 3 is a rear view showing an example of the arrangement of external terminals of the semiconductor device shown in FIG. 1, and FIG. 4 is a perspective view showing a part of the internal structure of the semiconductor device shown in FIG. 5 is a circuit block diagram showing an example of the circuit configuration of the semiconductor device shown in FIG. 1, FIG. 6 is a circuit layout diagram showing an example of the circuit layout of the semiconductor device shown in FIG. 1, and FIG. 7 is the semiconductor shown in FIG. It is sectional drawing which shows an example of the mounting structure of an apparatus.

  The semiconductor device of the present embodiment shown in FIGS. 1 to 4 is a resin-encapsulated semiconductor package in which a semiconductor chip is mounted on the upper surface 3a of the wiring board 3. In the present embodiment, as an example, A description will be given by taking up a BGA (Ball Grid Array) 8 in which a plurality of solder balls 5 which are external terminals of the semiconductor device are provided on the lower surface 3 b of the wiring board 3.

  The BGA 8 includes a wiring board 3 having an upper surface 3a on which a plurality of bonding leads (electrodes) 3c are formed and a lower surface 3b on the opposite side of the upper surface 3a and on which a plurality of lands (electrodes) 3d are formed. It has been incorporated. Further, a main surface (circuit formation surface) on which a plurality of pads (electrodes) 1c electrically connected to the plurality of circuit elements via a plurality of circuit elements and a plurality of wirings (bus wiring, internal wiring) are formed. 1a and a back surface 1b located on the opposite side of the main surface 1a, and a semiconductor chip mounted on the inner surface of the plurality of bonding leads 3c on the upper surface 3a of the wiring board 3. Yes.

  The semiconductor chip mounted on the BGA 8 is, for example, an SOC (system on chip) 1 in which various circuit elements are formed, and is made of silicon.

  Further, as shown in FIG. 2, the BGA 8 includes a plurality of wires (conductive members, Au wires, clips) 4 that electrically connect a plurality of pads 1c of the SOC 1 and a plurality of bonding leads 3c of the wiring board 3, respectively. And a sealing body 6 for sealing the SOC 1 and the plurality of wires 4, and solder balls 5 (ball electrodes, solder materials) which are external terminals respectively connected to the plurality of lands 3 d of the wiring board 3. Yes.

  As shown in FIG. 3, the plurality of solder balls 5 are provided in a grid pattern on the lower surface 3 b side of the wiring board 3.

  Further, as shown in FIG. 2, the wiring board 3 includes a core material 3h, a plurality of bonding leads 3c and substrate wiring 3e provided on the upper surface side, and a plurality of lands 3d and substrate wiring provided on the lower surface side. 3e, a through-hole wiring 3f that electrically connects the upper and lower substrate wirings 3e, and a solder resist 3g that is an insulating film that covers the upper and lower substrate wirings 3e. That is, the plurality of bonding leads 3c formed on the upper surface 3a are electrically connected to the plurality of lands 3d via the plurality of substrate wirings 3e formed on the wiring substrate 3, respectively, and further the plurality of substrate wirings 3e. Is formed below the back surface 1b of the SOC1 (a region overlapping the SOC1 in a plan view). Each wiring in the wiring board 3 is made of, for example, a copper alloy, and the core material 3h and the solder resist 3g are made of, for example, an insulating resin material.

  The SOC 1 is bonded to the upper surface 3 a of the wiring substrate 3 by a die bond material (adhesive) 2. The die bond material 2 is, for example, a conductive paste material containing silver filler or the like, or a conductive film.

  Further, the plurality of pads 1c of the SOC1 are formed such that a first pad 1h formed along each side of the main surface 1a of the SOC1 having a rectangular planar shape, and a center on the main surface 1a of the SOC1 than the first pad 1h. And a second pad (electrode, arithmetic circuit pad, heat dissipation pad) 1i located on the part side. In the present embodiment, for example, the planar shape is a quadrangle.

  Further, in the BGA 8, the plurality of wires 4 have a first wire 4a electrically connected to the first pad 1h and a second wire 4b electrically connected to the second pad 1i.

  In the BGA 8, as shown in FIG. 6, in the SOC1, the plurality of circuit elements are formed on the central portion side on the main surface 1a side of the SOC 1 rather than the plurality of pads 1c. That is, the plurality of circuit elements are formed in the circuit formation region 1s in the region inside the array of the plurality of first pads 1h formed on the peripheral portion on the main surface 1a side. The plurality of circuit elements are formed closer to the main surface 1a than the back surface 1b of the SOC1.

  Further, in the SOC 1, a plurality of circuit elements perform an operation for processing an input / output circuit 1 f for inputting / outputting a signal to / from the external device 7 (see FIG. 5) and a signal input from the external device 7 to the input / output circuit 1 f. The input / output circuit 1f is also called a peripheral circuit or the like, and is an analog circuit 1p, a digital circuit 1q, another circuit 1r, or the like. The analog circuit 1p is, for example, analog / digital conversion, USB (Universal Serial Bus), and the like, and the digital circuit 1q is, for example, SCIF (serial communication interface). Further, the other circuit 1r is, for example, a timer.

  On the other hand, the arithmetic circuit 1g is, for example, a CPU or a graphic controller.

  The BGA 8 according to the present embodiment inevitably includes the SOC 1 having at least a part of the region disposed on the central portion side of the SOC 1 and having the arithmetic circuit 1g having a large calorific value on the main surface 1a side. A second pad 1i different from the plurality of first pads 1h provided on the peripheral edge of the main surface 1a is provided on 1g, and the second pad 1i and one end of the second wire 4b are connected, and the second wire 4b The other end and the wiring board 3 are connected.

  As a result, the heat generated from the arithmetic circuit 1g on the main surface 1a side of the SOC 1 is transmitted to the solder balls 5 provided on the lower surface 3b side of the wiring board 3 through the conductive second wires 4b and the wiring board 3. I can escape.

  At this time, in the SOC 1, an arithmetic circuit 1g such as a CPU and an input / output circuit 1f having input / output terminals such as an analog circuit 1p and a digital circuit 1q are formed on the main surface 1a side. As shown in FIG. 6, the output circuit 1 f needs to be arranged on the peripheral side of the SOC 1. This is because the first pad 1h is arranged at the peripheral edge of the main surface 1a of the SOC 1 in order to process input / output of signals with the external device at high speed. In addition, among the input / output circuits 1f, for example, the analog circuit 1p is an independent power supply, so that it is desired to be placed as close as possible to the first pad 1h so as not to be affected by noise. Therefore, inevitably at least a partial region or the whole of the arithmetic circuit 1g is arranged inside the array of the first pads 1h, that is, on the central portion side of the main surface 1a.

  Therefore, in the BGA 8, as shown in FIGS. 1 and 2, the second pad 1i different from the plurality of first pads 1h provided on the outer peripheral portion of the main surface 1a on or near the arithmetic circuit 1g in the SOC 1. And by connecting the second wire 4b to the second pad 1i, a path for releasing heat from the immediate vicinity of the arithmetic circuit 1g serving as a heating element is provided.

  7 shows the mounting structure of the BGA 8. When the BGA 8 is mounted on the mother board (mounting substrate) 9, the heat generated from the SOC 1 as shown by the heat dissipation path 10 is transmitted via the second wire 4b. Can be transmitted to the solder balls 5 on the lower surface side of the BGA 8 and further escaped to the mother board 9.

  As described above, in the BGA 8, heat release from the SOC 1 is performed without using a heat sink and using a cheaper wire connection as compared with the flip-chip connection, so that the manufacturing cost of the BGA 8 can be reduced. .

  Next, features of a plurality of circuit elements provided in the SOC 1 included in the BGA 8 of the present embodiment will be specifically described.

  As shown in FIGS. 5 and 6, a plurality of first pads 1h are formed side by side on the peripheral surface of the SOC 1 on the main surface 1a side, and the circuit forming region 1s inside the plurality of first pads 1h is formed. A digital system circuit 1q, an arithmetic circuit 1g, an analog system circuit 1p, and another circuit 1r are formed. Of these, the digital system circuit 1q, the analog system circuit 1p, and the other circuit 1r are also referred to as an input / output circuit 1f. The input / output circuit 1f is a circuit that inputs a signal received from the outside and outputs the signal further processed by the arithmetic circuit 1g to the outside, and includes an input / output terminal. The input / output circuit 1f is also referred to as a peripheral circuit because it is arranged around the CPU (central processing unit).

  Here, the arithmetic circuit 1g is, for example, a CPU or a graphic controller. When each of the analog circuit 1p, the digital circuit 1q, and the other circuit 1r exchanges signals with the outside, the CPU once receives signals received from the outside by the respective circuits, and performs arithmetic processing therein. A signal is returned to each of the circuits.

  The analog circuit 1p is, for example, analog / digital conversion, USB, or the like. Since the analog circuit 1p is an independent power supply, it must be disposed on the outer peripheral side of the main surface 1a of the chip on which the first pad 1h is disposed so as not to be affected by noise.

  The digital system circuit 1q is, for example, SCIF, and the other circuit 1r is, for example, a timer. The digital system circuit 1q and the other circuit 1r are also close to the first pad 1h, that is, It is arranged near the outer periphery of the circuit formation region 1s.

  In the arithmetic circuit 1g and the input / output circuit 1f, the frequency of the arithmetic circuit 1g is, for example, about 400 MHz, while the frequency of the input / output circuit 1f is, for example, about 50 to 100 MHz. Is higher than the frequency of the input / output circuit 1f. Therefore, the power consumption of the arithmetic circuit 1g is higher than the power consumption of the input / output circuit 1f. That is, the power required to operate the arithmetic circuit 1g is larger than the power required to operate the input / output circuit 1f.

  In addition, the arithmetic circuit 1g performs arithmetic processing on a signal input to each of a plurality of input / output circuits 1f (peripheral circuits) provided around the arithmetic circuit 1g, compared with the plurality of input / output circuits 1f. Requires a lot of power.

  As described above, the arithmetic circuit 1g is much larger in heat generation than the input / output circuit 1f, and requires a heat dissipation measure.

  However, since the input / output circuit 1f is a peripheral circuit provided with input / output terminals, there are more regions (parts, areas) arranged near the plurality of first pads 1h in the peripheral portion than the arithmetic circuit 1g. . In other words, the arithmetic circuit 1g has more regions (parts, areas) arranged on the center side in the main surface 1a than the input / output circuit 1f.

  In other words, in the BGA 8 of the present embodiment, the SOC 1 is in a state where the whole or a part of the arithmetic circuit 1g requiring a heat dissipation measure is arranged on the center side.

  Therefore, in the BGA 8, a second pad 1i is provided on the central side of the peripheral portion of the main surface 1a of the SOC 1 from the first pad 1h, and a second wire 4b made of Au wire is connected to the second pad 1i. By connecting the second wire 4b to the bonding lead 3c of the wiring board 3, the solder on the lower surface 3b of the BGA 8 from the arithmetic circuit 1g having a high calorific value provided on the center side through the second wire 4b and the board wiring 3e. Heat can be released to the ball 5.

  At that time, the resistance component of the second wire 4b (Au wire) is smaller than the resistance component of the bus wiring (aluminum wiring) 1e formed on the main surface 1a of the SOC1. Therefore, the heat dissipation effect can be enhanced by connecting the arithmetic circuit 1g and the wiring board 3 via the second wire 4b made of Au.

  In addition, as shown in FIG. 6, the arithmetic circuit 1g in the SOC 1 has a first area 1j located on the first pad 1h side, a larger area than the first area 1j, and a position on the center side of the main surface 1a. And a second region 1k. Further, the distance between the second region 1k of the arithmetic circuit 1g and the second pad 1i is shorter than the distance between the second region 1k of the arithmetic circuit 1g and the first pad 1h.

  In that case, it is preferable that the 2nd pad 1i is formed on the arithmetic circuit 1g, and it is more preferable that it is provided on the 2nd area | region 1k of the center part side of the arithmetic circuit 1g.

  That is, by providing the second pad 1i as close to the arithmetic circuit 1g as possible, it is possible to obtain a higher heat dissipation effect, and preferably by providing the second pad 1i on the second region 1k on the central side of the arithmetic circuit 1g. A high heat dissipation effect can be obtained.

  As shown in FIG. 6, in the SOC 1, the plurality of first pads 1 h provided on the peripheral portion of the main surface 1 a are a power supply potential pad 1 d for supplying a power supply potential and a reference potential pad for supplying a reference potential. 1m and a signal pad 1n for transmitting a signal.

  Further, the plurality of first pads 1h are provided on the peripheral portion of the main surface 1a, and the input / output circuit 1f is arranged substantially along the outer periphery of the circuit formation region 1s inside the array of the plurality of first pads 1h. Therefore, the plurality of first pads 1h are formed adjacent to the input / output circuit 1f.

  Further, the signal pad 1n of the first pads 1h is electrically connected only to the input / output circuit 1f as shown in FIG. Furthermore, signals input / output between the input / output circuit 1f and the external device 7 are transmitted via the first wire 4a and the first pad 1h.

  The arithmetic circuit 1g is electrically connected to the input / output circuit 1f via the bus wiring 1e (internal wiring).

  The second pad 1i provided on or near the arithmetic circuit 1g is electrically connected to the arithmetic circuit 1g as shown in FIG. Further, as shown in FIG. 6, the second pad 1i is connected to a power supply potential pad 1d to which a power supply potential is supplied via a bus wiring 1e. Here, the power supply potential pad 1d may be an electrode to which a reference potential is supplied. In this case, the reference potential pad 1m is an electrode to which a power supply potential is supplied. Thus, the power supply potential or the reference potential is supplied to the arithmetic circuit 1g through the second wire 4b and the second pad 1i.

  The second pad 1i is not electrically connected to the signal pad 1n of the first pad 1h.

  Therefore, in other words, in the BGA 8 of the present embodiment, the plurality of first pads 1h provided on the peripheral portion of the main surface 1a of the SOC 1 are input / output circuit pads and are provided on the arithmetic circuit 1g. The obtained second pad 1i can be said to be an arithmetic circuit pad.

  Next, IR drop countermeasures in the BGA 8 of the present embodiment will be described.

  Since the arithmetic circuit 1g performs arithmetic processing on signals input to the input / output circuits (analog circuit 1p, digital circuit 1q, and other circuits 1r), the power consumption (driving power) is higher than that of the input / output circuit 1f. . Therefore, in the vicinity of the arithmetic circuit 1g (the bus wiring 1e (wiring) for supplying a power supply potential electrically connected to the arithmetic circuit 1g), an IR drop in which the current value (I) and the resistance value (R) decrease. Problems occur.

  Therefore, in the BGA 8 of the present embodiment, the second pad 1i is provided on the arithmetic circuit 1g, and the second pad 1i and the arithmetic circuit 1g are electrically connected in order to further improve the heat dissipation performance. Since the power supply potential is supplied to the arithmetic circuit 1g via the pad 1i, the loss of the power supply potential due to the IR drop can be compensated.

  Next, noise countermeasures for the analog circuit 1p in the BGA 8 of the present embodiment will be described.

  An analog signal is weaker than noise, for example, than a digital signal. Therefore, the analog circuit 1p and the corresponding first pad 1h (electrode) are electrically connected to each other and formed on the main surface 1a of the SOC1. Shorten the distance between the bus wiring 1e or the internal wiring. Therefore, it is preferable to arrange the analog system circuit 1p as close as possible to the first pad 1h (electrode) corresponding to the analog system circuit 1p.

  Therefore, in the BGA 8 according to the present embodiment, a plurality of first pads 1h (signal pads 1n) serving as a transmission path for signals input from the external device 7 (or signals output to the external device 7) are included in each SOC1. Since it is provided along the side, the analog circuit element (analog circuit 1p) as the input / output circuit 1f is also arranged on the peripheral side of the circuit formation region 1s at the center of the main surface 1a of the SOC1. Thus, the distance between the bus wiring 1e or the internal wiring can be shortened.

  Thereby, it can suppress that noise goes on an analog signal.

  Next, measures for heat radiation to the chip back side of the BGA 8 of the present embodiment will be described.

  In the BGA 8, the thermal conductivity of the resin forming the sealing body 6 is smaller than the thermal conductivity of the wiring board 3 having a metal wiring (for example, copper wiring). That is, when considering a path for releasing heat from the SOC1, since the resin is disposed above the SOC1 due to the structure of the BGA 8, the lower surface of the SOC1 (rather than releasing heat toward the upper surface (main surface 1a) of the SOC1) It is more effective to dissipate heat in the direction of the back surface 1b) and transmit the heat to the mother board 9 via the solder balls 5.

  Therefore, as a heat dissipation measure on the back surface 1b side of the SOC 1, a conductive paste material containing, for example, silver filler or the like is adopted as the die bond material 2. As described above, the circuit formation region (arithmetic circuit 1g) 1s, which is also a heat generation source, is formed on the main surface 1a side of the SOC1, but the SOC1 is made of silicon having a higher thermal conductivity than the wiring substrate 3. Therefore, heat is easily transmitted from the circuit element to the back surface 1b side of the SOC1. As a result, a heat dissipation path from the back surface of the chip can be secured, and in addition to releasing heat to the solder ball 5 via the second wire 4b, heat can be released via the die bond material 2, and the SOC1 The heat dissipation can be further enhanced. Further, as shown in FIG. 2, in the wiring substrate 3, a power plane 3 i (or a GND plane) made of a wide area wiring is provided in a region corresponding to the lower portion of the SOC 1. The heat dissipation effect from the back surface 1b side can be further enhanced. Further, since the substrate wiring 3e is also routed under the SOC1, the heat radiation effect from the back surface 1b side of the SOC1 can be further enhanced through the substrate wiring 3e.

  According to the present embodiment, in the BGA 8 equipped with the SOC 1 having the arithmetic circuit 1g which is a heating element at least a part of which is disposed on the center side of the SOC 1, the main surface 1a of the SOC 1 corresponds to the arithmetic circuit 1g. The second pad 1i is provided, and the second pad 1i and the bonding lead 3c of the wiring board 3 are directly and electrically connected by the second wire 4b, so that the heat generated from the arithmetic circuit 1g is second. It can escape to the wiring board 3 and the solder ball 5 provided on the lower surface 3b thereof via the wire 4b.

  In the case of the SOC 1 shown in FIG. 6, the second region 1k of the arithmetic circuit 1g having the first region 1j and the second region 1k is arranged on the center side. Therefore, when heat is released through the first pad 1h formed on the peripheral edge of the SOC1, the width (cross-sectional area) of the wiring path is smaller than that of the wire 4, and the wiring is formed in the first region 1j. Doing so will slow down the heat dissipation rate. However, in this embodiment, since the second pad 1i is provided on the second region 1k of the arithmetic circuit 1g, the second pad 4i and the bonding lead 3c of the wiring board 3 are directly connected to the second wire 4b. Can be connected, and the heat dissipation rate can be improved. At this time, by using Au as the material of the second wire 4b, the resistance component can be reduced as compared with the bus wiring (aluminum wiring) 1e formed on the main surface 1a of the SOC 1, so that the heat dissipation rate is further improved. be able to.

  Eventually, the heat generated from the arithmetic circuit 1g can be released to the bonding lead 3c of the wiring board 3 via the second wire 4b, and further, the wiring is connected via the board wiring 3e, the through-hole wiring 3f and the land 3d. It can escape to the solder balls 5 provided on the lower surface 3 b of the substrate 3. That is, as shown in the heat dissipation path 10 of FIG. 7, heat can be released to the solder balls 5 on the lower surface 3b of the wiring board 3 through the second wires 4b, and further, the motherboard from the leads 9a to which the solder balls 5 are connected. 9 can also release heat.

  As a result, the heat dissipation in the BGA 8 of the present embodiment can be improved.

  In addition, since heat dissipation can be improved in the BGA 8, it is possible to prevent the input / output circuit 1f from becoming unstable due to heat.

  Thereby, the reliability of the BGA 8 can be improved.

  In addition, since the connection between the SOC 1 and the wiring board 3 is not the flip chip connection but the wire 4, the manufacturing cost of the BGA 8 can be reduced as compared with the flip chip connection. Furthermore, in order to improve the heat dissipation of the BGA 8, it is possible to improve the heat dissipation through the wire 4 without attaching a heat sink, and as a result, an increase in the manufacturing cost of the BGA 8 can be suppressed.

  Thereby, the manufacturing cost of BGA8 can be reduced.

  Next, an example of an assembly procedure of the BGA 8 according to the present embodiment will be described with reference to FIGS. 8 is a process flow diagram and a plan view showing an example of the assembly procedure of the semiconductor device shown in FIG. 1, and FIG. 9 is a partial cross-sectional view showing an example of the structure of the wiring board used for assembling the semiconductor device shown in FIG. 10 is a partial sectional view showing an example of the structure after die bonding in the assembly of the semiconductor device shown in FIG. 1, and FIG. 11 is a partial sectional view showing an example of the structure after wire bonding in the assembly of the semiconductor device shown in FIG. . 12 is a partial cross-sectional view showing an example of the structure after resin molding in the assembly of the semiconductor device shown in FIG. 1, and FIG. 13 is a part showing an example of the structure after solder ball attachment in the assembly of the semiconductor device shown in FIG. 14 is a partial cross-sectional view showing an example of a structure after cutting an individual piece in the assembly of the semiconductor device shown in FIG.

  First, substrate preparation shown in step S1 of FIG. 8 is performed. Here, multiple wiring boards 3 capable of assembling a plurality of semiconductor devices are prepared. The wiring board 3 used in the present embodiment is a two-layer wiring board as shown in FIG. 9, and the structure thereof includes a core material 3h, a plurality of bonding leads 3c and a board wiring 3e provided on the upper surface side thereof. The plurality of lands 3d and the substrate wiring 3e provided on the lower surface side, the through-hole wiring 3f for electrically connecting the upper and lower substrate wirings 3e, and the solder resist which is an insulating film covering the upper and lower substrate wirings 3e 3g. Further, a wide area power plane 3i (or GND plane) is provided in the SOC1 mounting region of the wiring board 3.

  Thereafter, die bonding shown in step S2 of FIG. 8 is performed. Here, as shown in FIG. 10, the SOC 1 that is a semiconductor chip is mounted on the upper surface 3 a of the wiring substrate 3 through the die bonding material 2. At this time, the back surface 1b of the SOC 1 and the upper surface 3a of the wiring board 3 are bonded via the die bonding material 2 by face-up mounting with the main surface 1a of the SOC 1 facing upward. The die bond material 2 is a conductive paste material containing, for example, silver filler.

  Thereafter, wire bonding shown in step S3 of FIG. 8 is performed. Here, as shown in FIG. 11, the first pad 1h provided on the peripheral portion of the main surface 1a of the SOC 1 and the bonding lead 3c of the wiring board 3 corresponding thereto are electrically connected by the first wire 4a. . Further, the second pad 1i provided on the arithmetic circuit 1g on the central portion side of the main surface 1a of the SOC 1 and the bonding lead 3c of the wiring board 3 corresponding thereto are electrically connected by the second wire 4b.

  Thereafter, resin molding shown in step S4 of FIG. 8 is performed. Here, as shown in FIG. 12, the SOC 1 and the plurality of wires 4 are resin-sealed. That is, a sealing body 6 made of a sealing resin is formed on the upper surface 3 a of the wiring substrate 3, and the SOC 1 and the plurality of wires 4 are resin-sealed by the sealing body 6.

  Then, solder ball attachment shown in Step S5 of FIG. 8 is performed. That is, as shown in FIG. 13, a plurality of solder balls 5 serving as external terminals of the BGA 8 are joined to the lower surface 3 b of the wiring board 3. At that time, as shown in FIG. 3, the solder balls 5 are arranged in a grid pattern.

  Thereafter, the marking shown in step S6 of FIG. 8 is performed. Here, a desired mark 11 is formed on the surface of the sealing body 6 formed by resin molding, for example, with a laser or the like.

  Thereafter, individual piece cutting shown in step S7 in FIG. 8 is performed. Here, as shown in FIG. 14, individual BGAs 8 are obtained by cutting individual pieces by dicing.

  Thereby, the assembly of the BGA 8 of the present embodiment shown in FIG. 1 is completed.

  Next, a semiconductor device according to a modification of the present embodiment will be described.

  15 is a plan view showing the structure of a semiconductor device according to a modification of the embodiment of the present invention through a sealing body, and FIG. 16 is a cross-sectional view showing the structure cut along the line AA in FIG. is there.

  The semiconductor device (BGA 12) of the modification shown in FIG. 15 has a plurality of pads (here, two) provided on the arithmetic circuit 1g. That is, the BGA 8 shown in FIG. 1 has only one second pad 1i provided on the arithmetic circuit 1g, whereas the modified BGA 12 has two second pads 1i provided on the arithmetic circuit 1g. It has been. As described above, the number of the second pads 1 i provided on the arithmetic circuit 1 g may be plural, and the second wires 4 b are connected to the respective second pads 1 i, and these second wires 4 b are connected to the wiring board 3. By connecting to the bonding lead 3c, the number of the heat dissipation paths 10 shown in FIG. 7 is increased, so that the heat dissipation effect of the BGA 12 can be further improved.

  When the number of second pads 1i for the arithmetic circuit increases, it is necessary to increase the number of bonding leads 3c of the wiring board 3 connected to these second pads 1i. For example, in the example shown in FIG. 15, the second bonding lead 3j is further provided in an outer row different from the arrangement row of the signal bonding leads 3c on the wiring board 3, and the first wire for signals as shown in FIG. This can be realized by changing the loop height of the second wire 4b so as to exceed 4a and connecting to the second bonding lead 3j arranged outside the row of bonding leads 3c.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiments of the invention. However, the present invention is not limited to the embodiments of the invention, and various modifications can be made without departing from the scope of the invention. It goes without saying that it is possible.

  For example, in the above-described embodiment, the case where the connection of the pad of the semiconductor chip (SOC1) and the bonding lead of the wiring substrate is performed using a wire such as an Au wire, but the conductive such as a wide lead called clip bonding other than the wire is described. Connection by a sex member may be employed. In the above embodiment, the semiconductor device includes the analog circuit 1p, the digital circuit 1q, and the other circuit 1r as the input / output circuit 1f. However, the number of the input / output circuits 1f is as follows. The number is not limited to three, and may be one or two or more.

  In the semiconductor device of the embodiment, the case where the arithmetic circuit 1g and the second pad 1i on the arithmetic circuit 1g are electrically connected has been described. However, the arithmetic circuit 1g and the second pad 1i are not necessarily connected. It may not be electrically connected. For example, an insulating layer may be interposed between the arithmetic circuit 1g and the second pad 1i. That is, an insulating layer may be interposed between the arithmetic circuit 1g and the second pad 1i as long as it is an insulating layer capable of conducting heat.

  The present invention is suitable for an electronic device in which a semiconductor chip is mounted on a substrate.

It is a top view which permeate | transmits and shows an example of the structure of the semiconductor device of embodiment of this invention through a sealing body. It is sectional drawing which shows the structure cut | disconnected along the AA line of FIG. FIG. 2 is a back view showing an example of an array of external terminals of the semiconductor device shown in FIG. 1. FIG. 2 is a perspective view showing a partially broken internal structure of the semiconductor device shown in FIG. 1. FIG. 2 is a circuit block diagram illustrating an example of a circuit configuration of the semiconductor device illustrated in FIG. 1. FIG. 2 is a circuit layout diagram illustrating an example of a circuit layout of the semiconductor device illustrated in FIG. 1. It is sectional drawing which shows an example of the mounting structure of the semiconductor device shown in FIG. FIG. 4 is a process flow diagram and a plan view illustrating an example of an assembly procedure of the semiconductor device illustrated in FIG. It is a fragmentary sectional view which shows an example of the structure of the wiring board used for the assembly of the semiconductor device shown in FIG. It is a fragmentary sectional view showing an example of the structure after die bonding in the assembly of the semiconductor device shown in FIG. It is a fragmentary sectional view showing an example of the structure after wire bonding in the assembly of the semiconductor device shown in FIG. It is a fragmentary sectional view which shows an example of the structure after the resin molding in the assembly of the semiconductor device shown in FIG. FIG. 2 is a partial cross-sectional view showing an example of a structure after solder ball attachment in the assembly of the semiconductor device shown in FIG. 1. It is a fragmentary sectional view which shows an example of the structure after the piece cutting | disconnection in the assembly of the semiconductor device shown in FIG. It is a top view which permeate | transmits a sealing body and shows the structure of the semiconductor device of the modification of embodiment of this invention. It is sectional drawing which shows the structure cut | disconnected along the AA of FIG.

Explanation of symbols

1 SOC (semiconductor chip)
1a Main surface 1b Back surface 1c Pad 1d Power supply potential pad 1e Bus wiring (wiring)
1f I / O circuit 1g Arithmetic circuit 1h 1st pad 1i 2nd pad 1j 1st area 1k 2nd area 1m Reference potential pad 1n Signal pad 1p Analog system circuit 1q Digital system circuit 1r Other circuit 1s Circuit formation area 2 Die bond Material 3 Wiring board 3a Upper surface 3b Lower surface 3c Bonding lead 3d Land 3e Substrate wiring 3f Through-hole wiring 3g Solder resist 3h Core material 3i Power plane 3j Second bonding lead 4 Wire 4a First wire 4b Second wire 5 Solder ball (External terminal) )
6 Sealing body 7 External device 8 BGA (semiconductor device)
9 Motherboard 9a Lead 10 Heat dissipation path 11 Mark 12 BGA (Semiconductor device)

Claims (15)

A wiring board having an upper surface on which a plurality of bonding leads are formed, and a lower surface located on the side opposite to the upper surface, on which a plurality of lands are formed;
A main surface on which a plurality of pads electrically connected to the plurality of circuit elements via a plurality of circuit elements and a plurality of wirings are formed, and a back surface located on the opposite side of the main surface; On the upper surface of the wiring board, a semiconductor chip mounted in an inner region of the plurality of bonding leads,
A plurality of wires that electrically connect the plurality of pads of the semiconductor chip and the plurality of bonding leads of the wiring board, respectively.
A sealing body for sealing the semiconductor chip and the plurality of wires;
An external terminal connected to each of the plurality of lands of the wiring board;
Including
The plurality of circuit elements are formed on the central portion side of the main surface of the semiconductor chip rather than the plurality of pads,
The plurality of circuit elements include an input / output circuit that inputs and outputs signals to and from an external device, and an arithmetic circuit that performs arithmetic processing on a signal input from the external device to the input / output circuit
The frequency of the arithmetic circuit is higher than the frequency of the input / output circuit,
The arithmetic circuit has more regions arranged on the central portion side in the main surface than the input / output circuit,
The plurality of pads are a first pad formed along each side of the semiconductor chip having a rectangular planar shape, and is positioned closer to the central portion of the main surface of the semiconductor chip than the first pad. And a second pad that
The plurality of wires includes a first wire electrically connected to the first pad and a second wire electrically connected to the second pad. 2. The semiconductor device according to claim 1, wherein the plurality of bonding leads are electrically connected to the plurality of lands through a plurality of substrate wirings formed on the wiring substrate, respectively.
The plurality of substrate wirings are formed below the back surface of the semiconductor chip.   The semiconductor device according to claim 1, wherein the semiconductor chip is mounted on the upper surface of the wiring board via a conductive die-bonding material. 2. The semiconductor device according to claim 1, wherein the arithmetic circuit includes a first region located on the first pad side, a first region having a larger area than the first region, and located on the central portion side of the main surface. Two regions,
A distance between the second region of the arithmetic circuit and the second pad is shorter than a distance between the second region of the arithmetic circuit and the first pad. 2. The semiconductor device according to claim 1, wherein the first pad includes a power supply potential pad for supplying a power supply potential, a reference potential pad for supplying a reference potential, and a signal pad for transmitting a signal.
The first pad is formed adjacent to the input / output circuit,
The signal pad of the first pad is electrically connected only to the input / output circuit,
A signal input / output between the input / output circuit and the external device is transmitted through the first wire and the first pad,
The semiconductor device, wherein the arithmetic circuit is electrically connected to the input / output circuit through the wiring.   2. The semiconductor device according to claim 1, wherein the second pad is formed on the arithmetic circuit.   7. The semiconductor device according to claim 6, wherein the second pad is electrically connected to the arithmetic circuit.   8. The semiconductor device according to claim 7, wherein a power supply potential or a reference potential is supplied to the arithmetic circuit through the second wire and the second pad.   2. The semiconductor device according to claim 1, wherein a resistance component of the wire is smaller than a resistance component of the wiring formed on the main surface of the semiconductor chip.   2. The semiconductor device according to claim 1, wherein the plurality of circuit elements are formed on the main surface side of the semiconductor chip with respect to the back surface of the semiconductor chip.   2. The semiconductor device according to claim 1, wherein power required to operate the arithmetic circuit is larger than power required to operate the input / output circuit.   6. The semiconductor device according to claim 5, wherein the second pad is not electrically connected to the signal pad.   2. The semiconductor device according to claim 1, wherein the wire is an Au wire.   2. The semiconductor device according to claim 1, wherein the input / output circuit is an analog circuit or a digital circuit.   2. The semiconductor device according to claim 1, wherein the thermal conductivity of the resin forming the sealing body is smaller than the thermal conductivity of the wiring board having wiring made of metal.

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