JP2010032726A - Semiconductor device and manufacturing method therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To detect residue of film in a region in which a contact hole is formed in an interlayer insulation layer, and to accurately obtain thickness of residue of film of the interlayer insulation layer. <P>SOLUTION: A semiconductor layer 13 and the first metal layer 27 for inspection being hard to be oxidized more than the semiconductor layer 13 are formed at a substrate 11, after an insulation film 20 is formed so as to cover the semiconductor layer 13 and the first metal layer 27 for inspection, an interlayer insulation layer 21 is formed by forming in the insulation film 20 a contact hole 21a and a contact hole 21b for inspection for exposing respectively a part of the semiconductor layer 13 and the first metal layer 27 for inspection, a metal layer 22 and the second metal layer 28 for inspection extracted respectively from the inside of the contact hole 21a and the contact hole 21b for inspection to the surface are formed at the interlayer insulation layer 21, and an electric property between the first metal layer 27 for inspection and the second metal layer 28 for inspection is measured. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof.

  An active matrix driving type liquid crystal display device includes an active matrix substrate having a plurality of pixel electrodes arranged in a matrix, a counter substrate arranged to face the active matrix substrate, and a frame-like shape between the two substrates. And a liquid crystal layer sealed inside the sealing material.

  The active matrix substrate is provided with a plurality of thin film transistors (hereinafter referred to as TFTs) electrically connected to each pixel electrode. Each TFT is made of polysilicon whose carrier layer has higher carrier mobility than amorphous silicon from the standpoint of reducing power consumption and making it possible to integrate the drive circuit part into the substrate. Has been.

  Each of these TFTs often has a top gate type structure. A semiconductor layer formed on a substrate, a gate insulating film provided so as to cover the semiconductor layer, and a semiconductor layer on the gate insulating film And an interlayer insulating film provided so as to cover the gate electrode. A pair of contact holes exposing a part of the semiconductor layer are formed in the interlayer insulating layer composed of the gate insulating film and the interlayer insulating film so as to sandwich the gate electrode. A source electrode and a drain electrode are formed by being drawn from the inside to the surface.

  By the way, in the formation of each TFT, when the contact hole is formed in the interlayer insulating layer by etching and the etching conditions such as the etching time are not appropriate, the contact hole is not formed through the interlayer insulating layer, and the contact hole is not formed. There is a possibility that a film residue may be generated in which a part of the interlayer insulating layer remains in the region where the film is formed. If such a film residue of the interlayer insulating layer is generated, poor conduction occurs between the source and drain electrodes and the semiconductor layer, resulting in a defective product.

Therefore, as a method for inspecting the formation state of the contact hole formed in the interlayer insulating layer, an inspection semiconductor layer formed in the same layer as the semiconductor layer and a pair of inspection metal layers formed on the interlayer insulating layer Each of the inspection metal layers from the inside of the pair of inspection contact holes formed in the interlayer insulation layer together with the contact holes to expose a part of the inspection semiconductor layer, to the surface of the interlayer insulation layer. Each of the test metal layers and the test semiconductor layer are inspected for continuity by forming an extracted test pattern and measuring the electrical resistance between the pair of test metal layers, and an interlayer insulating layer is formed in the contact hole. There is known a method for inspecting whether or not a film residue is generated (see, for example, Patent Document 1).
JP-A-5-129390

  However, since the semiconductor layer is relatively easily oxidized in the manufacturing process, according to the contact hole inspection method described above, the contact resistance between each inspection metal layer and the inspection semiconductor layer is likely to vary depending on the oxidation state of the semiconductor layer surface. The electrical resistance between the pair of inspection metal layers is likely to fluctuate due to the fluctuation of the contact resistance. As a result, even if the film residue of the interlayer insulation layer is detected, the electrical resistance having a magnitude corresponding to the film residue of the interlayer insulation layer cannot be measured with high accuracy, and the film residue of the interlayer insulation layer is determined based on the electrical resistance. It is difficult to accurately determine how much thickness is. For this reason, it is difficult to improve the manufacturing process by adjusting the etching condition to an appropriate condition so that a similar interlayer insulating layer film residue does not occur on the active matrix substrate to be subsequently manufactured based on the inspection result.

  The present invention has been made in view of the above points, and an object of the present invention is to detect a film residue in a region where a contact hole is formed in an interlayer insulating layer, and to detect a film residue of the interlayer insulating layer. It is to obtain the thickness with high accuracy.

  In order to achieve the above object, a first inspection is performed together with a first inspection metal layer made of a metal material that is provided on a substrate and is less likely to be oxidized than a semiconductor layer, and a contact hole for exposing a part of the semiconductor layer. Measure electrical characteristics between the second inspection metal layer drawn from the inside of the contact hole for inspection formed in the interlayer insulating layer to expose a part of the metal layer for inspection to the surface of the interlayer insulating layer By doing so, the formation state of the contact hole for inspection was inspected.

  Specifically, a method for manufacturing a semiconductor device according to the present invention includes a semiconductor layer provided on a substrate and an interlayer formed on the semiconductor layer so as to expose a part of the semiconductor layer. A method of manufacturing a semiconductor device comprising an insulating layer and a metal layer drawn from the inside of the contact hole on the surface of the interlayer insulating layer, wherein the substrate is less likely to be oxidized than the semiconductor layer and the semiconductor layer. A first step of forming a first inspection metal layer made of a metal material; and after forming an insulating film so as to cover the semiconductor layer and the first inspection metal layer, forming the contact hole in the insulating film A second step of forming the interlayer insulating layer by forming an inspection contact hole for exposing a part of the first inspection metal layer; and the metal layer and the inspection in the interlayer insulating layer. A third step of forming a second inspection metal layer drawn from the inside of the contact hole to the surface of the interlayer insulating layer, and electrical connection between the first inspection metal layer and the second inspection metal layer. And a fourth step of inspecting the formation state of the inspection contact hole by measuring characteristics.

  According to this manufacturing method, in the fourth step, the first inspection metal layer made of a metal material which is provided on the substrate and is less oxidized than the semiconductor layer, and the contact hole for exposing a part of the semiconductor layer are provided. Electrical characteristics between the second inspection metal layer drawn from the inside of the contact hole for inspection formed in the interlayer insulating layer to expose a part of the first inspection metal layer to the surface of the interlayer insulating layer Is measured to inspect the formation state of the contact hole for inspection. In the fourth step, it is inspected whether or not the first inspection metal layer and the second inspection metal layer are conductive based on the measured electrical characteristics. Thus, when the first inspection metal layer and the second inspection metal layer are electrically connected, the contact hole is formed through the interlayer insulating layer, and the film is formed in the region where the contact hole is formed in the interlayer insulating layer. When it is confirmed that there is no residue and the first inspection metal layer and the second inspection metal are not conductive, the film residue in the region where the contact hole is formed in the interlayer insulating layer is detected.

  When the remaining film of the interlayer insulating layer is detected, the first inspection metal layer is less oxidized than the semiconductor layer, and thus the first inspection metal layer is caused by the surface state of the first inspection metal layer. Since the variation in the electrical characteristics between the metal layer and the second inspection metal layer is relatively small, the electrical characteristics having a size corresponding to the thickness of the remaining layer of the interlayer insulating layer are measured. Based on this, the remaining thickness of the interlayer insulating layer is accurately obtained. Therefore, the film residue in the region where the contact hole is formed in the interlayer insulating layer is detected, and the thickness of the film remaining in the interlayer insulating layer is accurately obtained.

  In the second step, a pair of the inspection contact holes are formed, and in the third step, the second inspection metal layer is drawn from the inside of each inspection contact hole to the surface of the interlayer insulating layer. In the fourth step, electrical characteristics between the pair of second inspection metal layers may be measured.

  Also in this manufacturing method, the first inspection metal is measured by measuring the electrical characteristics between the pair of second inspection metal layers drawn from the inside of the pair of inspection contact holes to the surface of the interlayer insulating layer. Since it is possible to measure the electrical characteristics between the layer and the second inspection metal layer, the effects of the present invention are specifically exhibited.

  In the fourth step, an electric capacity between the first inspection metal layer and the second inspection metal layer may be measured.

  According to this manufacturing method, when a film residue of the interlayer insulating layer occurs and the first inspection metal layer and the second inspection metal layer are not conductive, the first inspection metal layer and the second inspection metal layer Since the capacitor structure in which the film residue of the interlayer insulating layer is disposed between the metal layer and the metal layer is formed, the capacitance corresponding to the thickness of the film remaining of the interlayer insulating layer is measured. On the other hand, when the first inspection metal layer and the second inspection metal layer are conductive, a remarkably large electric capacity is measured as compared with the case where a film residue of the interlayer insulating layer is generated. For these reasons, it is possible to detect whether or not the first inspection metal layer and the second inspection metal layer are conductive and detect the film residue of the interlayer insulating layer.

  When a film residue of the interlayer insulating layer is detected, a general electric capacitance C between conductors is determined from the measured electric capacity C, the opening area S of the contact hole for inspection, and the dielectric constant ε of the interlayer insulating layer. It is possible to obtain the remaining thickness d of the interlayer insulating layer based on the equation C = ε × S / d for deriving Therefore, the effects of the present invention are specifically demonstrated.

  In the fourth step, an electrical resistance between the first inspection metal layer and the second inspection metal layer may be measured.

  According to this manufacturing method, when the first inspection metal layer and the second inspection metal layer are conductive, a predetermined electrical resistance is measured. On the other hand, when a film residue is generated in the interlayer insulating layer and the first inspection metal layer and the second inspection metal layer are not conductive, the first inspection metal layer and the second inspection metal layer are An electrical resistance that is larger than the predetermined electrical resistance measured when conducting is increased by the remaining thickness of the interlayer insulating layer. Therefore, it is possible to inspect whether the first inspection metal layer and the second inspection metal layer are conductive.

  When the film residue of the interlayer insulating layer is detected, a general electric resistance R is derived from the measured electric resistance R, the opening area S of the contact hole for inspection, and the electric resistivity ρ of the interlayer insulating layer. Based on the equation R = ρ × d / S, the remaining thickness d of the interlayer insulating layer can be obtained. Therefore, the effects of the present invention are specifically demonstrated.

  In the second step, a gate insulating film is formed so as to cover the semiconductor layer and the first inspection metal layer, a gate electrode is formed so as to overlap the semiconductor layer via the gate insulating film, Forming an interlayer insulating film so as to cover the gate electrode forms the insulating film composed of the gate insulating film and the interlayer insulating film, and pairs the contact holes so as to sandwich the gate electrode with respect to the insulating film. The interlayer insulating layer is formed, and in the third step, a thin film transistor is formed by forming a pair of metal layers by pulling out from the inside of each contact hole to the surface of the interlayer insulating layer. Also good.

  According to this manufacturing method, in a semiconductor device such as an active matrix substrate having a thin film transistor on the substrate, the formation state of each contact hole in the interlayer insulating layer in the thin film transistor is inspected, and the effects of the present invention are specifically exhibited.

  In addition, a semiconductor device according to the present invention includes a semiconductor layer provided on a substrate, an interlayer insulating layer formed on the semiconductor layer and formed with a contact hole for exposing a part of the semiconductor layer, A semiconductor device comprising a surface of an interlayer insulating layer provided with a metal layer provided from the inside of the contact hole, and is less likely to be oxidized between the substrate and the interlayer insulating layer than the semiconductor layer. A first inspection metal layer made of a metal material is provided, a second inspection metal layer is provided on the surface of the interlayer insulation layer, and a part of the first inspection metal layer is provided on the interlayer insulation layer. The second contact metal layer is drawn from the inside of the contact hole for inspection to the surface of the interlayer insulating layer.

  According to this configuration, the first inspection metal layer made of a metal material that is less likely to be oxidized than the semiconductor layer is provided between the substrate and the interlayer insulating layer, and the second inspection metal layer is formed on the surface of the interlayer insulating layer. An inspection contact hole for exposing a part of the first inspection metal layer is formed in the interlayer insulation layer, and the second inspection metal layer is formed on the surface of the interlayer insulation layer from the inside of the inspection contact hole. Has been drawn to. In the semiconductor device configured as described above, the inspection contact hole is formed in the interlayer insulating layer together with the contact hole for exposing a part of the semiconductor layer, and the first inspection metal layer and the second inspection metal layer are formed. In the meantime, it is manufactured by inspecting the formation state of the contact hole for inspection by measuring electrical characteristics such as electric capacity or electric resistance. Accordingly, it is inspected whether the first inspection metal layer and the second inspection metal layer are conductive based on the measured electrical characteristics, and the first inspection metal layer and the second inspection metal layer are inspected. When the metal layer is conductive, it is confirmed that the contact hole is formed through the interlayer insulating layer and there is no film residue in the region where the contact hole is formed in the interlayer insulating layer. And the second inspection metal are not conductive, the film residue in the region where the contact hole is formed in the interlayer insulating layer is detected.

  And when the film | membrane residue of an interlayer insulation layer is detected, when the 1st test | inspection metal layer is harder to oxidize than a semiconductor layer, the 1st test | inspection metal resulting from the surface state of the 1st test | inspection metal layer Since the variation of the electrical characteristics between the layer and the second inspection metal layer is relatively small, the electrical characteristics having a size corresponding to the thickness of the remaining layer of the interlayer insulating layer are measured and based on the electrical characteristics Therefore, the remaining thickness of the interlayer insulating layer is required with high accuracy. Therefore, the film residue in the region where the contact hole is formed in the interlayer insulating layer is detected, and the thickness of the film remaining in the interlayer insulating layer is accurately obtained.

  In addition, by measuring the electrical characteristics between the first inspection metal layer and the second inspection metal layer when a failure occurs in the semiconductor device, the cause of the failure is the interlayer insulating layer. It is possible to inspect whether or not the film remains in the contact hole.

  According to the present invention, a first inspection metal layer provided on a substrate and made of a metal material that is less likely to be oxidized than a semiconductor layer, and a contact hole for exposing a part of the semiconductor layer are provided. The electrical characteristics between the second contact metal layer provided on the surface of the interlayer insulation layer from the inside of the contact hole for inspection formed in the interlayer insulation layer so as to expose a part of the first insulation layer are measured. Thus, since the formation state of the contact hole for inspection is inspected, the film residue in the region where the contact hole is formed in the interlayer insulating film can be detected, and the thickness of the film remaining in the interlayer insulating film can be obtained.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The present invention is not limited to the following embodiments.

Embodiment 1 of the Invention
1 to 13 show Embodiment 1 of the present invention. FIG. 1 is a plan view schematically showing a liquid crystal display device S of the present embodiment. FIG. 2 is a cross-sectional view schematically showing the liquid crystal display device S along the line II-II in FIG. FIG. 3 is a cross-sectional view schematically showing a part of the active matrix substrate 10 constituting the liquid crystal display device S. In FIG. 1, the polarizing plate 35 is not shown.

  As shown in FIGS. 1 and 2, the liquid crystal display device S has an active matrix substrate 10 which is a semiconductor device having a plurality of thin film transistors (hereinafter referred to as TFTs), which will be described later, and an active matrix substrate 10 facing the active matrix substrate 10. And a liquid crystal display panel 1 having a liquid crystal layer 31 provided between the active matrix substrate 10 and the counter substrate 30, and the liquid crystal display panel 1 is connected to an external circuit. An unillustrated flexible printed circuit board (Flexible Printed Circuit, hereinafter referred to as FPC) is mounted. The liquid crystal display panel 1 includes a display area that displays an image including a plurality of pixels, and a non-display area that is arranged outside the display area and does not contribute to image display.

  The active matrix substrate 10 and the counter substrate 30 are formed in a rectangular shape as shown in FIG. 1, and as shown in FIG. 2, alignment films 32 and 33 are provided on the surface on the liquid crystal layer 31 side, respectively. Polarizing plates 34 and 35 are provided on the surface opposite to the liquid crystal layer 31, respectively. A frame-shaped sealing material 36 is disposed between the active matrix substrate 10 and the counter substrate 30, and a liquid crystal material is sealed inside the sealing material 36, thereby forming the liquid crystal layer 31. ing.

  Although not shown in the drawing, the active matrix substrate 10 is provided with a plurality of gate lines extending in parallel to each other and a plurality of source lines extending in parallel to each other in a direction intersecting each gate line. A TFT 23 shown in FIG. 3 is provided for each pixel in the vicinity of the intersection between each gate line and each source line, and each TFT 23 is connected to the gate line and the source line forming each intersection. Each TFT 23 is electrically connected to a plurality of pixel electrodes 25 arranged in a matrix corresponding to each pixel.

  Although not shown, the active matrix substrate 10 includes a drive circuit unit that is electrically connected to each gate line and each source line and drives each gate line and each source line in a non-display area. Is provided. This drive circuit unit is integrally formed on the substrate, and has a TFT (Complementary Metal Oxide Semiconductor) TFT 24 shown in FIG.

  As shown in FIG. 3, this active matrix substrate 10 has a glass substrate 11 on which each TFT (TFT of each pixel and TFT of a drive circuit section) 23, 24, each wiring and each electrode. 25 is formed. Each of the TFTs 23 and 24 is a top gate type TFT, the TFT 23 of each pixel is constituted by an n-type TFT, and the CMOS structure TFT 24 constituting the drive circuit section includes a p-type TFT 24p and an n-type TFT 24n.

  The semiconductor layer 13 constituting each of the TFTs 23 and 24 is made of polysilicon and is formed in an island shape on the surface of the glass substrate 11. A gate insulating film 14 is laminated on each semiconductor layer 13, and a gate electrode 15 is formed on the surface of the gate insulating film 14 so as to overlap each semiconductor layer 13 via the gate insulating film 14. .

  Further, an interlayer insulating film 19 is laminated on the gate insulating film 14 so as to cover each gate electrode 15. In the interlayer insulating layer 21 constituted by the gate insulating film 14 and the interlayer insulating film 19, a pair of contact holes 21 a for exposing the impurity regions 13 p and 13 n of the semiconductor layers 13 sandwich the gate electrodes 15. A plurality are formed. The interlayer insulating layer 21 is formed with a plurality of metal layers 22 that are drawn from the inside of each contact hole 21a to the surface and constitute the source electrode 22s and the drain electrode 22d of the TFTs 23 and 24, respectively.

  The semiconductor layers 13 of these TFTs 23 and 24 are provided on both outer sides in the channel length direction of the channel region 13c that overlaps the gate electrode 15 with the gate insulating film 14 interposed therebetween, and function as source and drain regions. And a pair of impurity regions 13p and 13n.

  Each semiconductor layer 13 is provided with an LDD (Lightly Doped Drain) region which is an impurity region having a lower concentration than the impurity regions 13p and 13n between the channel region 13c and the impurity regions 13p and 13n. May be.

  In each pixel TFT 23, the gate electrode 15 is connected to the gate line, the source electrode 22 s is connected to the source line, and the drain electrode 22 d is connected to the pixel electrode 25. In the TFT 24 having a CMOS structure constituting the drive circuit unit, the drain electrode 22d of the p-type TFT 24p and the source electrode 22s of the n-type TFT 24n are integrally formed, and the p-type TFT 24p and the n-type TFT 24n are connected in series with each other. . Each of these TFTs 23 and 24 is covered with a passivation film 26 made of an insulating material provided so as to expose each pixel electrode 25.

  Further, as shown in FIG. 1, the active matrix substrate 10 is provided with a protruding portion 10a that protrudes from the counter substrate 30 and is mounted with an FPC. The protruding portion 10a is provided with an inspection pattern 29 for inspecting the formation state of each contact hole 21a of the interlayer insulating layer 21 in each of the TFTs 23 and 24 described above.

  As shown in FIG. 3, the inspection pattern 29 includes the same layer as the semiconductor layer 13 of each TFT 23, 24, that is, the first inspection metal layer 27 disposed between the glass substrate 11 and the interlayer insulating layer 21. And a pair of second inspection metal layers 28 provided on the surface of the interlayer insulating layer 21 so as to overlap the inspection metal layer 27, respectively.

  The interlayer insulating layer 21 is formed with a pair of inspection contact holes 21b for exposing part of the first inspection metal layer 27. Each of these inspection contact holes 21b has the same opening area and the same shape as the contact holes 21a of the TFTs 23 and 24. Each second inspection metal layer 28 is drawn from the inside of each inspection contact hole 21 b to the surface of the interlayer insulating layer 21.

  The first inspection metal layer 27 is formed of a metal material such as Ti, Pt, Ta, Ag, and Au that is less likely to be oxidized than the semiconductor layer 13. The second inspection metal layer 28 is made of the same metal material as the metal layers (source electrode 22 s and drain electrode 22 d) 22 of each of the TFTs 23 and 24, and is exposed from the passivation film 26.

  Although not shown, the counter substrate 30 is provided with a plurality of color filters so as to overlap the pixel electrodes 25 in the display area, and a black matrix is provided so as to partition the color filters. The counter substrate 30 is provided with a common electrode so as to cover each color filter, and the common electrode is electrically connected to an external circuit through the FPC.

  In this way, the liquid crystal display device S supplies a predetermined gate signal to each gate line and a predetermined source signal to each source line by the drive circuit unit while supplying a certain common signal to the common electrode. As a result, the TFTs 23 connected to the respective gate lines are sequentially turned on, and predetermined charges are written to the respective pixel electrodes 25 through the drain electrodes 22d, and the liquid crystal layer 31 is interposed between the respective pixel electrodes 25 and the common electrode. By applying a predetermined voltage, a desired image display is performed by controlling the orientation of liquid crystal molecules for each pixel.

-Manufacturing method-
Next, a method for manufacturing the liquid crystal display device S will be described with reference to FIGS. 4 to 9 are cross-sectional views for explaining a manufacturing method of the active matrix mother substrate 50. FIG. FIG. 10 is a plan view schematically showing the active matrix mother substrate 50. FIG. 11 is a plan view schematically showing the counter mother substrate 55. FIG. 12 is a plan view schematically showing the liquid crystal display mother panel A. FIG. FIG. 13 is a plan view showing the dividing lines 61 and 62 in the active matrix mother board 50. In the present embodiment, a manufacturing method of the liquid crystal display device S by multi-chamfering for simultaneously manufacturing a plurality of liquid crystal display panels 1 will be described as an example.

  The manufacturing method of the liquid crystal display device S includes an active matrix mother substrate manufacturing step, a counter mother substrate manufacturing step, a bonding step, and a dividing step.

  In the active matrix mother substrate manufacturing process, the active matrix mother substrate 50 shown in FIG. 10 in which a plurality of regions (hereinafter referred to as active matrix substrate regions) 50a for forming the active matrix substrate 10 are arranged in a matrix is formed. The active matrix substrate 10 is produced as an aggregate. In the active matrix mother substrate manufacturing process, a first process, a second process, a third process, and a fourth process are performed.

  In the first step, first, the glass mother substrate 51 which is a large-sized glass substrate is made of a metal material such as Ti, Pt, Ta, Ag and Au which is less likely to be oxidized than each semiconductor layer 13 to be formed later by a sputtering method or the like. A metal film is formed. Subsequently, by patterning the metal film by photolithography or the like, as shown in FIG. 4, a first inspection metal layer 27 is formed in each active matrix substrate region 50a.

  Next, an amorphous silicon film is formed on the entire surface of the glass mother substrate 51 so as to cover each first inspection metal layer 27 by chemical vapor deposition (hereinafter referred to as CVD), and then the amorphous The polysilicon film 12 is formed by crystallizing the silicon film by laser annealing. Thereafter, the polysilicon film 12 is patterned by photolithography or the like, thereby forming each semiconductor layer 13 in each active matrix substrate region 50a as shown in FIG.

  In the second step to be performed next, the gate insulating film 14 is formed on the entire surface of the glass mother substrate 51 so as to cover each semiconductor layer 13 and the first inspection metal layer 27 by a CVD method or the like. Subsequently, after a metal film is formed on the surface of the gate insulating film 14 by a sputtering method or the like, the metal film is patterned by photolithography or the like, so that each active matrix substrate region 50a has each gate insulating film 14 interposed therebetween. Each gate electrode 15 is formed so as to overlap the semiconductor layer 13 and each gate line is formed.

  Next, as shown in FIG. 6, a resist layer 16 is formed on the glass mother substrate 51 so as to open in each region (hereinafter referred to as a p-type TFT region) Tp for forming a p-type TFT, and an n-type TFT. Each region (hereinafter referred to as an n-type TFT region) Tn that forms a layer is covered with the resist layer 16. Subsequently, a P-type impurity element (for example, boron) is ion-implanted into the semiconductor layer 13 in each p-type TFT region Tp using the resist layer 16 and each gate electrode 14 as a mask. An arrow 17 in FIG. 6 indicates a direction in which a P-type impurity element is implanted. Thus, each P-type impurity region 13p and channel region 13c are formed in the semiconductor layer 13 of each p-type TFT region Tp.

  At this time, when an N-type impurity element is also implanted into the semiconductor layer 13 in the p-type TFT region Tp when the N-type impurity element is implanted into the semiconductor layer 13 in the n-type TFT region Tn later, the N-type impurity element is used. The dose amount of the P-type impurity element is appropriately adjusted in consideration of the amount that is canceled out by the above.

  Next, as shown in FIG. 7, after removing the resist layer 16, an N-type impurity element (for each semiconductor layer 13 in both the p-type TFT region Tp and the n-type TFT region Tn, using each gate electrode 15 as a mask). For example, phosphorus is ion-implanted. An arrow 18 in FIG. 7 indicates a direction in which an N-type impurity element is implanted. As a result, each n-type impurity region 13n and channel region 13c are formed in the semiconductor layer 13 of each n-type TFT region Tn. Subsequently, the impurity element in the impurity regions 13p and 13n of each semiconductor layer 13 is activated by performing heat treatment for heating the glass mother substrate 51 on which each semiconductor layer 13 is formed.

  Next, as shown in FIG. 8, an interlayer insulating film 19 is formed on the surface of the gate insulating film 14 so as to cover each gate electrode 15 by a CVD method or the like. Thereafter, each semiconductor layer is sandwiched between the gate electrode 15 and the insulating film 20 including the gate insulating film 14 and the interlayer insulating film 19 in each active matrix substrate region 50a by photolithography or the like as shown in FIG. Each of the contact holes 21a for exposing a part of the impurity regions 13p and 13n in 13 is formed, and a pair of inspection contact holes 21b for exposing a part of the first inspection metal layer 26 are formed. Thus, the interlayer insulating layer 21 is formed.

  In the third step to be performed next, after forming a metal film on the interlayer insulating layer 21 by sputtering or the like, the metal film is patterned by photolithography or the like, whereby each source line is formed in each active matrix substrate region 50a. Each metal layer 22 is formed by being drawn out from the inside of each contact hole 21a to the surface of the interlayer insulating layer 21, and is also drawn out from the inside of each contact hole 21b for inspection to the surface of the interlayer insulating layer 21. The second inspection metal layer 28 is formed. In this way, the TFTs 23 and 24 and the inspection pattern 29 are formed in each active matrix substrate region 50a.

  Next, after forming an ITO (Indium Tin Oxide) film by sputtering or the like so as to cover each TFT 24, each pixel electrode 25 is formed by patterning the ITO film by photolithography or the like. Thereafter, a passivation film is formed so as to cover the TFTs 23 and 24 by a CVD method or the like, and the passivation film is patterned by photolithography or the like to expose each pixel electrode 25 and each second inspection metal layer 28. Through the above steps, the configuration of the active matrix substrate 10 is formed in each active matrix substrate region 50a.

  In a fourth step performed thereafter, an electric capacity that is an electric characteristic between the pair of second inspection metal layers 28 in the inspection pattern 29 of the plurality of active matrix substrate regions 50a is measured. In the fourth step, it is not necessary to measure the capacitance in the test pattern 29 for all of the active matrix substrate regions 50a in the active matrix mother substrate 50, and a plurality of active matrix substrates included in the active matrix mother substrate 50 are used. What is necessary is just to extract from the area | region 50a.

  In the fourth step, each contact hole 21a is not formed through the interlayer insulating layer 21 in the third step, and a film residue is left in which a part of the interlayer insulating layer 21 remains in the region where the contact hole 21a is formed. In this case, since the capacitor structure in which the film residue of the interlayer insulating layer 21 is disposed between the first inspection metal layer 27 and each of the second inspection metal layers 28, the film residue of the interlayer insulation layer 21 is formed. A capacitance having a size corresponding to the thickness is measured. On the other hand, when each contact hole 21a is formed through the interlayer insulating layer 21 and there is no film residue of the interlayer insulating layer 21, it is remarkably larger than when the film residue of the interlayer insulating layer 21 is generated. The capacitance is measured. From these facts, it is inspected whether or not the first inspection metal layer 27 and the second inspection metal layer 28 are conductive, and the remaining film in the region where each contact hole 21a is formed in the interlayer insulating layer 21. Check for presence.

  At this time, when the film residue of the interlayer insulating layer 21 is detected, the measured electric capacity C, the opening area S of the inspection contact hole 21b, and the interlayer insulating layer (that is, the gate insulating film 14 and the interlayer insulating film 19). From the dielectric constant ε of 21, the remaining thickness d of the interlayer insulating layer 21 is obtained based on the formula C = ε × S / d for deriving the electric capacity C between the general conductors. Based on the thickness d of the interlayer insulating layer 21, the etching conditions of the insulating film 20 in the third step are set appropriately so that the remaining film of the similar interlayer insulating layer 21 does not occur on the active matrix mother substrate 50 to be manufactured thereafter. Adjust to the conditions. The active matrix mother substrate 50 is manufactured through the above steps. Thereafter, a large alignment film is formed on the active matrix mother substrate 50 by a printing method or the like.

  In the counter mother substrate manufacturing process, a black matrix, each color filter, a common electrode and the like are sequentially formed on a glass mother substrate which is a large glass substrate, thereby forming a plurality of regions (hereinafter referred to as a plurality of regions) for forming the counter substrate 30. The counter mother substrate 55 shown in FIG. 11 in which the counter substrate region 55 a is arranged in a matrix is manufactured as an assembly of a plurality of counter substrates 30. Thereafter, a large alignment film is formed on the counter mother substrate 55 by a printing method or the like.

  In the subsequent bonding step, the active matrix mother substrate 50 and the counter mother substrate 55 are bonded together so that each active matrix substrate region 50a and each counter substrate region 55a face each other through the sealing material 36, By sealing each liquid crystal layer 31 between each active matrix substrate region 50a and each counter substrate region 55a by each sealing material 36, as shown in FIG. 12, a plurality of liquid crystal display panels 1 are formed. A liquid crystal display mother panel A in which regions (hereinafter referred to as liquid crystal display panel regions) 60 are arranged in a matrix is manufactured as an assembly of a plurality of liquid crystal display panels 1.

  In the next dividing step, the liquid crystal display mother panel A is divided by the dividing lines 61 and 62 shown in FIG. At this time, in the dividing line 61, both the active matrix mother substrate 50 and the counter mother substrate 55 are divided. On the other hand, in the dividing line 62, only the opposing mother substrate 55 is divided to expose the protruding portions 10 a of the active matrix substrates 10 from the opposing substrate 30. In this way, by dividing the liquid crystal display mother panel A into each liquid crystal display panel region 60, a plurality of liquid crystal display panels 1 shown in FIG.

  Thereafter, polarizing plates 34 and 35 are attached to both surfaces of each liquid crystal display panel 1 and an FPC is mounted on the protruding portion 10a to manufacture a plurality of liquid crystal display devices S.

-Effect of Embodiment 1-
Therefore, according to the first embodiment, in the fourth step, the first inspection metal layer 27 made of a metal material that is provided on the glass substrate 11 and is less likely to be oxidized than the semiconductor layer 13 and a part of the semiconductor layer 13 are formed. In order to expose a part of the first inspection metal layer 27 together with the contact hole 21a to be exposed, a first portion drawn from the inside of the inspection contact hole 21b formed in the interlayer insulation layer 21 to the surface of the interlayer insulation layer 21 is provided. (2) The state of formation of the inspection contact hole 12b is inspected by measuring the electric capacity between the inspection metal layer 28 and the metal layer 28 for inspection. By this fourth step, it is possible to inspect whether or not the first inspection metal layer 27 and the second inspection metal layer 28 are conductive based on the measured capacitance, and the contact hole 21a in the interlayer insulating layer 21 is formed. It is possible to detect the film residue in the formed region.

  When the remaining film of the interlayer insulating layer 21 is detected, the first inspection metal layer 27 is less likely to be oxidized than the semiconductor layer 13, and therefore the first inspection metal layer 27 is caused by the surface state of the first inspection metal layer 27. Since the variation in electric capacity between the first inspection metal layer 27 and each second inspection metal layer 28 is relatively small, the electric capacity having a size corresponding to the thickness of the remaining film of the interlayer insulating layer 21 can be measured. Based on the capacitance, the remaining thickness of the interlayer insulating layer 21 can be obtained with high accuracy. Therefore, it is possible to detect the film residue in the region where the contact hole 21a is formed in the interlayer insulating layer 21, and to obtain the thickness of the film remaining of the interlayer insulating layer 21 with high accuracy.

  In addition, since the inspection pattern 29 is provided on the protruding portion 10a of the active matrix substrate 10, the first inspection metal layer 27 and the second inspection metal are used when the liquid crystal display device S has a problem. By measuring the electric capacity with the layer 28, it is possible to inspect whether or not the cause of the failure is the film residue in the contact hole 21a in the interlayer insulating layer 21.

<< Embodiment 2 of the Invention >>
FIG. 14 shows Embodiment 2 of the present invention. In the following embodiments, the same portions as those in FIGS. 1 to 13 are denoted by the same reference numerals, and detailed description thereof is omitted. FIG. 14 is a plan view schematically showing the active matrix mother substrate 52 of the present embodiment.

  In the first embodiment, the test pattern 29 is formed on the protruding portion 10a of each active matrix substrate region 50a to produce the active matrix mother substrate 50. However, in the second embodiment, as shown in FIG. Thus, an inspection pattern 29 is formed for each active matrix substrate region 52a with respect to the region of the glass mother substrate 51 separated from each active matrix substrate region 50a, thereby producing the active matrix mother substrate 52. Then, in the fourth step, as in the first embodiment, by measuring the capacitance in the test pattern 29 corresponding to the active matrix substrate region 52a by extracting from the plurality of active matrix substrate regions 52a, the interlayer insulating layer 21 The formation state of the inspection contact hole 21b is inspected.

-Effect of Embodiment 2-
Therefore, according to the second embodiment, before the active matrix mother substrate 52 is divided, the film residue in the region where the contact hole 21a is formed in the interlayer insulating layer 21 can be detected as in the first embodiment. The remaining film thickness of the insulating layer 21 can be obtained with high accuracy.

<< Embodiment 3 of the Invention >>
In the first embodiment, the capacitance between the pair of second inspection metal layers 28 of the inspection pattern 29 is measured in the fourth step. However, in the present embodiment, the pair of second inspection metals in the inspection pattern 29 is measured. The electrical resistance between layers 28 is measured. The first inspection metal layer 27 is formed of a metal material that is less likely to be oxidized than the semiconductor layer 13 as in the first embodiment.

  In the fourth step in the present embodiment, when each contact hole 21a is formed through the interlayer insulating layer 21 and there is no film residue of the interlayer insulating layer 21 in the third step, a predetermined electric resistance is measured. On the other hand, when a film residue is generated in the interlayer insulating layer 21, an electrical resistance that is larger by the thickness of the film remaining in the interlayer insulating layer 21 than in the case where there is no film remaining in the interlayer insulating layer 21 is measured. From these, it is inspected whether the first inspection metal layer 27 and the second inspection metal layer 28 are conductive based on the measured electric resistance, and each contact hole 21a in the interlayer insulating layer 21 is determined. The presence or absence of film residue in the formed region is inspected.

  At this time, when the film residue of the interlayer insulating layer 21 is detected, the measured electric resistance R, the opening area S of the contact hole 21b for inspection and the interlayer insulating layer (that is, the gate insulating film 14 and the interlayer insulating film 19). From the electrical resistivity ρ of 21, the remaining film thickness d of the interlayer insulating layer 21 is obtained based on the equation R = ρ × d / S for deriving a general electrical resistance R.

-Effect of Embodiment 3-
Therefore, according to the third embodiment, in the fourth step, by measuring the electric resistance between the pair of second inspection metal layers 28, the first inspection metal layer 27 and the second inspection metal layer 27 are measured based on the measured electric resistance. It is possible to inspect whether or not each second inspection metal layer 28 is conductive, and it is possible to detect a film residue in a region where the contact hole 21 a is formed in the interlayer insulating layer 21.

  When a film residue of the interlayer insulating layer 21 is detected, the first inspection metal layer 27 is less likely to be oxidized than the semiconductor layer 13 as in the first embodiment, and thus the film residue of the interlayer insulating layer 21 is detected. The electrical resistance having a magnitude corresponding to the thickness of the interlayer insulating layer 21 can be measured, and the thickness of the remaining film of the interlayer insulating layer 21 can be accurately obtained based on the electrical resistance. Therefore, the same effect as in the first embodiment can be obtained.

<< Other Embodiments >>
In each of the above-described embodiments, a pair of inspection contact holes 21b for exposing the first inspection metal layer 27 is formed in the interlayer insulating layer 21, and the surface of the interlayer insulating layer 21 is formed from the inside of each of the inspection contact holes 21b. The second inspection metal layer 28 is formed in a pair and is measured to measure the electric capacity or electric resistance between the pair of second inspection metal layers 28. However, the present invention is not limited to this, One inspection contact hole is formed in the interlayer insulating layer, and one second inspection metal layer is formed by drawing from the inside of the inspection contact hole to the surface of the interlayer insulating layer. One end portion may be exposed from the interlayer insulating layer, and the electric capacity or electric resistance between the first inspection metal layer and the one end portion of the second inspection metal layer may be measured. As a result, the first inspection metal is measured. Layer and second inspection The capacitance or electrical resistance between the use metallic layer need only be measured.

  In each of the above embodiments, the contact holes 21a and the inspection contact holes 21b are formed in both the gate insulating film 14 and the interlayer insulating film 19 constituting the interlayer insulating layer 21, but the present invention is not limited to this. The insulating film may be formed only in a region overlapping with each gate electrode, and each contact hole and each inspection contact hole may be formed in a region of the interlayer insulating layer constituted only by the interlayer insulating film. In this way, when the remaining film thickness of the interlayer insulating layer is detected in the fourth step and the thickness of the remaining film thickness of the interlayer insulating layer is obtained, the contact hole and the inspection hole are formed in the interlayer insulating layer constituted by a plurality of films. When a contact hole is formed, it is necessary to consider each dielectric constant or electrical resistivity of a plurality of films constituting the interlayer insulating layer, whereas a single film (interlayer insulating layer) is formed. Therefore, the remaining thickness of the interlayer insulating layer can be obtained more easily.

  In each of the above embodiments, the active matrix substrate 10 in which the TFTs 23 and 24 are formed on the substrate 11 is described as an example of the semiconductor device according to the present invention. However, the present invention is not limited to this, and the semiconductor layer is formed on the substrate. And an interlayer insulating layer laminated on the semiconductor layer, and a metal layer is drawn from the inside of the contact hole formed in the interlayer insulating layer to the surface of the interlayer insulating layer to expose a part of the semiconductor layer The present invention can also be applied to other semiconductor devices having a structure.

  As described above, the present invention is useful for a semiconductor device and a method for manufacturing the same, and in particular, detects a film residue in a region where a contact hole is formed in an interlayer insulating layer, and detects the film residue of the interlayer insulating layer. It is suitable for a semiconductor device and a method for manufacturing the same that are required to obtain a thickness with high accuracy.

1 is a plan view schematically showing a liquid crystal display device of Embodiment 1. FIG. It is a figure which shows schematically the II-II sectional view taken on the line of FIG. It is sectional drawing which shows roughly each TFT and test | inspection pattern which were provided in the active matrix substrate. It is sectional drawing which shows roughly a part of glass mother substrate in the state in which the metal layer for 1st inspection and the polysilicon film were formed. It is sectional drawing which shows roughly a part of glass mother substrate in the state in which the gate insulating film and the gate electrode were formed. It is sectional drawing which shows roughly the state which is inject | pouring the P-type impurity element into the semiconductor layer of a p-type TFT area | region. It is sectional drawing which shows roughly the state which is inject | pouring the N-type impurity element into each semiconductor layer. It is sectional drawing which shows roughly a part of glass mother substrate in the state by which the interlayer insulation film was laminated | stacked. It is sectional drawing which shows roughly a part of glass mother substrate in the state in which each metal layer and each 2nd metal layer for a test | inspection were formed. 1 is a plan view schematically showing an active matrix mother substrate of Embodiment 1. FIG. It is a top view which shows a counter mother board | substrate schematically. FIG. 2 is a plan view schematically showing a liquid crystal display mother panel of Embodiment 1. It is a top view which shows roughly the dividing line of a liquid crystal display mother panel. FIG. 6 is a plan view schematically showing an active matrix mother substrate of Embodiment 2.

Explanation of symbols

S Liquid crystal display device 10 Active matrix substrate (semiconductor device)
11 Glass substrate (substrate)
DESCRIPTION OF SYMBOLS 13 Semiconductor layer 14 Gate insulating film 15 Gate electrode 19 Interlayer insulating film 20 Insulating film 21 Interlayer insulating layer 21a Contact hole 21b Inspection contact hole 22 Metal layer 22s Source electrode 22d Drain electrode 23 TFT (Thin film transistor)
24 CMOS structure TFT (Thin Film Transistor)
24p p-type TFT
24n n-type TFT
27 First metal layer for inspection 28 Second metal layer for inspection 50, 52 Active matrix mother substrate 51 Glass mother substrate (substrate)

Claims (6)

A semiconductor layer provided on the substrate; an interlayer insulating layer formed on the semiconductor layer to form a contact hole for exposing a part of the semiconductor layer; and the contact hole formed on the surface of the interlayer insulating layer. A method of manufacturing a semiconductor device comprising a metal layer drawn from the inside,
Forming a first inspection metal layer made of the semiconductor layer and a metal material that is less likely to be oxidized than the semiconductor layer on the substrate;
After forming an insulating film so as to cover the semiconductor layer and the first inspection metal layer, an inspection contact for forming the contact hole in the insulating film and exposing a part of the first inspection metal layer A second step of forming the interlayer insulating layer by forming holes;
A third step of forming, on the interlayer insulating layer, a second inspection metal layer drawn from the inside of the metal layer and the inspection contact hole to the surface of the interlayer insulating layer;
And a fourth step of inspecting the formation state of the inspection contact hole by measuring electrical characteristics between the first inspection metal layer and the second inspection metal layer. A method for manufacturing a semiconductor device. In the manufacturing method of the semiconductor device according to claim 1,
In the second step, a pair of the inspection contact holes are formed,
In the third step, a pair of the second inspection metal layers are formed by being drawn out from the inside of the inspection contact holes to the surface of the interlayer insulating layer,
In the fourth step, an electrical characteristic between the pair of second inspection metal layers is measured. In the manufacturing method of the semiconductor device according to claim 1,
In the fourth step, a capacitance between the first inspection metal layer and the second inspection metal layer is measured. In the manufacturing method of the semiconductor device according to claim 1,
In the fourth step, an electrical resistance between the first inspection metal layer and the second inspection metal layer is measured. In the manufacturing method of the semiconductor device according to claim 1,
In the second step, a gate insulating film is formed so as to cover the semiconductor layer and the first inspection metal layer, a gate electrode is formed so as to overlap the semiconductor layer via the gate insulating film, Forming an interlayer insulating film so as to cover the gate electrode forms the insulating film composed of the gate insulating film and the interlayer insulating film, and pairs the contact holes so as to sandwich the gate electrode with respect to the insulating film. Forming the interlayer insulating layer,
In the third step, a thin film transistor is formed by forming a pair of the metal layers by pulling out from the contact holes to the surface of the interlayer insulating layer. A semiconductor layer provided on a substrate;
An interlayer insulating layer formed on the semiconductor layer and having a contact hole for exposing a part of the semiconductor layer;
A semiconductor device comprising a metal layer drawn from the inside of the contact hole on the surface of the interlayer insulating layer,
A first inspection metal layer made of a metal material that is less likely to be oxidized than the semiconductor layer is provided between the substrate and the interlayer insulating layer,
A second inspection metal layer is provided on the surface of the interlayer insulating layer,
The interlayer insulating layer is formed with an inspection contact hole for exposing a part of the first inspection metal layer,
The semiconductor device according to claim 2, wherein the second inspection metal layer is drawn from the inside of the inspection contact hole to the surface of the interlayer insulating layer.

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