JP2010027637A - Conductor paste, and method of manufacturing ceramic substrate using the same - Google Patents

Conductor paste, and method of manufacturing ceramic substrate using the same Download PDF

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JP2010027637A
JP2010027637A JP2008183486A JP2008183486A JP2010027637A JP 2010027637 A JP2010027637 A JP 2010027637A JP 2008183486 A JP2008183486 A JP 2008183486A JP 2008183486 A JP2008183486 A JP 2008183486A JP 2010027637 A JP2010027637 A JP 2010027637A
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conductor paste
ceramic substrate
conductor
hole
paste
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Takashi Aihara
隆史 相原
Atsushi Shigemi
淳 重見
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Panasonic Corp
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Panasonic Corp
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a conductor paste and a method of manufacturing a ceramic substrate using the paste reducing a void in a through-hole in the burned ceramic substrate having the through-hole. <P>SOLUTION: In the method of manufacturing the ceramic substrate, carrying out burning treatment by filling the through-hole in the burned ceramic substrate having the through-hole with the conductor paste, the conductor paste is used, containing: a conductive metal powder; an organic component; and a solvent, wherein metal coagulation products are each formed by joining together some of particles of conductive metal powder with the organic component and the average grain diameter of the metal coagulation products is in a range of 20-52 μm. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

本発明は、導体ペースト及びその導体ペーストを用いたセラミック基板の製造方法に関するものである。特に、導体ペーストが充填された貫通孔にボイドがないセラミック基板の製造方法に関する。   The present invention relates to a conductor paste and a method for manufacturing a ceramic substrate using the conductor paste. In particular, the present invention relates to a method for manufacturing a ceramic substrate having no voids in a through hole filled with a conductive paste.

図5に、従来の導体ペーストの製造方法を示す。図中の第1の工程5は、金属粉末1と有機成分2と溶剤3を混練して混練済み導体ペースト4を得る工程である。次の第2の工程25では、第1の工程5で得た混練済み導体ペースト4を溶剤3によって粘度調整を行い、導体ペースト30を得る。   FIG. 5 shows a conventional method for producing a conductor paste. The first step 5 in the figure is a step of kneading the metal powder 1, the organic component 2 and the solvent 3 to obtain a kneaded conductor paste 4. In the next second step 25, the viscosity of the kneaded conductor paste 4 obtained in the first step 5 is adjusted with the solvent 3 to obtain the conductor paste 30.

図6に、従来のセラミック基板の製造方法を示す。図中の第1の工程18は、焼成済みのセラミック基板15に貫通孔16を設けた貫通孔付焼成済みセラミック基板17を準備する工程である。第2の工程33は、貫通孔16に図5で得られた導体ペースト30を充填し、導体ペースト30が焼成できる温度で焼成して充填済みセラミック基板32を得る工程である。導体ペースト30の充填方法は、一般に印刷方法が用いられる。次の第3の工程35では、充填済みセラミック基板32表面の貫通孔16の両端に所望の表層導体21を形成した後、この表層導体21が焼成できる温度で焼成する。このようにして表層導体付セラミック基板34を得る。表層導体21の形成方法は、一般に印刷方法が用いられる。次の第4の工程37にて、表層導体21の表面にメッキ層24を形成して、完成されたセラミック基板36を得る。   FIG. 6 shows a conventional method for manufacturing a ceramic substrate. The first step 18 in the figure is a step of preparing a fired ceramic substrate 17 with through holes provided with through holes 16 in the fired ceramic substrate 15. The second step 33 is a step of filling the through-hole 16 with the conductor paste 30 obtained in FIG. 5 and firing it at a temperature at which the conductor paste 30 can be fired to obtain a filled ceramic substrate 32. A printing method is generally used as a method of filling the conductor paste 30. In the next third step 35, the desired surface layer conductors 21 are formed at both ends of the through holes 16 on the surface of the filled ceramic substrate 32, and then fired at a temperature at which the surface layer conductors 21 can be fired. In this way, a ceramic substrate 34 with a surface layer conductor is obtained. A printing method is generally used as a method for forming the surface layer conductor 21. In the next fourth step 37, the plated layer 24 is formed on the surface of the surface conductor 21 to obtain a completed ceramic substrate 36.

以上のように作成されたセラミック基板36では、貫通孔16内に空隙(ボイド)の発生が見られる。このボイドが生じるメカニズムを、図7を用いて説明する。図7に、図6で説明したセラミック基板の製造方法での第1の工程から第4の工程における貫通孔16内の断面と充填された導体ペースト30の状態を模式的に示す。   In the ceramic substrate 36 prepared as described above, voids are generated in the through holes 16. The mechanism by which this void occurs will be described with reference to FIG. FIG. 7 schematically shows the cross section in the through hole 16 and the state of the filled conductor paste 30 in the first to fourth steps in the method of manufacturing the ceramic substrate described in FIG.

図中の第2の工程33は、貫通孔16内に印刷方法により充填された導体ペースト30の内部の金属粉末が偏り無く分散している状態を示す。このときはボイドが生じていない。図中の第2’の工程39は、導体ペースト30が乾燥した状態を示す。導体ペースト30の乾燥とは、その内部の溶剤が全て蒸発したために起こる。そのため、導体ペースト30の体積が減少すると同時に金属粉末1が矢印の様に中央に向かって移動する。このため、導体ペースト30の表面に大きなボイド38が発生する。ここで生じたボイド38は、導体ペースト30を焼成してもその形が保たれる。また、次の第3の工程で、貫通孔16の導体ペースト30の両端に表層導体21を形成しても、ボイド38を完全に埋めることはできない。   The second step 33 in the figure shows a state in which the metal powder inside the conductor paste 30 filled in the through holes 16 by the printing method is evenly dispersed. At this time, no void is generated. A second 'step 39 in the drawing shows a state where the conductor paste 30 is dried. The drying of the conductive paste 30 occurs because all the solvent in the inside has evaporated. Therefore, the metal powder 1 moves toward the center as shown by the arrow at the same time as the volume of the conductor paste 30 decreases. For this reason, a large void 38 is generated on the surface of the conductor paste 30. The shape of the void 38 generated here is maintained even when the conductive paste 30 is fired. Further, even if the surface layer conductor 21 is formed at both ends of the conductor paste 30 in the through hole 16 in the next third step, the void 38 cannot be completely filled.

このようなボイドが生じると次のような問題が起こる。すなわち、後工程である第4の工程では、前記表層導体21の表面には、耐半田喰われ性と半田濡れ性を向上させるため、無電解のNi/Auメッキ層24を形成するが、ボイド38にNiメッキ液が侵入し残留することでAuメッキが形成されない状態(無メッキ)が発生する。このような無メッキ部分は、Niが表層部に露出しているので腐食が発生し半田濡れ性を悪化させる。またボイド32にメッキ液、洗浄液等が溜まることで、後工程の部品実装や半田ボ−ル実装等のリフロ−時に、メッキ液や洗浄液等が気化して半田内部に空洞ができる不良(半田ボイド)の原因にもなった。さらにボイド38が発生すると、貫通孔16内の導体ペースト30と表層導体21の接続強度が低下するので、貫通孔16内の導体ペースト30と表層導体21の接続信頼性が低下する。   When such voids occur, the following problems occur. That is, in the fourth step, which is a subsequent step, an electroless Ni / Au plating layer 24 is formed on the surface of the surface conductor 21 in order to improve solder erosion resistance and solder wettability. When the Ni plating solution enters and remains in 38, a state where no Au plating is formed (no plating) occurs. In such a non-plated portion, since Ni is exposed on the surface layer portion, corrosion occurs and deteriorates the solder wettability. In addition, the plating solution, cleaning solution, etc. accumulate in the void 32, so that the plating solution, the cleaning solution, etc. are vaporized during the subsequent reflow process such as component mounting or solder ball mounting. ). Further, when the void 38 is generated, the connection strength between the conductor paste 30 in the through hole 16 and the surface layer conductor 21 is lowered, so that the connection reliability between the conductor paste 30 in the through hole 16 and the surface layer conductor 21 is lowered.

従来、貫通孔16内のボイド38を防止する方法としては、図8に示す技術が知られている。これは、導体ペーストの粒子径を調整することでボイドの防止を行っている。平均粒径が2μm以下の第1の金属粉末34と、平均粒径が5〜10μmの第2の金属粉末35とからなる導体ペーストを使用することが開示されている(例えば、特許文献1参照。)。
特開平8−97528号公報
Conventionally, the technique shown in FIG. 8 is known as a method for preventing the void 38 in the through hole 16. This prevents voids by adjusting the particle size of the conductor paste. It is disclosed to use a conductor paste composed of a first metal powder 34 having an average particle diameter of 2 μm or less and a second metal powder 35 having an average particle diameter of 5 to 10 μm (for example, see Patent Document 1). .).
JP-A-8-97528

しかし、前記従来の構成では、導体ペーストとグリーンシートとを同時に焼成する場合には有効であるが、焼成済みセラミック基板に適用すると、ボイド発生を完全に抑制することができないという課題を有していた。   However, the conventional configuration is effective when the conductor paste and the green sheet are fired at the same time. However, when applied to a fired ceramic substrate, there is a problem that void generation cannot be completely suppressed. It was.

本発明は、前記従来の課題を解決するもので、貫通孔付焼成済みセラミック基板における貫通孔内のボイドを抑えるための導体ペースト及びそれを用いたセラミック基板の製造方法を提供することを目的とする。   An object of the present invention is to solve the above-described conventional problems, and to provide a conductor paste for suppressing voids in a through-hole in a fired ceramic substrate with a through-hole and a method for manufacturing a ceramic substrate using the same. To do.

前記従来の課題を解決するために、本発明の導電性を持つ金属粉末と有機成分及び溶剤を含有する導体ペーストにおいて、前記金属粉末同士を前記有機成分にて結合させた平均粒径20〜52μmの金属凝集物を含むことを特徴としたものである。   In order to solve the conventional problems, in the conductive paste containing the conductive metal powder of the present invention, an organic component and a solvent, an average particle size of 20 to 52 μm in which the metal powder is bonded with the organic component. The metal agglomerates are included.

また、本発明は、貫通孔を備えた焼成済みセラミック基板の前記貫通孔に導体ペーストを充填し焼成処理を行うセラミック基板の製造方法において、前記導体ペーストは請求項1から2に記載の導体ペーストを用いることを特徴としたものである。   Moreover, this invention is a manufacturing method of the ceramic substrate which fills the said through-hole of the baked ceramic board | substrate provided with the through-hole, and performs a baking process, The said conductive paste is a conductor paste of Claim 1 to 2 It is characterized by using.

本発明の導体ペースト及びそれを用いたセラミック基板の製造方法によれば、貫通孔付焼成済みセラミック基板17の貫通孔16内に導体ペーストを充填した時に発生するボイドを効果的に抑えることで、表層導体21の表面のメッキ24に発生する無メッキや、部品を半田により実装する時に発生する半田ボイドを抑え、また貫通孔16内の導体ペーストと表層導体21の接続信頼性が高いセラミック基板を製造することが出来る。   According to the conductor paste of the present invention and the method of manufacturing a ceramic substrate using the same, by effectively suppressing voids generated when the conductor paste is filled into the through holes 16 of the fired ceramic substrate 17 with through holes, A ceramic substrate that suppresses non-plating that occurs in the plating 24 on the surface of the surface conductor 21 and solder voids that occur when components are mounted by soldering, and that has high connection reliability between the conductor paste in the through hole 16 and the surface conductor 21. Can be manufactured.

以下、本発明の実施の形態について、図面と表を用いて詳細に説明する。なお、従来と同じものについては、同符号を用い説明を簡略化している。   Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings and tables. In addition, about the same thing as the past, description is simplified using the same code | symbol.

(実施の形態1)
本発明の導体ペーストの作製方法を図1に示す。図中の第1の工程5は、金属粉末1と有機成分2と溶剤3とを混合して、混練済み導体ペースト4を作製する工程である。金属粉末1には、Ag、Pt、Pd、Auの中から少なくとも1つ以上の金属粉末を使用する。
(Embodiment 1)
A method for producing the conductor paste of the present invention is shown in FIG. The first step 5 in the figure is a step of preparing the kneaded conductor paste 4 by mixing the metal powder 1, the organic component 2 and the solvent 3. As the metal powder 1, at least one metal powder from Ag, Pt, Pd, and Au is used.

本実施例では、平均粒径8μmのAgを主成分とし、さらにPdを数%添加した。有機成分2は、エチルセルロースを使用したが、特にこれに限定されることはない。溶剤3は、ターピネオールを使用したが、これに限るものではなく有機成分2を溶解できる物質であれば良い。混練済み導体ペースト4の作製には、金属粉末1と有機成分2と溶剤3を十分に分散させるために3本ロールにより混練を行い作製した。   In this example, Ag having an average particle diameter of 8 μm was used as a main component, and Pd was further added by several percent. Although the organic component 2 used ethyl cellulose, it is not particularly limited to this. The solvent 3 is terpineol, but is not limited to this, and any material that can dissolve the organic component 2 may be used. The kneaded conductor paste 4 was produced by kneading with three rolls in order to sufficiently disperse the metal powder 1, the organic component 2 and the solvent 3.

次の第2の工程10は、混練済み導体ペースト4から凝集物9を作製する工程である。この工程では、第1の工程5で作製した混練済み導体ペースト4を乾燥6した後、粉砕7して粉末化する。その後、整粒8して凝集物9を得る。本実施例では、乾燥6を150℃で1時間行い、乳鉢にて粉砕7を行った。また、今回のサンプルの整粒8には分子ふるいを使用した。開口が20μmと52μmと90μmの3種類の分子ふるいにより、3種類の粒径をもつ凝集物9(20μm以下、20〜52μm及び52〜90μm)を作製した。   The next second step 10 is a step of producing an aggregate 9 from the kneaded conductor paste 4. In this step, the kneaded conductor paste 4 produced in the first step 5 is dried 6 and then pulverized 7 to be powdered. Thereafter, the size is adjusted 8 to obtain an aggregate 9. In this example, drying 6 was performed at 150 ° C. for 1 hour, and pulverization 7 was performed in a mortar. Moreover, the molecular sieve was used for the sizing 8 of this sample. Aggregates 9 (20 μm or less, 20 to 52 μm and 52 to 90 μm) having three types of particle diameters were prepared by three types of molecular sieves having openings of 20 μm, 52 μm, and 90 μm.

次の第3の工程12では、第2の工程10で得られた凝集物9と第1の工程5で得られた混練済み導体ペースト4とを混合し、凝集物添加済み導体ペースト11を得る。このときの凝集物9の粒径と添加量とが重要なので、詳細は後述する。   In the next third step 12, the agglomerate 9 obtained in the second step 10 and the kneaded conductor paste 4 obtained in the first step 5 are mixed to obtain the agglomerate-added conductor paste 11. . Since the particle size and added amount of the aggregate 9 at this time are important, details will be described later.

最後の第4の工程14では、第3の工程12で得られた凝集物添加済み導体ペースト11に溶剤3を入れて粘度調整を行い、セラミック基板に使用するための導体ペースト13を得る。これは、凝集物添加済み導体ペースト11の固形分の含有比率が高いので、粘度が高いためである。一般に印刷工法で使用するための導体ペーストの粘度は500P
a・s以下が望ましい。
In the final fourth step 14, the solvent 3 is added to the aggregate-added conductor paste 11 obtained in the third step 12, and the viscosity is adjusted to obtain a conductor paste 13 for use in a ceramic substrate. This is because the viscosity is high because the solid content of the aggregated conductor paste 11 is high. Generally, the viscosity of the conductor paste for use in the printing method is 500P
A · s or less is desirable.

図2に、第4の工程14で作製した導体ペースト13を用いるセラミック基板の製造方法を示す。第1の工程18は、焼成済みセラミック基板15に貫通孔16を設けて、貫通孔付焼成済みセラミック基板17を得る工程である。具体的には焼成済みセラミック基板15の素材としては、アルミナ、窒化アルミ、ガラスセラミック等が上げられる。焼成済みセラミック基板15の基板サイズは、一般に4インチサイズと言われる一辺4インチのサイズを使用した。本実施例での基板厚みは、0.8mmとした。貫通孔16のサイズは0.3mmφ、貫通孔16同士のピッチは1.27mmとし、貫通孔16は、レーザー加工で作製した。   FIG. 2 shows a method for manufacturing a ceramic substrate using the conductive paste 13 produced in the fourth step 14. The first step 18 is a step of providing a through-hole 16 in the fired ceramic substrate 15 to obtain a fired ceramic substrate 17 with a through-hole. Specifically, examples of the material of the fired ceramic substrate 15 include alumina, aluminum nitride, and glass ceramic. The substrate size of the fired ceramic substrate 15 was a size of 4 inches on a side, which is generally called a 4 inch size. The substrate thickness in this example was 0.8 mm. The size of the through holes 16 was 0.3 mmφ, the pitch between the through holes 16 was 1.27 mm, and the through holes 16 were produced by laser processing.

第2の工程20は、貫通孔付焼成済みセラミック基板17の貫通孔16に導体ペースト13を充填し、導体ペースト13の焼成温度で焼成して充填済みセラミック基板19を得る工程である。貫通孔16への導体ペースト13の充填は印刷工法で行った。印刷工法で使用する製版は0.1mmtのメタルマスクを使用した。導体ペースト13の焼成温度は850℃で行った。   The second step 20 is a step of filling the through holes 16 of the fired ceramic substrate 17 with through holes with the conductor paste 13 and firing at the firing temperature of the conductor paste 13 to obtain a filled ceramic substrate 19. Filling the through holes 16 with the conductor paste 13 was performed by a printing method. The plate making used in the printing method used a 0.1 mmt metal mask. The firing temperature of the conductor paste 13 was 850 ° C.

第3の工程23は、充填済みセラミック基板19の貫通孔16の両面に、表層導体21を形成した後、表層導体21の焼成温度で焼成し、表層導体付セラミック基板22を得る工程である。表層導体21の形成は、Agを主成分としたペーストを用いて、印刷工法で行った。また表層導体21の焼成は850℃で行った。   The third step 23 is a step in which the surface layer conductor 21 is formed on both surfaces of the through hole 16 of the filled ceramic substrate 19 and then fired at the firing temperature of the surface layer conductor 21 to obtain the ceramic substrate 22 with the surface layer conductor. The surface conductor 21 was formed by a printing method using a paste mainly composed of Ag. The surface conductor 21 was fired at 850 ° C.

第4の工程26は、表層導体21の表面にメッキ層24を形成し、セラミック基板25を得る工程である。メッキ層24は無電解のNi/Auメッキで形成した。   The fourth step 26 is a step of forming the plated layer 24 on the surface of the surface layer conductor 21 to obtain the ceramic substrate 25. The plating layer 24 was formed by electroless Ni / Au plating.

図1の凝集物添加済み導体ペースト11を得る工程で説明したとおり、凝集物9の粒径と添加量とが、導体ペースト13を充填した貫通孔16内のボイドの発生に大きく関与する。以下、その詳細を説明する。   As described in the step of obtaining the aggregate-added conductor paste 11 of FIG. 1, the particle size and the amount of the aggregate 9 are greatly involved in the generation of voids in the through holes 16 filled with the conductor paste 13. Details will be described below.

図1の第2の工程10で得られた3種類の粒径をもつ凝集物9(20μm以下、20〜52μm及び52〜90μm)を第1の工程5で得られた混練済み導体ペースト4に加え、そのときの添加量を0から40wt%まで変化させた導体ペースト13を用意した。これらの導体ペースト13を使用して図2の製造方法で、充填済みセラミック基板19を作製した。この充填済みセラミック基板19の貫通孔16内のボイドの発生と印刷時の粘度との関係を次のように評価した。   The aggregate 9 (20 μm or less, 20 to 52 μm and 52 to 90 μm) having three kinds of particle diameters obtained in the second step 10 of FIG. 1 is added to the kneaded conductor paste 4 obtained in the first step 5. In addition, a conductor paste 13 was prepared in which the addition amount at that time was changed from 0 to 40 wt%. Using these conductor pastes 13, a filled ceramic substrate 19 was manufactured by the manufacturing method of FIG. The relationship between the generation of voids in the through holes 16 of the filled ceramic substrate 19 and the viscosity during printing was evaluated as follows.

ボイドの有無の確認は、導体ペースト13の焼成後に、まず表面状態を目視確認で、内部状態をX線検査装置で確認した。目視及びX線検査で表面ボイド38及び内部ボイド29が確認されなかった基板は、○とした。目視で表面ボイド38が確認された基板は、×とした。目視では表面ボイド38は確認されなかったが、X線検査で内部ボイド29が確認された基板は××とした。また、印刷により、貫通孔内部へ導体ペーストによる充填ができない基板は、×××とした。尚、添加量で0wt%とは、混練済み導体ペースト4に凝集物9を添加していないものであり、従来混練済み導体ペースト4を意味する。   To confirm the presence or absence of voids, after firing the conductor paste 13, first the surface state was visually confirmed and the internal state was confirmed with an X-ray inspection apparatus. A substrate on which the surface voids 38 and the internal voids 29 were not confirmed by visual inspection and X-ray inspection was marked with ◯. The board | substrate with which the surface void 38 was confirmed visually was set as x. Although the surface void 38 was not visually confirmed, the substrate on which the internal void 29 was confirmed by the X-ray inspection was designated as xx. Moreover, the board | substrate which cannot be filled with a conductor paste inside a through-hole by printing was set to xxx. The addition amount of 0 wt% means that the aggregate 9 is not added to the kneaded conductor paste 4, and means the conventionally kneaded conductor paste 4.

凝集物9の粒径が20μm以下、20〜52μm、及び52〜90μmの場合の、添加量で0から40wt%に変化させたとき評価結果をそれぞれ表1、表2、及び表3に示す。   When the particle diameter of the aggregate 9 is 20 μm or less, 20 to 52 μm, and 52 to 90 μm, the evaluation results are shown in Table 1, Table 2, and Table 3 when the addition amount is changed from 0 to 40 wt%.

Figure 2010027637
Figure 2010027637

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Figure 2010027637
Figure 2010027637

表1の結果より、凝集物9の平均粒径が20μm以下では、添加量によらず、表面ボイド38の発生が見られるか、又は導体ペーストの印刷が出来なかった。すなわち、導体ペースト13の粘度が200〜500Pa・sの範囲では、表面ボイド38が発生しており、
導体ペースト13の粘度が600Pa・sの場合では、粘度が高すぎるため印刷が出来なかった。
From the results shown in Table 1, when the average particle size of the aggregate 9 was 20 μm or less, the generation of surface voids 38 was observed or the conductive paste could not be printed regardless of the addition amount. That is, in the range where the viscosity of the conductor paste 13 is 200 to 500 Pa · s, the surface void 38 is generated,
When the viscosity of the conductor paste 13 was 600 Pa · s, printing was not possible because the viscosity was too high.

表2の結果より、凝集物9の平均粒径が20μmから52μmの範囲では、添加量によらず、導体ペースト13の粘度が600Pa・sになると、表1と同様に印刷が出来なかった。また、導体ペースト13の粘度が400〜500Pa・sの範囲では、添加量を10〜30wt%にすると、表面ボイド38の発生が無く良好であった。導体ペースト13の粘度が300Pa・sでは、添加量を20〜30wt%の範囲で、表面ボイド38の発生が無く良好であった。その他の範囲では、表面ボイド38の発生が見られた。   From the results in Table 2, when the average particle size of the aggregate 9 was in the range of 20 μm to 52 μm, printing could not be performed in the same manner as in Table 1 when the viscosity of the conductor paste 13 was 600 Pa · s regardless of the amount added. Further, when the viscosity of the conductor paste 13 was in the range of 400 to 500 Pa · s, when the addition amount was 10 to 30 wt%, surface voids 38 were not generated, which was good. When the viscosity of the conductor paste 13 was 300 Pa · s, the addition amount was in the range of 20 to 30 wt%, and the surface voids 38 were not generated, which was good. In other ranges, generation of surface voids 38 was observed.

表3の結果より、凝集物9の平均粒径が52μmから90μmの範囲では、添加量によらず、表面ボイド38の発生が見られるか、又は導体ペーストの印刷が出来なかった。すなわち、導体ペースト13の粘度が200〜500Pa・sの範囲では、添加量が5wt%までなら表面ボイド38が発生しており、それ以上の添加量では、内部ボイド29が見られた。導体ペースト13の粘度が600Pa・sになると、表1と同様に印刷が出来なかった。   From the results in Table 3, when the average particle size of the aggregate 9 is in the range of 52 μm to 90 μm, the generation of surface voids 38 was observed or the conductor paste could not be printed regardless of the addition amount. That is, when the viscosity of the conductor paste 13 is in the range of 200 to 500 Pa · s, the surface void 38 is generated when the addition amount is up to 5 wt%, and the internal void 29 is observed when the addition amount is more than that. When the viscosity of the conductor paste 13 was 600 Pa · s, printing could not be performed as in Table 1.

本発明によるボイドの発生を抑制できるメカニズムを、図3と4とを用いて説明する。図3に、図2で説明した製造工程での第2の工程20から第4の工程26における貫通孔の断面模式図を示す。   A mechanism capable of suppressing the generation of voids according to the present invention will be described with reference to FIGS. FIG. 3 is a schematic cross-sectional view of the through hole in the second process 20 to the fourth process 26 in the manufacturing process described in FIG.

第2の工程20は、貫通孔16内に印刷方法により導体ペースト13を貫通孔16に充填する工程である。導体ペースト13は、図1の第2の工程で作成された凝集物9を含んでいる。この凝集物9は図1の第2の工程10で熱処理による乾燥で内部の有機成分2がゲル化し、その後に固まるために金属粉末1同士が団塊を作る。この金属粉末団塊となった凝集物9は、凝集物添加済み導体ペースト11を溶剤3により粘度調整した導体ペースト13を作成しても、硬化した有機成分2は再溶解することなく、導体ペースト13の内部に残る。   The second step 20 is a step of filling the through hole 16 with the conductive paste 13 by a printing method in the through hole 16. The conductive paste 13 includes the aggregate 9 created in the second step of FIG. The agglomerate 9 is dried by heat treatment in the second step 10 of FIG. 1 to gel the organic component 2 inside, and then the metal powders 1 form a nodule to solidify. The agglomerate 9 in the form of a metal powder nodule does not re-dissolve the cured organic component 2 even if the conductor paste 13 is prepared by adjusting the viscosity of the agglomerated conductor paste 11 with the solvent 3. Remain inside.

次の第2’の工程28は、導体ペースト13を乾燥した後の状態を示す。導体ペースト13を乾燥することで溶剤が揮発し、導体ペースト13体積が減少すると同時に、凝集物9と金属粉末1が矢印の様に中央に向かって移動しようとする。しかし凝集物9が大きな塊であるため、前記矢印方向の移動が阻害される、いわゆるブリッジング効果により貫通孔16内の導体ペースト13の表面に表面ボイド38が発生しない。   The next second step 28 shows a state after the conductor paste 13 is dried. When the conductive paste 13 is dried, the solvent is volatilized and the volume of the conductive paste 13 is reduced. At the same time, the aggregate 9 and the metal powder 1 try to move toward the center as shown by arrows. However, since the aggregate 9 is a large lump, the surface void 38 is not generated on the surface of the conductor paste 13 in the through hole 16 due to the so-called bridging effect in which the movement in the arrow direction is inhibited.

第3の工程23では、貫通孔16の表面に表層導体21を形成する工程であるが、表面ボイド38,内部ボイド29が発生していないため、良好な接続が確保される。さらに第4の工程26では表層導体21の表面に、メッキ層24を無電解のNi/Auメッキで形成する工程であるが、表面ボイド38,内部ボイド29が発生していないために、表面ボイド38,内部ボイド29にNiメッキ液が侵入し残留することでAuメッキが形成されない状態(無メッキ)は発生することはない。無メッキが発生しないため、半田濡れ性を悪化させることもなく、また表面ボイド38,内部ボイド29にメッキ液、洗浄液等が溜まることで、後工程の部品実装や半田ボ−ル実装等のリフロ−時に、メッキ液や洗浄液等が気化して半田内部に空洞ができる不良(半田ボイド)の発生もない。   The third step 23 is a step of forming the surface layer conductor 21 on the surface of the through hole 16. However, since the surface void 38 and the internal void 29 are not generated, a good connection is ensured. Further, in the fourth step 26, the plating layer 24 is formed on the surface of the surface conductor 21 by electroless Ni / Au plating. However, since the surface void 38 and the internal void 29 are not generated, the surface void is not generated. 38, the state in which the Au plating is not formed (no plating) does not occur when the Ni plating solution enters and remains in the internal void 29. Since no plating occurs, solder wettability is not deteriorated, and plating liquid, cleaning liquid, etc. are accumulated in the surface void 38 and the internal void 29, so that reflow for component mounting and solder ball mounting in a later process is performed. -Occasionally, there is no occurrence of defects (solder voids) in which the plating solution, the cleaning solution, etc. are vaporized and voids are formed inside the solder.

ところが、導体ペースト13に添加された凝集物9の添加量や粒径によっては貫通孔16内部に内部ボイド29が発生する。表2で示したように、導体ペースト13に添加された凝集物9の粒径が20〜52μmの場合では凝集物9の添加量が40wt%になると、内部ボイド29が発生した。また、表3で示したように、凝集物9の粒径が52〜90μmの場合では凝集物9の添加量が10wt%以上では、内部ボイド29が発生した。このメカニズムを、図4を用いて説明する。   However, an internal void 29 is generated inside the through hole 16 depending on the amount of the aggregate 9 added to the conductor paste 13 and the particle size. As shown in Table 2, when the particle size of the aggregate 9 added to the conductor paste 13 was 20 to 52 μm, the internal void 29 was generated when the added amount of the aggregate 9 was 40 wt%. Further, as shown in Table 3, when the particle size of the aggregate 9 is 52 to 90 μm, the internal void 29 is generated when the added amount of the aggregate 9 is 10 wt% or more. This mechanism will be described with reference to FIG.

図中の第2の工程20に示すように、貫通孔内での凝集物9の占める割合が大きくなる事により、凝集物9の間を埋める金属粉末1の割合が少なくなり、金属粉末1が疎の状態の部分27が発生する。この状態で、次の第2’の工程28の乾燥によって溶剤3が揮発すると、金属粉末1が疎の状態の部分27に内部ボイド29が発生する。一度生じた内部ボイド29は、表層導体21を形成する第3の工程23、及びメッキ層24を形成する第4の工程26においても、形状を保ったまま残存する。   As shown in the second step 20 in the figure, the proportion of the aggregate 9 in the through-hole increases, so that the proportion of the metal powder 1 filling the space between the aggregates 9 decreases, and the metal powder 1 A sparse part 27 occurs. In this state, when the solvent 3 is volatilized by drying in the next second 'step 28, an internal void 29 is generated in the portion 27 where the metal powder 1 is sparse. The internal void 29 once generated remains with its shape maintained in the third step 23 for forming the surface conductor 21 and the fourth step 26 for forming the plating layer 24.

表1から表3で示したように、表面ボイド38や内部ボイド29が発生しない条件が凝集物9の添加量や粒径によって変化するのは、以上のメカニズムが働くからである。すなわち、凝集物9の添加量が少ないとブリッジング効果が見られずに表面ボイド38が発生し、凝集物9添加量が多いと凝集物9の間を埋める金属粉末1の割合が減ることにより貫通孔の内部ボイド29が発生する。したがって、凝集物9添加量は、適切な範囲がある。本発明では、凝集物9の適切な添加量は、導体ペースト全体の10〜30wt%の範囲にあった。   As shown in Tables 1 to 3, the conditions under which the surface voids 38 and the internal voids 29 are not generated change depending on the addition amount and the particle size of the aggregate 9 because the above mechanism works. That is, when the addition amount of the aggregate 9 is small, the bridging effect is not observed, and the surface void 38 is generated. When the addition amount of the aggregate 9 is large, the ratio of the metal powder 1 filling between the aggregates 9 is reduced. An internal void 29 of the through hole is generated. Therefore, the aggregate 9 addition amount has an appropriate range. In the present invention, the appropriate amount of the agglomerate 9 is in the range of 10 to 30 wt% of the entire conductor paste.

また、凝集物9の粒径が小さいと、ブリッジング効果が見られずに表面ボイド38が発生する。一方、凝集物9の粒径が大きいと、凝集物9の間を埋める金属粉末1の割合が減ることにより貫通孔の内部ボイド29が発生する。したがって、凝集物9の粒径も適切な範囲でないといけない。本発明では、凝集物9の適切な平均粒径は、20〜52μmであった。   Moreover, when the particle size of the aggregate 9 is small, the surface void 38 is generated without the bridging effect. On the other hand, when the particle size of the aggregate 9 is large, the ratio of the metal powder 1 filling the space between the aggregates 9 is reduced, and the internal voids 29 of the through holes are generated. Therefore, the particle size of the aggregate 9 must be in an appropriate range. In the present invention, the appropriate average particle size of the aggregate 9 was 20 to 52 μm.

次に、本発明の導体ペーストを用いることによる貫通孔16内の導体の抵抗値への影響について表4を用いて説明する。表4における導体ペースト13の凝集物9の添加量が0〜40wt%、導体ペースト13の粘度が200〜500Pa・sの範囲は、貫通孔11に印刷形成可能な範囲である。サンプルは、表2に示す凝集物9の添加量が0〜40wt%の場合の、充填済みセラミック基板19の貫通孔16内の導体ペースト13のボイドの状態と、導体ペースト13の凝集物9の添加量が0〜40wt%と印刷時の粘度との関係を評価した時と同一である。貫通孔16内の導体の抵抗値は、第3の工程23で作成した表層導体付セラミック基板22で、低抵抗計を用いて4端子法にて測定を行った。測定は、貫通孔16内の表面ボイド38,内部ボイド29の有無にかかわらず行った。   Next, the influence of the conductor paste of the present invention on the resistance value of the conductor in the through hole 16 will be described with reference to Table 4. In Table 4, the range in which the added amount of the aggregate 9 of the conductor paste 13 is 0 to 40 wt% and the viscosity of the conductor paste 13 is 200 to 500 Pa · s is the range in which the through holes 11 can be printed. In the sample, when the addition amount of the aggregate 9 shown in Table 2 is 0 to 40 wt%, the void state of the conductor paste 13 in the through hole 16 of the filled ceramic substrate 19 and the aggregate 9 of the conductor paste 13 are shown. This is the same as the evaluation of the relationship between the addition amount of 0 to 40 wt% and the viscosity during printing. The resistance value of the conductor in the through hole 16 was measured by the 4-terminal method using a low resistance meter on the ceramic substrate 22 with a surface layer conductor prepared in the third step 23. The measurement was performed regardless of the presence or absence of the surface void 38 and the internal void 29 in the through hole 16.

Figure 2010027637
Figure 2010027637

測定の結果、表面ボイド38,内部ボイド29の発生が無い凝集物9の添加量が10〜15wt%で導体ペースト13の粘度が400〜500Pa・sと、凝集物9の添加量が20〜30wt%で導体ペースト13の粘度が300〜500Pa・sの範囲において、貫通孔16内の導体の抵抗値は0.6〜0.8mΩであるのに対して、表面ボイド38,内部ボイド29が発生しているその他の範囲も貫通孔16内の導体の抵抗値は0.6〜0.8mΩである。特に凝集物9を添加していない0wt%の場合でも、貫通孔16内の導体の抵抗値は0.6〜0.8mΩであり同等であるため、混練済み導体ペースト4に凝集物9を添加することによる貫通孔16内の導体の抵抗値への影響が無いことがわかる。   As a result of the measurement, the addition amount of the aggregate 9 without generation of the surface void 38 and the internal void 29 is 10 to 15 wt%, the viscosity of the conductor paste 13 is 400 to 500 Pa · s, and the addition amount of the aggregate 9 is 20 to 30 wt%. %, The resistance value of the conductor in the through hole 16 is 0.6 to 0.8 mΩ in the range of 300 to 500 Pa · s of the viscosity of the conductor paste 13, whereas the surface void 38 and the internal void 29 are generated. In other ranges, the resistance value of the conductor in the through hole 16 is 0.6 to 0.8 mΩ. In particular, even in the case of 0 wt% in which no agglomerate 9 is added, the resistance value of the conductor in the through hole 16 is 0.6 to 0.8 mΩ, which is equivalent, so the agglomerate 9 is added to the kneaded conductor paste 4 It can be seen that there is no influence on the resistance value of the conductor in the through hole 16 by doing so.

本発明にかかる導体ペースト及びその導体ペーストを用いたセラミック基板の製造方法は、導体ペーストが充填された貫通孔にボイドがないセラミック基板の製造に有用である。また本発明によって得られたセラミック基板は、特にボイドによって発生するメッキ不良や半田ボイドの低減に有用である。   The conductor paste and the method for producing a ceramic substrate using the conductor paste according to the present invention are useful for producing a ceramic substrate having no voids in the through holes filled with the conductor paste. The ceramic substrate obtained by the present invention is particularly useful for reducing plating defects and solder voids generated by voids.

本発明の実施の形態1に示す導体ペーストの製造工程図Manufacturing process diagram of conductor paste shown in Embodiment 1 of the present invention 本発明の実施の形態1に示すセラミック基板の製造工程図Manufacturing process diagram of ceramic substrate shown in Embodiment 1 of the present invention 本発明の実施の形態1に示すセラミック基板の製造工程の詳細図Detailed view of the manufacturing process of the ceramic substrate shown in Embodiment 1 of the present invention 本発明の実施の形態1に示すセラミック基板の製造工程の詳細図Detailed view of the manufacturing process of the ceramic substrate shown in Embodiment 1 of the present invention 従来の導体ペーストの製造工程図Manufacturing process diagram of conventional conductor paste 従来のセラミック基板の製造工程図Manufacturing process diagram of conventional ceramic substrate 従来のセラミック基板の製造工程の詳細図Detailed view of conventional ceramic substrate manufacturing process 特許文献1の導体ペーストの断面図Sectional drawing of the conductor paste of patent document 1

符号の説明Explanation of symbols

1 金属粉末
2 有機成分
3 溶剤
4 混練済み導体ペースト
9 凝集物
11 凝集物添加済み導体ペースト
13 導体ペースト
15 セラミック基板
16 貫通孔
21 表層導体
24 メッキ
29 内部ボイド
38 表面ボイド
DESCRIPTION OF SYMBOLS 1 Metal powder 2 Organic component 3 Solvent 4 Kneaded conductor paste 9 Aggregate 11 Aggregate-added conductor paste 13 Conductor paste 15 Ceramic substrate 16 Through-hole 21 Surface layer conductor 24 Plating 29 Internal void 38 Surface void

Claims (3)

導電性を持つ金属粉末と有機成分及び溶剤を含有する導体ペーストにおいて、
前記金属粉末同士を前記有機成分にて結合させた平均粒径20〜52μmの金属凝集物を含む導体ペースト。
In a conductive paste containing conductive metal powder and organic components and solvent,
A conductor paste comprising metal aggregates having an average particle size of 20 to 52 μm, wherein the metal powders are bonded together by the organic component.
前記金属凝集物は、前記導体ペースト全体の10〜30wt%の範囲にある請求項1に記載の導体ペースト。 2. The conductor paste according to claim 1, wherein the metal aggregate is in a range of 10 to 30 wt% of the entire conductor paste. 貫通孔を備えた焼成済みセラミック基板の前記貫通孔に導体ペーストを充填し焼成処理を行うセラミック基板の製造方法において、
前記導体ペーストは請求項1から2に記載の導体ペーストを用いるセラミック基板の製造方法。
In the method for manufacturing a ceramic substrate, a conductive paste is filled in the through-hole of the fired ceramic substrate having a through-hole and a firing process is performed.
The said conductive paste is a manufacturing method of the ceramic substrate using the conductive paste of Claim 1 or 2.
JP2008183486A 2008-07-15 2008-07-15 Conductor paste, and method of manufacturing ceramic substrate using the same Pending JP2010027637A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20140095083A (en) * 2011-11-03 2014-07-31 세람테크 게엠베하 Circuit board made of ain with copper structures
CN110730574A (en) * 2018-07-17 2020-01-24 株式会社日立电力解决方案 Double-sided circuit non-oxide ceramic substrate and method for producing same

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20140095083A (en) * 2011-11-03 2014-07-31 세람테크 게엠베하 Circuit board made of ain with copper structures
JP2014532996A (en) * 2011-11-03 2014-12-08 セラムテック ゲゼルシャフト ミット ベシュレンクテル ハフツングCeramTec GmbH Circuit board made of AlN having a copper structure
KR102029901B1 (en) * 2011-11-03 2019-10-08 세람테크 게엠베하 Circuit board made of ain with copper structures
CN110730574A (en) * 2018-07-17 2020-01-24 株式会社日立电力解决方案 Double-sided circuit non-oxide ceramic substrate and method for producing same
US12028984B2 (en) 2018-07-17 2024-07-02 Hitachi Power Solutions Co., Ltd. Double-sided circuit non-oxide-based ceramic substrate and method for manufacturing same

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