JP2010021207A - Semiconductor device and fabrication process therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device which fully controls interference between adjacent nodes at the opposite ends of trench isolation by reducing the routing resistance of a buried conductive layer in a trench, and to provide a fabrication process therefor. <P>SOLUTION: A semiconductor substrate SUB includes a major surface in which a trench TR for element isolation is provided. The trench TR is filled with a buried conductive layer BC. A silicide layer SC is formed to touch the buried conductive layer BC. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a semiconductor device having a buried conductive layer embedded in a trench for element isolation and a method for manufacturing the same.

  In devices with trench isolation, the trench isolation width scales as the device scales. For example, in a 45 nm node SoC (System on Chip) which is the latest state-of-the-art logic, the trench isolation width is said to be 70 nm, and the next generation is said to be 50 nm. At this time, there is a concern about interference caused by capacitive coupling between the nodes formed on both sides of the trench isolation (potential fixed or floating) between the trench-embedded oxide films.

  In order to avoid this, so-called polysilicon buried FS (Field Shield) -STI (Shallow Trench Isolation) is used. That is, the above-described interference due to capacitive coupling is suppressed by embedding polysilicon doped with impurities (hereinafter referred to as doped polysilicon) in the trench isolation and fixing the potential.

The structure in which a conductive layer is embedded in the trench in such trench isolation is disclosed in, for example, Japanese Patent Application Laid-Open Nos. 2001-148418, 2000-31268, and International Publication No. 2006/046442.
JP 2001-148418 A JP 2000-31268 A International Publication No. 2006/046442 Pamphlet

  However, the contact for fixing the potential of the buried conductive layer made of doped polysilicon buried in the trench in the FS-STI is, for example, a logic-equipped SRAM (Static Random Access Memory) memory array. It is formed where the buried conductive layer is drawn to the periphery. For this reason, so-called wiring resistance increases, and a considerable potential drop occurs near the center of the memory array. As a result, the potential of the buried conductive layer cannot be sufficiently fixed near the center of the memory array, and there is a possibility that the interference due to the capacitive coupling cannot be sufficiently suppressed.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a semiconductor capable of sufficiently suppressing interference between adjacent nodes at both ends of trench isolation by reducing the wiring resistance of the buried conductive layer. An apparatus and a method for manufacturing the same are provided.

  The semiconductor device of this embodiment includes a semiconductor substrate, a buried conductive layer, and a first silicide layer. The semiconductor substrate has a main surface, and has a trench for element isolation on the main surface. The buried conductive layer fills the trench. The first silicide layer is formed in contact with the buried conductive layer.

  According to the semiconductor device of the present embodiment, since the first silicide layer is formed so as to be in contact with the buried conductive layer embedded in the trench, the wiring resistance of the buried conductive layer is reduced by this first silicide layer. Therefore, the potential of the buried conductive layer can be sufficiently fixed.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a cross-sectional view schematically showing a configuration of a semiconductor device according to an embodiment of the present invention. Referring to FIG. 1, for example, trench isolation is formed on the main surface of semiconductor substrate SUB having p-type conductivity. A CMOS (Complementary Metal Oxide Semiconductor) transistor, for example, is formed on the main surface of the semiconductor substrate SUB where the trench isolation is formed.

  The trench isolation includes an element isolation trench TR, an in-trench insulating layer TI, and a buried conductive layer BC. Trench TR is formed on the main surface of semiconductor substrate SUB. The buried conductive layer BC is made of doped polysilicon, for example, and fills the trench TR. The in-trench insulating layer TI is made of, for example, a silicon oxide film, a silicon oxynitride film, or the like, and is formed along the wall surface of the trench TR between the trench TR and the buried conductive layer BC.

  The CMOS transistor is composed of an n-channel MOS transistor (hereinafter referred to as an nMOS transistor) NT and a p-channel MOS transistor (hereinafter referred to as a pMOS transistor) PT.

The nMOS transistor NT mainly has a pair of n ⁺ source / drain regions (impurity regions) SD1, a pair of Extension / Halo regions EH1, a gate oxide film GI, and a gate electrode (conductive layer) GE. ing.

A p-type well WE1 is formed in the formation region of the nMOS transistor NT on the p-type semiconductor substrate SUB. A pair of n ⁺ source / drain regions SD1 are formed on the surface of the p-type well WE1 at a distance from each other. Each of the pair of Extension / Halo regions EH1 is formed in contact with each of the pair of n ⁺ source / drain regions SD1. The Extension region and the Halo region are of opposite conductivity types. In the nMOS transistor NT, the Extension region is an n-type impurity region, and the Halo region is a p-type impurity region. In FIG. 1, only the Extension area is shown as Extension / Halo area EH1. The gate electrode GE is made of, for example, doped polysilicon doped with n-type impurities, and a gate oxide film (silicon oxide film) is formed on the region of the semiconductor substrate SUB sandwiched between a pair of n ⁺ source / drain regions SD1. It is formed via GI.

  A sidewall insulating layer SW is formed on the main surface of the semiconductor substrate SUB so as to cover the sidewall of the gate electrode GE. Sidewall insulating layer SW is made of, for example, a silicon oxide film or a silicon nitride film. The Extension / Halo region EH1 is located below the side wall insulating layer SW.

The pMOS transistor PT mainly has a pair of p ⁺ source / drain regions (impurity regions) SD2, a pair of Extension / Halo regions EH2, a gate oxide film GI, and a gate electrode (conductive layer) GE. ing.

An n-type well WE2 is formed in the formation region of the pMOS transistor PT on the p-type semiconductor substrate SUB. A pair of p ⁺ source / drain regions SD2 are formed on the surface of the n-type well WE2 at a distance from each other. Each of the pair of Extension / Halo regions EH2 is formed in contact with each of the pair of p ⁺ source / drain regions SD2. The Extension region and the Halo region are of opposite conductivity types. In the pMOS transistor PT, the Extension region is a p-type impurity region, and the Halo region is an n-type impurity region. In FIG. 1, only the Extension area is shown as the Extension / Halo area EH2. The gate electrode GE is made of, for example, doped polysilicon doped with a p-type impurity, and a gate oxide film (silicon oxide film) is formed on a region of the semiconductor substrate SUB sandwiched between a pair of p ⁺ source / drain regions SD2. It is formed via GI. The gate electrode GE of the nMOS transistor NT and the gate electrode GE of the pMOS transistor PT are doped with mutually opposite conductivity type impurities, resulting in a dual gate.

  A sidewall insulating layer SW is formed on the main surface of the semiconductor substrate SUB so as to cover the sidewall of the gate electrode GE. Sidewall insulating layer SW is made of, for example, a silicon oxide film or a silicon nitride film. The Extension / Halo region EH2 is located below the side wall insulating layer SW.

  First silicide layer SC is formed so as to be in contact with the surface of buried conductive layer BC constituting the trench isolation. Second silicide layer SC is formed in contact with each surface of source / drain regions SD1 and SD2 of nMOS transistor NT and pMOS transistor PT. A third silicide layer SC is formed in contact with the surface of each gate electrode GE of transistors NT and PT. The first to third silicide layers SC are, for example, refractory metal silicide layers.

  An in-trench insulating layer TI is located between the first silicide layer SC and the second silicide layer SC. A sidewall insulating layer SW is located between the third silicide layer SC and the second silicide layer SC.

  An interlayer insulating layer II1 is formed on the main surface of the semiconductor substrate SUB so as to cover the CMOS transistor. A plurality of contact holes CH are formed in the interlayer insulating layer II1. The plurality of contact holes CH include a contact hole CH reaching the second silicide layer SC and a contact hole CH reaching the third silicide layer SC. Each of the plurality of contact holes CH is filled with a plug conductive layer PG. Plug conductive layer PG is made of a refractory metal such as tungsten.

  A wiring layer IL is formed on the interlayer insulating layer II1 so as to be electrically connected to the plug conductive layer PG. An interlayer insulating layer II2 is formed on the interlayer insulating layer II1 so as to cover the wiring layer IL.

Next, a method for manufacturing the semiconductor device of the present embodiment will be described.
2 to 5 are schematic cross-sectional views showing a method of manufacturing a semiconductor device according to an embodiment of the present invention in the order of steps. Referring to FIG. 2, trench TR is first formed in p-type semiconductor substrate SUB using a normal photolithography technique and etching technique. When the wall surface of the trench TR is oxidized, for example, an in-trench insulating layer TI made of, for example, a silicon oxide film is formed on the wall surface of the trench TR.

  Thereafter, a buried conductive layer BC made of, for example, doped polysilicon is formed so as to fill the trench. The upper surface of the buried conductive layer BC is capped with a cap insulating layer CI made of, for example, a silicon oxide film. As a result, an FS-STI in which the trench TR is filled with doped polysilicon is formed.

  Next, by performing a plurality of ion implantations, a p-type well WE1 and an n-type well WE2 are formed on the main surface of the semiconductor substrate SUB. The p-type well WE1 is a region where the nMOS transistor NT is formed, and the n-type well WE2 is a region where the pMOS transistor PT is formed.

  In the formation of each transistor described above, first, an oxidation process is performed on the entire surface of the semiconductor substrate SUB. Thereby, a silicon oxide film GI is formed on the surface of the semiconductor substrate SUB. A silicon oxynitride film may be formed by performing nitriding after the oxidation.

  A polysilicon film GE is formed on the entire surface of the semiconductor substrate SUB. Thereafter, the polysilicon film GE is patterned using a normal photolithography technique and an etching technique. During the etching for this patterning, the silicon oxide film (or silicon oxynitride film) GI under the polysilicon film GE functions as an etching stopper. As a result, a gate electrode GE made of the patterned polysilicon film GE is formed, and the portion of the silicon oxide film (or silicon oxynitride film) GI below the gate electrode GE functions as the gate insulating layer GI.

  A resist pattern (not shown) is formed on the n-type well WE2 by a normal photoengraving technique, and ion implantation is performed a plurality of times in the p-type well WE1 using the resist pattern and the gate electrode GE as a mask. Thus, a pair of Extension / Halo regions EH1 of the nMOS transistor NT are formed in the p-type well WE1 so as to sandwich the region below the gate electrode GE. Further, by this ion implantation, ions are also implanted into the gate electrode GE of the nMOS transistor NT. Thereafter, the resist pattern is removed by ashing or the like.

  Thereafter, a resist pattern (not shown) is formed on the p-type well WE1 by a normal photolithography technique, and ion implantation is performed a plurality of times in the n-type well WE2 using the resist pattern and the gate electrode GE as a mask. Thus, a pair of Extension / Halo regions EH2 of the pMOS transistor PT are formed in the n-type well WE2 so as to sandwich the region below the gate electrode GE. Further, by this ion implantation, ions are also implanted into the gate electrode GE of the pMOS transistor PT. Thereafter, the resist pattern is removed by ashing or the like.

  Referring to FIG. 3, an insulating film (silicon oxide film, silicon nitride film, etc.) is deposited on the entire main surface of semiconductor substrate SUB, and anisotropic etching is performed on the entire surface of the insulating film. Thereby, the insulating film remains only on the side wall of the gate electrode GE, and the side wall insulating layer SW made of a silicon oxide film, a silicon nitride film, or the like is formed. By this anisotropic etching, the sidewall insulating layer SW is formed, and the cap insulating layer CI on the buried conductive layer BC is removed, and the upper surface of the buried conductive layer BC is exposed. At the same time, the silicon oxide film (or silicon oxynitride film) other than that immediately below the gate electrode GE and the sidewall insulating layer SW is removed, and the surfaces of the source / drain regions SD1 and SD2 are exposed.

A resist pattern (not shown) is formed on the n-type well WE2 by a normal photoengraving technique, and n-type impurity ions are applied to the p-type well WE1 a plurality of times using the resist pattern, the gate electrode GE and the sidewall insulating layer SW as a mask. Ion implanted. Thereby, a pair of n ⁺ source / drain regions SD1 of the nMOS transistor NT are formed on the surface of the p-type well WE1 so as to sandwich the region below the gate electrode GE and the sidewall insulating layer SW. By this ion implantation, ions are also implanted into the gate electrode GE of the nMOS transistor NT. Thereafter, the resist pattern is removed by ashing or the like.

Thereafter, a resist pattern (not shown) is formed on the p-type well WE1 by a normal photolithography technique, and p-type impurity ions are formed in the n-type well WE2 using the resist pattern, the gate electrode GE and the sidewall insulating layer SW as a mask. Are implanted multiple times. Thus, a pair of p ⁺ source / drain regions SD2 of the pMOS transistor PT are formed on the surface of the n-type well WE2 so as to sandwich the region below the gate electrode GE and the sidewall insulating layer SW. By this ion implantation, ions are also implanted into the gate electrode GE of the pMOS transistor PT. Thereafter, the resist pattern is removed by ashing or the like.

  During the above ion implantation, at least one of n-type impurity ions and p-type impurity ions is also implanted into the buried conductive layer BC. The buried conductive layer BC is doped with either n-type or p-type impurity ions before the ion implantation. Therefore, to fix the idea, assuming that the buried conductive layer BC is doped with n-type impurity ions, p-type impurity ions are implanted into the buried conductive layer BC in the formation region of the pMOS transistor PT. It will be. As a result, there is a concern that the n-type impurity ions originally doped in the buried conductive layer BC and the p-type impurity ions newly implanted for the source / drain are offset. However, there is no problem if the n-type impurity concentration is sufficiently high so that the n-type impurity ions originally doped in the buried conductive layer BC are not offset by the p-type impurity ions.

Thus, an nMOS transistor NT having a pair of n ⁺ source / drain regions SD1, a pair of Extension / Halo regions EH1, a gate oxide film GI, and a gate electrode GE is formed. Further, a pMOS transistor PT having a pair of p ⁺ source / drain regions SD2, a pair of Extension / Halo regions EH2, a gate oxide film GI, and a gate electrode GE is formed.

  Referring to FIG. 4, refractory metal (Ti, Co, Ni, etc.) HM is deposited on the entire surface of semiconductor substrate SUB. The refractory metal HM is formed in contact with each of the buried conductive layer BC, the source / drain regions SD1 and SD2, the gate electrode GE, the sidewall insulating layer SW, and the in-trench insulating layer TI. In this state, RTA (Rapid Thermal Anneal) is performed a plurality of times.

  Referring to FIG. 5, the above RTA causes silicon and the refractory metal to react at the contact portion between each of buried conductive layer BC, source / drain regions SD1 and SD2 and gate electrode GE and refractory metal HM. A refractory metal silicide SC is formed. Thus, the first silicide layer SC is formed so as to be in contact with the surface of the buried conductive layer BC, the second silicide layer SC is formed so as to be in contact with the surfaces of the source / drain regions SD1 and SD2, and the gate electrode GE Third silicide layer SC is formed in contact with the surface. Thereafter, unreacted refractory metal HM is removed.

  Referring to FIG. 1, an interlayer insulating layer II1 is formed by depositing and planarizing a plurality of insulating films on the entire surface of semiconductor substrate SUB. A plurality of contact holes CH are formed in the interlayer insulating layer II1 by a normal photolithography technique and etching technique. Each of the plurality of contact holes CH is formed to reach each of the second silicide layer SC on the source / drain regions SD1 and SD2 and the third silicide layer SC on the gate electrode GE.

  The plurality of contact holes CH are filled with a plug conductive layer PG made of a refractory metal such as tungsten. A wiring layer IL is formed in contact with the plug conductive layer PG, and an interlayer insulating layer II2 is formed so as to cover the wiring layer IL. As a result, the semiconductor device of the present embodiment shown in FIG. 1 is manufactured.

Next, functions and effects of the semiconductor device of this embodiment will be described.
For example, as shown in FIG. 6, when the silicide layer is not formed on the upper surface of the buried conductive layer BC of the FS-STI and the cap insulating layer CI is formed, if the trench isolation width is reduced according to the scaling rule, The resistance of the buried conductive layer BC is increased. Since the configuration other than the above in FIG. 6 is substantially the same as the configuration shown in FIG. 1, the same elements are denoted by the same reference numerals and the description thereof will not be repeated.

  Further, the contact for fixing the potential of the buried conductive layer BC is arranged at a position P1 between the plurality of array blocks AB in the memory array MA as shown in FIG. This is because a plurality of memory cells and wirings for connecting them are densely arranged in the array block AB and it is difficult to arrange contacts.

  When the contacts are arranged at the position P1 outside the array block AB in this way, the distance for routing the buried conductive layer BC from the position P1 to the position P2 at the center of the array block AB becomes long. Here, when the resistance of the buried conductive layer BC increases due to the scaling law, the lead wiring resistance of the buried conductive layer BC increases. As a result, the potential drop of the buried conductive layer BC becomes remarkably large at the position P2 at the center of the array block AB, and interference due to capacitive coupling may not be sufficiently suppressed.

  On the other hand, according to the present embodiment, as shown in FIG. 1, since the silicide layer SC is formed so as to be in contact with the surface of the buried conductive layer BC, the wiring resistance can be reduced by the silicide layer SC. . Therefore, even if the embedded conductive layer BC is routed from the position P1 outside the array block AB to the center position P2 as shown in FIG. 7, the potential drop at the center P2 can be suppressed more than the configuration of FIG. . Therefore, interference due to capacitive coupling can be sufficiently suppressed by FS-STI.

  Further, according to the present embodiment, the first silicide layer SC and the second silicide layer SC are separated from each other by the in-trench insulating layer TI. Further, the third silicide layer SC and the second silicide layer SC are separated from each other by the sidewall insulating layer SW. For this reason, in forming these three silicide layers SC, there is no need to consider a dimensional penalty due to an overlap margin caused by the photomechanical technology.

  Further, according to the present embodiment, as shown in FIG. 3, the cap insulating layer CI can be simultaneously removed by anisotropic etching when the sidewall insulating layer SW is formed. Further, the buried conductive layer BC can be silicided in the same process as the silicidation of the source / drain regions SD1, SD2 and the gate electrode GE. For this reason, the buried conductive layer BC can be silicided by a simple process.

  In the above embodiment, the MOS transistor has been described. However, the gate insulating film is not limited to the silicon oxide film, and may be another insulating layer such as a silicon oxynitride film. Therefore, the present invention is not limited to a MOS transistor but can be applied to a MIS (Metal Insulator Semiconductor) transistor.

  The present invention can also be applied to other electric elements other than the MIS transistor. In this case, the silicide layer is formed so as to be in contact with the impurity region of the electric element and the upper surface of the conductive layer.

  The removal of the cap insulating layer CI may not be performed simultaneously with the anisotropic etching for forming the sidewall insulating layer SW, but may be performed by other methods.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  The present invention can be applied particularly advantageously to a semiconductor device having FS-STI and a method for manufacturing the same.

1 is a cross-sectional view schematically showing a configuration of a semiconductor device in an embodiment of the present invention. It is a schematic sectional drawing which shows the 1st process of the manufacturing method of the semiconductor device in one embodiment of this invention. It is a schematic sectional drawing which shows the 2nd process of the manufacturing method of the semiconductor device in one embodiment of this invention. It is a schematic sectional drawing which shows the 3rd process of the manufacturing method of the semiconductor device in one embodiment of this invention. It is a schematic sectional drawing which shows the 4th process of the manufacturing method of the semiconductor device in one embodiment of this invention. FIG. 6 is a schematic cross-sectional view showing a configuration in which a silicide layer is not formed on the upper surface of the FS-STI buried conductive layer BC and a cap insulating layer CI is formed. It is a schematic plan view which shows a mode that the memory array was comprised by the several array block.

Explanation of symbols

  AB array block, BC buried conductive layer, CH contact hole, CI cap insulating layer, EH1, EH2 Extension / Halo region, GE gate electrode, GI gate oxide film, HM refractory metal, II1, II2 interlayer insulating layer, IL wiring layer MA memory array, NT nMOS transistor, PG plug conductive layer, SC silicide layer, SD1, SD2 source / drain region, SUB semiconductor substrate, SW sidewall insulating layer, TI insulating layer in trench, TR trench, WE1 p-type well, WE2 n-type well.

Claims (7)

A semiconductor substrate having a main surface and having a trench for element isolation on the main surface;
A buried conductive layer filling the trench;
And a first silicide layer formed so as to be in contact with the surface of the buried conductive layer. An impurity region formed on the main surface of the semiconductor substrate;
The semiconductor device according to claim 1, further comprising a second silicide layer formed so as to be in contact with a surface of the impurity region. A conductive layer formed on the main surface of the semiconductor substrate;
The semiconductor device according to claim 2, further comprising a third silicide layer formed so as to be in contact with the surface of the conductive layer.   4. The semiconductor device according to claim 3, wherein the impurity region is a source / drain region of an insulated gate field effect transistor and the conductive layer is a gate electrode of the insulated gate field effect transistor. An in-trench insulating layer formed along the wall surface of the trench between the buried conductive layer and the trench;
A sidewall insulating layer formed on the main surface of the semiconductor substrate so as to cover the sidewall of the gate electrode;
The sidewall insulating layer is located between the second silicide layer and the third silicide layer;
The semiconductor device according to claim 4, wherein the in-trench insulating layer is located between the first silicide layer and the second silicide layer. Forming a buried conductive layer so as to fill a trench formed in the main surface of the semiconductor substrate;
An insulated gate field effect transistor having the gate electrode and the source / drain region is formed by forming a gate electrode on the main surface of the semiconductor substrate and forming a source / drain region on the main surface of the semiconductor substrate. And a process of
Forming a refractory metal in contact with each of the buried conductive layer, the source / drain region and the gate electrode;
Forming a silicide layer on each of the portions where the buried conductive layer, the source / drain regions, and the gate electrode are in contact with the refractory metal by performing heat treatment, . Forming an insulating layer in the trench along the wall surface of the trench;
Forming a sidewall insulating layer on the main surface of the semiconductor substrate so as to cover the sidewall of the gate electrode,
The method for manufacturing a semiconductor device according to claim 6, wherein the refractory metal is formed so as to be in contact with both the sidewall insulating layer and the in-trench insulating layer.

Images