JP2010020837A - Nonvolatile semiconductor memory device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor memory device which has a write means for controlling a threshold of a memory cell at high speed and with high accuracy without complicating write control. <P>SOLUTION: A word voltage supply section 20 outputs a voltage with a step voltage added thereto as a word voltage every time a predetermined step voltage is added to a write start voltage, and a verify section 30 verifies a degree of change in threshold of each memory cell with respect to a plurality of determination levels at every write operation, and skips next write operation a plurality of times according to the verify result and sets all the thresholds of the memory cells at a predetermined threshold while stopping write to a memory cell whose threshold has reached the predetermined threshold. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to writing of a nonvolatile semiconductor memory, and more particularly to a nonvolatile semiconductor memory device having a writing means capable of controlling a threshold value of a memory cell at high speed and with high accuracy.

  When it is necessary to control the memory threshold with high precision at the time of writing, such as a memory chip composed of multi-value cells, a writing method using a gate voltage step method such as ISPP (Incremental Step Pulse Programming) is applied. However, in ISPP, the gate voltage is stepped up in multiple steps, and thus there is a problem that the writing time is delayed due to variations in memory cells.

  A writing method using the ISPP gate voltage step method will be described. FIG. 5 is a cell writing diagram showing the relationship between the word voltage and the memory cell threshold value by the ISPP voltage step method. The horizontal axis shows the word voltage at the time of writing, and the vertical axis shows the memory cell threshold voltage Vtm after writing for a certain time under the conditions.

  In FIG. 5, of the two diagonal lines, the line with the higher threshold indicates the write operation of the cell with faster writing, and the line with the lower side indicates the write operation of the cell with the slower write. The threshold values of all the memory cells are distributed between the two lines indicated by the arrows, and the cell corresponding to the right end of the arrow indicates a memory cell that is slowly written. The write start voltage of the word line is set so that the fast write cell is not over-programmed with respect to all the memory cells in the write unit. A range indicated by an arrow on the left side of a line with a higher threshold indicates a margin voltage set so that a cell with fast writing is not overprogrammed. The word voltage when writing of all the memory cells in the writing unit is completed is determined by the memory cell that is slow to write.

Vcg-range is a variation in word voltage necessary for completion of writing between a cell with early writing and a memory cell with slow writing, and a margin voltage set so that a cell with early writing is not overprogrammed is Vcg-margin. Assuming that the step voltage at which the write voltage monotonously increases is ΔVcg, the number N of times of writing required for completion of writing is expressed by the following equation.
N = (Vcg−range + Vcg−margin) / ΔVcg + 1
For example, if Vcg-range = 1.6V, Vcg-margin = 0.5V, and ΔVcg = 0.1V, the number of times of writing N is 22 times.

  This write operation will be described again in detail with reference to FIG. It is assumed that the threshold values Vtm11 of all the memory cells in the writing unit are distributed with a threshold variation indicated by '11'. When writing is performed to change the threshold values of all the memory cells to the threshold value Vtm10 distributed with variation indicated by '10', a lower limit voltage (a margin voltage that is set so as not to overprogram the cells that are written quickly) Vcg1 = 2.7) is applied as a word voltage to all memory cells in the writing unit, and if there is a memory cell whose changed threshold value falls within the distribution of the threshold value Vtm10, the writing of that cell is completed.

  Subsequently, the step voltage (ΔVcg = 0.1V) is continuously added to the voltage of Vcg1 = 2.7V, and each time the addition is performed, cells other than the memory cell that has been written are read, and the changed threshold value is the distribution of the threshold Vtm10 If there is a memory cell that enters, the writing of the cell is completed, and the process is repeated until the word voltage reaches a voltage Vcg2 = 5.5V at which the word voltage reaches the upper limit of the variation Vcg-range of the word voltage. In this case, the write count N is 29 times. Similarly, when writing is performed to change to the threshold value Vtm01 distributed with variations indicated by “01”, since Vcg3 = 4.5V and Vcg4 = 7.2V, the number of times of writing N is 28 times. .

  From this, the time required for the completion of writing to set the threshold value of the memory cell to a predetermined value is determined by applying a word voltage, determining a change in the threshold value, excluding the memory cell that has been written, and then setting the next word voltage. Assuming that the time until application is T, in the case of the threshold value Vtm10, a time of 29 · T is required, and in the case of the threshold value Vtm01, a time of 28 · T is required. In order to reduce this time, it is necessary to reduce the number N of times of writing.

Patent Document 1 discloses a writing circuit for writing data to a nonvolatile semiconductor memory cell in which data can be electrically rewritten for the purpose of narrowing the distribution width of threshold voltage after writing while suppressing an increase in writing time. Yes, by supplying a write voltage and a write control voltage to the memory cell, writing to the memory cell to change the write state of the memory cell, changing the supply state of the write control voltage to reduce the change speed of the write state, It is described that the supply state of the write control voltage is further changed to control the relaxed write state change speed, and the write to the memory cell is completed while the write state change speed is relaxed. However, according to this, since the two voltage levels of the write voltage and the write control voltage are controlled and supplied in order to change the write state of the memory cell, the control becomes complicated.
JP 2005-174414 A

  The present invention has been made to solve such a problem, and an object of the present invention is to control the threshold value of the memory cell at high speed and with high accuracy without complicating the write control. An object of the present invention is to provide a nonvolatile semiconductor memory device having a writing means.

  The nonvolatile semiconductor memory device of the present invention includes a word voltage supply means for outputting a word voltage to each word line on the memory cell array and writing, and a change in threshold value of each memory cell in the memory cell array with respect to a plurality of determination levels. A word voltage supply unit that outputs a write start voltage as a word voltage to perform a first write, and subsequently applies a predetermined step voltage to the write start voltage. Each time the voltage is added, the voltage obtained by adding the step voltage is output as a word voltage, and the verify means determines the degree of change in the threshold value of each memory cell with respect to a plurality of determination levels each time writing is performed. Depending on the determination result, the next write is skipped a predetermined number of skips, and the memory cell that has reached a predetermined threshold While complete writing to, and sets all threshold values of the memory cells to a predetermined threshold value. As a result, since the next writing is skipped a predetermined number of times according to the determination result, the number of write operations can be reduced without complicating the write control.

  The write start voltage of the nonvolatile semiconductor memory device of the present invention is a voltage that is set so that a memory cell that is quickly written out of each memory cell is not over-programmed, and the last determination level is a write completion determination level It is characterized by. Thereby, since all the memory cells are programmed without being overprogrammed, highly accurate threshold value control is possible.

  The step voltage of the nonvolatile semiconductor memory device of the present invention is a voltage set so that memory cells distributed in the vicinity of a plurality of determination levels are not overprogrammed by the word voltage to which the step voltage is added, The skip count is a count obtained by dividing a level difference between a plurality of determination levels by the step voltage. Thereby, highly accurate threshold control in which the number of times of writing is controlled to the minimum is possible, and the writing time can be greatly shortened.

  Since the memory cell array of the nonvolatile semiconductor memory device of the present invention is composed of multi-value cells and each threshold value of the multi-value cell is written to a predetermined multi-value threshold value, a plurality of determinations for each threshold value of the multi-value cell are performed. Depending on the determination result corresponding to the level, the next writing is skipped for a predetermined number of skips, and all threshold values of the multi-value cells are set while completing the writing to the memory cells that have reached the predetermined threshold value. A predetermined threshold value is set. As a result, similarly in the multilevel cell, the next write is skipped a predetermined number of times according to the determination result, so that the number of write operations can be reduced without complicating the write control.

  In order to perform writing of a predetermined threshold value to each of the multi-value cells of the nonvolatile semiconductor memory device of the present invention, the write start voltage is a voltage that is set so that a memory cell that is quickly written out of the multi-value cells is not over-programmed. Yes, the last determination level is a write completion determination level. As a result, all the memory cells in the multi-value cell are programmed without being overprogrammed, so that highly accurate threshold control is possible.

  In order to perform writing of a predetermined threshold value to each of the multi-value cells of the nonvolatile semiconductor memory device of the present invention, the step voltage added to the write start voltage is a memory cell distributed in the vicinity of a plurality of determination levels. The skip voltage is a voltage set so as not to be overprogrammed by the word voltage to which the step voltage is added, and the skip count is a count obtained by dividing a level difference between a plurality of determination levels by the step voltage. Thereby, highly accurate threshold control in which the number of times of writing in the multi-value cell is controlled to the minimum is possible, and the writing time can be greatly shortened.

  The verify means for determining the change of the threshold value of the multilevel cell of the nonvolatile semiconductor memory device of the present invention determines a plurality of determination levels for determining the multilevel level at the time of reading the multilevel cell and the change of the write target cell. It has a switching means for switching between a plurality of determination levels. Thereby, the usage of the memory is switched by a simple switching operation.

  According to the present invention, since the next writing is skipped a predetermined number of times according to the determination result and is not overprogrammed, it is possible to reduce the number of times of writing without complicating the writing control. In addition, it is possible to provide a nonvolatile semiconductor memory device having writing means that can control the threshold value of the memory cell with high accuracy and can significantly reduce the writing time.

  FIG. 1 is a block diagram of a device configuration showing an embodiment of a nonvolatile semiconductor memory device according to the present invention. In FIG. 1, the nonvolatile semiconductor memory device 100 includes a memory cell array 10, a word voltage supply unit 20, and a verify unit 30. The word voltage supply means 20 includes a program counter 22, a word voltage generator 24, and an X decoder 26. The verify unit 30 includes a sense amplifier 33 and a comparator 37.

  FIG. 2 is a cell writing diagram showing the relationship between the word voltage at the time of writing and the threshold value of the memory cell in the embodiment according to the present invention. Description of items common to FIG. 5 is omitted. The write operation of FIG. 2 will be described based on the circuit of FIG. The verify means 30 has three levels of verify levels V1 (4V), V2 (5V), and V3 (6V), and the initial threshold value Vtm11 is distributed with the threshold variation indicated by the region '11'. It is assumed that writing is performed to change all the memory cells in the unit to the threshold value Vtm00 distributed in the variation indicated by the region of “00” exceeding the verify level V3 (6V). However, in the following description, a 3-bit cell indicated by a circle in FIG.

  First, the word voltage generator 24 of the word voltage supply means 20 sets a write start voltage (Vcg1 = 2.5V), which is a voltage that reaches a lower limit of a margin voltage set so that a cell with early writing is not overprogrammed. The voltage VPW is applied to all the memory cells in the writing unit via the X decoder 26. Thereafter, a predetermined step voltage (0.1 V) is added to the write start voltage in synchronization with the timing of the step voltage control signal PGCOUNT output from the program counter 22, and the word voltage VPW is output at each timing.

  The sense amplifier 33 of the verify unit 30 determines whether there is a memory cell whose threshold value changed by the write start voltage falls within the range of the threshold value Vtm10 or Vtm01, based on the verify level V1 / V2 / V3 that is a determination level. The 2-bit digital value SAOUT that determines the number of skips for skipping writing is output to the comparator 37. The comparator 37 controls the write circuit 40 based on the 2-bit digital value, and skips the supply of the drain voltage of the memory cell in synchronization with the timing of the word voltage output from the word voltage generator 24.

  First, the write operation of n = 20 times in FIG. 2 will be described. Like the cell 1, if the threshold value does not exceed the verify level V1 and is not within the range of the threshold value Vtm10, the threshold values of all the cells are still within the threshold value Vtm11. Even if the voltage of the difference of (V3−V1 = 2.0V) is further added, it is not overprogrammed far beyond the verify level V3. Therefore, the sense amplifier 33 outputs a 2-bit digital value SAOUT ('11') indicating that there is no memory cell that falls within the range of the thresholds Vtm10 and Vtm01.

  Based on this, the comparator 37 increases the word voltage VPW by a step voltage (0.1 V) and reaches the maximum step voltage of 2 V added to 4.5 V, that is, the step voltage addition count Ns is 2. The writing circuit 40 is controlled so that writing is skipped as many times as 0 / 0.1-1 = 19 times, and supply of the drain voltage of the memory cell is skipped 19 times. At this time, the write data WDATA necessary for the comparator 37 to execute writing only after skipping 19 times based on the skip timing signal PGMn which becomes high once for a plurality of writing times output from the program counter 22. Is output to the writing circuit 40.

  Like the cell 2, when the threshold value exceeds the verify level V1 and does not exceed the verify level V2, the threshold value of the memory cell exists in the range of the threshold value Vtm10. For this reason, even if the voltage of the verify level difference (V3−V2 = 1 volt), which is an intermediate step voltage, is further added, the program is not overprogrammed far beyond the verify level V3.

  For this reason, the sense amplifier 33 outputs a 2-bit digital value SAOUT ('10'), and based on this, the comparator 37 increases the word voltage VPW by a step voltage (0.1 V) to 5.5 V. In other words, the write circuit 40 is controlled so that the write is skipped as many times as the step voltage addition number Ns is 1.0 / 0.1-1 = 9 times, and the drain voltage of the memory cell is supplied. After skipping nine times, write data WDATA is output and writing is performed only when the word voltage obtained by adding the intermediate step voltage of 1.0 V becomes 5.5 V.

  In the case of the cell 3, the threshold value of the memory cell exists in the range of the threshold value Vtm01. For this reason, if the minimum step voltage necessary to finally realize the target distribution width is not applied, cells that are overprogrammed far beyond the verify level V3 may occur.

  Therefore, the sense amplifier 33 outputs a 2-bit digital value SAOUT (“01”) indicating that there is a memory cell that falls within the distribution of the threshold value Vtm01. Based on this, the comparator 37 controls the writing circuit 40. In this case, writing is performed each time the minimum step voltage (0.1 V) is added. If there is a memory cell in which the changed threshold falls within the distribution of the threshold Vtm00 by this writing, the sense amplifier 33 outputs a 2-bit digital value SAOUT (00) indicating that there is a memory cell that falls within the distribution of the threshold Vtm00. . In the cell in which this signal is detected, it is determined that the writing is completed, and the writing is terminated. When the threshold values of all the memory cells exceed the predetermined verify level V3, the write operation is finished.

  FIG. 3 is a write timing diagram showing the relationship between the word voltage and the bit line voltage during writing. First, the word voltage supply means 20 applies the write start voltage as the word voltage VPW to all the memory cells in the write unit. For example, the case where the writing is performed in each memory cell connected to the intersection of the word line WL0 and the bit lines BL0 to BLn in FIG. 1 is shown in the PGM section, and the drain voltages of the memory cells are successively applied to BL0 to BLn. Supplied from the writing circuit. In addition, the threshold values of the memory cells connected to BL0, BL1, and BLn move in the same manner as the cells 1, 2, and 3 described in FIG.

  The operation at the n = 20th time will be described below. The sense amplifier 33 of the verify means 30 of BL0 has a memory cell threshold value in the range of threshold variation indicated by '10', and therefore skips n = 21 to 29 times of writing, so that the 2-bit digital value SAOUT ( '10') is output. Based on this, the comparator 37 controls the write circuit 40 to skip the supply of the drain voltage of the memory cell nine times, and then the word voltage obtained by adding the intermediate step voltage of 1.0 V is 5.5 V. Write at that point. In BLn, since the threshold value of the memory cell is in the range of the threshold variation indicated by “11”, the word voltage obtained by adding 2.0 V which is the maximum step voltage after skipping n = 19 times is 6. Writing is performed when the voltage reaches 5V.

  Since the threshold value of the memory cell BL0 is in the range of the threshold variation indicated by “01”, a 2-bit digital value SAOUT (“01”) is output from the sense amplifier 33, and the comparator 37 has a minimum step voltage ( Writing is performed every time 0.1V) is added. As a result, at the time of n = 21th writing, the sense amplifier 33 determines that the threshold value of the memory cell of BL0 is in the range of threshold variation indicated by “00”, and indicates that the changed threshold value is in the range of threshold value Vtm00. A 2-bit digital value SAOUT (00) is output. When this signal is detected, it is determined that writing of the memory cell of BL0 is completed, and writing is stopped.

  Also for the memory cell of BL1, since the threshold value is in the range of threshold variation indicated by '01' at the time of n = 30th write operation, the write with the minimum step voltage (0.1V) added thereafter is performed. When it is repeatedly performed and the threshold value enters the range of the threshold variation indicated by “00”, it is determined that the writing of the memory cell of BL1 is completed, and the writing is stopped.

  The BLn memory cell is determined to be within the threshold variation range indicated by '10' after 20 writing is skipped and 6.5V with the maximum step voltage of 2.0V is applied. Is done. The following is not shown in FIG. 3, but, similarly to the memory cell connected to BL1, n = 9 writes are skipped in the next step, and an intermediate step voltage of 1.0V is added to 7.5V. A voltage is applied. This time, since the threshold value of the memory cell is in the range of the threshold variation indicated by “01”, the writing with the minimum step voltage (0.1 V) added is repeatedly performed, and the threshold value is indicated by “00”. When entering the range of variation, it is determined that writing of the memory cell of BLn is completed, and writing is stopped. Thereby, the writing of the memory cell on the word line WL0 is completed.

  As described above, the number of times of writing by the word voltage supply means 20 is 8 in total in the case of FIG. 2, and the number of times of writing can be greatly reduced. For this reason, the writing time can be significantly reduced. Further, it is not necessary to control and supply the two voltage levels of the write voltage and the write control voltage, and only the write voltage may be controlled, so that complicated control is not required. Further, in the write method of the present invention, the number of write skips can be changed for each memory cell of the simultaneous write unit on the same word line, so the write time is greatly shortened even when the number of simultaneous writes is large and the write variation is large. It becomes possible to do.

  Further, when the memory cell array is composed of multi-value cells, the above-described verify level V3 is determined corresponding to each multi-value threshold level, and the verify level corresponding to the write start voltage depending on the memory cell array. By determining V1, verify level V2 is determined, and three verify levels for each threshold level can be determined. As a result, it is possible to speed up the write operation of each threshold value of the memory cell array composed of multi-value cells.

  FIG. 4 is a circuit block diagram showing an embodiment of the sense amplifier according to the present invention. In FIG. 4, the sense amplifier 33 includes a verify level input switching unit 34, a level determination unit 35, and a decoder 36. The verify level input switching means 34 is composed of a plurality of switches 34-1 to 43-3, and verify levels V1 to V3 for determining the threshold level of the write target cell are input to one of the inputs of each switch, respectively. Are supplied with reference levels Vm1 to Vm3 necessary for multi-level reading.

  The output of each switch is input to one input of level determiners 35-1 to 35-3 of the level determining means, and the threshold Vmt of the memory cell changed by writing is read and input to the other. The level determiners 35-1 to 35-3 determine the degree of change in the threshold value Vmt based on the reference level and the verify level, and output the result. Based on the determination result, the decoder 36 outputs one of the binary digital outputs SAOUT ('11' to '00') indicating to which of the four states the threshold value Vmt belongs to the verify check circuit 37.

  As described above, by turning on the switches 34-1 to 43-3 to the verify levels V1 to V3, it is possible to determine the change in the write threshold value of the write target cell described in FIG. 1, and the reference levels Vm1 to Vm3. By turning on the multi-level memory cell, it is possible to determine the multi-level level during normal reading in the memory cell array composed of multi-level memory cells described in paragraph [0035]. The verify levels V1 to V3 and the reference levels Vm1 to Vm3 are supplied from each current / voltage conversion circuit (not shown), and the verify levels V1 to V3 have verify levels corresponding to multi-value threshold levels. It is switched and supplied as appropriate. As a result, in a nonvolatile semiconductor memory device employing a multi-valued memory, the present invention can be applied by adding only a switch to a sense amplifier used during normal reading.

  As described above, according to the present invention, the number of times of the write operation can be reduced without complicating the write control by skipping the next write a plurality of times according to the determination result of the written threshold value change. it can. Therefore, there is provided a non-volatile semiconductor memory device having a writing means capable of controlling the threshold value of a memory cell with high reliability and high speed and high accuracy since drain disturbance for unselected cells is alleviated. It becomes possible.

1 is a block diagram showing a device configuration of a nonvolatile semiconductor memory device according to the present invention. FIG. 4 is a cell writing diagram showing a relationship between a word voltage and a memory cell threshold at the time of writing according to the present invention. The word voltage level figure which shows the relationship between the voltage level concerning each memory cell on a word line, and a step voltage. The circuit block diagram which shows the sense amplifier by this invention. The cell write figure which shows the relationship between the word voltage by an ISPP voltage step system, and the threshold value of a memory cell.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Memory cell array 20 Word voltage supply means 22 Program counter 24 Word voltage generator 26 X decoder 30 Verification means 33 Sense amplifier 34 Verification level input switching means 34-1-3 Switch 35 Level determination means 35-1-3 Level determination device 36 Decoder 37 Comparator circuit 40 Write circuit 100 Non-volatile semiconductor memory device Vtm Memory cell threshold value VPW Word voltage V1 to V3 Verify level Vm1 to Vm3 Reference level '11' Threshold value set region of V1 or less '10' Threshold value between V1 and V2 Set region '01' V2-V3 threshold set region '00' V3 or more threshold set region WL0-WLn Word lines BL0-BLn Bit lines Ns Step voltage addition count n Skip count WDATA Write data S AOUT Binary digital value PGMn Skip timing signal PGCOUNT Step voltage control signal

Claims (7)

Nonvolatile having word voltage supply means for outputting by writing word voltage to each word line on the memory cell array, and verify means for judging a change in threshold value of each memory cell in the memory cell array with respect to a plurality of judgment levels A semiconductor memory device,
The word voltage supply means outputs a write start voltage as the word voltage to perform the first write, and each time a predetermined step voltage is subsequently added to the write start voltage, the voltage obtained by adding the step voltage is used. Output as the word voltage,
The verify means determines the degree of change in the threshold value of each memory cell for each of the plurality of determination levels each time the write is performed, and skips the next write for a predetermined number of skips according to the determination result. In addition, the nonvolatile semiconductor memory device is characterized in that all threshold values of the memory cells are set to the predetermined threshold value while completing writing to the memory cells that have reached the predetermined threshold value.   2. The write start voltage is a voltage that is set so that a memory cell that is quickly written among the memory cells is not over-programmed, and a final determination level is a write completion determination level. The non-volatile semiconductor memory device described in 1.   The step voltage is a voltage set so that the memory cells distributed in the vicinity of the plurality of determination levels are not overprogrammed by the word voltage to which the step voltage is added, and the skip count is The nonvolatile semiconductor memory device according to claim 1, wherein the non-volatile semiconductor memory device is a number of times the level difference between the plurality of determination levels is divided by the step voltage.   The memory cell array is composed of multi-value cells, and each threshold value of the multi-value cell is written to a predetermined multi-value threshold value, and therefore corresponds to the plurality of determination levels for the respective threshold values of the multi-value cell. Depending on the determination result, the next writing is skipped for a predetermined number of skips, and all the threshold values of the multi-value cells are set to the predetermined threshold value while completing writing to the memory cells that have reached the predetermined threshold value. The nonvolatile semiconductor memory device according to claim 1, wherein   In order to write a predetermined threshold value to each of the multi-value cells, the write start voltage is a voltage that is set so that a memory cell that is quickly written out of the multi-value cells is not over-programmed, and the final determination level is The nonvolatile semiconductor memory device according to claim 4, which is at a write completion determination level.   In order to write a predetermined threshold value to each of the multi-value cells, the step voltage added to the write start voltage is added to the memory cells distributed in the vicinity of the plurality of determination levels. 5. The voltage set so as not to be over-programmed by the word voltage, and the skip count is a count obtained by dividing a level difference between the plurality of determination levels by the step voltage. Nonvolatile semiconductor memory device.   The verification means for determining a change in the threshold value of the multi-value cell includes a plurality of determination levels for determining a multi-value level at the time of reading the multi-value cell, and a plurality of determination levels for determining a change in the threshold value of the write target cell. 5. The nonvolatile semiconductor memory device according to claim 4, further comprising switching means for switching between the two.

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