JP2010009689A - Nonvolatile semiconductor memory device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor memory device having a write means which controls a threshold value of a memory cell at high speed and with high accuracy without complicating write control. <P>SOLUTION: A word voltage supply means 20 writes information by applying word voltage to respective memory cells corresponding to a step voltage adding signal of a verify means 30. The verify means 30 determines repeatedly degree of changes of threshold values of respective memory cells for each of a plurality of determination levels, repeats outputting the step voltage adding signal to which step voltage becoming smaller in accordance with the determination result is added to the word voltage supply means 20, and sets all threshold values of respective memory cells to a predetermined threshold value while stopping writing to the memory cells having reached the predetermined threshold value. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to writing of a nonvolatile semiconductor memory, and more particularly to a nonvolatile semiconductor memory device having a writing means capable of controlling a threshold value of a memory cell at high speed and with high accuracy.

  When it is necessary to control the memory threshold with high precision at the time of writing, such as a memory chip composed of multi-value cells, a writing method using a gate voltage step method such as ISPP (Incremental Step Pulse Programming) is applied. However, in ISPP, the gate voltage is stepped up in multiple steps, and thus there is a problem that the writing time is delayed due to variations in memory cells.

  A writing method using the ISPP gate voltage step method will be described. FIG. 5 is a cell writing diagram showing the relationship between the word voltage and the memory cell threshold value by the ISPP voltage step method. The horizontal axis shows the word voltage at the time of writing, and the vertical axis shows the memory cell threshold voltage Vtm after writing for a certain time under the conditions.

  In FIG. 5, of the two diagonal lines, the line with the higher threshold indicates the write operation of the cell with faster writing, and the line with the lower side indicates the write operation of the cell with the slower write. The threshold values of all the memory cells are distributed between the two lines indicated by the arrows, and the cell corresponding to the right end of the arrow indicates a memory cell that is slowly written. The write start voltage of the word line is set so that the fast write cell is not over-programmed with respect to all the memory cells in the write unit. A range indicated by an arrow on the left side of a line with a higher threshold indicates a margin voltage set so that a cell with fast writing is not overprogrammed. The word voltage when writing of all the memory cells in the writing unit is completed is determined by the memory cell that is slow to write.

Vcg-range is a variation in word voltage necessary for completion of writing between a cell with early writing and a memory cell with slow writing, and a margin voltage set so that a cell with early writing is not overprogrammed is Vcg-margin. Assuming that the step voltage at which the write voltage monotonously increases is ΔVcg, the number N of times of writing required for completion of writing is expressed by the following equation.
N = (Vcg−range + Vcg−margin) / ΔVcg + 1
For example, if Vcg-range = 1.6V, Vcg-margin = 0.5V, and ΔVcg = 0.1V, the number of times of writing N is 22 times.

  This write operation will be described again in detail with reference to FIG. It is assumed that the threshold values Vtm11 of all the memory cells in the writing unit are distributed with a threshold variation indicated by '11'. When writing is performed to change the threshold values of all the memory cells to the threshold value Vtm10 distributed with variation indicated by '10', a lower limit voltage (a margin voltage that is set so as not to overprogram the cells that are written quickly) Vcg1 = 2.7) is applied as a word voltage to all memory cells in the writing unit, and if there is a memory cell whose changed threshold value falls within the distribution of the threshold value Vtm10, the writing of that cell is completed.

  Subsequently, the step voltage (ΔVcg = 0.1V) is continuously added to the voltage of Vcg1 = 2.7V, and each time the addition is performed, cells other than the memory cell that has been written are read, and the changed threshold value is the distribution of the threshold Vtm10 If there is a memory cell that enters, the writing of the cell is completed, and the process is repeated until the word voltage reaches a voltage Vcg2 = 5.5V at which the word voltage reaches the upper limit of the variation Vcg-range of the word voltage. In this case, the write count N is 29 times. Similarly, when writing is performed to change to the threshold value Vtm01 distributed with variations indicated by “01”, since Vcg3 = 4.5V and Vcg4 = 7.2V, the number of times of writing N is 28 times. .

  From this, the time required for the completion of writing to set the threshold value of the memory cell to a predetermined value is determined by applying a word voltage, determining a change in the threshold value, excluding the memory cell that has been written, and then setting the next word voltage. Assuming that the time until application is T, in the case of the threshold value Vtm10, a time of 29 · T is required, and in the case of the threshold value Vtm01, a time of 28 · T is required. In order to reduce this time, it is necessary to reduce the number N of times of writing.

Patent Document 1 discloses a writing circuit for writing data to a nonvolatile semiconductor memory cell in which data can be electrically rewritten for the purpose of narrowing the distribution width of threshold voltage after writing while suppressing an increase in writing time. Yes, by supplying a write voltage and a write control voltage to the memory cell, writing to the memory cell to change the write state of the memory cell, changing the supply state of the write control voltage to reduce the change speed of the write state, It is described that the supply state of the write control voltage is further changed to control the relaxed write state change speed, and the write to the memory cell is completed while the write state change speed is relaxed. However, according to this, since the two voltage levels of the write voltage and the write control voltage are controlled and supplied in order to change the write state of the memory cell, the control becomes complicated.
JP 2005-174414 A

  The present invention has been made to solve such a problem, and an object of the present invention is to control the threshold value of the memory cell at high speed and with high accuracy without complicating the write control. An object of the present invention is to provide a nonvolatile semiconductor memory device having a writing means.

  The nonvolatile semiconductor memory device of the present invention includes a word voltage supply means for supplying a word voltage of a plurality of write voltage levels to each word line on the memory cell array, and a threshold value of each memory cell of the memory array for the plurality of write voltage levels. A non-volatile semiconductor memory device having verify means for judging a change corresponding to a plurality of judgment levels, wherein a word voltage supply means applies an initial write voltage to each memory cell and then outputs it from the verify means The word voltage corresponding to the step voltage addition signal is applied to each memory cell to perform writing, and the verifying means repeatedly determines the degree of change in the threshold value of each written memory cell for each of a plurality of determination levels, The step voltage addition signal obtained by adding the step voltage changed according to the determination result is used as the word voltage supply means. Repeat the process of outputting, while stopping the write to the memory cell reaches a predetermined threshold value, and sets all threshold values of the memory cells to a predetermined threshold value. As a result, the step voltage of the word voltage at the time of writing is gradually changed to a smaller value based on the voltage difference between the verification determination levels.

  The first write voltage of the nonvolatile semiconductor memory device of the present invention is a write start voltage that is set so that a memory cell that is fast written out of each memory cell is not over-programmed, and the last determination level is a write completion determination level It is characterized by being. As a result, overprogramming at the start and end of writing is suppressed.

  The step voltage of the nonvolatile semiconductor memory device of the present invention includes a maximum step voltage that does not exceed the level difference between the write completion determination level and the first determination level, and the first determination level and the last determination level among a plurality of determination levels. An intermediate step voltage that does not exceed the level difference between each judgment level except the previous judgment level and the write completion judgment level, and the last judgment level of the plurality of judgment levels and the previous judgment level. And a minimum step voltage obtained by dividing the level difference by an arbitrary number. As a result, the number of writes is controlled to be minimized.

  Since the memory array of the nonvolatile semiconductor memory device of the present invention is composed of multi-value cells and each threshold value of the multi-value cell is written to a predetermined multi-value threshold value, a plurality of determinations for each threshold value of the multi-value cell are performed. Writing is performed by repeating the operation of generating a step voltage corresponding to the level, and all threshold values of the multi-value cell are set to the predetermined threshold value while completing the writing to the memory cell that has reached the predetermined threshold value. It is characterized by. As a result, the step voltage of the word voltage at the time of writing in the multi-value cell is similarly changed to a gradually smaller value based on the voltage difference of the verification determination level.

  In order to perform writing with a predetermined threshold value to each of the multi-value cells of the nonvolatile semiconductor memory device of the present invention, the initial write voltage is set so that the memory cells that are written earlier among the multi-value cells are not over-programmed. It is a start voltage, and the last determination level is a write completion determination level. As a result, overprogramming at the start and end of writing in the multilevel cell is suppressed.

  The step voltage generated for each of the plurality of determination levels for each of the multilevel cells of the nonvolatile semiconductor memory device of the present invention is the maximum step voltage that does not exceed the level difference between the write completion determination level and the first determination level. The intermediate step voltage that does not exceed the level difference between each judgment level and the write completion judgment level excluding the judgment level immediately before the first judgment level and the last judgment level among the plurality of judgment levels, and the plurality of judgments It has a minimum step voltage obtained by dividing a level difference between the last determination level of the level and the previous determination level by an arbitrary number. Thus, the number of times of writing in the multi-value cell is controlled to be minimized.

  The verify means for determining the change of the threshold value of the multi-value cell of the nonvolatile semiconductor memory device of the present invention includes a plurality of determination levels for determining the multi-value level at the time of reading the multi-value cell and the change of the threshold value of the write target cell It has a switching means for switching between a plurality of determination levels to be determined. Thereby, the usage of the memory is switched by a simple switching operation.

  According to the present invention, the number of times of performing a write operation can be reduced without complicating the write control by changing the step voltage of the word voltage at the time of writing to a gradually smaller value based on the voltage difference of the verification determination level. Therefore, it is possible to provide a nonvolatile semiconductor memory device having writing means that can control the threshold value of the memory cell with high speed and high accuracy.

  FIG. 1 is a block diagram of a device configuration showing an embodiment of a nonvolatile semiconductor memory device according to the present invention. In FIG. 1, the nonvolatile semiconductor memory device 100 includes a memory cell array 10, a word voltage supply unit 20, and a verify unit 30. The word voltage supply means 20 includes a program counter 22, a word voltage generator 24, and an X decoder 26. The verifying unit 30 includes a sense amplifier 33 and a verify check circuit 37.

  FIG. 2 is a cell writing diagram showing the relationship between the word voltage at the time of writing and the threshold value of the memory cell in the embodiment according to the present invention. Description of items common to FIG. 5 is omitted. The write operation of FIG. 2 will be described based on the circuit of FIG. The verify means 30 has three levels of verify levels V1 (4V), V2 (5V), and V3 (6V), and the initial threshold value Vtm11 is distributed with the threshold variation indicated by the region '11'. It is assumed that writing is performed to change all the memory cells in the unit to the threshold value Vtm00 distributed in the variation indicated by the region of “00” exceeding the verify level V3 (6V). However, in the following description, a 3-bit cell indicated by a circle in FIG.

  First, the word voltage generator 24 of the word voltage supply means 20 sets a write start voltage (Vcg1 = 2.5 V), which is a voltage that reaches the lower limit of the margin voltage set so that a cell with fast writing is not overprogrammed. The voltage is applied to all memory cells in the writing unit via the X decoder 26. The sense amplifier 33 of the verify means 30 determines whether there is a memory cell whose changed threshold value falls within the range of the threshold value Vtm10 or Vtm01 based on the verify level V1 / V2 / V3 that is the determination level, and determines the step voltage. The 2-bit digital value SAOUT to be determined is output to the verify check circuit 37. The verify check circuit 37 outputs a step voltage addition signal PGSKIP obtained by adding a step voltage composed of a digital value based on the 2-bit digital value.

First, case 1 in FIG. 2 will be described. Without memory cell threshold is in the range of the threshold Vtm10 beyond the verify level V1, since the threshold values of all the cells remains still within the range of the threshold value Vtm11, difference verify level is the largest step voltage (V3 Further application of a voltage of −V1 = 2 volts does not generate cells that are overprogrammed far beyond the verify level V3. Therefore, the sense amplifier 33 indicates that there is no memory cell that falls within the range of the thresholds Vtm10 and Vtm01, and outputs a 2-bit digital value SAOUT (all SAOUTs are '11' or '00') that determines the step voltage. Based on this, the verify check circuit 37 outputs a voltage control signal PGSKIP for causing the word voltage generator 24 to generate a voltage of 4.5 V obtained by adding the maximum step voltage 2 V to the write start voltage. The program counter 22 outputs a word voltage control signal PGCOUNT based on this PGSKIP. The word voltage generator 24 receives this PGCOUNT and applies a 4.5 V word voltage VPW to the memory cell via the X decoder 26.

  Next, case 2 in FIG. 2 will be described. When there is a memory cell whose threshold exceeds the verify level V1 and falls within the range of the threshold Vtm10, and when there is no cell that exceeds the verify level V2 and falls within the range of the threshold Vtm01, the thresholds of the memory cells are the thresholds Vtm00, Vtm10, and Vtm11. It is in a state of being mixed in both ranges. For this reason, even if a voltage of a verify level difference (V3−V2 = 1 volt), which is an intermediate step voltage, is further applied, a cell that is overprogrammed far beyond the verify level V3 does not occur.

  Therefore, the sense amplifier 33 similarly has a 2-bit digital value SAOUT (all SAOUTs are '11') indicating that there are memory cells that fall within the range of the threshold value Vtm10 and no memory cells that fall within the range of the threshold value Vtm01. Or “10” or “00”), and based on this, the verify check circuit 37 adds a voltage of 5.9 V obtained by adding an intermediate step voltage 1 V to the write word voltage 4.9 V of the previous cycle. PGSKIP to be generated by the word voltage generator 24 is output. Based on this, the program counter 22 outputs PGCOUNT. The word voltage generator 24 receives this and applies a word voltage VPW of 5.9 V to the memory cell via the X decoder 26.

  Next, case 3 in FIG. 2 will be described. In this case, the threshold value of the memory cell is mixed in any of the ranges of the threshold values Vtm10, Vtm01, and Vtm00. For this reason, among the remaining memory cells mixed in the ranges of the threshold values Vtm10 and Vtm01, the cells distributed in the vicinity of the verify level V3 have the minimum step voltage necessary to finally realize the target distribution width. Otherwise, there may be cells that are overprogrammed far beyond verify level V3.

  Therefore, the sense amplifier 33 outputs a 2-bit digital value SAOUT (a case where the combination of SAOUTs of all sense amplifiers is other than cases 1 and 2) indicating that there is a memory cell that falls within the range of the threshold value Vtm01. Based on this, the check circuit 37 outputs a step voltage addition signal PGSKIP for causing the word voltage generator 24 to generate 5.5 V, for example, by adding the minimum step voltage (0.1 V) divided into ten. Based on this, the program counter 22 outputs a word voltage control signal PGCOUNT. The word voltage generator 24 receives this and applies a 5.5 V word voltage VPW to the memory cell via the X decoder 26.

  The verify unit 30 and the word voltage supply unit 20 repeat the operation of adding the minimum step voltage (0.1 V), and if there is a memory cell in which the changed threshold value falls within the distribution of the threshold value Vtm00, the sense amplifier 33 A binary digital value SAOUT (00) indicating that there is a memory cell that falls within the distribution is output. In the cell in which this signal is detected, it is determined that the writing is completed, and the writing is stopped. When the threshold values of all the memory cells exceed the predetermined verify level V3, the write operation is finished.

  As described above, the number of times of writing by the word voltage supply means 20 is 12 in total in the case of FIG. 2, and the number of times of writing can be greatly reduced. For this reason, the writing time can be significantly reduced. Further, it is not necessary to control and supply the two voltage levels of the write voltage and the write control voltage, and only the write voltage may be controlled, so that complicated control is not required.

  Further, when the memory cell array is composed of multi-value cells, the above-described verify level V3 is determined corresponding to each multi-value threshold level, and the verify level corresponding to the write start voltage depending on the memory cell array. By determining V1, verify level V2 is determined, and three verify levels for each threshold level can be determined. As a result, it is possible to speed up the write operation of each threshold value of the memory cell array composed of multi-value cells.

  FIG. 3 is a word voltage level diagram showing the relationship between the voltage level applied to each memory cell on the word line and the step voltage. First, the word voltage supply means 20 applies the write start voltage as the word voltage VPW to all the memory cells in the write unit. For example, the case where the writing is performed in each memory cell connected to the intersection of the word line WL0 and the bit lines BL0 to BLn in FIG. 1 is shown in the PGM section, and the drain voltages of the memory cells are successively applied to BL0 to BLn. Supplied. Next, the verifying means 30 is such that the threshold value of these memory cells is distributed with a threshold variation indicated by '11', so that the voltage obtained by adding the maximum step voltage (2.0 V) to the word voltage at the time of writing in the previous cycle. Is output to the word voltage generator 24 as a digital value PGSKIP (PV period). The word voltage generator 24 applies a word voltage VPW, which is a voltage obtained by adding the maximum step voltage (2.0 V) to the word voltage at the time of writing in the previous cycle, to the memory cell via the X decoder 26.

  Similarly, the verifying unit 30 determines the presence of a cell in which the threshold value of the memory cell is distributed with a threshold variation indicated by “10”, and an intermediate step voltage (1.0 V) is added to the word voltage at the time of writing in the previous cycle. ) Is output as a digital value PGSKIP for causing the word voltage generator 24 to generate a voltage. The word voltage generator 24 applies a word voltage VPW, which is a voltage obtained by adding an intermediate step voltage (1.0 V) to the word voltage at the time of writing in the previous cycle, to the memory cell via the X decoder 26. Further, the verifying means 30 determines the presence of a cell in which the threshold value of the memory cell is distributed with a threshold variation indicated by “01”, and adds the minimum step voltage (0.1 V) to the word voltage at the time of writing in the previous cycle. A digital value PGSKIP for generating a voltage to the word voltage generator 24 is output.

  The word voltage generator 24 applies a word voltage VPW, which is a voltage obtained by adding the minimum step voltage (0.1 V) to the word voltage at the time of writing in the previous cycle, to the memory cell via the X decoder 26. Subsequently, the word voltage generator 24 repeats the step of adding the minimum step voltage (0.1 V) and applying it to the memory cell. When the verifying unit 30 determines that there is a cell that falls within the threshold variation distribution indicated by the memory cell threshold value “00” every time it is repeated, writing to the cell is stopped and the threshold values of all the memory cells are set to “00”. When it is determined that the distribution of the threshold variation indicated by 'is found, the writing ends.

  FIG. 4 is a circuit block diagram showing an embodiment of the sense amplifier according to the present invention. In FIG. 4, the sense amplifier 33 includes a verify level input switching unit 34, a level determination unit 35, and a decoder 36. The verify level input switching means 34 is composed of a plurality of switches 34-1 to 43-3, and verify levels V1 to V3 for determining the threshold level of the write target cell are input to one of the inputs of each switch, respectively. Are supplied with reference levels Vm1 to Vm3 necessary for multi-level reading.

  The output of each switch is input to one input of level determiners 35-1 to 35-3 of the level determining means, and the threshold Vmt of the memory cell changed by writing is read and input to the other. The level determiners 35-1 to 35-3 determine the degree of change in the threshold value Vmt based on the reference level and the verify level, and output the result. Based on the determination result, the decoder 36 outputs one of the binary digital outputs SAOUT ('11' to '00') indicating to which of the four states the threshold value Vmt belongs to the verify check circuit 37.

  As described above, by turning on the switches 34-1 to 43-3 to the verify levels V1 to V3, it is possible to determine the change in the write threshold value of the write target cell described in FIG. 1, and the reference levels Vm1 to Vm3. By turning on the multi-level memory cell, it is possible to determine the multi-value level during normal reading in the memory cell array composed of multi-value memory cells described in paragraph [0029]. The verify levels V1 to V3 and the reference levels Vm1 to Vm3 are supplied from each current / voltage conversion circuit (not shown), and the verify levels V1 to V3 have verify levels corresponding to multi-value threshold levels. It is switched and supplied as appropriate. As a result, in a nonvolatile semiconductor memory device employing a multi-valued memory, the present invention can be applied by adding only a switch to a sense amplifier used during normal reading.

  As described above, according to the present invention, the step voltage of the word voltage at the time of writing is changed to a plurality of values based on the voltage difference of the verification determination level, so that the writing control is not complicated. The number of operations can be reduced. Therefore, there is provided a non-volatile semiconductor memory device having a writing means capable of controlling the threshold value of a memory cell with high reliability and high speed and high accuracy since drain disturbance for unselected cells is alleviated. It becomes possible.

1 is a block diagram showing a device configuration of a nonvolatile semiconductor memory device according to the present invention. FIG. 4 is a cell writing diagram showing a relationship between a word voltage and a memory cell threshold at the time of writing according to the present invention. The word voltage level figure which shows the relationship between the voltage level concerning each memory cell on a word line, and a step voltage. The circuit block diagram which shows the sense amplifier by this invention. The cell write figure which shows the relationship between the word voltage by an ISPP voltage step system, and the threshold value of a memory cell.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Memory cell array 20 Word voltage supply means 22 Program counter 24 Word voltage generator 26 X decoder 30 Verification means 33 Sense amplifier 34 Verification level input switching means 34-1-3 Switch 35 Level determination means 35-1-3 Level determination device 36 Decoder 37 Verify check circuit 100 Non-volatile semiconductor memory device Vtm Memory cell threshold value VPW Word voltage V1 to V3 Verify level Vm1 to Vm3 Reference level '11' Set threshold value region below V1 '10' Set of threshold values between V1 and V2 Threshold value set region '01' between V2 and V3 '00' Set value region above threshold value V3 WL0 to WLn Word line BL0 to BLn Bit line SAOUT Binary digital value PGSKIP Step voltage addition signal PGCOUNT Word voltage control signal

Claims (7)

Word voltage supply means for supplying word voltages of a plurality of write voltage levels to each word line on the memory cell array, and changes in threshold values of each memory cell of the memory array with respect to the plurality of write voltage levels correspond to a plurality of determination levels A non-volatile semiconductor memory device having verify means for determining
The word voltage supply means applies an initial write voltage to each memory cell, and then applies a word voltage corresponding to a step voltage addition signal output from the verify means to each memory cell to perform writing. ,
The verify means repeatedly determines the degree of change of the threshold value of each written memory cell for each of the plurality of determination levels, and adds the step voltage addition signal obtained by adding a step voltage that is changed according to the determination result. The process of outputting to the word voltage supply means is repeated, and all threshold values of the memory cells are set to the predetermined threshold value while writing is stopped for the memory cells that have reached a predetermined threshold value. A nonvolatile semiconductor memory device.   The first write voltage is a write start voltage that is set so that a memory cell that is quickly written out of the memory cells is not over-programmed, and the last determination level is a write completion determination level. The nonvolatile semiconductor memory device according to claim 1.   The step voltage is a maximum step voltage that does not exceed a level difference between the write completion determination level and the first determination level, and a determination immediately before the first determination level and the last determination level among the plurality of determination levels. Arbitrarily set the step voltage at an intermediate stage not exceeding the level difference between each judgment level except the level and the write completion judgment level, and the level difference between the last judgment level of the plurality of judgment levels and the previous judgment level The non-volatile semiconductor memory device according to claim 1, further comprising: a minimum step voltage divided by the number of.   The memory array is composed of multi-value cells, and each threshold value of the multi-value cell is written to a predetermined multi-value threshold value, and therefore corresponds to the plurality of determination levels for the respective threshold values of the multi-value cell. Performing the writing by repeating the operation of generating a step voltage, and setting all the thresholds of the multi-valued cells to the predetermined threshold while completing the writing to the memory cells that have reached the predetermined threshold. The nonvolatile semiconductor memory device according to claim 1.   In order to perform writing with a predetermined threshold value to each of the multi-value cells, the first write voltage is a write start voltage that is set so that memory cells that are written earlier among the multi-value cells are not over-programmed. The nonvolatile semiconductor memory device according to claim 4, wherein the determination level is a write completion determination level.   The step voltage generated for each of the plurality of determination levels for each of the multi-value cells is a maximum step voltage that does not exceed a level difference between a write completion determination level and an initial determination level, and the plurality of determination levels. And a step voltage at an intermediate stage not exceeding a level difference between each determination level except the determination level immediately before the first determination level and the last determination level and the write completion determination level, and the plurality of determination levels 5. The nonvolatile semiconductor memory device according to claim 4, further comprising a minimum step voltage obtained by dividing an arbitrary number of level differences between the last determination level and the previous determination level.   The verification means for determining a change in the threshold value of the multi-value cell includes a plurality of determination levels for determining a multi-value level at the time of reading the multi-value cell, and a plurality of determination levels for determining a change in the threshold value of the write target cell. 5. The nonvolatile semiconductor memory device according to claim 4, further comprising switching means for switching between the two.

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