JP2010014921A - Display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a display device for preventing the occurrence of flickering caused by change of parasitic capacity among a source electrode, a drain electrode, and a gate electrode and increasing operation speed of a thin film transistor. <P>SOLUTION: In this display device 100, the gate electrode 1A in the thin film transistor 4 is formed to protrude from a gate line 1 and extend in a predetermined direction in a plane view, the source electrode 8 and the drain electrode 9 are arranged in parallel to each other in a plane view and are bent in a circle in a region where the gate electrode 1A and a semiconductor layer 7 are mutually overlapped in a plane view. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a display device.

  Conventionally, display devices are known (see, for example, Patent Document 1). The thin film transistor of the display device disclosed in Patent Document 1 includes a gate electrode, a semiconductor layer disposed so as to overlap with the gate electrode, and a source electrode and a drain electrode disposed so as to overlap with the gate electrode and the semiconductor layer. It is configured. The source electrode and the drain electrode of this thin film transistor are branched electrodes in which the portion in the region of the semiconductor layer is branched into a plurality, and each branched electrode extends in a direction orthogonal to the direction in which the gate electrode extends. It is comprised from the elongate shape part formed. The elongated portion of the source electrode and the elongated portion of the drain electrode are arranged in parallel, and a channel region is formed in the region of the semiconductor layer corresponding to the elongated portion.

In Patent Document 1, the elongated portion of the source electrode and the distal end portion of the elongated portion of the drain electrode are formed so as to protrude from the semiconductor layer when seen in a plan view. As a result, even when the source electrode (drain electrode) is formed so as to be shifted in the direction in which the elongated shape portion extends in a plan view with respect to the semiconductor layer and the gate electrode, the magnitude of this shift is determined by the source electrode (drain electrode). The area of the portion where the source electrode (drain electrode) overlaps the semiconductor layer and the gate electrode when viewed in plan if the elongated shape portion of the electrode is less than the length of the portion protruding from the semiconductor layer when viewed in plan (Overlapping area) does not change. Thereby, it is possible to suppress the occurrence of flicker due to a change in parasitic capacitance between the source electrode (drain electrode) and the gate electrode. Further, even when the source electrode (drain electrode) is formed in a direction perpendicular to the direction in which the elongated portion extends as viewed in plan with respect to the semiconductor layer and the gate electrode, the source electrode (drain electrode) and the semiconductor are formed. Since the overlapping area between the layer and the gate electrode does not change, it is possible to suppress the occurrence of flicker due to a change in parasitic capacitance between the source electrode (drain electrode) and the gate electrode.
JP 2005-535147 A

  However, in the thin film transistor of the display device described in Patent Document 1, the source electrode and the drain electrode are formed so as to extend in a direction orthogonal to the direction in which the gate electrode extends (the short direction of the gate electrode). The channel width of the semiconductor layer corresponding to the region between the electrode and the drain electrode is at most the length in the short direction of the gate electrode. For this reason, since the channel width is reduced, the current drive capability is reduced correspondingly, and as a result, it is difficult to improve the operation speed.

  The present invention has been made to solve the above-described problems, and one object of the present invention is to suppress flicker caused by a change in parasitic capacitance between the source electrode, the drain electrode, and the gate electrode. At the same time, it is an object to provide a display device capable of improving the operation speed of a thin film transistor.

  In order to achieve the above object, a display device according to one aspect of the present invention includes a gate line including a gate electrode, a semiconductor layer formed so as to overlap the gate electrode in plan view, the gate electrode, and the semiconductor layer And a source electrode and a drain electrode electrically connected to the semiconductor layer, respectively, and the gate electrode protrudes from the gate line in a plan view and extends in a predetermined direction. The source electrode and the drain electrode are formed so as to extend in parallel with each other when seen in a plan view, and are bent or curved while swiveling on a region where the gate electrode and the semiconductor layer overlap in a plan view. Yes.

  In the display device according to this aspect, as described above, the source electrode and the drain electrode formed on the gate electrode and the semiconductor layer are formed so as to be bent or curved so as to rotate. Since the effect of increasing the channel width and the carrier mobility can be obtained, the operation speed of the thin film transistor can be improved. In the manufacturing process, even if the source electrode and the drain electrode are shifted in the horizontal direction or the vertical direction due to the problem of the accuracy of the exposure machine, the gate electrode and the semiconductor layer overlap because the channel is formed by turning. Since there is no change in the overlapping area of the upper source electrode and the drain electrode, flicker caused by a change in parasitic capacitance between the source electrode, the drain electrode and the gate electrode can be suppressed. As a result, a high-quality display device can be provided without impairing TFT characteristics.

  In the display device according to this aspect, the source electrode and the drain electrode have a substantially L shape and are disposed so that the inner portions of the substantially L shape face each other when viewed in a plan view. Thereby, an L-shaped channel region is formed in the region of the semiconductor layer corresponding to the region between the source electrode and the drain electrode. As a result, the channel width of the semiconductor layer can be increased, so that the current driving capability of the thin film transistor can be increased. Thereby, the operation speed of the thin film transistor can be improved.

  In the display device according to the one aspect described above, preferably, the channel region formed between the source electrode and the drain electrode is between the source electrode and the drain electrode formed by bending or bending while turning each other. Is formed. With this configuration, the channel width formed on the gate electrode and the semiconductor layer can be increased. Thereby, the current drive capability of the thin film transistor can be increased.

  In this case, preferably, the channel length of the channel region formed by turning or bending while turning is formed while maintaining a uniform interval. With this configuration, the source electrode and the drain electrode are arranged while being rotated in parallel while maintaining a certain distance, so that the distance between each source electrode and the drain electrode can be formed while maintaining a uniform distance. The channel length can be made constant. Even if pattern misalignment or the like occurs, the parasitic area generated between the gate electrode, the source electrode, and the drain electrode is difficult because the overlapping area between the source electrode and the drain electrode formed on the gate electrode is difficult to change. Can be suppressed.

  In the display device according to the above aspect, the length of the source electrode and the drain electrode in the short direction is preferably 1 / of the length in the short direction of the region where the gate electrode and the semiconductor layer overlap in plan view. 3 or less. With such a configuration, it is possible to easily prevent the source electrode and the drain electrode from protruding from the semiconductor layer when seen in a plan view while forming a channel region between the source electrode and the drain electrode.

  In the display device according to the above aspect, the drain electrode preferably includes a contact portion connected to the pixel electrode, and the contact portion is disposed in the vicinity of the gate line. If comprised in this way, it can suppress that the length of the wiring of a drain electrode becomes large.

  In the display device according to the above aspect, the source electrode and the drain electrode are preferably disposed on the inner side of the outer edge portion along the longitudinal direction of the gate electrode in a region where the gate electrode and the semiconductor layer overlap. As a result, even when the source electrode (drain electrode) is formed to be shifted in the direction of the gap when seen in a plan view, if the deviation is within the size of the gap, the source electrode (drain electrode) and the gate electrode It is possible to suppress the change of the overlapping area. As a result, flicker caused by a change in parasitic capacitance between the source electrode (drain electrode) and the gate electrode can be suppressed.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(First embodiment)
FIG. 1 is an overall configuration diagram of a display device according to a first embodiment of the present invention. 2 and 3 are plan views of thin film transistors of the display device according to the first embodiment of the present invention. 4 is a cross-sectional view taken along line 200-200 in FIG. First, with reference to FIGS. 1-4, the structure of the display apparatus 100 by 1st Embodiment of this invention is demonstrated.

  As shown in FIG. 1, the display device 100 according to the first embodiment includes a gate line 1 and a signal line 2 arranged so as to intersect the gate line 1. Pixels 3 are provided at positions where the gate line 1 and the signal line 2 intersect each other. In the first embodiment, each of the plurality of pixels 3 is provided with a bottom gate type thin film transistor (TFT) 4.

Further, as a cross-sectional structure of the thin film transistor 4, a gate electrode 1A is provided on a glass substrate 5 as shown in FIG. In the first embodiment, as shown in FIG. 2, the gate electrode 1A protrudes from the gate line 1 in the direction of the arrow Y1 (direction in which the signal line 2 extends) and also in the direction of the arrow Y1 as viewed in a plan view. It is formed in a rectangular shape so as to extend to the side. Further, as shown in FIG. 4, on the gate electrode 1A, the a-Si layer 7A and n ⁺ having n-type conductivity so as to overlap the gate electrode 1A in plan view through the gate insulating film 6 are provided. A semiconductor layer 7 made of the Si layer 7B is formed.

  A source electrode 8 and a drain electrode 9 are formed on the semiconductor layer 7 so as to overlap the gate electrode 1 </ b> A and the semiconductor layer 7 in plan view and electrically connected to the semiconductor layer 7. A channel region 73 is formed in a region between the source electrode 8 and the drain electrode 9 of the semiconductor layer 7.

  As shown in FIG. 2, the source electrode 8 is electrically connected to the signal line 2. Here, in the first embodiment, the source electrode 8 is formed in an L shape. Further, the two sides 81A and 81B in the direction in which the source electrode 8 extends are formed so as to overlap both the gate electrode 1A and the semiconductor layer 7 in plan view. As shown in FIG. 3, the source electrode 8 is composed of a first portion 82 on the tip side of the bent portion 81C (see FIG. 2) and a second portion 83 on the opposite side of the tip portion of the bent portion 81C. ing. The first portion 82 is formed in the direction in which the signal line 2 extends, and the second portion 83 is formed in the direction in which the gate line 1 extends.

  As shown in FIG. 2, the drain electrode 9 is connected to a contact portion 10 that is electrically connected to a pixel electrode 13 described later. Here, in the first embodiment, the contact portion 10 is formed in the vicinity of the gate electrode 1 </ b> A and the gate line 1. In the first embodiment, the drain electrode 9 is formed in an L shape. Two sides 91A and 91B in the direction in which the drain electrode 9 extends are formed so as to overlap both the gate electrode 1A and the semiconductor layer 7 when seen in a plan view. As shown in FIG. 3, the drain electrode 9 is composed of a third portion 92 on the tip side of the bent portion 91C (see FIG. 2) and a fourth portion 93 on the side opposite to the tip side of the bent portion 91C. ing. The third portion 92 is formed in the direction in which the signal line 2 extends, and the fourth portion 93 is formed in the direction in which the gate line 1 extends. From the above configuration, in the first embodiment, the source electrode 8 and the drain electrode 9 are formed to be bent or curved so as to turn on the stack of the gate electrode 1 </ b> A and the semiconductor layer 7.

  The length L1 in the long side direction of the first portion 82 of the source electrode 8 is larger than the length L2 in the long side direction of the second portion 83, and the long side direction of the third portion 92 of the drain electrode 9 is long. The length L3 is configured to be larger than the length L4 of the fourth portion 93 in the long side direction.

  Further, the long side 82A of the first portion 82 of the source electrode 8 and the long side 92A of the third portion 92 of the drain electrode 9 are opposed to each other. Further, the long side 83A of the second portion 83 of the source electrode 8 and the short side 92B (tip portion 9A) of the third portion 92 of the drain electrode 9 face each other. Further, the short side 82B (tip portion 8A) of the first portion 82 of the source electrode 8 and the long side 93A of the fourth portion 93 of the drain electrode 9 are opposed to each other.

  In addition, a gap L5 is provided between the first portion 82 of the source electrode 8 and the long side of the gate electrode 1A on the first portion 82 side, and the third portion 92 of the drain electrode 9 and the gate electrode There is a gap L6 between the long side of 1A on the third portion 92 side. That is, in the first embodiment, the first portion 82 of the source electrode 8 is formed from the outer edge of the overlapping portion of the gate electrode 1A and the semiconductor layer 7 (the long side of the gate electrode 1A on the first portion 82 side) to the inner side (signal (Line 2 side) with a gap L5. Further, the third portion 92 of the drain electrode 9 extends from the outer edge of the overlapping portion of the gate electrode 1A and the semiconductor layer 7 (the long side on the third portion 92 side of the gate electrode 1A) to the inner side (the side opposite to the signal line 2). Are arranged at a distance L6.

  In addition, a gap L7 is provided between the second portion 83 of the source electrode 8 and the short side of the semiconductor layer 7 on the second portion 83 side, the fourth portion 93 of the drain electrode 9, and the semiconductor layer. 7 is spaced from the short side on the fourth portion 93 side. In other words, in the first embodiment, the second portion 83 of the source electrode 8 extends from the outer edge portion (the long side of the gate electrode 1A on the second portion 83 side) to the inner side (gate side) of the gate electrode 1A and the semiconductor layer 7. It is arranged on the opposite side of the line 1 with a gap L7. Further, the fourth portion 93 of the drain electrode 9 is spaced from the outer edge portion (the long side of the gate electrode 1A on the fourth portion 93 side) to the inner side (gate line 1 side) of the overlapping portion of the gate electrode 1A and the semiconductor layer 7. It arrange | positions across L8.

  In the first embodiment, the semiconductor layer 7 includes a semiconductor layer 7 corresponding to a region between the first portion 82 of the source electrode 8 and the third portion 92 of the drain electrode 9 in plan view. A channel region 73A is formed in the region, and a channel region 73B is formed in the region of the semiconductor layer 7 corresponding to the region between the first portion 82 of the source electrode 8 and the fourth portion 93 of the drain electrode 9. A channel region 73 </ b> C is formed in the region of the semiconductor layer 7 corresponding to the region between the second portion 83 of the source electrode 8 and the third portion 92 of the drain electrode 9.

  Further, the distance L9 in the direction in which the gate line 1 extends between the first portion 82 of the source electrode 8 and the third portion 92 of the drain electrode 9, the fourth portion of the first portion 82 of the source electrode 8, and the fourth portion of the drain electrode 9. An interval L10 in the direction in which the signal line 2 extends between the portion 93 and an interval L11 in the direction in which the signal line 2 extends between the second portion 83 of the source electrode 8 and the third portion 92 of the drain electrode 9. Are approximately equal.

  In the first embodiment, the channel length L 12 of the semiconductor layer 7 in the direction in which the gate line 1 extends between the first portion 82 of the source electrode 8 and the third portion 92 of the drain electrode 9, The channel length L13 of the semiconductor layer 7 in the direction in which the signal line 2 extends between the first portion 82 and the fourth portion 93 of the drain electrode 9, the second portion 83 of the source electrode 8, and the third portion of the drain electrode 9. The channel length L14 in the direction in which the signal line 2 between the portion 92 extends is substantially equal.

  In the first embodiment, the length L15 in the short side direction of the first portion 82 of the source electrode 8, the length L16 in the short side direction of the second portion 83, and the short side of the third portion 92 of the drain electrode 9 are used. The length L17 in the direction and the length L18 in the short side direction of the fourth portion 93 are not more than 1/3 of the length L19 in the short direction of the region where the gate electrode 1A and the semiconductor layer 7 overlap.

  As shown in FIG. 4, an insulating film 11 is formed on the source electrode 8 and the drain electrode 9, and an interlayer film 12 is formed on the insulating film 11. A pixel electrode 13 made of a transparent electrode is formed on the interlayer film 12. As described above, in the first embodiment, the thin film transistor 4 is a bottom gate type in which the gate electrode 1 </ b> A is formed below the semiconductor layer 7 via the gate insulating film 6.

  FIG. 5 and FIG. 6 are diagrams for explaining a positional shift between the source electrode and the drain electrode of the thin film transistor of the display device according to the first embodiment of the present invention. Next, with reference to FIG. 5 and FIG. 6, the positional shift of the source electrode 8 and the drain electrode 9 of the thin film transistor 4 will be described.

  The source electrode 8 (drain electrode 9) indicated by the solid line in FIG. 5 represents a case where the length is shifted by a length L20 from the predetermined position (two-dot chain line) shown in FIG. The fourth portion 93 of the drain electrode 9 and the fourth portion of the semiconductor layer 7 when the drain electrode 9 is shifted from the predetermined position by the length L20 in the direction of the arrow Y1 and when the drain electrode 9 is not shifted from the predetermined position. Since an interval L8 (see FIG. 3) is provided between the short side on the 93 side, the overlapping area of the portion where the drain electrode 9 overlaps both the gate electrode 1A and the semiconductor layer 7 in plan view. Does not change. Even if the source electrode 8 is displaced in the direction of the arrow Y1, the overlapping area of the source electrode 8 does not change. Similarly, when the source electrode 8 is displaced from the predetermined position in the arrow Y2 direction side and when it is not displaced from the predetermined position, the second portion 83 of the source electrode 8 and the second portion 83 side of the semiconductor layer 7 are arranged. Since an interval L7 (see FIG. 3) is provided between the short sides, the overlapping area of the portion where the source electrode 8 overlaps both the gate electrode 1A and the semiconductor layer 7 in plan view does not change. . Even if the drain electrode 9 is displaced in the direction of the arrow Y2, the overlapping area of the drain electrode 9 does not change.

  Next, the source electrode 8 (drain electrode 9) indicated by the solid line in FIG. 6 represents a case where the length is shifted by the length L21 from the predetermined position (two-dot chain line) shown in FIG. The source electrode 8 (drain electrode 9) is the gate electrode when the source electrode 8 (drain electrode 9) is shifted from the predetermined position by the length L21 in the direction of the arrow X1 and when it is not shifted from the predetermined position. The overlapping area of the portion overlapping with both 1A and the semiconductor layer 7 in plan view is the shifted length L21 and the length L16 in the short side direction of the source electrode 8 (drain electrode 9) shown in FIG. It changes by the area A (area B) corresponding to the product of L18). Similarly, even when the source electrode 8 (drain electrode 9) is shifted from the predetermined position in the direction of the arrow X2 by the length L21, the overlapping area of the overlapping portion changes by the area A (area B). Since the width of the source electrode 8 (drain electrode 9) is small, the width L16 (L18) in the short side direction of the source electrode 8 (drain electrode 9) is large when the source electrode 8 (drain electrode 9) is formed in a large shape. ), The amount of change in the overlapping area is small.

  In the first embodiment, as described above, the source electrode 8 and the drain electrode 9 are formed so as to be bent so as to be swiveled, so that the configured channel width is widened and the carrier mobility is increased. Therefore, the operation speed of the thin film transistor 4 can be improved. In the manufacturing process, even if the source electrode 8 and the drain electrode 9 are shifted in the horizontal direction or the vertical direction due to the problem of the accuracy of the exposure machine, the channel is formed by swiveling. 7 does not change in the overlapping area of the source electrode 8 and the drain electrode 9 that overlap each other, so that flicker caused by a change in parasitic capacitance between the source electrode 8 and the drain electrode 9 and the gate electrode 1A is suppressed. be able to. As a result, the high-quality display device 100 can be obtained without impairing the TFT characteristics.

  Further, in the first embodiment, as described above, the source electrode 8 and the drain electrode 9 are L-shaped when viewed in a plan view, and the L-shaped inner portions are arranged so as to face each other. Thus, an L-shaped channel region 73 is formed in the region of the semiconductor layer 7 corresponding to the region between the source electrode 8 and the drain electrode 9. As a result, since the channel width of the semiconductor layer 7 can be increased, the current driving capability of the thin film transistor 4 can be increased. Thereby, the operation speed of the thin film transistor 4 can be improved.

  Further, in the first embodiment, as described above, the channel region 73 formed between the source electrode 8 and the drain electrode 9 is bent while rotating with respect to each other. The channel width formed on the gate electrode 1A and the semiconductor layer 7 can be increased. Thereby, the current drive capability of the thin film transistor 4 can be increased.

  Further, in the first embodiment, as described above, the channel length of the channel region 73 formed by turning while being bent is formed with the channel length uniformly maintained at a constant interval, so that the source electrode 8 and the drain electrode 9 are formed. Since they are arranged while rotating in parallel while maintaining a certain distance, the distance between each source electrode 8 and drain electrode 9 can be formed uniformly while maintaining a constant distance, and the channel length can be made constant. Even if pattern misalignment or the like occurs, the overlapping area between the source electrode 8 and the drain electrode 9 formed on the gate electrode 1A is difficult to change, so the gate electrode 1A, the source electrode 8 and the drain electrode 9 are not changed. It is possible to suppress a change in parasitic capacitance that occurs between the two.

  In the first embodiment, as described above, the lengths L15 and L17 in the short direction of the source electrode 8 and the drain electrode 9 are set to be short of the region where the gate electrode 1A and the semiconductor layer 7 overlap in a plan view. By making the length L19 in the hand direction or less to 1/3 or less, the channel region 73 is easily formed between the source electrode 8 and the drain electrode 9, and the source electrode 8 and the drain electrode 9 are planarly formed. It is possible to suppress the protrusion from the semiconductor layer 7.

  Moreover, in 1st Embodiment, it can suppress that an aperture ratio falls by arrange | positioning the contact part 10 in the vicinity of the gate line 1 side as mentioned above.

  In the first embodiment, as described above, the source electrode 8 and the drain electrode 9 are arranged on the inner side of the outer edge portion along the longitudinal direction of the gate electrode 1A in the region where the gate electrode 1A and the semiconductor layer 7 overlap. As a result, even when the source electrode 8 (drain electrode 9) is formed in a gap in the direction of the gap when seen in a plan view, the source electrode 8 (drain electrode 9) can be used if the deviation is within the gap size. And the gate electrode 1A overlap area can be prevented from changing. As a result, flicker caused by a change in parasitic capacitance between the source electrode 8 (drain electrode 9) and the gate electrode 1A can be suppressed.

(Second Embodiment)
FIG. 7 is a plan view of a thin film transistor of a display device according to a second embodiment of the present invention. Referring to FIG. 7, in the second embodiment, unlike the first embodiment in which the contact portion 10 is formed on the opposite side of the gate line 1, the contact portion 10 is formed in the vicinity of the gate line 1. The thin film transistor 4A of the display device 100 will be described.

  In the thin film transistor 4A of the display device 100 according to the second embodiment, the second portion 83 of the source electrode 8 is connected to the signal line 2 on the side opposite to the gate line 1 side of the gate electrode 1A. 8A is opposed to the gate line 1. The fourth portion 93 of the drain electrode 9 is disposed on the gate line 1 side of the gate electrode 1A, and the tip portion 9A of the drain electrode 9 is disposed on the side in which the gate electrode 1A extends. A contact portion 10 that electrically connects the pixel electrode 13 and the drain electrode 9 is formed in the vicinity of the gate line 1.

  In addition, the other structure of 2nd Embodiment is the same as that of the said 1st Embodiment.

  In the second embodiment, the aperture ratio of the pixel 3 can be increased by forming the contact portion 10 in the vicinity of the gate line 1 as described above. The remaining effects of the second embodiment are similar to those of the aforementioned first embodiment.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is shown not by the above description of the embodiments but by the scope of claims for patent, and further includes all modifications within the meaning and scope equivalent to the scope of claims for patent.

  For example, in the first and second embodiments, the source electrode and the drain electrode are formed so as to be bent at a right angle. However, the present invention is not limited to this, and the source electrode and the drain electrode are curved. You may form so that it may do.

  In the first and second embodiments, the example in which the first portion of the source electrode and the third portion of the drain electrode are formed in parallel to the direction in which the signal line extends is shown. However, the present invention is not limited to this. Alternatively, the first portion of the source electrode and the third portion of the drain electrode may be formed to extend obliquely with respect to the signal line.

  In the first and second embodiments, the gate electrode is formed to extend in the direction in which the signal line extends. However, the present invention is not limited to this, and the gate electrode extends in the direction in which the gate line extends. You may form so that it may extend.

1 is an overall configuration diagram of a display device according to a first embodiment of the present invention. 1 is a plan view of a thin film transistor of a display device according to a first embodiment of the present invention. 1 is a plan view of a thin film transistor of a display device according to a first embodiment of the present invention. FIG. 3 is a cross-sectional view taken along line 200-200 in FIG. 2. FIG. 6 is a view for explaining a positional shift between a source electrode and a drain electrode of a thin film transistor of the display device according to the first embodiment of the present invention. FIG. 6 is a view for explaining a positional shift between a source electrode and a drain electrode of a thin film transistor of the display device according to the first embodiment of the present invention. It is a top view of the thin-film transistor of the display apparatus by 2nd Embodiment of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Gate line 1A Gate electrode 7 Semiconductor layer 8 Source electrode 9 Drain electrode 10 Contact part 73 Channel region

Claims (7)

A gate line including a gate electrode;
A semiconductor layer formed to overlap the gate electrode in plan view;
A source electrode and a drain electrode, which are formed so as to overlap the gate electrode and the semiconductor layer in plan view and are electrically connected to the semiconductor layer, respectively;
The gate electrode is formed to protrude from the gate line in a plan view and extend in a predetermined direction,
The source electrode and the drain electrode are arranged in parallel with each other when seen in a plan view, and are formed to bend or bend while turning, on a region where the gate electrode and the semiconductor layer overlap when seen in a plan view, Display device.   2. The display device according to claim 1, wherein the source electrode and the drain electrode have a substantially L shape in a plan view and are disposed so that inner portions of the substantially L shape face each other. .   The channel region formed between the source electrode and the drain electrode is formed between the source electrode and the drain electrode formed to bend or bend while turning relative to each other. 2. The display device according to 2.   The display device according to claim 3, wherein a channel length of the channel region formed by bending or curving while turning is formed while maintaining a uniform interval.   The length in the short direction of the source electrode and the drain electrode is 1/3 or less of the length in the short direction of a region where the gate electrode and the semiconductor layer overlap when viewed in plan. The display apparatus of any one of -4. The drain electrode includes a contact portion connected to the pixel electrode,
The display device according to claim 1, wherein the contact portion is disposed in the vicinity of the gate line.   The said source electrode and the said drain electrode are arrange | positioned inside the outer edge part along the longitudinal direction of the said gate electrode of the area | region where the said gate electrode and the said semiconductor layer overlap, The any one of Claims 1-6 The display device according to item.

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