JP2010010583A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device that reduces a leakage current Idss of SBD while improving forward voltage Vf characteristics by incorporating the SBD in a power transistor, and a method of manufacturing the same. <P>SOLUTION: In the semiconductor device 1, a power transistor cell T1 has a first trench 41 formed by connecting a first first-stage trench 411 and a first second-stage trench 412 to each other, and also has a second semiconductor region (a body region) 51 with a uniform width in a first semiconductor region (a drift layer) 3 along an internal wall of the first first-stage trench 411. A power transistor T2 adjoining the power transistor cell T1 has a second trench 42 formed by connecting a second first-stage trench 421 and a second second-stage trench 422 to each other, and also has a third semiconductor region (body region) 52 with a uniform width in the first semiconductor region (drift layer) 3 along an internal wall of the second first-stage trench 421. <P>COPYRIGHT: (C)2010,JPO&amp;INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device in which a power transistor and a Schottky barrier diode (SBD) are incorporated in one chip and a manufacturing method thereof.

  A semiconductor device (semiconductor chip) incorporating a power transistor is required to have a low on-resistance in response to a demand for a large current. Furthermore, there is a demand for the development of a power transistor that can handle a large current in the forward direction.

Patent Document 1 below discloses a semiconductor device in which a Schottky barrier diode (SBD) is built in a power MOSFET and forward voltage Vf characteristics are improved. In the disclosed semiconductor device, a drift layer is exposed between base regions of a plurality of power MOSFET cells, and the drift layer and a source electrode (or emitter electrode) are in Schottky contact. That is, when the power MOSFET is turned off, the depletion layer generated on the drift layer side from the pn junction between the base region and the drift layer overlaps between adjacent power MOSFET cells, and a high voltage is not applied to the SBD due to the electric field relaxation effect Therefore, the forward voltage Vf can be lowered.
JP 2003-17701 A

  However, in the semiconductor device disclosed in Patent Document 1 described above, the following points have not been considered. Since the base region of the power MOSFET is formed by diffusion of impurities from the surface of the drift layer, the cross-sectional shape of the base region, particularly the side surface shape for generating SBD, is formed by an arc shape in which impurities are isotropically diffused. . For this reason, the depletion layers generated in the drift layer from the respective base regions of the adjacent power MOSFET cells overlap only on the surface side of the drift layer, and do not overlap on the bulk side of the drift layer. In such a depletion layer overlapping state, the leakage current Idss in the SBD increases when the power MOSFET is turned off.

  The present invention has been made to solve the above problems. Accordingly, an object of the present invention is to provide a semiconductor device capable of improving the leakage voltage Idss in the SBD while improving the forward voltage Vf characteristics by incorporating the SBD in the power transistor, and a manufacturing method thereof.

  In order to solve the above-described problem, a first feature according to an embodiment of the present invention is that, in a semiconductor device, the first conductivity type first semiconductor region and the main surface of the first semiconductor region A first first-stage trench extending inside the first semiconductor region and a first second-stage trench connected to the first first-stage trench and further extending inside the first semiconductor region. And a second first-stage trench disposed adjacent to the first trench and extending from one main surface of the first semiconductor region into the first semiconductor region, and the second first-stage trench. And a second trench having a second second-stage trench extending into the first semiconductor region, and between the first trench and the second trench inside the first semiconductor region. And a first first-stage tray of the first trench. A second semiconductor region of a second conductivity type opposite to the first conductivity type having a uniform width along the inner wall of the first and second trenches; a first trench and a second trench inside the first semiconductor region; A third semiconductor region of a second conductivity type disposed adjacent to and spaced apart from the second semiconductor region and having a uniform width along the inner wall of the second first-stage trench of the second trench. The fourth semiconductor region of the first conductivity type disposed in the second semiconductor region on the one main surface side of the first semiconductor region, and the third semiconductor on the one main surface side of the first semiconductor region A fifth semiconductor region of the first conductivity type disposed in the region, a first gate insulating film disposed along the second semiconductor region on the inner wall of the first trench, and a second trench A second gate insulating film disposed along the third semiconductor region on the inner wall of the first trench, and a first trench A first gate electrode disposed in the portion via a first gate insulating film, a second gate electrode disposed in the second trench via a second gate insulating film, The first semiconductor is electrically connected to the second semiconductor region, the third semiconductor region, the fourth semiconductor region, and the fifth semiconductor region, and between the second semiconductor region and the third semiconductor region. And an electrode that is Schottky connected to the region.

  Furthermore, in the semiconductor device according to the first feature, the second semiconductor region is connected to the first second-stage trench from one end of the first semiconductor region of the first first-stage trench on the one main surface side. The third semiconductor region has a uniform width to the other end, and the third semiconductor region extends from one end on the one main surface side of the first semiconductor region of the second first-stage trench to the other end connected to the second second-stage trench. It is preferable to have a uniform width.

  Furthermore, in the semiconductor device according to the first feature, the second semiconductor region has a uniform diffusion amount from the inner wall to the inside of the first semiconductor region, starting from the inner wall of the first first-stage trench. The semiconductor region preferably has a uniform diffusion amount from the inner wall of the second first-stage trench to the inside of the first semiconductor region.

  Furthermore, in the semiconductor device according to the first feature, the length in the depth direction from the one main surface of the first semiconductor region having the uniform width of the second semiconductor region or the third semiconductor region is the second semiconductor region. Alternatively, the depth of the third semiconductor region is preferably set to 0.7 times or more of the depth from one main surface of the first semiconductor region.

  Furthermore, in the semiconductor device according to the first feature, the impurity density on the inner side relative to the impurity density on the one main surface side of the first semiconductor region is between the second semiconductor region and the third semiconductor region. It is preferable that the impurity density is set high.

  A second feature of the embodiment of the present invention is that, in the method of manufacturing a semiconductor device, the step of forming the first semiconductor region of the first conductivity type and the first surface of the first semiconductor region Forming a first first-stage trench extending inside one semiconductor region, and extending from one main surface of the first semiconductor region adjacent to the first first-stage trench into the first semiconductor region; Forming a second first-stage trench, introducing an impurity of a second conductivity type opposite to the first conductivity type into the first semiconductor region from the inner wall of the first first-stage trench, A second semiconductor region having a uniform width is formed from the inner wall of the first first-stage trench, an impurity of the second conductivity type is introduced into the first semiconductor region from the inner wall of the second first-stage trench, Forming a third semiconductor region having a uniform width from the inner wall of the first-stage trench Forming a first second-stage trench connected to the first first-stage trench and extending into the first semiconductor region, and forming the first first-stage trench and the first second-stage trench. Forming a first trench having a second trench that is connected to the second first-stage trench and extends into the first semiconductor region; and the second first-stage trench and the second trench Forming a second trench having a second-stage trench, forming a first semiconductor region of the first conductivity type in the second semiconductor region on one main surface side of the first semiconductor region, Forming a fifth semiconductor region of the first conductivity type in the third semiconductor region on one main surface side of the first semiconductor region, and a first semiconductor region along the second semiconductor region on the inner wall of the first trench Forming a gate insulating film on the inner wall of the second trench Forming a second gate insulating film along the third semiconductor region, forming a first gate electrode in the first trench through the first gate insulating film, and forming an inner portion of the second trench. And forming a second gate electrode through the second gate insulating film and electrically connecting to the second semiconductor region, the third semiconductor region, the fourth semiconductor region, and the fifth semiconductor region. And forming a Schottky-connected electrode in the first semiconductor region between the second semiconductor region and the third semiconductor region.

  According to the present invention, it is possible to provide a semiconductor device capable of improving the leakage voltage Idss in the SBD while improving the forward voltage Vf characteristics by incorporating the SBD in the power transistor, and a manufacturing method thereof.

  Next, embodiments of the present invention will be described with reference to the drawings. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. However, the drawings are schematic and different from actual ones. In addition, there may be a case where the dimensional relationships and ratios are different between the drawings.

  Further, the following embodiments exemplify apparatuses and methods for embodying the technical idea of the present invention, and the technical idea of the present invention is to arrange the components and the like as follows. Not specific. The technical idea of the present invention can be variously modified within the scope of the claims.

(First embodiment)
In the first embodiment of the present invention, an example in which the present invention is applied to a power semiconductor device mounted with a vertical power transistor having a trench structure and a manufacturing method thereof will be described.

[Structure of semiconductor device]
As shown in FIG. 1, the semiconductor device 1 according to the first embodiment includes a first conductivity type first semiconductor region 3 and a first main surface 3 </ b> A of the first semiconductor region 3. A first first-stage trench 411 extending into the semiconductor region 3 and a first second-stage trench 412 connected to the first first-stage trench 411 and further extending into the first semiconductor region 3 are provided. A first trench 41 and a second first-stage trench 421 that is disposed adjacent to the first trench 41 and extends from one main surface 3A of the first semiconductor region 3 to the inside of the first semiconductor region 3. And a second trench 42 having a second second-stage trench 422 connected to the second first-stage trench 421 and extending into the first semiconductor region 3, and the inside of the first semiconductor region 3. First trench 41 and second trench 4 And a second semiconductor region of the second conductivity type opposite to the first conductivity type having a uniform width along the inner wall of the first first-stage trench 411 of the first trench 41 51 and a first trench 41 and a second trench 42 inside the first semiconductor region 3 are arranged adjacent to and separated from the second semiconductor region 51, and the second trench 42 The second conductive type third semiconductor region 52 having a uniform width along the inner wall of the first stage trench 421, and the second semiconductor region 51 on the one main surface 3A side of the first semiconductor region 3 A fourth semiconductor region 61 of the first conductivity type provided, and a fifth fifth of the first conductivity type disposed in the third semiconductor region 52 on the one main surface 3A side of the first semiconductor region 3. The semiconductor region 62 and the inner wall of the first trench 41 are arranged along the second semiconductor region 51. The first gate insulating film 71 formed, the second gate insulating film 72 disposed along the third semiconductor region 52 on the inner wall of the second trench 42, and the first trench 41 inside the first trench 41. A first gate electrode 81 disposed via one gate insulating film 71, a second gate electrode 82 disposed within the second trench 42 via a second gate insulating film 72, and The second semiconductor region 51, the third semiconductor region 52, the fourth semiconductor region 61, and the fifth semiconductor region 62 are electrically connected to the second semiconductor region 51 and the third semiconductor region 52. And an electrode 9 that is Schottky connected to the first semiconductor region 3.

  Here, in the first embodiment, the first conductivity type is n-type, and the second conductivity type is p-type. However, in the present invention, these conductivity types may be reversed.

The first semiconductor region 3 mainly functions as a drift layer (drain region or collector region) of the power transistor T. The first semiconductor region 3 is disposed on the main surface 2A of the substrate 2 having the same first conductivity type as that of the first semiconductor region 3 and having an impurity density higher than that of the first semiconductor region 3. . Here, an n-type silicon single crystal substrate is used as the substrate 2, and this silicon single crystal substrate is set to an impurity density of, for example, 10 ¹⁸ atoms / cm ³ -10 ¹⁹ atoms / cm ³ . The first semiconductor region 3 is, for example, an epitaxial layer grown on the main surface 2A of the substrate 2. This epitaxial layer is set to an impurity density of, for example, 10 ¹⁴ atoms / cm ³ -10 ¹⁶ atoms / cm ³ . The thickness (film thickness) of this epitaxial layer is set to, for example, 5 μm-80 μm.

  The first trench 41 constructs a vertical structure of the power transistor cell T1. The first first-stage trench 411 of the first trench 41 is disposed from the one main surface 3A of the first semiconductor region 3 in the depth direction (to the main surface 2A of the substrate 2), and is substantially uniform. Has a wide groove width. The first second-stage trench 412 is connected to the first first-stage trench 411 and has a substantially uniform groove width in the depth direction. Both the first first-stage trench 411 and the first second-stage trench 412 are formed by anisotropic etching such as reactive ion etching (RIE) method in the manufacturing process, and the groove depth is set to the groove width. It is large (the aspect ratio is large). Here, the groove width of the first first-stage trench 411 is set to be equal to the groove width of the first second-stage trench 412, but in the present invention, the groove width of the first first-stage trench 411 is The groove width of the first second-stage trench 412 may be set larger.

  The first first-stage trench 411 makes the width dimension of the second semiconductor region 51 from the inner wall of the first first-stage trench 411 uniform, and the side surface of the second semiconductor region 51 is made to be the same as that of the first semiconductor region 3. It has a function of generating a flat shape from one main surface 3A in the depth direction. In the first embodiment, the first first-stage trench 411 has a groove width set to 0.4 μm to 0.6 μm, for example, and a groove depth set to 1.0 μm to 1.4 μm, for example. The first second-stage trench 412 has a groove width substantially the same as the groove width of the first first-stage trench 411 and a groove depth set to, for example, 0.6 μm to 1.0 μm.

  The second trench 42 constructs a vertical structure of another power transistor cell T2 arranged adjacent to the power transistor cell T1. The second first-stage trench 421 of the second trench 42 has the same structure and the same groove width and groove depth as the first first-stage trench 411 of the first trench 41, and the second second-stage trench 422. Is configured with the same structure as the first second-stage trench 412 and the same groove width and depth.

  The second semiconductor region 51 functions as a p-type body region (p-type base region) of the power transistor cell T1. In the second semiconductor region 51, a second conductivity type impurity (here, p-type impurity) is introduced into the first semiconductor region 3 on the inner wall of the first first-stage trench 411 of the first trench 41. Therefore, the inner wall of the first first-stage trench 411 is configured to have an isotropic diffusion amount (diffusion distance), particularly an equal lateral diffusion amount, starting from the diffusion of impurities. That is, the flat dimension of the side surface of the second semiconductor region 51 is maintained in the dimension equivalent to the groove depth of the first first-stage trench 411. In other words, the other end of the first first-stage trench 411 connected to the first second-stage trench 412 of the first first-stage trench 411 from one end of the first semiconductor region 3 on the main surface 3A side. Until then, the flat shape of the side surface of the second semiconductor region 51 is maintained (formed with a uniform groove width).

  Similarly, the third semiconductor region 52 functions as a p-type body region (p-type base region) of the power transistor cell T2. In the third semiconductor region 52, the second conductivity type impurity is introduced into the first semiconductor region 3 on the inner wall of the second first-stage trench 421 of the second trench 42, so that the second first-stage trench The inner wall of 421 is configured to have isotropic diffusion amount (diffusion distance), particularly equal lateral diffusion amount, starting from the diffusion of impurities. That is, the flat dimension of the side surface of the third semiconductor region 52 is maintained in a dimension equivalent to the groove depth of the second first-stage trench 421. In other words, the other end of the second first-stage trench 421 connected to the second second-stage trench 422 of the second first-stage trench 421 from one end of the first semiconductor region 3 on the first main surface 3A side. Until then, the flat shape of the side surface of the third semiconductor region 52 is maintained (formed with a uniform groove width).

The second semiconductor region 51 is set to an impurity density of, for example, 10 ¹⁷ atoms / cm ³ -10 ¹⁸ atoms / cm ³ . Although it varies depending on the conditions such as the impurity density of the first semiconductor region 3 and is not necessarily limited to these values, the width of the second semiconductor region 51 is set to 0.4 μm−0.6 μm, for example. The depth (pn junction depth xj) of the second semiconductor region 51 from the first main surface 3A of the first semiconductor region 3 is deeper than the groove depth of the first first-stage trench 411, and the first second-stage trench. For example, the depth is set to 1.2 μm to 1.6 μm, which is shallower than the groove depth of 412. The impurity density, width and depth of the third semiconductor region 52 are the same as the impurity density, width and depth of the second semiconductor region 51. The separation distance between the side surface of the second semiconductor region 51 and the side surface of the third semiconductor region 52 adjacent to the second semiconductor region 51 is set to 0.2 μm−0.4 μm, for example. 3 from the first principal surface 3A to the groove depths of the first first-stage trench 411 and the second first-stage trench 421.

The fourth semiconductor region 61 functions as an n-type source region (n-type emitter region) of the power transistor cell T1. As shown in FIG. 2, the fourth semiconductor region 61 is set to an impurity density of, for example, 10 ¹⁹ atoms / cm ³ -10 ²⁰ atoms / cm ³ , and the pn junction depth is set to, for example, 0.2 μm-0.4 μm. The The fifth semiconductor region 62 functions as an n-type source region (n-type emitter region) of the power transistor cell T2. The impurity density and pn junction depth of the fifth semiconductor region 62 are the same as the impurity density and pn junction depth of the fourth semiconductor region 61.

  The first gate insulating film 71 is disposed along the inner wall of the first trench 41, specifically, the inner wall of the first first-stage trench 411, the inner wall and the bottom surface of the first second-stage trench 412. Yes. The first gate insulating film 71 functions as a gate insulating film of the power transistor cell T1, and a silicon oxide film, for example, is used for the first gate insulating film 71. Similarly, the second gate insulating film 72 is arranged along the inner wall of the second trench 42, specifically, the inner wall of the second first-stage trench 421, the inner wall and the bottom surface of the second second-stage trench 422. It is installed. The second gate insulating film 72 functions as a gate insulating film of the power transistor cell T2, and for example, a silicon oxide film is similarly used for the second gate insulating film 72.

  The first gate electrode 81 is used as the gate electrode of the power transistor cell T1, and the second gate electrode 82 is used as the gate electrode of the power transistor cell T2. For each of the first gate electrode 81 and the second gate electrode 82, for example, a silicon polycrystalline film doped with an impurity that decreases the resistance value is used.

  In the first embodiment, the power transistor cell T1 includes the first semiconductor region 3, the first trench 41, the second semiconductor region 51, the fourth semiconductor region 61, and the first gate insulating film 71 described above. This is a vertical insulated gate field effect transistor (IGFET) having a first gate electrode 81 and having a trench structure. Here, the IGFET is used to mean both a MOSFET having the first gate insulating film 71 as an oxide film and a MISFET having the first gate insulating film 71 as an insulating film. Similarly, the power transistor cell T2 includes the first semiconductor region 3, the second trench 42, the third semiconductor region 52, the fifth semiconductor region 62, the second gate insulating film 72, and the second gate. This is a vertical IGFET having an electrode 82 and having a trench structure.

  Although only two power transistor cells T1 and T2 are shown in FIG. 1, the power transistor cell T1 is actually arranged on the left side of the power transistor cell T1 in FIG. 1 and on the right side of the power transistor cell T2 in FIG. A plurality of power transistor cells Tn having a relationship with T2 are arranged. These power transistor cells Tn are electrically connected in parallel to form the power transistor T.

In the first embodiment, for example, silicon that prevents alloy spikes or copper that prevents electromigration is added to the electrode 9 and an aluminum alloy film is used. The electrode 9 is connected to the second semiconductor region 51 and the third semiconductor region 52 and functions as a source electrode (or emitter electrode), and between the second semiconductor region 51 and the third semiconductor region 52. A Schottky connection is made to one main surface 3A of the first semiconductor region 3 (no Schottky contact is made) to construct a Schottky barrier diode D. The Schottky barrier diode D uses the electrode 9 as an anode electrode and the first semiconductor region 3 as a cathode electrode. Note that the surface concentration (impurity density) of one main surface 3A of the first semiconductor region 3 that forms a Schottky connection with the electrode 9 is, for example, 10 ¹⁶ atoms / cm ³ or less, and the specific resistance value is, for example, 0.5 Ω · cm or more. Set to

  A passivation film 10 is disposed on the electrode 10. For example, a silicon nitride film or a polyimide resin film can be used practically for the passivation film 10.

[Electrical characteristics of semiconductor devices]
In the semiconductor device 1 according to the first embodiment described above, the leakage current Idss characteristic can be improved while improving the forward voltage (forward breakdown voltage or source-drain breakdown voltage) Vf characteristic as follows. it can.

  FIG. 3 shows a cross-sectional structure that models the semiconductor device 1 according to the first embodiment. On the other hand, FIG. 4 shows a cross-sectional structure that is a comparative example 1 and models a semiconductor device in which no Schottky barrier diode is provided between adjacent power transistor cells T1 and T2. FIG. 5 shows a semiconductor device in which a p-type body region is formed by diffusion from the surface of the drift layer, although a Schottky barrier diode is disposed between adjacent power transistor cells T1 and T2, which is a comparative example 2. The modeled cross-sectional structure is shown.

  FIG. 6 is a graph showing the relationship between the forward voltage Vf and the forward current I. As shown in FIG. 6, since the semiconductor device 1 according to the first embodiment shown in FIG. 3 includes the Schottky barrier diode D in comparison with the comparative example 1 shown in FIG. Vf can be lowered. Specifically, in the normal range 20A-30A, the forward voltage Vf of the semiconductor device 1 according to the first embodiment can be lowered by about 1.0V-0.4V with respect to the comparative example 1.

  FIG. 7 is a graph showing the relationship between the reverse bias voltage (source-drain breakdown voltage) BVdss and the leakage current Idss. In the semiconductor device 1 according to the first embodiment shown in FIG. 3, the side surfaces of the second semiconductor region (p-type body region) 51 of the power transistor cell T1 and the third semiconductor region of the adjacent power transistor cell T2 are used. The side surface of the (p-type body region) 52 is flattened, and the flat shape is maintained in the depth direction from one main surface 3A of the first semiconductor region (n-type drift layer) 3. As a result, when the power transistor cells T1 and T2 are off, the depletion layer 31 extending from the pn junction interface between the side surface of the second semiconductor region 51 and the first semiconductor region 3 to the first semiconductor region 3 side, The overlap between the side surface of the semiconductor region 52 and the depletion layer 32 extending from the pn junction interface between the first semiconductor region 3 toward the first semiconductor region 3 is deeper than the main surface 3A of the first semiconductor region 3. Increase in the direction. The region where the depletion layers 31 and 32 overlap corresponds to the region of the Schottky barrier diode D, and the leakage current path is blocked by the depletion layers 31 and 32.

  As shown in FIG. 7, the leakage current Idss can be reduced in the semiconductor device 1 according to the first embodiment compared to the comparative example 2 shown in FIG. 5. Furthermore, in the semiconductor device 1 according to the first embodiment, the junction depth xj is 0.5 μm from one main surface 3A of the first semiconductor region 3 of the second semiconductor region 51 and the third semiconductor region 52. , 0.7 μm, 0.8 μm, and 0.9 μm sequentially increase, and the leakage current Idss can be further reduced as the cross-sectional shapes of the second semiconductor region 51 and the third semiconductor region 52 approach a rectangle.

  Although it depends on the circuit configuration used, it is generally desirable to reduce the leakage current Idss as much as possible in order to reduce standby power and suppress power consumption. For example, the leakage current Idss is required to be set within one digit μA as the main switching element in the switching power supply circuit of the AC-DC converter. In the semiconductor device 1 according to the first embodiment, as shown in FIG. As such, this request can be cleared. When used in the same application, the semiconductor device 1 according to the first embodiment can reduce power consumption by 20 to 30 times compared to the comparative example 2.

  Here, in order to set the leakage current Idss within one digit μA, as shown in FIG. 3, one of the first semiconductor regions 3 having the uniform width W of the second semiconductor region 51 or the third semiconductor region 52 is provided. The length Lf in the depth direction from the main surface 3A is set to the junction depth La (= xj) of the first semiconductor region 3 of the second semiconductor region 51 or the third semiconductor region 52 from the main surface 3A. It is preferable to set it to 0.7 times or more.

[Method for Manufacturing Semiconductor Device]
A method for manufacturing the semiconductor device 1 according to the first embodiment described above is as follows.

  First, the first semiconductor region 3 having the first conductivity type set to a lower impurity density is formed on the main surface 2A of the substrate 2 having the first conductivity type (see FIG. 8). .) Here, the stage of the manufacturing process is a pretreatment process, and the substrate 2 is in a wafer state before the dicing process.

  Next, a mask 11 is formed on one main surface 3A of the first semiconductor region 3 (see FIG. 8). The mask 11 has openings in the formation region of the first trench 41 and the formation region of the second trench 42. For example, a silicon oxide film can be used for the mask 11.

  Using mask 11 as an etching mask, first semiconductor region 3 exposed from the opening of mask 11 is removed by etching from one main surface 3A toward the depth direction (see FIG. 8). As a result, the first first-stage trench 411 is formed in the formation region of the first trench 41, and the second first-stage trench 421 is formed in the formation region of the second trench 42 in the same process. For the etching, anisotropic etching such as RIE is used.

  As shown in FIG. 8, using the mask 11 as an ion implantation mask, the inner wall (and bottom surface) of the first first-stage trench 411 and the inner wall (and bottom surface) of the second first-stage trench 421 exposed from the opening of the mask 11. The second conductivity type impurity 53 is introduced into the surface layer of the first semiconductor region 3 along). The second conductivity type impurities 53 are introduced (implanted) using the ion implantation method in the first embodiment. In order to introduce the second conductivity type impurities 53 into the surface layer of the first semiconductor region 3 along the inner wall of the first first-stage trench 411 and the inner wall of the second first-stage trench 421, a wafer is placed. An oblique ion implantation method having an inclination angle in the ion implantation direction with respect to the axial direction of the table rotation axis is used. Although not particularly designated, a thin buffer film made of, for example, a silicon oxide film is formed prior to the introduction of impurities in order to alleviate damage to the surface layer of the first semiconductor region 3 due to the introduction of impurities. It is formed. Hereinafter, description of the buffer film is omitted.

  As shown in FIG. 9, the mask 11 is again used as an etching mask, and the first semiconductor region 3 is formed on the bottom surface of the first first-stage trench 411 and the bottom surface of the second first-stage trench 421 exposed from the opening of the mask 11. Is further removed by etching in the depth direction. As a result, a first second-stage trench 412 connected to the first first-stage trench 411 is formed in the formation region of the first trench 41, and the first first-stage trench 411 and the first second-stage trench 411 are formed. A first trench 41 having a trench 412 is formed. By the same process, a second second-stage trench 422 connected to the second first-stage trench 421 is formed in the formation region of the second trench 42, and the second first-stage trench 421 and the second second-stage trench 421 are formed. A second trench 42 having an eye trench 422 is formed. For the etching, anisotropic etching such as RIE is used.

  As shown in FIG. 10, the surface layer of the first semiconductor region 3 along the inner wall of the first first-stage trench 411 of the first trench 41 and the inner wall of the second first-stage trench 421 of the second trench 42. An activation process (drive-in diffusion process) is performed on the second conductivity type impurities 53 introduced in step (b). As a result, the second semiconductor region 51 having a uniform width is formed from the inner wall along the inner wall of the first first-stage trench 411, and the inner wall of the second first-stage trench 421 is uniformly formed from the inner wall. A third semiconductor region 52 having a width is formed. As described above, since the second conductivity type impurity 53 is diffused isotropically starting from the inner wall of the first first-stage trench 411, the side surface of the second semiconductor region 51 is the first semiconductor region 3. The first main surface 3A is formed to have a flat shape in the depth direction. Similarly, since the second conductivity type impurity 53 is diffused isotropically starting from the inner wall of the second first-stage trench 421, the side surface of the third semiconductor region 52 is the same as that of the first semiconductor region 3. The main surface 3A is formed with a flat shape in the depth direction.

  After the mask 11 is removed, the surface of the second semiconductor region 51 and the first surface along the inner wall and the bottom surface of the first second-stage trench 412 and the first wall of the first-stage trench 412 of the first trench 41 and the first The surface of the semiconductor region 3 is exposed and the surface of the third semiconductor region 52 along the inner wall of the second first-stage trench 421 of the second trench 42, the inner wall and the bottom surface of the second second-stage trench 422. Then, the surface of the first semiconductor region 3 is exposed (see FIG. 11).

  Subsequently, a first gate insulating film 71 is formed on the exposed surface of the second semiconductor region 51 and the surface of the first semiconductor region 3 in the first trench 41, and the second trench 42 is formed. A second gate insulating film 72 is formed on the exposed surface of the third semiconductor region 52 and on the surface of the first semiconductor region 3 (see FIG. 11).

  As shown in FIG. 11, a first gate electrode 81 is formed inside the first trench 41 via a first gate insulating film 71, and a second gate electrode is inside the second trench 42. A second gate electrode 82 is formed via 72. For the first gate electrode 81 and the second gate electrode 82, for example, a silicon polycrystalline film formed by using the CVD method is used. This silicon polycrystalline film is left in each of the first trench 41 and the second trench 42 by removing an excess portion using an etching back method after the film formation. The silicon polycrystalline film left inside the first trench 41 functions as the first gate electrode 81, and the silicon polycrystalline film left inside the second trench 42 functions as the second gate electrode. . Note that in order to form the fourth semiconductor region 61 and the fifth semiconductor region 62, the first gate electrode 81 is formed with a film thickness that does not reach the opening of the first trench 41, and the second gate electrode 82. Is formed with a film thickness less than the opening of the second trench 42.

  Next, a mask 12 is formed on one main surface 3A of the first semiconductor region 3 (see FIG. 12). The mask 12 has openings in the region of the first trench 41 and the region of the second trench 42. For the mask 12, for example, a resist film formed by using a photolithography technique can be used.

  As shown in FIG. 12, using the mask 12 as an ion implantation mask, the surface layer of the second semiconductor region 51 and the second first step along the inner wall of the first first-step trench 411 exposed from the opening of the mask 12. A first conductivity type impurity 63 is introduced into the surface layer of the second semiconductor region 52 along the inner wall of the eye trench 421. The first conductivity type impurity 63 is introduced using the oblique ion implantation method in the first embodiment. The first conductivity type impurity 63 is also introduced into the first gate electrode 81 and the second gate electrode 82. Thereafter, the mask 12 is removed, and an activation process is subsequently performed to form the fourth semiconductor region 61 and the fifth semiconductor region 62 from the first conductivity type impurities 63 (see FIG. 13).

  When the fourth semiconductor region 61 is formed, the power transistor cell T1 is completed, and when the fifth semiconductor region 62 is formed, the power transistor cell T2 is completed. That is, the power transistor T is substantially completed.

  Next, although no particular reference is made, the first semiconductor region 3 on one main surface 3A, the second semiconductor region 51, the third semiconductor region 52, the fourth semiconductor region 61, the fifth An interlayer insulating film is formed on the semiconductor region 62, on the first gate electrode 81 in the first trench 41, and on the second gate electrode 82 in the second trench 42 (see FIG. 13). . An opening (contact hole) is formed in the interlayer insulating film in each of the partial regions on the second semiconductor region 51, the third semiconductor region 52, the fourth semiconductor region 61, and the fifth semiconductor region 62. Is formed. In the same process, an opening is also formed on one main surface 3A of the first semiconductor region 3 between the second semiconductor region 51 and the third semiconductor region 52 adjacent thereto.

  As shown in FIG. 13, the second semiconductor region 51, the third semiconductor region 52, the fourth semiconductor region 61, and the fifth semiconductor region 62 are electrically connected to each other through the opening on the interlayer insulating film. At the same time, the Schottky-connected electrode 9 is formed on one main surface 3A of the first semiconductor region 3 between the second semiconductor region 51 and the third semiconductor region 52 adjacent thereto. For the electrode 9, for example, an aluminum alloy film formed using a sputtering method can be used. When the electrode 9 is formed, a Schottky barrier diode D having the first semiconductor region 3 as an anode region and the electrode 9 as a cathode region is completed.

  Thereafter, a passivation film 10 is formed on the electrode 9 as shown in FIG. When these series of manufacturing steps are completed, the semiconductor device 1 according to the first embodiment can be manufactured.

  In the semiconductor device 1 according to the first embodiment configured as described above, the Schottky barrier diode D can be improved by incorporating the Schottky barrier diode D in the power transistor T, and the Schottky barrier diode D can be improved. The leakage current Idss can be improved.

  Furthermore, in the method of manufacturing the semiconductor device 1 according to the first embodiment, after the first first-stage trench 411 of the first trench 41 is formed, the first along the inner wall of the first first-stage trench 411 is formed. The second conductivity type impurity 53 is introduced into the first semiconductor region 3, the second semiconductor region 2 is formed by utilizing the lateral diffusion of the second conductivity type impurity 53, and the second trench 42 After the second first-stage trench 421 is formed, a second conductivity type impurity 53 is introduced into the first semiconductor region 3 along the inner wall of the first first-stage trench 411. Since the second semiconductor region 2 is formed by utilizing the lateral diffusion, the side surface of the second semiconductor region 51 and the side surface of the third semiconductor region 52 are deeply formed from one main surface 3A of the first semiconductor region 3. By making it flat toward the direction That.

(Second Embodiment)
The second embodiment of the present invention describes an example in which the characteristics of the Schottky barrier diode D are changed in the semiconductor device 1 according to the first embodiment described above.

  As shown in FIG. 14, the semiconductor device 1 according to the second embodiment is provided between the second semiconductor region 51 of the power transistor cell T1 and the third semiconductor region 52 of the power transistor cell T2 adjacent thereto. In the region on the cathode electrode side of the Schottky barrier diode D, the impurity density on the inner side is set higher than the impurity density on the one main surface 3A side of the first semiconductor region 3. That is, the sixth semiconductor region 35 having a first conductivity type and a higher impurity density than that of the first semiconductor region 3 in a region slightly deeper than the one main surface 3A of the first semiconductor region 3. Is arranged.

  In the semiconductor device 1 according to the second embodiment configured as described above, since the resistance value of the current path on the cathode electrode side of the Schottky barrier diode D can be reduced, the forward voltage Vf characteristic is further increased. Can be improved.

(Other embodiments)
As described above, the present invention has been described according to the first embodiment and the second embodiment. However, the description and the drawings constituting a part of this disclosure do not limit the present invention. The present invention can be applied to various alternative embodiments, examples, and operational technologies. For example, the present invention can be applied to a power semiconductor device equipped with an insulated gate bipolar transistor (IGBT) having a trench structure and a method for manufacturing the same.

1 is a cross-sectional view of main parts of a semiconductor device according to a first embodiment of the present invention. FIG. 2 is a schematic cross-sectional view modeling the semiconductor device shown in FIG. 1. It is the schematic sectional drawing which modeled the semiconductor device of the comparative example 1 which concerns on 1st Embodiment. It is the schematic sectional drawing which modeled the semiconductor device of the comparative example 2 which concerns on 1st Embodiment. 3 is a graph showing a relationship between a forward voltage and a forward current of the semiconductor device according to the first embodiment. 4 is a graph showing a relationship between a reverse bias voltage and a leakage current of the semiconductor device according to the first embodiment. FIG. 6 is a first process cross-sectional view illustrating the method for manufacturing the semiconductor device according to the first embodiment. It is 2nd process sectional drawing. It is 3rd process sectional drawing. It is a 4th process sectional view. FIG. 10 is a fifth process cross-sectional view. It is 6th process sectional drawing. It is principal part sectional drawing of the semiconductor device which concerns on the 2nd Embodiment of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Semiconductor device 2 ... Substrate 3 ... 1st semiconductor region 3A ... One main surface 31, 32 ... Depletion layer 35 ... 6th semiconductor region 41 ... 1st trench 411 ... 1st 1st step trench 412 ... 1st Second stage trench 42 ... Second trench 421 ... Second first stage trench 422 ... Second second stage trench 51 ... Second semiconductor region 52 ... Third semiconductor region 61 ... Fourth semiconductor region 62 ... 5th semiconductor region 71 ... 1st gate insulating film 72 ... 2nd gate insulating film 81 ... 1st gate electrode 82 ... 2nd gate electrode 9 ... Electrode T ... Power transistor T1, T2 ... Power transistor cell D ... Schottky barrier diode

Claims (6)

A first semiconductor region of a first conductivity type;
A first first-stage trench extending from one main surface of the first semiconductor region to the inside of the first semiconductor region, and connected to the first first-stage trench and further extended to the inside of the first semiconductor region. A first trench having a first second-stage trench that
A second first-stage trench disposed adjacent to the first trench and extending from one main surface of the first semiconductor region into the first semiconductor region; and the second first-stage trench. A second trench having a second second-stage trench connected and further extending into the first semiconductor region;
The first semiconductor region is disposed between the first trench and the second trench, and has a uniform width along an inner wall of the first first-stage trench of the first trench. A second semiconductor region of a second conductivity type opposite to the first conductivity type;
The second stage of the second trench is disposed between and adjacent to the second semiconductor region between the first trench and the second trench inside the first semiconductor region. A third semiconductor region of the second conductivity type having a uniform width along the inner wall of the eye trench;
A fourth semiconductor region of the first conductivity type disposed in the second semiconductor region on one main surface side of the first semiconductor region;
A fifth semiconductor region of the first conductivity type disposed in the third semiconductor region on one main surface side of the first semiconductor region;
A first gate insulating film disposed along the second semiconductor region on the inner wall of the first trench;
A second gate insulating film disposed along the third semiconductor region on the inner wall of the second trench;
A first gate electrode disposed inside the first trench via the first gate insulating film;
A second gate electrode disposed inside the second trench via the second gate insulating film;
The second semiconductor region, the third semiconductor region, the fourth semiconductor region, and the fifth semiconductor region are electrically connected to each other, and the second semiconductor region and the third semiconductor region An electrode that is Schottky connected to the first semiconductor region in between,
A semiconductor device comprising:   The second semiconductor region has a uniform width from one end on the one main surface side of the first semiconductor region of the first first-stage trench to the other end connected to the first second-stage trench. The third semiconductor region has a uniform width from one end on the one main surface side of the first semiconductor region of the second first-stage trench to the other end connected to the second second-stage trench. The semiconductor device according to claim 1.   The second semiconductor region has a uniform diffusion amount from the inner wall of the first first-stage trench to the inside of the first semiconductor region, and the third semiconductor region includes the second semiconductor region. 3. The semiconductor device according to claim 1, wherein the semiconductor device has a uniform diffusion amount from the inner wall to the inside of the first semiconductor region starting from the inner wall of the first stage trench.   The length in the depth direction from one main surface of the first semiconductor region having a uniform width of the second semiconductor region or the third semiconductor region is the length of the second semiconductor region or the third semiconductor region. 4. The semiconductor device according to claim 1, wherein the depth is set to 0.7 times or more of a depth from one main surface of the first semiconductor region. 5.   Between the second semiconductor region and the third semiconductor region, the impurity density on the inner side is set higher than the impurity density on the one main surface side of the first semiconductor region. The semiconductor device according to claim 1, wherein: Forming a first semiconductor region of a first conductivity type;
A first first-stage trench extending from one main surface of the first semiconductor region to the inside of the first semiconductor region is formed, and adjacent to the first first-stage trench, the first semiconductor region Forming a second first-stage trench extending from one main surface into the first semiconductor region;
Impurities of a second conductivity type opposite to the first conductivity type are introduced into the first semiconductor region from the inner wall of the first first-stage trench, and uniform from the inner wall of the first first-stage trench. Forming a second semiconductor region having a width; introducing an impurity of the second conductivity type into the first semiconductor region from an inner wall of the second first-stage trench; Forming a third semiconductor region having a uniform width from the inner wall;
A first second-stage trench connected to the first first-stage trench and extending into the first semiconductor region is formed, and the first first-stage trench and the first second-stage trench are formed. Forming a first trench having,
A second second-stage trench connected to the second first-stage trench and extending into the first semiconductor region is formed, and the second first-stage trench and the second second-stage trench are formed. Forming a second trench having:
The fourth semiconductor region of the first conductivity type is formed in the second semiconductor region on the one main surface side of the first semiconductor region, and the third semiconductor region is formed on the one main surface side of the first semiconductor region. Forming a fifth semiconductor region of the first conductivity type in the semiconductor region;
A first gate insulating film is formed along the second semiconductor region on the inner wall of the first trench, and a second gate insulating film is formed along the third semiconductor region on the inner wall of the second trench. Forming a step;
A first gate electrode is formed in the first trench through the first gate insulating film, and a second gate electrode is formed in the second trench through the second gate insulating film. Forming a step;
Electrically connected to the second semiconductor region, the third semiconductor region, the fourth semiconductor region, and the fifth semiconductor region, and between the second semiconductor region and the third semiconductor region; Forming an electrode connected to the first semiconductor region in a Schottky connection;
A method for manufacturing a semiconductor device, comprising:

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