JP2010010514A - Production method of semiconductor device, and semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve the production yield and reliability of a semiconductor device. <P>SOLUTION: Cleavages are generated at a mid-depth in the depth direction of the semiconductor substrate from the bottom of the concave portion while forming recesses on the main surface of the semiconductor substrate by contacting the leading edge of a blade serving as a cutting jig with the upper side of the plate-like semiconductor substrate. Subsequently, a film is disposed on the back side of the semiconductor substrate. Then, the generation of the cleavages is promoted to separate the semiconductor substrate by extending the film after generating cleavages. Use of such a method allows improvement in the production yield and reliability of the semiconductor device. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor device and a semiconductor device, and more particularly to a method for manufacturing a semiconductor device according to individualization of a semiconductor device and a semiconductor device manufactured by the method for manufacturing a semiconductor device.

  In recent years, there has been a demand for downsizing and thinning of semiconductor devices mounted on electronic devices. Along with this, CSP (Chip Size Package), which is a semiconductor device packaged in substantially the same size as the outer size of the semiconductor element, has attracted attention.

The semiconductor device is obtained by forming an external connection terminal on a semiconductor element in a wafer state and then dicing it into individual pieces. In such singulation, a rotary dicing blade is usually used. That is, after bringing the tip of the dicing blade into contact between the semiconductor elements in a wafer state placed on a support member such as a resin tape, the tip of the dicing blade is penetrated from the front side to the back side of the wafer, and the semiconductor The element is separated (for example, refer to Patent Document 1).
Japanese Patent No. 37279939

However, in the above-described singulation method, the tip of the dicing blade is penetrated into the wafer until the tip of the dicing blade reaches the support member.
When the tip of the dicing blade is inserted deeply into the wafer in this way, so-called chatter vibration in which the dicing blade vibrates in the vertical direction with respect to the main surface becomes large, and the wafer cut surface is damaged by the vibration.

  In particular, in recent years, the dicing area has been narrowed in order to increase the number of semiconductor elements extracted from the wafer substrate. In the CSP described above, for example, an electronic circuit layer may be formed in the vicinity of the dicing region. Accordingly, the side surface of the semiconductor element is increasingly susceptible to damage (for example, chipping phenomenon), and chip separation is caused by the above-described singulation.

As described above, the individualization method has a problem that individual semiconductor elements are damaged, the manufacturing yield of the semiconductor device is reduced, and the reliability is not improved.
The present invention has been made in view of these points, and has been manufactured by a method for manufacturing a semiconductor device that improves the manufacturing yield of the semiconductor device and improves the reliability of the semiconductor device, and the method for manufacturing the semiconductor device. An object is to provide a semiconductor device.

  According to one aspect of the present invention, a blade is brought into contact with the surface of a semiconductor substrate, thereby forming a recess in the main surface of the semiconductor substrate, and from a bottom of the recess to a part in a depth direction of the semiconductor substrate. A step of generating cleavage; a step of disposing a film on a back surface of the semiconductor substrate; and a step of dividing the semiconductor substrate by promoting the cleavage by stretching the film after generating the cleavage. , A method for manufacturing a semiconductor device is provided.

  According to another aspect of the present invention, a semiconductor substrate and a circuit unit formed on the semiconductor substrate are provided, and the semiconductor substrate is continuous with the main surface on which the circuit unit is formed and the main surface. There is provided a semiconductor device having a first surface that is inclined with respect to the main surface and a side surface that includes a second surface that is continuous with the first surface and includes a cleaved surface.

  According to the above means, the manufacturing yield of the semiconductor device is improved and the reliability of the semiconductor device is improved.

Hereinafter, a semiconductor device manufacturing method according to the present embodiment and a semiconductor device manufactured by the semiconductor device manufacturing method will be described in detail with reference to the drawings.
A manufacturing process flow according to the present embodiment is shown in FIG.

First, the tip of a cutting jig such as a dicing blade is positioned between a plurality of semiconductor devices continuously formed on the surface side of the plate-like semiconductor substrate (step S1).
Next, the tip of the cutting jig is brought into contact with the semiconductor substrate to form a recess corresponding to the shape of the tip of the cutting jig on the main surface of the semiconductor substrate located between the semiconductor devices, for example, the scribe region. Cleavage is generated from the bottom of the substrate to a part in the depth direction of the semiconductor substrate (step S2).

Next, the resin film disposed on the back side of the plate-like semiconductor substrate is stretched to promote cleavage. Then, the plate-like semiconductor substrate is divided individually (step S3).
According to such a manufacturing process, a recess corresponding to the shape of the tip of the cutting jig is formed between the semiconductor devices continuously formed on the surface side of the plate-shaped semiconductor substrate, and the bottom of the recess is formed. The cleavage occurs in a part of the depth direction of the semiconductor substrate. And if the resin film arrange | positioned at the back surface side of a plate-shaped semiconductor substrate is extended | stretched, a plate-shaped semiconductor substrate will be parted simply and with high precision. Thereby, the semiconductor device continuously formed on the semiconductor substrate is separated into individual semiconductor elements.

  Next, a semiconductor device manufacturing method including a process for testing the electrical characteristics of the semiconductor devices arranged on the semiconductor substrate based on the manufacturing process flow will be described in more detail with reference to FIGS.

  In the manufacturing method illustrated below, a method of manufacturing a WLCSP (Wafer Level Chip Size Package) is illustrated as an example. However, the present embodiment is not particularly limited to the production of WLCSP.

In the following description and drawings, the same members are denoted by the same reference numerals, and detailed description thereof is omitted.
2 to 9 are schematic views of the relevant part for explaining the method of manufacturing the semiconductor device of the present embodiment.

First, as shown in FIG. 2A, an insulating layer 10id is disposed on a semiconductor substrate 10s in a wafer state, and an insulating layer 10i is disposed on the insulating layer 10id.
On the main surface of the semiconductor substrate 10s, a wafer process is applied in advance to form an active element such as a transistor, a passive element such as a capacitive element, and an electronic circuit layer that connects these functional elements (illustrated). do not do).

  In addition, in the insulating layer 10id, wiring layers or via electrodes are arranged in multiple layers, and an interlayer insulating film is arranged between the wiring layers (not shown). Such an insulating layer 10id is covered and protected by the insulating layer 10i.

  Further, wiring layers (rewiring layers) 10la and 10lb are selectively disposed on the insulating layer 10i, and the post electrode 10p is disposed on the wiring layer 10la. The electronic circuit layer disposed on the semiconductor substrate 10s and the wiring layers 10la and 10lb are electrically connected through, for example, a wiring layer disposed in the insulating layers 10id and 10i.

  In addition, the semiconductor substrate 10s is provided with a scribe region sca for dividing the semiconductor substrate 10s and the like by a dicing process. That is, the scribe area sca is cut by a dicing blade (dicer), and the semiconductor substrate 10s and the like are divided by the scribe area sca. The width of the scribe area sca is, for example, 50 μm to 90 μm.

Further, in the insulating layer 10id in the vicinity of the scribe region sca, a moisture resistant layer (moisture resistant ring) 10rg for preventing permeation of moisture and the like into the insulating layer 10id is provided.
As the material of the semiconductor substrate 10s, for example, a semiconductor material such as silicon (Si) or gallium arsenide (GaAs) is applied.

In addition, as the material of the insulating layer 10id, for example, a low dielectric constant insulating material (Low-k material) is applied. As the low dielectric constant insulating material, a porous inorganic material or organic material is applied. For example, fluorine-doped silicon glass (FSG), silicon oxide carbide (SiOC), silicon oxide ( SiO _2), organic resin or the like is applied.

The material of the insulating layer 10i is, for example, polyimide (PI).
Moreover, for example, copper (Cu) is applied as the material of the wiring layers 10la and 10lb and the post electrode 10p.

Next, such a semiconductor substrate 10s or the like is mounted on a table (not shown) of a dicing apparatus, and the first dicing process is performed on the semiconductor substrate 10s or the like.
For example, after the tip of the rotary dicing blade DB is positioned at the center portion of the scribe region sca, the tip of the dicing blade DB is brought into contact with the center portion of the scribe region sca from the surface side of the semiconductor substrate 10s, and the semiconductor substrate Insert the tip of the dicing blade DB into the surface of 10s. Such a state is shown in FIG.

  Such a dicing blade DB has, for example, silicon carbide (SiC) or a diamond sintered body as a main component (base material), and diamond abrasive grains are arranged on the surface thereof. The cross-sectional shape of the tip portion of the dicing blade DB is a semicircle. The thickness of the dicing blade DB is 20 μm to 40 μm.

  In this embodiment, the tip of the dicing blade DB is not allowed to reach the back surface side of the semiconductor substrate 10s, and the tip of the dicing blade DB is kept near the surface of the semiconductor substrate 10s.

  By such a method, the insulating layer 10id is completely divided. However, in the semiconductor substrate 10s, only the vicinity of the surface of the semiconductor substrate 10s is cut. In addition, cleavage 10cl occurs halfway in the depth direction of the semiconductor substrate 10s.

  That is, a recess (notch) 10ct corresponding to the tip shape of the dicing blade DB is formed on the main surface of the semiconductor substrate 10s, and a cleavage 10cl is formed from the bottom of the recess 10ct to a part in the depth direction of the semiconductor substrate 10s. appear.

  Such cleavage 10cl occurs when the dicing blade DB is inserted into the semiconductor substrate 10s to form the recess 10ct, and the recess 10ct is pushed and widened by the tip of the dicing blade DB.

That is, when a force for expanding the recess 10ct is applied to the semiconductor substrate 10s, the semiconductor substrate 10s is cleaved because the semiconductor substrate 10s is a crystal.
However, since the tip of the dicing blade DB is held in the vicinity of the front surface of the semiconductor substrate 10s, the cleavage 10cl does not reach the back side of the semiconductor substrate 10s, and extends from the bottom of the recess 10ct to the middle of the semiconductor substrate 10s in the depth direction. A cleave 10cl is formed.

Therefore, at this stage, the semiconductor substrate 10s is in a wafer state and is in a state before being singulated.
In the present embodiment, since the tip of the dicing blade DB is kept in contact with the vicinity of the front surface of the semiconductor substrate 10s, a method for causing the tip of the dicing blade DB to reach the back side of the semiconductor substrate 10s. Compared with, chatter vibration of the dicing blade DB is suppressed. Thereby, the insulating layer 10id and the semiconductor substrate 10s are not easily damaged.

  Therefore, even if the first dicing process is performed, the wiring layer, the via electrode and the moisture-resistant layer 10 rg disposed in the insulating layer 10 id, or the electronic circuit layer formed on the main surface side of the semiconductor substrate 10 s are damaged. Without changing the original form.

  Then, the recess 10ct is formed vertically and horizontally on the semiconductor substrate 10s by the dicing blade DB. This is shown in FIG. FIG. 3 illustrates a state in which the semiconductor substrate 10s and the like are viewed obliquely from above. In FIG. 3, the insulating layers 10id and 10i, the wiring layers 10la and 10lb, and the post electrode 10p are not shown.

  As shown in the drawing, a recess 10ct is formed vertically and horizontally on the semiconductor substrate 10s. Such a recess 10ct is formed in the scribe region sca as described above. In the region defined in the recess 10ct, the semiconductor device before separation is formed.

Next, as shown in FIG. 4A, the dicing blade DB is moved upward to release the contact between the dicing blade DB and the semiconductor substrate 10s.
Next, as shown in FIG. 4B, the recess 10ct of the semiconductor substrate 10s, the exposed surfaces of the insulating layers 10id and 10i, the exposed surfaces of the wiring layers 10la and 10lb, and the side surface of the post electrode 10p are sealed with a sealing resin 10rs. Seal with. As a sealing method of the sealing resin 10rs, for example, a transfer mold method is applied.

Here, an epoxy resin is applied as the material of the sealing resin 10rs. The epoxy resin may contain an inorganic filler mainly composed of silica (SiO ₂ ) or alumina (Al ₂ O ₃ ), or an organic filler mainly composed of silicon rubber.

  Next, as shown in FIG. 4C, a bump electrode 10bp which is an electrode terminal is formed on the post electrode 10p. By such a process, the semiconductor element 20c (WLCSP) before separation is completed.

  The bump electrode 10 bp may be made of, for example, tin (Sn) -copper solder, tin-silver (Ag) solder, binary solder such as tin-zinc (Zn) solder, tin-silver-copper solder, tin, etc. -Any of ternary solder such as silver-indium (In) solder, tin-zinc-bismuth (Bi) solder, quaternary solder such as tin-silver-copper-bismuth solder, tin-silver-indium-bismuth solder, etc. Is applied.

In addition, before forming the bump electrode 10 bp, a two-layer plating of nickel (Ni) / gold (Au) may be coated on the surface of the post electrode 10 p from the lower layer.
Next, as shown in FIG. 5A, the electrical characteristics of the semiconductor element 20c are tested using a prober.

  For example, the semiconductor substrate 10s is placed on a prober stage (not shown), and the tip of the probe pin PP fixed to the probe card PC is brought into contact with the surface of the bump electrode 10bp to test the electrical characteristics of the semiconductor element 20c. To do.

  When the electrical characteristic test is completed, the probe card PC is moved upward to release the contact between the probe pin PP and the bump electrode 10bp. Such a state is shown in FIG.

As described above, in the present embodiment, the electrical characteristic test of the semiconductor element 20c is completed before the semiconductor substrate 10s is separated.
Note that the electrical characteristic test of the semiconductor element 20c can be performed even after the semiconductor substrate 10s is separated.

  For example, the electrical characteristics can be tested by placing the separated semiconductor element 20c on a dedicated test tray and bringing the probe pin PP into contact with the bump electrode 10bp of the semiconductor element 20c.

  However, in the contact between the probe pin PP and the bump electrode 10bp, since the material of the bump electrode 10bp is a solder material, the tip of the probe pin PP is sunk into the surface of the bump electrode 10bp, and the probe pin PP and the bump electrode 10bp are in contact with each other. It may be difficult to release the contact.

  In such a case, due to the light weight of WLCSP, the semiconductor element 20c may be lifted by the probe pin PP, and the semiconductor element 20c may be detached from the test tray. Then, the semiconductor element 20c may fall again on the test tray, and the semiconductor element 20c may be damaged or damaged.

  In this regard, in the present embodiment, the electrical characteristics of the semiconductor element 20c are tested in the wafer state. Therefore, even if the tip of the probe pin PP is sunk into the surface of the bump electrode 10bp, the device under test is heavier than each semiconductor element 20c, so that the probe pin PP and the bump electrode 10bp Is easily released.

As a result, even if the electrical characteristic test of the semiconductor element 20c is performed, the above-described drop does not occur, and the semiconductor element 20c is not damaged or damaged.
In other words, according to the present embodiment, the electrical characteristic test of the semiconductor element 20c can be stably performed.

Next, the semiconductor substrate 10s and the like are mounted on a table (not shown) of a dicing apparatus, and the semiconductor substrate 10s and the like are subjected to a second dicing process.
For example, as shown in FIG. 6A, the dicing blade DB is inserted between the semiconductor elements 20c from above until the tip of the dicing blade DB contacts the bottom of the recess 10ct.

  As a result, the sealing resin 10rs disposed in the recess 10ct and on the recess 10ct is cut and removed by the dicing blade DB. The removal operation of the sealing resin 10rs at this stage may be performed using laser light.

Then, the dicing blade DB is moved upward (not shown), and the dicing blade DB is separated from the semiconductor substrate 10s.
Subsequently, the back surface side of the semiconductor substrate 10s is polished. Such a state is shown in FIG.

  As illustrated, the back side of the semiconductor substrate 10s is polished to a predetermined thickness. In addition, a recess (notch) 10h exposed from the sealing resin 10rs is formed on the side surface of each semiconductor element 20c. As described above, the concave portion 10h corresponds to the tip shape of the dicing blade DB.

  Subsequently, as shown in FIG. 7A, a tape member (resin film) TP provided with an adhesive layer is fixed and disposed on the back side of the semiconductor substrate 10s. Then, the tape member TP is extended in the horizontal direction (see the arrow A direction in the figure).

  By such horizontal expansion of the tape member TP, the cleavage 10cl further proceeds. Finally, the cleavage 10cl reaches the back side of the semiconductor substrate 10s. Such a state is shown in FIG.

  Subsequently, the tape member TP is removed from the semiconductor substrate 10s. As a result, the semiconductor element 20c using the semiconductor substrate 10s as a support substrate is separated into chips. Such a state is shown in FIG.

  As shown in the figure, the semiconductor element 20c singulated has a semiconductor substrate 10s having a concave surface 10h formed of a curved surface corresponding to the tip shape of the dicing blade DB and a cleavage surface 10clf generated by cleavage as a support substrate. Yes. The insulating layers 10id and 10i disposed on the semiconductor substrate 10s, the wiring layers 10la and 10lb selectively disposed on the insulating layers 10id and 10i, the post electrode 10p electrically connected to the wiring layer 10la, and the post electrode A bump electrode 10bp electrically connected to 10p is provided.

In addition, since the semiconductor element 20c includes the recess 10h on the side surface, the area of the main surface of the insulating layers 10id and 10i is smaller than the area of the back surface of the semiconductor substrate 10s.
In the semiconductor device singulation, in addition to the expansion of the tape member TP, the contact between the semiconductor element 20c and the tape member TP may be released by pushing it up with a push-up pin (not shown). ). That is, the semiconductor element 20c is singulated into individual chips by pushing up the semiconductor element 20c through the tape member TP from the back side by a push pin and reducing the contact area between the tape member TP and the semiconductor element 20c. Also good.

In the present embodiment, the dicing blade DB having the shape described above is not limited, and the dicing blade DB illustrated in FIGS. 8 and 9 may be used.
For example, as shown in FIG. 8A, a dicing blade DB having a sharp tip (triangular shape) may be used. As the sharp angle, a dicing blade DB having an illustrated angle θ of 100 ° to 160 ° is used.

  When such a dicing blade DB is brought into contact with the surface of the semiconductor substrate 10s, the tip shape is sharp, so that the pressing force is further increased in the direction of the arrow a in FIG. work. Thereby, the said recessed part 10ct is spread easily, and it becomes easier to generate | occur | produce the cleavage 10cl in the semiconductor substrate 10s. An inclined surface corresponding to the tip shape of the dicing blade DB is formed on the semiconductor substrate 10s cut by the dicing blade DB.

Moreover, as shown to Fig.9 (a), you may use what provided the projection part BP containing a super steel material, for example in the forefront of dicing blade DB.
When such a dicing blade DB is brought into contact with the surface of the semiconductor substrate 10s, the shape of the tip portion is sharp and the protrusion BP is formed at the forefront. ) More pressing force acts in the direction of arrow a. As a result, the concave portion 10ct is easily spread and the cleavage 10cl is likely to occur in the semiconductor substrate 10s. Further, the surface of the semiconductor substrate 10s can be more easily cut by the protrusion BP.

Such a protrusion BP may be provided in the dicing blade DB exemplified in FIG.
Such a dicing blade DB may be applied to the present embodiment.

Next, specific effects brought about by the present embodiment will be described.
First, chatter vibration due to the dicing blade DB is suppressed as compared with the case of penetrating to the back surface side of the semiconductor substrate 10s, so that the insulating layer 10id and the semiconductor substrate 10s are not easily damaged. Thereby, the wiring layer or via electrode disposed in the insulating layer 10id and the electronic circuit layer formed on the main surface side of the semiconductor substrate 10s are not easily damaged. In particular, even when a low dielectric constant insulating material with weak strength is used as the material of the insulating layer 10id, the insulating layer 10id is hardly damaged.

In addition, the moisture-resistant layer 10 rg is not easily damaged, and moisture or the like is prevented from penetrating from the side surface of the insulating layer 10 id.
Further, since the semiconductor element 20c is less likely to be damaged or damaged, the number of semiconductor elements 20c taken out per wafer substrate increases.

  In the present embodiment, since the tip of the dicing blade DB is kept in contact with the surface of the semiconductor substrate 10s, it is difficult to apply a load to the dicing blade DB itself.

  Thereby, in the dicing process, for example, an extremely thin dicing blade DB having a thickness of about 20 μm can be used. Therefore, dicing can be performed while keeping the side surface of the dicing blade DB away from the side surface of the insulating layer 10id. As a result, the insulating layer 10id is hardly damaged or damaged.

Thus, according to the present embodiment, the manufacturing yield and reliability of the semiconductor device are improved, and the productivity of the semiconductor device is improved.
As a means for cleaving the semiconductor substrate, there is a method of cleaving by irradiating the surface of the semiconductor substrate with laser light. However, when the laser beam is used, its crystallinity is modified inside the semiconductor substrate. Therefore, the cleavage plane may be distorted after cleavage. In addition, when an element test wiring or the like is arranged in the scribe region sca, there is a problem that the laser light is blocked by the wiring or the like.

  However, in the present embodiment, by controlling the insertion position of the dicing blade DB with respect to the semiconductor substrate 10s, the position of the cleavage 10cl can be controlled easily and with high accuracy. Then, the semiconductor substrate 10s can be easily divided at the formed cleavage 10cl as a boundary. Even if the above-described wirings are arranged in the scribe region sca, the wirings can be easily cut by using the dicing blade DB.

(Supplementary Note 1) A step of causing cleavage from a bottom of the concave portion to a part in a depth direction of the semiconductor substrate while forming a concave portion on the main surface of the semiconductor substrate by bringing a blade into contact with the surface of the semiconductor substrate. When,
Placing a film on the back surface of the semiconductor substrate;
After generating the cleavage, stretching the film to promote the cleavage and dividing the semiconductor substrate;
A method for manufacturing a semiconductor device, comprising:

(Appendix 2) Before dividing the semiconductor substrate, sealing the semiconductor substrate with resin;
Removing the resin disposed on the recess;
The method for manufacturing a semiconductor device according to appendix 1, further comprising:

  (Additional remark 3) Before dividing | segmenting the said semiconductor substrate, the electrical property of the semiconductor device formed in the said semiconductor substrate is tested with a prober, The manufacturing method of the semiconductor device of Additional remark 1 characterized by the above-mentioned.

  (Supplementary note 4) The method of manufacturing a semiconductor device according to supplementary note 1, further comprising a step of forming a low dielectric constant insulating layer on the surface of the semiconductor substrate before bringing a blade into contact with the surface of the semiconductor substrate.

(Additional remark 5) The said blade whose cross-sectional shape of a front-end | tip is a semicircle shape or a sharp shape is used, The manufacturing method of the semiconductor device of Additional remark 1 characterized by the above-mentioned.
(Additional remark 6) The manufacturing method of the semiconductor device of Additional remark 1 or 5 characterized by using the said blade by which the protrusion part was provided at the front-end | tip.

(Appendix 7) a semiconductor substrate;
A circuit unit formed on the semiconductor substrate,
The semiconductor substrate is
A main surface on which the circuit portion is formed;
A side surface including a first surface that is continuous from the main surface and that is inclined with respect to the main surface; and a second surface that is continuous from the first surface and is a cleavage surface;
A semiconductor device comprising:

(Additional remark 8) The semiconductor device of Additional remark 7 characterized by the area of the main surface of the insulating layer arrange | positioned on the said semiconductor substrate being smaller than the area of the back surface of the said semiconductor substrate.
(Additional remark 9) The semiconductor device of Additional remark 8 characterized by the material of the said insulating layer having a low dielectric constant insulating material as a main component.

It is a figure explaining the manufacturing process flow which concerns on this Embodiment. It is a principal part schematic diagram explaining the manufacturing method of the semiconductor device of this Embodiment (the 1). It is a principal part schematic diagram explaining the manufacturing method of the semiconductor device of this Embodiment (the 2). FIG. 6 is a schematic diagram for explaining a main part of the semiconductor device according to the present embodiment (No. 3); FIG. 10 is a schematic diagram for explaining a main part of the semiconductor device according to the present embodiment (No. 4); FIG. 10 is a schematic diagram for explaining a main part of the method for manufacturing the semiconductor device according to the embodiment (No. 5); It is a principal part schematic diagram explaining the manufacturing method of the semiconductor device of this Embodiment (the 6). FIG. 7 is a schematic view of a principal part for explaining the method of manufacturing a semiconductor device according to the present embodiment (No. 7); It is a principal part schematic diagram explaining the manufacturing method of the semiconductor device of this Embodiment (the 8).

Explanation of symbols

10 bp Bump electrode 10cl Cleavage 10clf Cleaved surface 10ct, 10h Recess 10id, 10i Insulating layer 10la, 10lb Wiring layer 10p Post electrode 10 rg Moisture resistant layer 10 rs Resin for sealing 10 s Semiconductor substrate 20 c Semiconductor element BP Projection part DB Dicing blade Probe DB Dicing blade Pin sca scribing area TP tape material

Claims (5)

Forming a crevice in the depth direction of the semiconductor substrate from the bottom of the concave portion while forming a concave portion on the main surface of the semiconductor substrate by bringing a blade into contact with the surface of the semiconductor substrate; and
Placing a film on the back surface of the semiconductor substrate;
After generating the cleavage, stretching the film to promote the cleavage and dividing the semiconductor substrate;
A method for manufacturing a semiconductor device, comprising: Before dividing the semiconductor substrate, sealing the semiconductor substrate with resin;
Removing the resin disposed on the recess;
The method of manufacturing a semiconductor device according to claim 1, further comprising:   2. The method of manufacturing a semiconductor device according to claim 1, wherein the electrical characteristics of the semiconductor device formed on the semiconductor substrate are tested by a prober before the semiconductor substrate is divided.   2. The method of manufacturing a semiconductor device according to claim 1, further comprising a step of forming a low dielectric constant insulating layer on the surface of the semiconductor substrate before bringing a blade into contact with the surface of the semiconductor substrate. A semiconductor substrate;
A circuit unit formed on the semiconductor substrate,
The semiconductor substrate is
A main surface on which the circuit portion is formed;
A side surface including a first surface that is continuous from the main surface and that is inclined with respect to the main surface; and a second surface that is continuous from the first surface and is a cleavage surface;
A semiconductor device comprising:

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