JP2010002257A - Probe card - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a probe card capable of passing a high speed electric signal by controlling the intrinsic impedance of a through-hole in a proper range by reducing parasitic capacitance. <P>SOLUTION: The probe card for probing by contacting an electrode pad on a semiconductor integrated circuit includes a multilayer wiring board 1, and a plurality of probe needles 51 for inputting and outputting signals between a semiconductor integrated circuit 56 and the multilayer wiring board 1 by contacting one terminal part to an electrode pad 3 of the multilayer wiring board 1 and by contacting the other terminal part to an electrode pad 57 on the semiconductor integrated circuit 56, wherein on the multilayer wiring board 1, a plurality of through-holes 10 connected to the electrode pad 3 of the multilayer wiring substrate 1 and having the different intrinsic impedance are mixedly disposed. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a probe card, and more particularly to a probe card used in a tester for confirming the operation of a semiconductor integrated circuit.

  A probe card (Probe Card) is used by being attached to an LSI tester for confirming the operation of a semiconductor integrated circuit such as an LSI (Large Scale Integrated Circuit), and is used for probing in contact with an electrode pad of the semiconductor integrated circuit. This is a multilayer printed wiring board provided with a probe needle (Probe), an electrode pad connected to the probe needle, and a connection terminal for connection to an LSI tester.

  FIG. 9 is a schematic view of the probe card as viewed from the side. The multilayer printed wiring board 100 is connected to a probe needle 101, a block 102 that supports the probe needle 101, an electrode 103 that connects the probe needle 101, and an LSI tester. Connection terminal 104. Part A of FIG. 9 is a part for attaching the probe needle 101 to the multilayer printed wiring board 100, and part B of FIG. 9 shows a part including a connection terminal 104 for connection to the LSI tester.

  FIG. 10A shows an enlarged view of the cross section of the substrate in part A of FIG. 9, and FIG. 10B shows an inner layer solid pattern in part A. In FIG. 10A, the substrate cross section has a through hole 105, a signal wiring 106, and an inner layer solid pattern 107, and the electrode 103 is connected to the probe needle 101 by solder 108. The inner layer solid pattern 107 in FIG. 10B has a plurality of through holes 105, and a clearance 118 is provided in each through hole 105.

  FIG. 11A shows an enlarged view of the substrate cross section of the B part in FIG. 9, and FIG. 11B shows an inner layer solid pattern of the B part. In FIG. 11A, the cross section of the substrate has through holes 120, and the inner layer solid pattern 122 of FIG. 11B has a plurality of through holes 120, and each through hole 120 has a clearance 121. Is provided.

  Comparing FIG. 11 and FIG. 10, the arrangement density of the through holes 105 on the probe needle mounting side shown in FIG. 10 is higher than the density of the through holes 120 on the side connected to the LSI tester shown in FIG. This is a feature of the multilayer printed wiring board 100 used in the card.

Incidentally, a multilayer printed wiring board is disclosed in Patent Document 1. In this multilayer printed wiring board, the capacitance component is reduced with respect to the signal through hole by increasing the diameter of each clearance formed in the plurality of solid conductor layers for one signal through hole. The clearance diameters of the plurality of solid conductor layers are different.
JP 2001-244633 A

  In the probe card described above, the through hole of the multilayer printed wiring board where the probe needle is attached has a large parasitic capacitance (capacitance) due to the following reasons, and the characteristic impedance value of the through hole is lowered, resulting in a high-speed electric signal. Is difficult to pass through the through hole. The reason why the parasitic capacitance in the multilayer printed wiring board increases is as follows.

  (A) The multilayer printed wiring board has a needle base electrode pad for attaching a needle base which is one end of the probe needle, and the position of the needle base electrode pad is in a specific narrow region, They are arranged in a grid pattern with a narrow pitch (the basic grid shape is rectangular, square, isosceles triangle, equilateral triangle, etc.).

  The position of the needle base electrode pad must be arranged in this way because the tip of the probe needle must correspond to the electrode pad of the semiconductor integrated circuit concentrated in a very narrow area. This is because it must not.

  (B) The needle electrode pad of the multilayer printed wiring board in (a) is electrically connected to the conductor pattern formed on the inner layer (or the opposite surface) of the multilayer printed wiring board using a through hole. Connected. A plurality of inner layer solid patterns are formed on the inner layer of the multilayer printed wiring board through which the through hole penetrates. Of these inner layer solid patterns, the inner layer solid pattern that is not electrically connected has a clearance (hole, anti-pad). ) To insulate.

  However, when the clearance is formed in the inner layer solid pattern in this way, a parasitic capacitance (parasitic capacitance) is generated between the conductor in the through hole and the inner layer solid pattern.

  The number of layers of the inner layer solid pattern for the power supply and ground for the multilayer printed wiring board used for the probe card reaches several to ten times that of the usual printed circuit board, so compared to the inductance component of the through hole. And excessive parasitic capacitance. Therefore, the characteristic impedance of the through hole (defined by the square root of {inductance / parasitic capacitance}) decreases as the parasitic capacitance increases. For this reason, since the characteristic impedance of the through hole is lower than the characteristic impedance of the electric signal wiring, mismatching of the characteristic impedance becomes large in the through hole portion, and a high-speed electric signal cannot pass through the through hole.

  (C) The problem (b) can be solved by reducing the parasitic capacitance of the through hole. A technique for reducing the parasitic capacitance by increasing the clearance diameter in the plurality of conductor solid pattern layers on the inner layer with respect to one signal through hole is disclosed in Patent Document 1, but as described in (a) above. Since the electrode pads for needles on the multilayer printed wiring board are densely arranged in a narrow area, the arrangement density of the through holes is high, and when the clearance diameter is increased until the parasitic capacitance is sufficiently small, Since adjacent clearances are connected to each other, this is not applicable when attaching a probe needle of a probe card to a through hole of a multilayer printed wiring board.

  The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to reduce the parasitic capacitance and control the characteristic impedance of the through hole within an appropriate range so that a high-speed electric signal can be passed. It is to provide a probe card.

  The probe card of the present invention is a probe card that is mounted on a tester for confirming the operation of a semiconductor integrated circuit and contacts an electrode pad on the semiconductor integrated circuit. A signal is input / output between the semiconductor integrated circuit and the multilayer wiring substrate via the probe needle by connecting to the electrode pad of the substrate and contacting the other end of the electrode pad on the semiconductor integrated circuit. A plurality of probe needles, and the multilayer wiring board includes a plurality of through holes connected to the electrode pads of the multilayer wiring board, wherein the through holes having different characteristic impedances are mixedly arranged. It is characterized by being.

  According to the present invention, it is possible to provide a probe card capable of reducing a parasitic capacitance and controlling a characteristic impedance of a through hole within an appropriate range and passing a high-speed electric signal.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

(First embodiment)
FIG. 1 is a plan view showing a shape example of an inner layer solid pattern 2 in a region 1A where probe needle connection electrode pads of a multilayer wiring board of a probe card of the present invention are arranged.

  The probe card is used in an LSI tester for confirming the operation of a semiconductor integrated circuit, and the layer configuration of the multilayer printed wiring board (an example of the multilayer wiring board) of the probe card is, for example, 10 or more inner solid patterns and 4 or more layers. The signal wiring layer. The inner solid pattern layer is used as a power source and a GND (ground). A configuration example of the probe card will be described later with reference to FIGS.

  A region 1A of the multilayer printed wiring board shown in FIG. 1 where the probe needle connection electrode pads are arranged has an inner layer solid pattern 2 and a plurality of through holes 10. These through holes 10 are circular when viewed from above and have the same diameter. The centers of the through holes 10 are two-dimensionally arranged at a predetermined pitch P along the X direction and the Y direction, and the four adjacent through holes 10 are four corners of a square basic lattice H indicated by broken lines. It is arranged at the position. Each through hole 10 is arranged corresponding to a plurality of electrode pads 3 to which probe needles of the probe card are electrically connected, and the plurality of electrode pads 3 are formed by the above-described square basic lattice H. It is arrange | positioned in the position of each corner | angular part.

  The inner layer solid pattern 2 in the region 1A in which the probe needle connection electrode pads of the multilayer printed wiring board shown in FIG. 1 are disposed has clearances 5 and 6 corresponding to the respective through holes 10. The clearance is also called an antipad. Both the clearance 5 and the clearance 6 have a circular shape and have different diameters. The diameter D1 of the clearance 5 is smaller than the diameter D2 of the clearance 6. The clearance 5 is formed concentrically with respect to the through hole 10. Similarly, the clearance 6 is formed concentrically with respect to the adjacent through hole 10. The clearances 5 and 6 having different diameters in the inner layer solid pattern 2 are arranged alternately along the X direction and the Y direction, and the clearances 5 and 6 are arranged in a mixed manner.

  In the inner layer solid pattern 2, a clearance 6 having a large diameter is formed in addition to the clearance 5 having a normal diameter, so that the portion of the inner layer solid pattern 2 that forms the clearance 6 having a large diameter and the through hole 10. The parasitic capacitance generated between the conductor and the other conductor can be reduced as compared with the parasitic capacitance generated between the portion of the inner layer solid pattern 2 forming the clearance 5 having a small diameter and the conductor of the through hole 10.

  Therefore, the characteristic impedance of the through hole 10 in the clearance 6 having a large diameter can be made larger than the characteristic impedance of the through hole 10 in the clearance 5 having a small diameter. As a result, the characteristic impedance of the through hole 10 having a large diameter clearance 6 is prevented from becoming too small compared to the transmission path (signal wiring) to be connected, and the through hole 10 having the large diameter clearance 6 is disposed. A high-speed signal is assigned to the electrode pad 3 from the needle base of the probe needle and input / output. That is, it is possible to improve the high-speed signal passing characteristic in the through hole 10 having the clearance 6 having a large diameter. From this, the characteristic impedance value of the through hole 10 can be easily controlled.

(Second Embodiment)
Next, a second embodiment of the present invention will be described with reference to FIG.

  FIG. 2 is a plan view showing an example of the shape of the inner layer solid pattern 2B in the region 1B where the probe needle connection electrode pads of the multilayer printed wiring board of another probe card of the present invention are arranged.

  As shown in FIG. 2, the region 1B in which the probe needle connection electrode pads of the multilayer printed wiring board are arranged has an inner layer solid pattern 2B and a plurality of through holes 10B. These through-holes 10B are circular when viewed from above and have the same diameter. The centers of the three adjacent through holes 10B are two-dimensionally arranged along the X direction and the Y direction at the positions of three corners of a basic lattice G of equilateral triangles indicated by broken lines. Each through hole 10B is arranged corresponding to a plurality of electrode pads to which the probe needles are electrically connected, and the plurality of electrode pads are arranged in an equilateral triangular basic lattice shape.

  The inner layer solid pattern 2B in the region 1B in which the probe needle connection electrode pads of the multilayer printed wiring board are disposed has clearances 5B and 6B corresponding to the respective through holes 10B. Both the clearance 5B and the clearance 6B have a circular shape, and the diameters of the clearance 5B and the clearance 6B are different. The diameter D3 of the clearance 5B is smaller than the diameter D4 of the clearance 6. The clearance 5B is concentrically formed with respect to the through hole 10B, and similarly, the clearance 6B is concentrically formed with respect to the adjacent through hole 10B. The clearances 5B and 6B having different diameters in the inner layer solid pattern 2B are mixedly arranged along the X direction and the Y direction.

  In addition to the normal diameter clearance 5B, the inner layer solid pattern 2B is formed with a clearance 6B having a large diameter, so that the portion of the inner layer solid pattern 2B that forms the clearance 6B having a large diameter and the through hole 10B. The parasitic capacitance generated between the conductor and the other conductor can be reduced as compared with the parasitic capacitance generated between the portion of the inner layer solid pattern 2B forming the clearance 5B having a small diameter and the conductor of the through hole 10B.

  Therefore, the characteristic impedance of the through hole 10B in the clearance 6B having a large diameter can be made larger than the characteristic impedance of the through hole 10B in the clearance 5B having a small diameter. This prevents the characteristic impedance of the through hole 10B having a large diameter clearance 6B from becoming too small compared to the transmission path (signal wiring) to be connected, and the through hole 10B having the large diameter clearance 6B is disposed in the through hole 10B. A high-speed signal is assigned to the electrode pad from the needle base of the probe needle and input / output. In other words, in the through hole 10B having the large diameter clearance 6B, high-speed signal passing characteristics can be improved.

(Third embodiment)
Next, a third embodiment of the present invention will be described with reference to FIG.

  In the first embodiment and the second embodiment described above, the diameters of the through holes 10 and 10B in the regions 1A and 1B in which the probe needle connection electrode pads of the multilayer printed wiring board are arranged are the same.

  On the other hand, in the region 1C where the probe needle connection electrode pads of the multilayer printed wiring board in the embodiment shown in FIG. 3 are arranged, the through holes 10C and the through holes 10D are provided at the corners of the square basic lattice H. In the position, they are alternately mixed at a predetermined pitch along the X and Y directions. The through hole 10C is a normal size through hole, and the clearance 5C is a normal size clearance.

  The diameter of the through hole 10D is a through hole that is smaller than the diameter of the normal (normal) size through hole 10C. The clearance 5C of the inner layer solid pattern 2C is provided concentrically with respect to the through hole 10C, and the clearance 6C is provided concentrically with respect to the through hole 10D.

  The diameter of the clearance 6C is larger than the diameter of the normal (normal) size clearance 5C. The through hole 10D is a through hole having a diameter smaller than that of the normal through hole 10C. Thereby, the characteristic impedance of the through hole can be increased. Thus, in order to increase the characteristic impedance of the through hole, the diameter of the through hole 10D is made smaller than the diameter of the normal size through hole 10C, and the diameter of the clearance 6C is larger than the diameter of the normal size clearance 5C. Is getting bigger.

  As a result, the inner layer solid pattern 2C is formed with the clearance 6C having a diameter larger than the normal size, so that the diameter of the inner layer solid pattern 2C forming the clearance 6C is made smaller than the normal size. The parasitic capacitance generated between the conductor of the through hole 10D is reduced as compared with the parasitic capacitance generated between the portion of the inner layer solid pattern 2C forming the normal size clearance 5C and the conductor of the normal size through hole 10C. can do.

  Moreover, since the diameter of the through hole 10D is reduced as compared with the through hole 10C, an effect of increasing the inductance component occurs. From this, the characteristic impedance value of the through hole 10D can be easily controlled.

  Accordingly, the characteristic impedance of the through hole 10D having a smaller diameter than the normal size in the clearance 6C having a larger diameter than the normal size is larger than the characteristic impedance of the normal size through hole 10C in the normal size clearance 5C. can do. This prevents the characteristic impedance of the through hole 10D having a reduced diameter of the clearance 6C having an increased diameter from becoming too small compared to the transmission path (signal wiring), and the electrode pad 3 disposed in the through hole 10D having the clearance 6C. A high-speed signal is assigned and inputted / outputted from the base of the probe needle. That is, it is possible to improve the high-speed signal passing characteristics in the through hole 10D having the clearance 6C having an increased diameter.

(Fourth embodiment)
Next, a fourth embodiment of the present invention will be described with reference to FIG.

  In the embodiment shown in FIG. 4, unlike the embodiment shown in FIG. 3, the inner layer solid pattern 2 </ b> D in the region 1 </ b> D where the probe needle connection electrode pads of the multilayer printed wiring board are arranged has a diameter larger than that of the normal through hole 10 </ b> C. Through-holes 10D having a smaller diameter are arranged at the respective corners of the regular triangular basic lattice G, and six through-holes 10C having a normal size are arranged around the through-hole 10D having a smaller diameter. Has been. The through hole 10C is a normal size through hole, and the clearance 5C is a normal size clearance.

  In the inner layer solid pattern 2D, a through hole 10C having a normal size is formed concentrically with respect to a clearance 5C having a normal size, and the through hole 10D having a diameter smaller than that of the normal through hole 10C is a normal one. It is formed concentrically with respect to the clearance 6C having a diameter larger than that of the clearance 5C.

  The inner layer solid pattern 2D is formed with a clearance 6C having a diameter larger than that of the normal size clearance 5C. The parasitic capacitance generated between the conductor of the through hole 10D having a smaller diameter than that of the inner layer solid pattern 2D forming the normal size clearance 5C and the conductor of the normal size through hole 10C. It can be reduced compared to the parasitic capacitance. Moreover, since the diameter of the through hole 10D is reduced as compared with the through hole 10C, an effect of increasing the inductance component occurs. From this, the characteristic impedance value of the through hole 10D can be easily controlled.

  Therefore, the characteristic impedance of the through hole 10D in the clearance 6C having a larger diameter than the normal size clearance 5C can be made larger than the characteristic impedance of the normal size through hole 10C in the normal size clearance 5C. . This prevents the characteristic impedance of the through hole 10D with the clearance 6C from becoming too small as compared with the transmission line (signal wiring), and the electrode pad disposed in the through hole 10D with the clearance 6C has the needle from the probe needle. High-speed signals are assigned and input / output. That is, it is possible to improve the high-speed signal passing characteristic in the through hole 10D having the clearance 6C.

(Fifth embodiment)
Next, a fifth embodiment of the present invention will be described with reference to FIGS.

  In the example of the region 1F in which the probe needle connection electrode pads of the multilayer printed wiring board shown in FIGS. 5 and 6 are arranged, the shape examples of the three-layer inner solid patterns 2F, 2G, and 2H are shown. The clearance diameters corresponding to are different for each inner layer solid pattern 2F, 2G, 2H, and are mixed. Each through hole 10R has the same diameter. 5A is a cross-sectional view taken along line MM in FIGS. 5B, 6A, and 6B.

  FIG. 5A shows an example of a cross-sectional shape of three inner layer solid patterns 2F, 2G, and 2H, FIG. 5B is a plan view of the inner layer solid pattern 2H, and FIG. FIG. 6B is a plan view of the inner layer solid pattern 2G, and FIG. 6B is a plan view of the inner layer solid pattern 2F. The inner layer solid pattern 2H is the (n + 2) th layer, the inner layer solid pattern 2G is the (n + 1) th layer, and the inner layer solid pattern 2F is the nth layer.

  In the inner layer solid pattern 2F shown in FIG. 6B, clearances 6D and 5D having different diameters are arranged corresponding to the adjacent through holes 10R having the same diameter. In the inner layer solid pattern 2G shown in FIG. 6A, clearances 5D and 6D having different diameters are arranged corresponding to adjacent through holes 10R having the same diameter. Furthermore, in the inner layer solid pattern 2H shown in FIG. 5B, clearances 6D and 5D having different diameters are arranged corresponding to adjacent through holes 10R having the same diameter. That is, in the inner layer solid patterns 2F, 2G, and 2H, the clearances 6D and 5D having different diameters are alternately mixed with each through-hole 10R, and the clearance diameter is alternately changed for each inner layer solid pattern. ing.

  Next, referring to FIGS. 7 and 8, an example of the structure of a probe card including the multilayer wiring board described above will be described.

  7A is a view of the probe card 50 viewed from the bottom side, and FIG. 7B is a side view showing the probe card 50 and the prober 80. FIG. FIG. 8A is a diagram showing an example of the arrangement of the electrode pads 3 in the surface pattern portion W of the probe card 50 shown in FIG. 7A, and FIG. 8B is the probe card in FIG. 8A. An arrangement example of the clearances 5 and 6 of the inner layer solid pattern 2 arranged corresponding to the electrode pads 3 in 50 portions W is shown. The clearances 5 and 6 are representatively shown as an example of the clearances 5 and 6 in the embodiment shown in FIG. 1, but the probe card 50 can be applied to the above-described embodiments.

  A probe card 50 shown in FIG. 7A has a multilayer printed wiring board 1, a plurality of probe needles 51, and a rectangular fixing resin member 52. On the multilayer printed wiring board 1, a plurality of electrode pads 53 for connecting to the LSI tester 70 and a plurality of electrode pads 3 for connecting the needle base of the probe needle 51 are arranged.

  As shown in FIGS. 7A and 7B, each probe needle 51 is fixed to the multilayer printed wiring board 1 by a fixing resin member 52. A needle base 54 that is one end of each probe needle 51 is electrically connected to the electrode pad 3 of the multilayer printed wiring board 1 by soldering or the like, and a needle tip 55 that is the other end of each probe needle 51 is a semiconductor. The electrode pad 57 of the integrated circuit 56 is electrically connected.

  In the embodiment of the present invention, a normal (normal) size clearance and a clearance larger than normal are mixed in a region where the through holes of the multilayer wiring board are densely arranged side by side. The clearance diameter is alternately changed for each inner layer solid pattern.

  The diameter of the clearance can be increased while securing the remaining portion of the inner layer solid pattern, and the parasitic capacitance of the through hole can be reduced. The characteristic impedance of the through hole can be prevented from becoming too low compared to the transmission line (signal wiring part), and the high-speed signal passing characteristic can be improved.

  The multi-layer wiring board of the LSI tester is composed of, for example, an inner layer solid pattern (for power supply and GND) of 10 layers or more and a signal wiring layer of 4 layers or more, but there are electrode pads for soldering for connecting the probe needle points. In the concentrated region, it is possible to prevent the through-hole parasitic capacitance from becoming excessive, and to improve the passing characteristics for high-speed signals. By using the probe card of the embodiment of the present invention, it is possible to increase the upper limit frequency (operation speed) that the LSI tester can handle. The probe card according to the embodiment of the present invention can be used for measurement of an LSI having an interface (I / F) that operates at, for example, 150 MHz or more.

  A probe card according to the present invention is a probe card that is attached to a tester for confirming the operation of a semiconductor integrated circuit and is connected to an electrode pad on the semiconductor integrated circuit for probing, and includes a multilayer wiring board and one end portion. A plurality of probe needles connected to the electrode pads of the multilayer wiring board and connected to the electrode pads on the semiconductor integrated circuit to input and output signals between the semiconductor integrated circuit and the multilayer wiring board; In the multilayer wiring board, a plurality of through holes connected to the electrode pads of the multilayer wiring board and having different characteristic impedances are mixedly arranged.

  As a result, the parasitic capacitance can be reduced and the characteristic impedance of the through hole can be controlled within an appropriate range so that a high-speed electric signal can be passed.

  Further, a clearance is provided between the inner layer solid pattern of the multilayer wiring board and the through hole, and the clearance diameters of the adjacent through holes are different. Accordingly, the clearance diameter can be increased while securing the remaining portion of the inner layer solid pattern, and the parasitic capacitance of the through hole can be reduced. The characteristic impedance of the through hole can be prevented from becoming too low compared to the transmission line (signal wiring part), and the high-speed signal passing characteristic can be improved.

  Furthermore, through holes having different diameters are mixedly arranged. Thereby, when the diameter of the through hole is reduced, an effect of increasing the inductance component occurs. From this, the characteristic impedance value of the through hole can be easily controlled.

  The multilayer wiring board has a plurality of layers of inner layer solid patterns. Clearances corresponding to through holes are formed in each inner layer solid pattern, and the diameter of the clearance is alternately different for each inner layer solid pattern. As a result, the parasitic capacitance can be reduced and the characteristic impedance of the through hole can be controlled within an appropriate range so that a high-speed electric signal can be passed.

  Note that the present invention is not limited to the above-described embodiments as they are, and can be embodied by modifying the constituent elements without departing from the scope of the invention in the implementation stage. Unlike the example shown in FIG. 2, the centers of the three through holes 10B are two-dimensionally arranged at the three corner positions of the basic lattice of isosceles triangles indicated by broken lines along the X and Y directions. May be. As the shape of the basic lattice, a rectangle, a square, an isosceles triangle, an equilateral triangle, or the like can be adopted.

  Various inventions can be formed by appropriately combining a plurality of constituent elements disclosed in the above embodiments. For example, some components may be deleted from all the components shown in the embodiment. Furthermore, you may combine the component covering different embodiment suitably.

It is a top view which shows 1st Embodiment of the inner layer solid pattern of the area | region which has arrange | positioned the electrode pad which connects a probe needle | hook in the multilayer wiring board of the probe card | curd of this invention. It is a top view which shows 2nd Embodiment of the inner layer solid pattern of the area | region which has arrange | positioned the electrode pad which connects a probe needle | hook in the multilayer wiring board of the probe card | curd of this invention. It is a top view which shows 3rd Embodiment of the inner layer solid pattern of the area | region which has arrange | positioned the electrode pad which connects a probe needle | hook in the multilayer wiring board of the probe card | curd of this invention. It is a top view which shows 4th Embodiment of the inner layer solid pattern of the area | region which has arrange | positioned the electrode pad which connects a probe needle | hook in the multilayer wiring board of the probe card | curd of this invention. It is a figure which shows 5th Embodiment of the inner layer solid pattern of the area | region which has arrange | positioned the electrode pad which connects a probe needle | hook in the multilayer wiring board of the probe card of this invention. It is a figure which shows 5th Embodiment of the inner layer solid pattern shown in FIG. It is a figure which shows the plane and side surface of a probe card. It is a figure which shows the electrode pad and through hole which connect the probe needle | hook of the probe card of FIG. It is the schematic which looked at the conventional probe card from the horizontal direction. FIG. 10 is an enlarged view of a cross-section of the substrate at section A of the probe card of FIG. It is an enlarged view of the board | substrate cross section of the B section of the probe card of FIG.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1A ... Area | region which has arrange | positioned the probe needle connection electrode pad of a multilayer printed wiring board, 2 ... Inner layer solid pattern, 3 ... Electrode pad, 4 ... 5 ... Clearance, 6 ... Clearance, 10 ... Through-hole, 50 ... Probe card, DESCRIPTION OF SYMBOLS 51 ... Probe needle, 52 ... Resin member for fixation, 5 ... Needle base of each probe needle, 55 ... Needle tip of probe needle, 56 ... Semiconductor integrated circuit, 57 ... Electrode pad of semiconductor integrated circuit, 80 ... Prober.

Claims (4)

A probe card attached to a tester for confirming the operation of the semiconductor integrated circuit and in contact with an electrode pad on the semiconductor integrated circuit,
A multilayer wiring board;
One end is connected to the electrode pad of the multilayer wiring board, and the other end is brought into contact with the electrode pad on the semiconductor integrated circuit to input / output signals between the semiconductor integrated circuit and the multilayer wiring board. A plurality of probe needles,
The probe card, wherein the multilayer wiring board includes a plurality of through holes connected to the electrode pads of the multilayer wiring board and having different characteristic impedances.   2. The probe according to claim 1, wherein a clearance is provided between the inner layer solid pattern of the multilayer wiring board and the through hole, and the diameters of the clearances of the adjacent through holes are different. card.   The probe card according to claim 1 or 2, wherein the through holes having different diameters are mixedly arranged.   The multilayer wiring board has a plurality of layers of the inner layer solid pattern, and each inner layer solid pattern has the clearance corresponding to the through hole, and the diameter of the clearance is determined by the inner layer solid pattern. The probe card according to claim 1, wherein the probe card is alternately different.

Images