JP2006339563A - Circuit board and semiconductor package employing the same - Google Patents

Circuit board and semiconductor package employing the same Download PDF

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JP2006339563A
JP2006339563A JP2005165172A JP2005165172A JP2006339563A JP 2006339563 A JP2006339563 A JP 2006339563A JP 2005165172 A JP2005165172 A JP 2005165172A JP 2005165172 A JP2005165172 A JP 2005165172A JP 2006339563 A JP2006339563 A JP 2006339563A
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circuit board
electrode pad
conductor
dielectric
wiring
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Hiroyasu Omori
寛康 大森
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Toppan Inc
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Toppan Printing Co Ltd
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a circuit board relating to an electrode pad for connecting a semiconductor element mounting substrate, an electrode pad for mounting components of the circuit board or the like which can be designed in highly dense wiring without degrading characteristic impedance and has high speed transmission characteristics and high design accuracy. <P>SOLUTION: A conductor 8 is placed so that an area of the conductor 8 in the electrode pad 1 of the circuit board is at or smaller than a predetermined value. A dielectric substance is introduced into a region of the pad 1 where the conductor 8 is not provided, thereby reducing a ratio of the area occupied by the conductor 8 in the electrode pad 1. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は、高速伝送用回路基板に関する。さらに詳しくは、半導体素子搭載用基板の接続用電極パッド、回路基板の部品搭載用電極パッドなどに関する。   The present invention relates to a circuit board for high-speed transmission. More specifically, the present invention relates to a connection electrode pad for a semiconductor element mounting board, a component mounting electrode pad for a circuit board, and the like.

電子機器などにおいては、回路基板と部品を接続するために基板上にパッド電極が設けられている。例えば半導体装置と回路基板を接続する方法として、ワイヤボンディングによるパッド電極接続や、半田ボールを用いたパッド電極接続方法が知られている。半田ボールを用いた実装方式として、半導体装置の底面に半田ボールを規則正しく配置し、この半田ボールを介して、半導体装置と回路基板を電気的に接続するBGA実装がある。半導体装置と半田ボールの接続及び回路基板と半田ボールの接続には電極パッドを用いることができる。   In electronic devices and the like, pad electrodes are provided on a substrate in order to connect a circuit board and components. For example, as a method of connecting a semiconductor device and a circuit board, a pad electrode connection method using wire bonding and a pad electrode connection method using solder balls are known. As a mounting method using solder balls, there is BGA mounting in which solder balls are regularly arranged on the bottom surface of a semiconductor device and the semiconductor device and a circuit board are electrically connected via the solder balls. Electrode pads can be used for connection between the semiconductor device and the solder balls and between the circuit board and the solder balls.

回路基板は、一般的に信号を伝送する配線を構成する配線層と、導電体からなるグランドプレーンと、該導電体層の間に形成された誘電体層からなる。回路基板には、回路基板外部の部品や半導体装置と電気的接続を確保するため、又は、回路基板を半導体装置搭載用基板として用いる場合にはマザーボードとの接続を確保するため、表層に電極パッドが設けられる。回路基板による信号伝送は、回路設計により、信号の伝送特性に影響を与えるため、適切な配線設計が必要になる。そして、配線設計を定めるための重要な要素の一つに、電極パッドの位置や大きさが挙げられている。
回路基板の電極パッドの上層に導電体であるグランドプレーンが存在すると、電極パッドとグランドプレーンが電磁界的に結合し、電気容量を有してしまう。このため、電極パット部の特性インピーダンスは、この回路基板の伝送線路の特性インピーダンスに比べ著しく低下する。この特性インピーダンスの低下により電極パットは、インピーダンス不連続部となる。そして、インピーダンス不連続部では、伝送線路を伝搬してきた信号が反射もしくは放射を起こし、信号のエネルギーを損失する問題を生じていた。
そこで、従来は、回路基板の電極パッド上層のグランドプレーンのうち、電極パッドに対応する領域にはクリアーと呼ばれる導電体の存在しない領域を設けていた。回路基板の配線層のうち、クリアーと重なる領域に回路を設けると、クリアー領域に対応する配線部位の特性インピーダンスが著しく低下する。このため、従来、回路基板の伝送線路の特性インピーダンスの低下を防止するため、クリアー領域には配線回路を設置できなかった(図1)。そして、電極パットの大きさは接続の位置精度を担保するため、半導体装置や回路基板の伝送線路の大きさに比べ非常に大きく、配線回路を設置できない領域も、大きな面積を占めていた。このような構造の回路基板に関する先行文献として、特許文献1を挙げる。
The circuit board is generally composed of a wiring layer constituting wiring for transmitting a signal, a ground plane made of a conductor, and a dielectric layer formed between the conductor layers. The circuit board has electrode pads on the surface layer to ensure electrical connection with components and semiconductor devices outside the circuit board, or when the circuit board is used as a semiconductor device mounting board, to ensure connection with the motherboard. Is provided. Since signal transmission by a circuit board affects signal transmission characteristics by circuit design, appropriate wiring design is required. One of the important elements for determining the wiring design is the position and size of the electrode pad.
If a ground plane, which is a conductor, is present above the electrode pads on the circuit board, the electrode pads and the ground plane are electromagnetically coupled to have an electric capacity. For this reason, the characteristic impedance of the electrode pad portion is significantly reduced as compared with the characteristic impedance of the transmission line of the circuit board. The electrode pad becomes an impedance discontinuity due to the decrease in the characteristic impedance. And in the impedance discontinuity part, the signal which propagated through the transmission line reflected or radiated | emitted, and the problem of having lost the energy of the signal had arisen.
Therefore, conventionally, in the ground plane on the upper layer of the electrode pad of the circuit board, the region corresponding to the electrode pad is provided with a region called “clear” where no conductor exists. If a circuit is provided in a region overlapping with the clear in the wiring layer of the circuit board, the characteristic impedance of the wiring portion corresponding to the clear region is significantly reduced. For this reason, conventionally, in order to prevent the characteristic impedance of the transmission line of the circuit board from being lowered, a wiring circuit cannot be installed in the clear region (FIG. 1). The size of the electrode pad is very large compared to the size of the transmission line of the semiconductor device or the circuit board in order to ensure the positional accuracy of the connection, and the area where the wiring circuit cannot be installed also occupies a large area. Patent Document 1 is given as a prior document relating to a circuit board having such a structure.

しかし、近年のICチップの高速化に伴い、回路基板の高速化・高信頼性化・高密度化が要求されるようになった。このため、特性インピーダンスを低下させずに、回路基板全体に配線設計することができる回路基板が要望されるようになった。そして、特性インピーダンスを低下させずに配線設計できる領域を広げる方策として、電極パット自体の大きさを小さくす方法が挙げられるが、電極パッドの大きさを小さくすると、これに従い回路基板の設計精度が低下する問題が発生した。
特開平7−307578号公報
However, with the recent increase in the speed of IC chips, it has become necessary to increase the speed, reliability, and density of circuit boards. For this reason, there has been a demand for a circuit board capable of designing wiring on the entire circuit board without reducing the characteristic impedance. And, as a measure to expand the area where wiring design can be done without reducing the characteristic impedance, there is a method of reducing the size of the electrode pad itself, but if the size of the electrode pad is reduced, the design accuracy of the circuit board will be increased accordingly. There was a problem that decreased.
Japanese Patent Laid-Open No. 7-307578

本発明は、上記の問題を解決するためになされるものであり、特性インピーダンスを低下させることなく、高密度配線設計の可能で、高速伝送特性を有する設計精度の高い回路基板を提供することにある。   The present invention has been made to solve the above-mentioned problems, and provides a circuit board with high design accuracy and high-speed transmission characteristics, capable of high-density wiring design without reducing characteristic impedance. is there.

ところで、本発明者の検討によれば、回路基板の電極パッドのうち導電体の面積が一定以下になるよう導電体を配置し、該電極パッドのうち導電体を設けない領域に誘電体を導入して、電極パッドにおける導電体の占める面積割合を減少させたところ、電極パッドと電極パッドの上層のグランドプレーンの電磁界的な結合が減衰し、クリアーを設けなくとも特性インピーダンスの低下が抑えられることを見出した。そして、このため、クリアーのため従来配線を設計できなかった領域においても、回路基板の配線設計が可能となることを見出した。   By the way, according to the study of the present inventor, the conductor is arranged so that the area of the conductor is less than a certain value among the electrode pads of the circuit board, and the dielectric is introduced into a region of the electrode pad where no conductor is provided. When the area ratio of the conductor in the electrode pad is reduced, the electromagnetic coupling between the electrode pad and the ground plane above the electrode pad is attenuated, and the characteristic impedance can be prevented from lowering without providing a clear. I found out. For this reason, it has been found that the wiring design of the circuit board can be performed even in a region where the conventional wiring cannot be designed due to clearness.

本発明はこのような知見に基づいてなされたもので、請求項1に記載の発明は、少なくとも配線層、グランドプレーン層、誘電体層、電極パッドを含む回路基板において、前記電極パッドが少なくとも導電体と誘電体を含み、前記電極パッドの接続面積のうち、導電体の占める割合が10%〜95%であることを特徴とする回路基板である。   The present invention has been made based on such knowledge. The invention according to claim 1 is a circuit board including at least a wiring layer, a ground plane layer, a dielectric layer, and an electrode pad, wherein the electrode pad is at least conductive. The circuit board includes a body and a dielectric, and the proportion of the conductor in the connection area of the electrode pad is 10% to 95%.

請求項2に記載の発明は、前記電極パッドが、少なくとも複数の同心円のリング形状を有する導電体を含んでなることを特徴とする請求項1に記載の回路基板である。   The invention according to claim 2 is the circuit board according to claim 1, wherein the electrode pad includes a conductor having at least a plurality of concentric ring shapes.

請求項3に記載の発明は、前記電極パッドが、少なくともコイル形状を有する導電体を含んでなることを特徴とする請求項1に記載の回路基板である。   The invention according to claim 3 is the circuit board according to claim 1, wherein the electrode pad includes a conductor having at least a coil shape.

請求項4に記載の発明は、前記電極パッドの導電体の間隙に誘電体が充填されていることを特徴とする請求項1〜3のいずれかに記載の回路基板である。   A fourth aspect of the present invention is the circuit board according to any one of the first to third aspects, wherein a dielectric is filled in a gap between the conductors of the electrode pad.

請求項5に記載の発明は、請求項1〜4のいずれかに記載の回路基板を用いることを特徴とする半導体パッケージである。   A fifth aspect of the present invention is a semiconductor package using the circuit board according to any one of the first to fourth aspects.

本発明によると、電極パッドを有する回路基板のクリアーが不要となったため、配線設計可能な領域が増え、配線自由度が大幅に向上した。このため、従来よりも、高密度配線を有する回路基板を設計できるようになった。また、電極パッド全体の大きさを小さくするものでもないため、回路基板の設計精度を低下させるものでもない。   According to the present invention, since it is not necessary to clear the circuit board having the electrode pads, the area where wiring design is possible increases, and the degree of freedom of wiring is greatly improved. For this reason, it has become possible to design a circuit board having high-density wiring as compared with the prior art. Further, since the size of the entire electrode pad is not reduced, the design accuracy of the circuit board is not lowered.

さらに、本発明では、電極パッドにコイル形状を有する導電体を用いたところ、導電体がコイルとして機能した。このため、電極パッドに対応する領域上に設けられた配線の信号伝送特性の信頼性を向上させることができた。   Furthermore, in this invention, when the conductor which has a coil shape was used for the electrode pad, the conductor functioned as a coil. For this reason, it was possible to improve the reliability of the signal transmission characteristics of the wiring provided on the region corresponding to the electrode pad.

以下に本発明の詳細な実施の形態を説明する。   Detailed embodiments of the present invention will be described below.

図2は、本発明の回路基板の電極パッド部の断面図である。図2に示すように、回路基板は、誘電体層とグランドプレーン層と配線層を積層して公知の方法で形成される。ただし、本発明ではグランドプレーンにはクリアーを設ける必要はない。また電極パッドは、誘電体と導電体により形成される。電極パッドは導電体と誘電体を含み、電極パッドの面積のうち、導電体の占める割合が30%〜99%であることを特徴とする。99%以上であると、電極パッドとグランドプレーンがキャパシタンスとして機能するため好ましくない。30%以下であると、本発明の効果を得られないため、好ましくない。電極パッドの導電体の形状について図3〜5を用いてさらに詳細に説明する。電極パッドの導電体の形状は、電気的接続が確保される限り、特に限定されるものではないが、例えば円形の電極パッドにおいては、同心円のリング形状(図3、図4)、渦巻形状(図5)などを挙げることができる。四角形等、他の形状の電極パッドにおいても、上記円形の電極パッドと同様の形状とすることができる。電極パッドは、電気的接続が可能な径を維持する。例えば、半田ボール接続を用いて半導体装置と回路基板を接続する場合、図3に示すように、半導体装置の電極パットと、これを実装する回路基板の電極パッドが、半田ボールで現状の実装が可能な径を維持しつつ、リング状に導電体を配置する。   FIG. 2 is a cross-sectional view of the electrode pad portion of the circuit board of the present invention. As shown in FIG. 2, the circuit board is formed by a known method by laminating a dielectric layer, a ground plane layer, and a wiring layer. However, in the present invention, it is not necessary to provide a clear on the ground plane. The electrode pad is formed of a dielectric and a conductor. The electrode pad includes a conductor and a dielectric, and the proportion of the conductor in the area of the electrode pad is 30% to 99%. If it is 99% or more, the electrode pad and the ground plane function as capacitance, which is not preferable. If it is 30% or less, the effect of the present invention cannot be obtained, which is not preferable. The shape of the conductor of the electrode pad will be described in more detail with reference to FIGS. The shape of the electrode pad conductor is not particularly limited as long as electrical connection is ensured. For example, in the case of a circular electrode pad, a concentric ring shape (FIGS. 3 and 4), a spiral shape ( Fig. 5). Also in electrode pads having other shapes such as a quadrangle, the same shape as that of the circular electrode pad can be obtained. The electrode pad maintains a diameter that allows electrical connection. For example, when a semiconductor device and a circuit board are connected using solder ball connection, as shown in FIG. 3, the electrode pad of the semiconductor device and the electrode pad of the circuit board on which the semiconductor device is mounted are solder balls. The conductor is arranged in a ring shape while maintaining a possible diameter.

本発明の回路基板の電極パッドは、例えば、半田ボール接続を用いて半導体装置と回路基板を接続する場合、図3に示すように、半導体装置の電極パットと、これを実装する回路基板の電極パッドが、半田ボールで現状の実装が可能な径を維持しつつ、リング状に導電体を配置することで構成される。この際、リング状の中心は、製造ルールに基づき、回路基板のビアランド径と同等以上の径にしておくのが望ましい。また導電体が存在しない領域(以下、クリアランスとする。)において、リング状の導電体の線幅と、外径リングと内径リングに存在するクリアランス幅の比は、1:1〜1:5となることが好ましい。クリアランス幅が、この範囲よりも狭いと半田ボールパットのベタパターンとの結合によるキャパシタンス増加が現れ、特性インピーダンスの低下が引き起こされる問題が生じる。また、逆にクリアランス幅が、この範囲より大きいと、接触不良の問題等が発生する。また、クリアランスには、誘電体を充填することが好ましい。クリアランスに何も充填せずに半田ボールを付けると、半田ボールとICチップパッケージの間に空気が入り、不良の原因となる可能性がある。誘電体に用いることができる材料として、比誘電率が5.0以下の材料を用いることが好ましい。誘電体として用いることができる材料として、ソルダーレジストに用いる樹脂などを挙げることができる。比誘電率がこの値よりも高い誘電体を充填してしまうと、キャパシタンスの増加につながる。   For example, when the semiconductor device and the circuit board are connected by using solder ball connection, the electrode pad of the circuit board of the present invention includes an electrode pad of the semiconductor device and an electrode of the circuit board on which the semiconductor device is mounted as shown in FIG. The pad is configured by arranging conductors in a ring shape while maintaining a diameter that allows the current mounting with solder balls. At this time, it is desirable that the ring-shaped center has a diameter equal to or larger than the via land diameter of the circuit board based on the manufacturing rule. In a region where no conductor is present (hereinafter referred to as clearance), the ratio of the line width of the ring-shaped conductor to the clearance width present in the outer diameter ring and the inner diameter ring is 1: 1 to 1: 5. It is preferable to become. If the clearance width is narrower than this range, the capacitance increases due to the coupling with the solid pattern of the solder ball pad, which causes a problem that the characteristic impedance is lowered. On the other hand, if the clearance width is larger than this range, a problem of poor contact or the like occurs. The clearance is preferably filled with a dielectric. If a solder ball is attached without filling the clearance, air may enter between the solder ball and the IC chip package, which may cause defects. As a material that can be used for the dielectric, a material having a relative dielectric constant of 5.0 or less is preferably used. Examples of a material that can be used as a dielectric include a resin used for a solder resist. If a dielectric having a relative dielectric constant higher than this value is filled, the capacitance increases.

また、電極パッドの導電体の形状を上記のような複数の同心円からなるリング状とし、該電極パットと、回路基板の伝送線路が同一層内にあり、さらに電極パットの外円の導電対と該伝送線路が接続している場合は、外円の導電体と内円の導電体が直接電気的に導通することが好ましい。外円の導電体と内円の導電体が直接電気的に導通していないと、半田ボールの接続精度が悪い場合、内円の導電体のみが半田ボールと接続し、この結果、半導体装置と回路基板が適切に接続されない問題が発生する可能性がある。外円の導電体と内円の導電体が直接電気的に導通するために、例えば、電極パッドの導電体のうち、外円と内円に、電気的接続をするラインを形勢することが望ましい。また、電極パッドの導電体の形状をコイル状又は渦巻き状にすると、キャパシタンスを低減しつつ、インダクタンスを増加させることができた。   In addition, the shape of the conductor of the electrode pad is a ring shape composed of a plurality of concentric circles as described above, the electrode pad and the transmission line of the circuit board are in the same layer, and the conductive pair of the outer circle of the electrode pad When the transmission line is connected, it is preferable that the outer circle conductor and the inner circle conductor are directly electrically connected. If the outer circle conductor and the inner circle conductor are not directly electrically connected, if the solder ball connection accuracy is poor, only the inner circle conductor is connected to the solder ball. There is a possibility that the circuit board is not properly connected. Since the outer circle conductor and the inner circle conductor are directly electrically connected, for example, it is desirable to form a line for electrical connection between the outer circle and the inner circle of the electrode pad conductors. . Moreover, when the shape of the conductor of the electrode pad was coiled or spiral, the inductance could be increased while the capacitance was reduced.

:従来の回路基板の断面図: Cross-sectional view of a conventional circuit board :本発明の回路基板の断面図: Cross-sectional view of the circuit board of the present invention :本発明の回路基板の平面図: Plan view of the circuit board of the present invention :本発明の回路基板の平面図: Plan view of the circuit board of the present invention :本発明の回路基板の平面図: Plan view of the circuit board of the present invention

符号の説明Explanation of symbols

1 電極パッド
2 クリアー
3 グランドプレーン
4 配線
5 誘電体層
7 誘電体
8 導電体
1 Electrode Pad 2 Clear 3 Ground Plane 4 Wiring 5 Dielectric Layer 7 Dielectric 8 Conductor

Claims (5)

少なくとも配線層、グランドプレーン層、誘電体層、電極パッドを含む回路基板において、
前記電極パッドが少なくとも導電体と誘電体を含み、前記電極パッドの接続面積のうち、導電体の占める割合が30%〜99%であることを特徴とする回路基板。
In a circuit board including at least a wiring layer, a ground plane layer, a dielectric layer, and an electrode pad,
The circuit board, wherein the electrode pad includes at least a conductor and a dielectric, and a proportion of the conductor in a connection area of the electrode pad is 30% to 99%.
前記電極パッドが、少なくとも複数の同心円のリング形状を有する導電体を含んでなることを特徴とする請求項1に記載の回路基板。   The circuit board according to claim 1, wherein the electrode pad includes a conductor having at least a plurality of concentric ring shapes. 前記電極パッドが、少なくともコイル形状を有する導電体を含んでなることを特徴とする請求項1に記載の回路基板。   The circuit board according to claim 1, wherein the electrode pad includes a conductor having at least a coil shape. 前記電極パッドの導電体の間隙に誘電体が充填されていることを特徴とする請求項1〜3のいずれかに記載の回路基板。   The circuit board according to claim 1, wherein a dielectric is filled in a gap between conductors of the electrode pad. 請求項1〜4のいずれかに記載の回路基板を用いることを特徴とする半導体パッケージ。   A semiconductor package using the circuit board according to claim 1.
JP2005165172A 2005-06-06 2005-06-06 Circuit board and semiconductor package employing the same Pending JP2006339563A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015103745A (en) * 2013-11-27 2015-06-04 京セラ株式会社 Wiring board
US9754830B2 (en) 2012-07-20 2017-09-05 Fujitsu Limited Wiring substrate, method for manufacturing wiring substrate, electronic device and method for manufacturing electronic device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9754830B2 (en) 2012-07-20 2017-09-05 Fujitsu Limited Wiring substrate, method for manufacturing wiring substrate, electronic device and method for manufacturing electronic device
JP2015103745A (en) * 2013-11-27 2015-06-04 京セラ株式会社 Wiring board

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