JP2009511904A - Ultrasonic fault detection system using analog-digital conversion system with wide dynamic range - Google Patents

Abstract

  A method and apparatus for performing ultrasonic testing of an object processes echo signals received on at least three signal channels from the object under test. The echo signal is applied to individual channels to extend the dynamic range of the associated A / D converter system in a way that eliminates the use of multiple analog high and low pass filters and variable gain amplifiers. Scaled to different degrees along. Thus, complexity is reduced and performance limits are avoided. The digital-to-analog converter samples the differently scaled input signal, and the selection circuit produces the output of the digital output obtained from the analog-to-digital converter with the highest gain and no overflow. Selected. The digital outputs are combined seamlessly to produce an output that can be displayed as a scanned display indicating the location of the fault.

Description

  This application is filed on 14 October 2005, named “ULTRASONIC FAULT DETECTION SYSTEM USING A HIGH DYNAMIC RANGE ANALOG TO DIGITAL CONVERSION SYSTEM”, the entire disclosure of which is incorporated herein by reference. U.S. Provisional Patent Application No. 60 / 726,798, U.S. Provisional Patent Application No. 60 / 726,776, filed October 14, 2005, entitled `` ULTRASONIC DETECTION MEASUREMENT SYSTEM USING A TUNABLE DIGITAL FILTER WITH 4X INTERPOLATOR '', and 2005 It claims the benefit and priority of US Provisional Patent Application No. 60 / 726,575, filed Oct. 14, entitled “DIGITAL TIME VARIABLE AMPLIFIER FOR NON-DETRUCTIVE TEST INSTRUMENT”.

  The present invention generally employs an ultrasonic inspection utilized to detect internal structural failures of critical structures such as airline wings, such as cracks, discontinuities, corrosion changes or thickness changes in an object or material. About the system. The detection of the internal structural failure is performed by transmitting an ultrasonic pulse to the target object and analyzing an echo signal detected from the target object. More particularly, the present invention relates to a wide dynamic range analog-to-digital conversion system and method that can be used in such an ultrasound inspection system, and more particularly, with these analog-to-digital conversion system and method. The object is scanned using a sonic probe or transducer. The present invention also relates to an eddy current inspection system used to detect internal structural faults.

  The prior art of ultrasonic flaw detectors has been demonstrated by products such as the Epoch 4 Plus product of the assignee of the present invention. Competing products available from General Electric are known as USM 35X flaw detection system, USN 58L flaw detection system and USN 60 flaw detection system. Prior art ultrasonic flaw detectors typically utilize extremely complex analog front ends, but these analog front ends contain many components and are calibrated for specific applications and settings. Poses particularly difficult problems in terms of reliability, setup time, results consistency and optimization.

  A typical ultrasonic flaw detector according to the prior art includes a gain calibrator, which is placed opposite the object to be tested, operates in many different frequency bands and requires careful calibration and maintenance. Converters are included that operate with many analog circuits, such as preamplifiers and attenuators, variable gain amplifiers, high pass analog filters, and low pass analog filters.

  Thus, current flaw detectors pose many problems for designers and users of such devices, and their complexity has a strong impact on their troubleshooting and repair. These problems include problems such as matching input impedances that vary with different gain amplifiers that are switched in and out of the signal path as seen by the converter. This adversely affects the frequency response and causes various gain nonlinearities. Since analog circuitry is switched in and out of the signal path, it poses a calibration problem.

  Another problem with existing flaw detectors is due to their back wall damping performance, which has a strong impact on the ability to detect flaws located very close to the back wall of the object under test. Is exerting. This problem raises the problem of time-varying gain functions, among others, and limits the gain range and gain change rate of prior art devices.

  Another disadvantage of the prior art is that it is null to maintain the input signal at the midpoint of such analog-to-digital converters in order to utilize the analog-to-digital converters utilized at maximum full amplitude scale. This is due to the analog circuit coupling method in which individual operational amplifiers are placed in signal paths with different DC offset errors that must be made. Also, the DC offset error causes the waveform appearing on the display to be off-center on the waveform portion of the screen in the vertical direction, which desirably causes anomalies in the waveform that the operator analyzes to determine the test results. Sometimes. Therefore, the error nulling process in the prior art has a low DC base line measurement accuracy due to noise, and is particularly unreliable at a large gain.

  The passionate analog implementation of the existing flaw detector front end poses additional problems due to the need to utilize the entire instrument dynamic range, resulting in various gain linearity calibration problems. ing.

US Pat. No. 5,671,154 describes a prior art ultrasonic inspection apparatus providing background information for the apparatus and method according to the present invention.
US Provisional Patent Application No. 60 / 726,798 US Provisional Patent Application No. 60 / 726,776 US Provisional Patent Application No. 60 / 726,575 U.S. Patent No. 5,671,154 U.S. Pat.No. 4,497,210 U.S. Patent No. 6,789,427

  An object of the present invention is generally to provide an apparatus and method for ultrasonic inspection of an object that avoids or improves the disadvantages of the prior art referred to above.

  Another object of the present invention is to provide an ultrasonic inspection apparatus and method implemented with a simpler circuit.

  Another object of the present invention is to provide a simpler ultrasonic inspection apparatus and method that requires a shorter calibration and adjustment process prior to use.

  Still another object of the invention is to provide an ultrasonic inspection apparatus and method that provides an electronic inspection apparatus and method that delivers consistent inspection results that are more accurate and easier to read.

  These and other objects of the present invention extend the dynamic range of A / D converter circuits and eliminate the need for variable gain amplifier (VGA) circuits and the associated complexity and performance limitations. Implemented by the method and apparatus.

  In accordance with one aspect of the present invention, an apparatus and method according to the present invention comprises a plurality of channels coupled to receive a single analog input signal, the means for converting the analog input signal to a digital signal. It is embodied as a multiplex A / D circuit having a plurality of individual channels.

  Another aspect of the invention compensates for any timing skew source, including propagation delays of individual preamplifiers, and eliminates any other skew source that has been revealed by examination of A / D converter output data. Means for adjusting individual sample times to compensate and prevent saturation of individual channel preamplifier input stages to prevent signal distortions from affecting inputs to other channels Means for adjusting the frequency response of individual channels to be substantially matched, and means for adjusting the overall frequency response of the device, and one of the plurality of channels having greater gain Or means for detecting a plurality of channel overflow conditions and means for combining the plurality of channels into a continuous output stream.

  In accordance with another aspect of the present invention, a multi-channel converter circuit according to the present invention is by injecting a DC signal from a D / A converter at various points in the analog signal path to nullify offset errors. Means are provided for removing signal offset errors for individual channels.

  According to another aspect of the invention, the means for combining a plurality of channels can be operated as a function of the result generated by the channel overflow condition detection means. Also, the means for combining the plurality of channels may be operated to output the result of the channel having the smaller gain if a channel overflow condition is detected for any of the channels having the larger gain. it can.

  In accordance with another aspect of the invention, means for substantially matching the frequency response of individual analog channels are provided to minimize amplitude matching errors between channels, particularly at high frequencies. .

  According to another aspect of the invention, each of the A / D converter circuits comprises means for changing the reference voltage to adjust the full scale range using the D / A converter. This is used to optimize signal amplitude matching.

  According to another aspect of the invention, the multiple A / D converter circuit according to the invention comprises means for matching the results of individual channels having different gains.

  According to another aspect of the invention, the multiple A / D circuit according to the invention further comprises means for timing the placement of the rising edge of one channel's sample clock relative to the clock circuit portion of the other channel. Therefore, by adjusting the sample time of the individual channels, the propagation delay of the individual preamplifier channels is compensated, and any other sources of skew revealed by examination of the A / D converter output data. Is compensated.

  According to another aspect of the present invention, the channel overflow condition detection means is provided so that all the amplifiers in the signal path from the first amplifier to the amplifier inside the A / D converter return to their linear operating region. In order to ensure that the appropriate time is satisfied, a means for extending the time duration of the overflow signal output from the A / D converter is further provided.

  According to yet another aspect of the invention, the means for combining the plurality of channels further includes one or more having a smaller gain to match the result of the one or more channels having the larger gain. Means are provided for adjusting the resulting data bit positions of the plurality of channels, eg, means for scaling. This can be accomplished by shifting the bits using, for example, a shift register, multiplexer, etc., or can be accomplished by any means.

  According to yet another aspect of the invention, for example, the input signal is divided into a larger signal channel and a smaller signal channel, and the smaller signal channel has a higher resolution than the larger signal channel. Scales on larger and smaller signal channels, uses separate A / D converters to sample larger and smaller signal channels, and allows larger signal channels Outputting a result of one of the larger signal channel and the smaller signal channel as a factor for determining whether or not the analog signal is converted to a digital signal. .

  The method according to the present invention further includes the steps of combining the result of the larger signal channel and the result of the smaller signal channel into a combined result, and outputting the combined result.

  Other features and advantages of the present invention will become apparent from the following description of the invention which refers to the accompanying drawings.

  First, referring to FIGS. 1 and 2, the general environment of the present invention and background information for various problems solved by the present invention will be described.

  In FIG. 1, the ultrasonic transmission / reception unit 10 transmits an electric pulse signal 10a to the probe or transducer 12 at a predetermined cycle. The probe or transducer 12 is coupled to a target object 14, such as a steel material, either directly or via a delay material, such as water or quartz. As shown in FIG. 2, the probe 12 converts the trigger pulse signal 12a into an ultrasonic pulse 10a and transmits it through the target object 14. The ultrasonic pulse 10 a applied to the target object 14 is subsequently reflected by the bottom surface 14 a of the target object 14 and received by the probe 12. The probe 12 converts the reflected wave into an electric signal. This electrical signal is supplied to the ultrasonic transmission / reception unit 10 as an electrical echo signal 10b. The ultrasonic transmission / reception unit 10 amplifies the electrical signal 10 b and transmits the amplified signal 11 as an echo signal 11 to the signal processing device 16. As used herein, the term probe or transducer includes embodiments where the transducer is implemented using one or more completely different transmitters and one or more receivers. It is.

  The echo signal 11 includes a bottom surface echo 11a corresponding to a wave reflected by the bottom surface 14a, and a wound echo 11b caused by a wound 14b in the object 14. The frequency of the ultrasonic echo pulse 11 is determined mainly by the thickness of the ultrasonic vibrator incorporated in the probe 12 or other characteristics. The frequency of the ultrasonic pulse 10a used for the inspection is set to several tens kHz to several tens MHz. Therefore, the frequency range of the signal waveforms of the bottom surface echo 11a and the flaw echo 11b included in the echo signal 11 covers a wide range from about 50 KHz to several tens of MHz.

  The signal processing device 16 performs various signal processing of the echo signal 11 received from the ultrasonic transmission / reception unit 10, and the signal processing device 16 outputs an output result indicating presence / absence of one or more scratches. In some cases, the thickness of the target object 14 is displayed on the display unit 18. In order to perform signal processing on the echo signal 11 and display the echo signal, a trigger signal S synchronized with the pulse signal 10a is supplied from the ultrasonic transmission / reception unit 10 to the signal processing device 16.

  In the case of the scratch inspection apparatus having the structure described above, the echo signal 11 output from the ultrasonic transmission / reception unit 10 includes a certain amount of noise in addition to the bottom surface echo 11a and the scratch echo 11b. When the amount of noise included in the ultrasonic pulse 11 is large, the reliability of the inspection result is significantly lowered. Noise is roughly classified into electrical noise and material noise.

  Electrical noise includes external noise caused by mixing electromagnetic waves or electrostatic waves into the probe 12, the ultrasonic transmission / reception unit 10, connection cables such as the cable 13, and one or more amplifiers and the ultrasonic transmission / reception unit 10. Contains internal noise generated by one or more embedded amplifiers.

  Reduction of noise contained in the echo signal 11 is extremely important in order to perform ultrasonic inspection with high accuracy. Conventionally, an analog filter is used to suppress a noise component included in the echo signal 11. For example, a BPF (Band Pass Filter) is used to pass the frequency component of an ultrasonic echo against electrical noise having a wide range of frequency components. Further, LPF (low-pass filter) or BPF is used for the material noise, and it can be seen that the frequency distribution of the flaw echo 11b (FIG. 2) is lower than the frequency distribution of the echo generated by signal scattering. According to this method in which the analog filter is used, it is possible to suppress the noise component included in the echo signal 11b to a level equal to or lower than a predetermined level.

  It is widely known that the frequency distribution of the wound echo signal changes based on the ultrasonic attenuation characteristics of the target object 14. Therefore, when BPF is used due to material noise indicated by scattered echoes or the like, it is desirable to use a filter having an optimum characteristic according to the target object 14. However, since the pass frequency characteristics of the analog filter cannot be easily changed, more filters with different pass frequency characteristics corresponding to different ultrasonic attenuation characteristics of the various materials associated with the target object 14 must be prepared. I must. This method, where different filters are used depending on the material properties of the target object 14, presents practical difficulties, considering the operational or economic advantages versus the cost and complexity of the total system. Yes.

  The flaw echo 11b may be present very close to the front surface 14c of the target object 14 in some cases, in which case the flaw echo 11b will be located near the trailing edge of the transmitted pulse 10a. . Therefore, in order not to disturb the returning wound echo 11b, the end of the trailing edge of the transmission pulse 10a (enlarged as the trailing edge 10at in FIG. 3) should be set to the zero baseline 10ab as quickly as possible. Is desirable. The settling time 7a to the zero baseline is a determinant of the near surface resolution of the flaw detector.

  Considering that the gain of the ultrasonic transmission / reception unit 10 can be adjusted up to 110 dB (as required by the European standard EN 12668-1), the baseline error before the gain amplification stage in the ultrasonic transmission / reception unit 10 is very small. Even if it is a quantity, if the gain level is set too high, it causes a large error in the output section of the gain amplification stage.

The resulting baseline error in the input to signal processing device 16 is
(a) The maximum vertical displacement of the signal on the screen is reduced by the amount of baseline offset, which reduces the sensitivity of the device that detects the flaw echo, which may cause the dynamic range to narrow, or
(b) If the amplitude is sufficiently large, either one or more of the gain amplification stages will saturate, thereby causing the echo signal detection to be completely disturbed.

  Conventionally, the baseline error problem described above has been addressed in one of two ways. According to the first method, HPF is used for the signal path of the input of the ultrasonic transmission / reception unit 10 in order to filter out the low frequency part of the trailing edge 10at of the transmission pulse 10a. The trailing edge 10at of the transmission pulse 10a can be improved by HPF as indicated by the approximate dotted line 7c.

  However, the effectiveness of HPF solutions is limited in several ways. First, in order to minimize the low frequency part of the trailing edge 10at of the transmission pulse 10a, the cutoff frequency (f HPF-3dB) of the HPF must be made as high as possible. For example, if the excitation frequency of probe 12 is 10 MHz and f HPF-3dB is 5 MHz, undesirable effects on the receiver baseline are significantly suppressed.

  Unfortunately, using a low frequency of 500 kHz for the excitation frequency of the probe 12 is not common because it requires f HPF-3dB to be less than 500 kHz. This HPF solution is significantly less effective in this frequency range because an undesirable amount of low frequency portion of the trailing edge 10at of the transmit pulse 10a is allowed to pass through the HPF, causing baseline errors.

  Second, to prevent damage to the amplifier circuit, the maximum amplitude of the transmitted pulse applied to the first amplifier stage (not shown) of the ultrasonic transceiver unit 10 is limited to a few volts (clamped). ing). It is very common to operate the ultrasound transceiver unit 10 at a gain level that will saturate the amplifier each time a pulse is applied. If the filter is not critically damped, the response of the filter after saturation will cause the trailing edge of the transmit pulse 10a to be worse than if the filter is not applied. Although it is possible to have a large number of filters tuned to ensure critical braking in individual manufactured equipment, there are practical difficulties when considering the manufacturability of the filter components and temperature variations.

  It should also be noted that once the amplifier is saturated, it takes a considerable amount of time for the amplifier to return to the linear operating region. This causes the time required for the trailing edge of the transmit pulse 10a to return to zero baseline is longer than if the amplifier input signal is kept below the saturation level (i.e. within the linear operating range). Yes.

  An alternative method that has been used to address the baseline error problem is to couple the clamped transmit pulse 10a directly to the input of the ultrasound transmit / receive unit 10. This method avoids one of the problems described above because no HPF filter or BPF filter is used.

  The effectiveness of the direct binding solution is limited in two ways. First, this direct coupling solution does nothing to reduce the low frequency portion of the trailing edge 10at of the transmit pulse 10a. Second, the DC component of the baseline error and offset error of the amplifier of the ultrasonic transmission / reception unit 10 is amplified through the signal path. This in some cases is responsible for various dynamic range and saturation problems that are further described below.

  Traditionally, flaw detectors have provisions that allow the user to operate the instrument using filters or via direct coupling to select the optimal settings for the wound measurement scenario.

  Next, detection of a flaw near the back surface of the object 14 will be described with reference to FIG. The scratch 14d may be present very close to the back surface 14a of the target object 14 in some cases, and in that case, the scratch echo 11b is located in the vicinity of the back wall echo 11a. In order to perform proper inspection (according to many formal inspection procedures), the peak of the back wall echo 11a must remain observable on the waveform display 18 at all times. It is not as large as 1) can be observed on the corrugated display 18 due to micro-scratches 2d in the target object 14 caused by porous or material contaminants, but in some cases towards the back wall 14a A flaw echo is generated that reduces the amplitude of the moving echo, which can reduce the amplitude of the flaw echo 11b and the back wall echo 11a, and 2) the probe 12 is intermittently on the surface 14c of the target object 14 This is because the amplitude of the back wall echo 11a may be reduced. These two conditions cause the inability to observe the echo of the wound 14d on the waveform display 18 in some cases. However, the reduction in back wall echo 11a may indicate a problem associated with the material of the target object 14 or the coupling of the probe 12. If the peak of the back wall echo 11a is allowed to exceed the top observable portion of the waveform display 18, the peak amplitude reduction may not be observable on the waveform display 18. The test performer sets up the detection parameters for the back wall echo 11a by adjusting the back wall echo gate 6d (see Figure 4) and setting the area on the horizontal time axis where the back wall echo 11a is allowed. Yes. The threshold for the vertical amplitude axis is set for the minimum allowable echo amplitude. Usually, an alarm is generated when the back wall echo 11a deviates from these parameters.

  This measurement method poses certain problems.

  The difference in echo amplitude between the wound echo 11b and the back wall echo 11a can be increased as much as possible (maximum several digits). However, using several methods (a, b, c and d) described below, both the wound echo 11b and the back wall echo 11a peaks can be reliably observed on the waveform display 18. Can be maintained.

  (a) Connect the probe 12 to the two parallel receiver and A / D converter channels (A and B). The gain of channel A is adjusted by the tester to optimize the amplitude of the wound 14d echo so that it can be clearly observed on the waveform display 18. The gain of channel B is adjusted to maintain a state in which the peak of the back wall echo 11a can be reliably observed on the waveform display 18 for the reason described above.

  The digital outputs of the A / D converters of channels A and B are combined in such a way that the entire horizontal time scale of the waveform display 18 shows all the outputs of channel A, except for the area of its back wall echo gate 6d. The leftmost side of the back wall echo gate 6d represents a time point at which the channel A is switched to the channel B.

  Unfortunately, this two-channel method has drawbacks. Since the presence or position of the flaw in the target object is unknown until the flaw is detected, the inspection is usually performed by moving the probe 12 along the surface of the target object 14 during the scanning motion Is done. If the thickness between the front surface 14c and the back surface 14a of the target object in the scanning area is not constant, this thickness change is only included to avoid losing the detection of the back wall echo 11a. Therefore, it is necessary to adjust the back wall echo gate 6d to a sufficient size.

  Therefore, the back wall flaw echo 11b is generated in the region of the back wall echo gate 6d. Therefore, when the near back wall flaw echo 11b is very close to the back surface 14a, the near back wall flaw echo 11b is detected. It will not be possible. This is responsible for the undesirable effect on near surface resolution by the back surface 14a. Also, the amount of receiver hardware is approximately twice that required for a single channel solution.

  (b) The concept of the two continuous pulse reception measurement cycle method is the same as the concept of the two parallel receiver and A / D converter channel method except that only one channel is required. The description in section (a) above also applies to this two-continuous pulse reception measurement cycle scheme. Also, instead of processing the flaw echo 11b and the back wall echo 11a in two parallel channels set to different gains, the echo is processed in the same channel with a different gain for each pulse reception cycle.

  A disadvantage inherent to this continuous pulse reception measurement cycle scheme is that the wound echo 11b is time separated from the back wall echo 11a by an additional pulse interval To (shown in FIG. 2). Therefore, when the probe 12 moves, the position of the probe 12 may change between the time when the wound echo 11b is measured and the time when the back wall echo 11a is measured, which may cause a measurement error. taller than.

  (c) The time-varying gain (TVG) dynamically changes the gain of the amplifier of the ultrasonic transmission / reception unit 10 in order to optimize the amplitudes of the wound echo 11b and the back wall echo 11a (for the reason already explained) It is a single channel solution.

  This TVG system also has the same disadvantages as the near surface resolution due to the back surface 14a, as in the case of the two parallel receiver and A / D converter channel system.

  However, this TVG system has other drawbacks. Accordingly, FIG. 5 shows an ideal TVG curve 6e that changes instantaneously from gain 6f to gain 6h, so that no additional near surface resolution error from the analog TVG amplifier is introduced. As explained in the above method, the errors associated with measuring flaws near the back wall of the target object that are not of constant thickness remain.

  Unfortunately, with an analog TVG amplifier, it is impossible to achieve the ideal curve 6e (especially it is impossible to achieve the instantaneous slope 6g). Analog TVG amplifiers and the external signals that control them have a response time that limits the gain change rate 6g, which causes undesirable effects on the near surface resolution by the back surface 14a. In order to provide a time interval of 6 m for the gain to change, the flaw 14d must be further away from the back surface 14c of the target object 14, resulting in poor near surface resolution. The wound echo 11b referred to in the form of an important echo must occur prior to the start of the time interval 6m, and the back wall echo 11a must not occur before the end of the time interval 6m.

  Another problem that the TVG system has is due to various sources of DC offset error in the receiver section of the ultrasound transceiver unit 10. The error source includes the DC component of the input DC offset error and the baseline error of the amplifier IC.

  DC offset errors present in certain existing flaw detectors by the assignee of the present invention are compensated with individual gain settings each time the gain is adjusted from one level to the next. The DC offset error is compensated in this way to account for temperature effects, long-term stability, DC offset error variations, and the like. This compensation method uses a receiver to inject a DC null signal that reliably maintains the baseline at the center of the full-scale range of the A / D converter and that is reliably maintained at the optimal position on the waveform display 18. A plurality of D / A converters are used along the signal path. Every time the instrument is turned on or the gain setting is changed, the microprocessor has an algorithm that takes a baseline error reading, calculates the necessary DC error correction, and sets the DAC to that value. Run inside.

  It is not practical to execute the DC offset compensation method described above at a speed necessary for operating the TVG for each gain setting. Instead, a DC offset correction value for the intermediate gain is set, thereby dividing the error between the endpoints. For example, if the TVG range is set to operate between 20 dB and 60 dB, the DC offset correction value is set to 40 dB to compensate for the error. The problem with this technique is that an error is introduced into the echo amplitude that is not desirable to accurately detect and size the flaw.

  (d) A logarithmic amplifier is used to cover the infinite dynamic range required and echoes are displayed on the waveform display 18 on a logarithmic scale. This logarithmic scale provides a very wide dynamic range so that both low amplitude wound echoes and back wall echo peaks of much higher amplitude can be observed on the waveform display.

  Unfortunately, the use of this logarithmic method has certain undesirable consequences. Therefore, for a given back wall echo amplitude and amplitude change, the vertical change in the peak of the echo waveform is almost observable on the waveform display compared to the receiver using a linear amplifier. Can not. In some cases, this makes it more difficult to detect a scratch by observing the change in the peak amplitude of the back wall echo described above.

  Furthermore, the logarithmic amplifier output can only provide a rectified waveform. Therefore, the position of the negative echo lobe cannot be identified because it is removed by half-wave rectification or converted to a positive lobe by full-wave rectification. Since one lobe can be observed more easily than the other lobes, the exact location of both the positive and negative echo lobes is extremely important for accurately measuring the thickness of the target object 14. Also, the polarity of the echo lobe is required to determine that the echo phase has been reversed. When sound waves pass from a material with low acoustic impedance to a material with high acoustic impedance, phase inversion of the ultrasonic echo occurs.

  Furthermore, since a linear signal is required for the filter to operate properly (the logarithmic amplifier is a non-linear device), all filters must be placed before the logarithmic amplifier section. If a filter circuit is placed in front of the high gain logarithmic amplifier section, the PCB traces required to connect the filter components together are susceptible to the effects of electromagnetic noise and internal noise generated by the filter. The receiver will have a much higher noise sensitivity and the amplifier will be amplified to the maximum limit. The present invention ameliorates these problems with logarithmic amplifiers because full dynamic range sample data is provided every sample clock cycle and can therefore be expressed in a linear or logarithmic scale. Thus, according to the present invention, either linear or logarithmic system output is selected for display on display 18 and is expanded and saved such for later analysis. The operator can instruct the system, eg, an FPGA described further below.

  The object of the present invention is to remedy or avoid the disadvantages of the prior art, and the present invention operates at 100 MHz 24 which is virtually free of DC offset, baseline error and other disadvantages of the prior art, operating at large input voltages. It is essentially equivalent to a bit A / D converter. Although the present invention has been implemented with performance essentially equivalent to a 100 MHz 24-bit A / D converter as described above, the present invention should be implemented with a sampling frequency and resolution other than 100 MHz and 24 bits, respectively. It is important to note that this is also possible. The present invention utilizes three (or more) A / D converters operating on a corresponding number of channels. The inventor has recognized that a multi-function A / D converter that will be developed sometime uses fewer A / D converters.

  FIG. 6 shows a more detailed version of a prior art circuit used to implement an ultrasound inspection system in a block diagram. This passionate analog circuit includes a series of parallel-provided amplifier / attenuators 28, 30, with gains of 14dB, 0dB, -8dB, -14dB and -20dB, respectively, via switch 24 as one selectable input The signal from the converter 12 to supply 32, 34 and 36 is utilized. The switch 24 further receives the input of the gain calibrator 20 and provides the received signal directly to the attenuators 32, 34 and 36 and to the amplifiers 28 and 30 via the switch 26.

  Variable gain amplifiers (VGA) 40, 42 and 44 receive their inputs from amplifiers 28 and 30 and from switch 29, respectively. Switch 29 provides an output 31 consisting of a selected one of the outputs of attenuators 32, 34 and 36. The output of VGA is provided to switch 46. The switch 46 further receives as its other input signals from the gain calibrator 22 and passes these signals through a bus 48 to a series of high pass filters 50, 52, 54, 56, 58, Selectively offers 60, 62 and 64. The outputs of these high pass filters are switched to low pass filters 70, 72, 74, 76, 78, 80, 82 and 84 via switching network 66. Thus, by controlling the selection of the desired signal via switches 66 and 67, the signal from VGA 40, 42 and 44 or the signal from gain calibrator 22 can be supplied, thereby selecting the selected signal. Can be provided to another VGA 86 downstream. The output of VGA 86 is further provided to amplifier 90 via switch 92.

  Next, finally, the output of amplifier 90 or the output of gain calibrator 94 is provided to 100 MHz 10-bit analog-to-digital (A / D) converter 100.

  A rewritable gate array (FPGA) 106 incorporates a real-time sample data control and storage circuit 102 and a measurement gain detection and compensation circuit 104 for providing an output to a digital signal processor and control 110. The digital signal processor and control 110 further obtains a properly processed output of the analog-to-digital converter 100, provides time-varying gain control, and generates a signal that can be displayed on the display 18. Therefore, the setting value of the FPGA 106 is controlled.

  To avoid inconsistencies and changes that can be attributed to the different frequency responses of many high-pass and low-pass filters, and to avoid the effects of DC offsets and variations in analog devices and temperature from the point of view of the introduction It will be readily apparent that the task of calibrating various analog circuits presents severe challenges for both designers and users of prior art circuits.

  A rough comparison of the block diagram of the present invention shown in FIG. 7 shows that in the case of the present invention utilizing a triple A / D channel where many of the disadvantages and complexity of the prior art are avoided, a problematic analog It shows much less circuit usage.

  In the block diagram shown in FIG. 7, when switch 114a is closed, output 13a of converter 12 is provided directly to only two preamplifiers 110 and 112. The preamplifier 112 supplies the third amplifier 122. These amplifier signals are processed by frequency response trim and filter blocks 116, 118 and 120, respectively, and subsequently provided to differential amplifier drivers 126, 128 and 130 along three channels A, B and C. The analog signals along the three channels are then provided directly to A / D converters 132, 134 and 136, respectively. The digital outputs of these A / D converters are then fed to a rewritable gate array 140 that incorporates a control and storage block 142, a time varying gain 146 and a measurement gate detection and composite A-scan compression circuit 152. The FPGA 140 operates with a DSP 160 that provides a signal to the display 18.

  The embodiment shown in FIG. 7 (the function and features of this embodiment will be described in more detail below in connection with the description of FIGS. 8a and 8b) includes analog high-pass and low-pass filters, additional amplifiers. And most of the prior art analog circuits and drawbacks, including the passionate use of calibrators and various VGA circuits, eliminates all of them with the circuits shown in Figures 7, 8a and 8b become.

  Thus, as further shown in FIGS. 8a and 8b, the present invention is an apparatus and method for extending the dynamic range of A / D converter circuits used in flaw detectors, thickness measuring instruments or corrosion measuring instruments. Thus, an apparatus and method that eliminates the need for variable gain amplifier (VGA) circuitry and the associated complexity and performance limitations. The apparatus and method according to the present invention utilizes three A / D converters that sample three differently scaled versions of the same input signal on different channels. The individual channel sample times are adjusted to compensate for the propagation delay of the individual amplifier channels, thereby minimizing signal skew errors between the sample data outputs of the individual A / D converters. Scaling is performed such that the resolution of the maximum gain channel (C) is 32 times higher than the resolution of the intermediate gain channel (B) and 1024 times higher than the resolution of the minimum gain channel (A). The data overflow of the higher resolution channel is monitored and the channel with the highest resolution data that has not overflowed is selected as the output. By combining the selected outputs, a continuous stream of output data is generated. The resulting output is a data stream in which the quantization step size is larger for large signals and the quantization step size is 32 or 1024 times smaller for small signals. Therefore, the level of dynamic range provided by the present invention controls the level of the analog input signal, thereby bringing the peak voltage level of the analog input signal to an input at or near the full scale value of the A / D converter. Eliminates traditional VGA implementations that are maintained.

  When sampled using the circuit shown in FIGS. 8a and 8b, the input signal from the converter 12 is split into two channels 19a and 19b, each with a dedicated buffer. Accordingly, each buffer amplifier 110 and 112 amplifies the input signal 13a on each channel with a gain of 0.1 (−20 dB) and a gain of 3.2 (10.1 dB), respectively. The output of the buffer amplifier 112 is connected to the input of the buffer amplifier 122 to generate a third channel having a gain of 102.4 (40.2 dB). Each of the channels is sampled by one of three substantially identical A / D converters 132, 134, 136. The three channels A, B, C are sampled with a time delay between them to compensate for the input signal timing skew error caused by the propagation delay of all amplifiers in the analog signal path. This time delay is controlled by the rising edges of the clocks CLKA, CLKB, CLKC driving the A / D converter, and this clock is adjusted by a calibration algorithm.

  In the practiced embodiment, the sample timing adjustment is divided into two parts.

  A) Coarse adjustment: Data is delayed by a selectable integer number of clock cycles using one FIFO and a control circuit per A / D channel.

  B) Tweak: There are four phase-locked loops (PLLs) that follow 0, 90, 180 and 270 phase angles with respect to the clock. By selecting the PLL output independently for each A / D, the clock timing of each A / D can be adjusted in 1/4 steps of the clock cycle.

  If the conversion data for the maximum gain channel (C) is valid, the result passes unmodified as the output 132OUT of the 3-channel A / D converter circuit (FIG. 8b). If the conversion data of the maximum gain channel (C) overflows, the result is discarded, the conversion data result of the intermediate gain channel (B) passes (if it does not overflow), and the gain of the buffer amplifier 112 is increased. Scaled to correct and used as output 134OUT. If the conversion data result for the intermediate gain channel (B) overflows, the result is also discarded, the conversion data result for the minimum gain channel is scaled, and the signal path gain is modified. This scaling gain is

Gain = buffer amplifier 112 + buffer amplifier 122-buffer amplifier 110
And then used as output 136OUT.

  In the embodiment shown in FIGS. 8a and 8b, the three-channel A / D converter circuit according to the present invention can remove the signal offset error of all three individual channels, each with three independent settings set to different gains. The buffered amplifier channel can be used to scale the input signal, and the analog signal input for each of the three individual channels can be digitally adjusted with individual sample times that can be adjusted to compensate for input signal timing skew errors. A channel overflow condition of a channel that can be converted to a signal, at least a greater gain, can be detected, and the A / D converter outputs of the three channels can be combined in real time.

  As pointed out above, the analog input signal 13a from the converter 12 is routed to two signal clamping amplifier channels, and the second amplifier 112 of the two amplifier channels is connected to the first channel 110. It has a gain that is larger than the gain by a predetermined coefficient. The output of the channel B amplifier 112 is connected to the downstream filter 118, and is also connected to the downstream side amplifier 32 having a gain of 32 to generate the channel C. For example, channel A has a gain of 0.1, while channel B has a gain of 3.2 and channel C has a gain of 102.4. Therefore, when compared with each other, channels A and B differ in gain factor by 32, and channels C and B also differ in gain factor by 32. Channels A and C differ by a gain factor of 1024.

  The clamping voltage thresholds of the amplifiers 110 and 112 are set to a level where the obtained output slightly exceeds the effective input range of the A / D converters 132, 134 and 136 of the individual channels A, B and C. The clamp circuits 111a, 111b and 113 also limit the input voltage to the gain channel amplifier and prevent the gain channel amplifier from saturating.

  Once an amplifier is saturated, it takes a significant amount of time for the amplifier to return to the linear operating region, so preventing amplifier saturation is important. Preventing the gain channel amplifier from saturating minimizes the length of time that the higher gain A / D converter is in overflow, and therefore uses output data with higher resolution more quickly. be able to. Also, the clamp circuit in preamplifier 112 functions to maintain a constant input impedance for input signal 19a, regardless of the input signal level up to a signal level higher than the maximum input to channel A preamplifier 110. ing. If a constant input impedance is not maintained, the input signal will be distorted.

  The inventor found that the amplifier 122 is separated from the converter 12 by the amplifier 112 so that the amplifier 122 does not require a clamp 113 to maintain a constant input impedance to the converter 12 over its signal amplitude operating range. I recognize that. Thus, other amplifier circuit configurations can be used for the amplifier 122 when it is necessary to provide other advantages, such as lower power or simpler circuitry.

  In the practiced embodiment, channel C amplifier 122 may saturate and a fast recovery operational amplifier is used. Preferably, clamping can be added to reduce noise generation.

  The outputs of each of the gain channel amplifiers 110, 112, 122 are connected to frequency response trim and filter circuits 116, 118, 120, respectively. The frequency responses of channels A, B, and C are matched as closely as possible using frequency response adjustment control signals 116a, 118a, 120a, respectively. This is necessary to ensure that all important signal frequencies have gains as close to the same as possible. The frequency response is adjusted using a calibration algorithm as described above. This frequency trim scheme can be used for multiple analog-to-digital converter channels.

  The anti-aliasing filter functions for channels A, B and C are distributed in frequency response trim and filters 116, 118, 120 and differential amplifiers 126, 128, 130, respectively.

  The DC offset inherent in the individual channel amplifiers is compensated for by injecting DC signals 112a, 122a, 126a and 128a and balancing DC offset errors present throughout the analog signal path. This compensation is performed using a calibration algorithm. Note that this DC offset compensation method has the following two limitations.

  1) Extremely fast pulse generator / receiver repetition rate (To in Figure 2) can be used between To cycles and the DC offset correction process required to compensate for DC offset variations over time There is not enough time to run. This limits the performance of the DC offset calibration and can only be calibrated when the instrument is not performing a measurement.

  2) At very large gain settings, a small DC offset error that exists after equilibration will produce a large offset in the stored sample data and thus in the waveform that appears on the display.

  In order to further improve the influence of the DC offset error existing in the whole analog signal path, including the influence described in the above items 1 and 2, this embodiment is a digital DC offset compensation scheme whose block diagram is shown in FIG. Only equipped.

  Still referring to FIG. 8c, the output of the A / D converter 136 is provided to the baseline capture block 146 during the period 10c shown in FIG. Sample points from period 10c are in a relatively "quiet" area in time, i.e., an area that occurs before the pulse generator emits a pulse and after there is a substantial amplitude ultrasound response signal Therefore, the baseline is monitored using these sample points. In this embodiment, the baseline capture block 146 uses 256 signed integer sample points to calculate the average, although a different number of sample points can be used. When multiplexer 147 is enabled by control signal 149 and the signed integer output of baseline capture block 146 passes toward baseline correction block 148, signal 147a is subtracted from signed integer signal 145a, thereby removing the baseline error. . Register 150 is not shown in the figure, but is intended to allow the use of alternative baseline compensation values generated by software algorithms or hardware devices.

  The three channel A / D converters 132, 134, and 136 are sampled by the sample clocks CLKA, CLKB, and CLKC, respectively, derived from the 100 MHz oscillator block 131 using the delay control elements included in the FPGA circuit. 14-bit high-speed converter provided. With this delay control element, the placement of the rising edge of one channel's sample clock relative to the clock circuit portion of the other channel can be timed, and therefore by adjusting the sample time of each individual channel, The amplifier channel propagation delay is compensated, and any other timing skew sources revealed by examination of the A / D converter output data. This compensation is performed using a calibration algorithm.

  As already pointed out, in the practiced embodiment, the sample timing adjustment is divided into two parts.

  1) Coarse adjustment: Data is delayed by a selectable integer number of clock cycles using one FIFO and a control circuit per A / D channel.

  2) Tweak: There are four phase-locked loops (PLLs) that perform 0 phase angle, 90 phase angle, 180 phase angle and 270 phase angle with respect to the clock. By selecting the PLL output independently for each A / D, the clock timing of each A / D can be adjusted in 1/4 steps of the clock cycle.

  The inventor contemplates an alternative method of adjusting sample data timing using fine analog adjustment in conjunction with the coarse digital adjustment described above. Instead of the digital clock timing adjustment scheme described above, the timing of the analog signal will be adjusted using adjustable signal delay elements. This analog signal delay can be achieved using any one of the following methods.

  1) A delay line with multiple taps, where one tap is selected by the switch to control the delay.

  2) Delay filter elements that are switched inside or outside the signal path as needed.

  3) Adjustable delay built using variable elements such as all-pass delay filters using voltage-controlled components. The delay can be controlled by the DAC, providing very fine control. The inventor has recognized that this method provides the best adjustment resolution.

  Also provided is a method of calibrating the system gain by adjusting the full scale range of A / D converters 132, 134 and 136. This is achieved by adjusting the reference voltage (not shown) of each A / D converter using a D / A converter (not shown). This function is performed using a calibration algorithm.

The digital outputs of the A / D converters 132, 134 and 136 are connected to the digital multiplexing circuit 135. The overflow signals of the two A / D converters 134 and 136 having higher gains are connected to the channel selection logic circuit 137. Channel selection logic 137 also overflows from A / D converters 134 and 136 to provide time for all amplifier circuits preceding the inputs of A / D converters 134 and 136 to exit saturation. The time duration of the signal has been extended. This circuit 137 selects the output data bus from the A / D converter of the maximum gain channel that has not overflowed. If all three A / D converter channels are overflowing, the lowest gain channel A / D converter output data bus is selected because the channel that exits the overflow condition first is the channel with the lowest gain. Is done. Overflow signals from channel selection logic 137 and A / D converter 132 are connected to exponent generator circuit 139. The circuit 139 calculates an index associated with the selected A / D converter data in the RAM 141. The floating point conversion circuit 143 effectively adds accurate bits to the A / D conversion of small signals while maintaining range capacity for large signals. The floating point converter 143 reduces the number of bits required for the sample data RAM. The sample data RAM has 18 bits, of which 14 bits are used for the mantissa and 4 bits are used for the exponent. When the sample value is stored, the value of the selected A / D converter is stored in the mantissa and the exponent value 0, 5 or 10 is stored in the exponent to indicate the scale of the data. It is also possible to set the index to 15 to indicate that all channels are overflowing. Further, when data is read from the sample RAM 141, the data is placed in the mantissa using the exponent and the 24-bit integer output of the floating point-integer converter 143 is constructed. This is the final output 145 of the present invention. This output can be expressed as:
Output 145 = 2 ^exponent x mantissa = 24-bit integer

  Although the present invention has been described in connection with an embodiment utilizing three signal processing channels that individually incorporate their respective analog-to-digital converters, the inventor has also demonstrated that a smaller number of analog- It contemplates the use of digital converters and even a single analog-to-digital converter. Thus, when an analog-to-digital converter operating at, for example, 200 MHz becomes available, one of these channels can be used using a single analog-to-digital converter that produces two consecutive high-speed samples of the same signal point. Can handle two of them. To that end, the first sample of the signal can be obtained while the amplified version of the same signal is delayed for a time delay approximately equal to the clock period of the 200 MHz analog-to-digital converter (only the analog delay time). The delayed amplified signal is then sampled by the same A / D converter. It also uses analog comparators to compare the magnitudes of the signals at the output of the preamplifier, thereby determining their magnitude range and the magnitude of that signal among the analog-to-digital converters. It is also possible to control the channeling of signals to an analog-to-digital converter that does not overflow.

  Also, although three channels are utilized, to extend the total dynamic range of the test system and / or to any one of several analog-to-digital converters that have been saturated and temporarily overflowed Utilizing more than four channels to use a given analog-to-digital converter as a temporary substitute is also within the scope of the inventive concept.

  Describing the above extension of the invention in more detail, one embodiment takes the form of a two-channel system using a pair of 16-bit ultrafast analog-to-digital converters whose clock speed is sufficient for the application of the invention. be able to. Also, certain users may need less than full dynamic range, so only one of multiple analog-to-digital converter channels can be used, so it is not necessarily fully dynamic for all applications. Note that a range is not always necessary. For a two-channel system where one channel is switched between a small gain and a large gain, only two channels can be utilized to provide a good portion of the advantages of a three-channel system.

  With respect to the above problem of detecting a flaw echo that is very close to the back wall of the target object, we solve this problem if both channels are stored and the channel change is performed in post-processing. Recognize that you can. This would be a “tracking back wall attenuator” solution. It is also possible to use double or split display windows, one showing scratches and the other showing the back wall. By using this split display window, the need to track the back wall and possibly adjust the display is eliminated. The small section of the received signal will be displayed twice and will first be displayed on the wound section with a large gain and then again on the back wall section with a small gain. This method can only support a flaw alarm gate that detects flaws very close to the back wall when the gate position is calculated in post-processing.

  With respect to the above concept of individually adjusting the frequency response of the channel to fit closely the assembled data stream without stepping or jumping, this adjustment can be performed using factory adjustments or run-time adjustments. Please keep in mind. It should also be noted that in the case of a three channel system, it may be sufficient to provide frequency response trim for only two of these channels in some cases.

  The present invention also provides for the overrange indication signal to prevent the output data of the analog-to-digital converter from being selected before the signal channel of the analog-to-digital converter is fully recovered from saturation. It can also be implemented by extending the duration. This extension can take one or more of the following forms.

  1. In this embodiment, time is added to the end of the overrange indicator bit from the analog-to-digital converter. This function is implemented within the channel selection logic 137 shown in FIG. 8b. The channel selection logic 137 may consist of an OR gate that receives an overflow signal as one input and receives its shifted version as the other input.

  2. Even if the analog-to-digital converter still indicates overrange, the next channel with the lowest gain is digitally detected to detect that the analog-to-digital converter has gone out of severe saturation. A comparator is used. Adding delay to this “severe saturation” detector is comparable to providing delay to the overrange indicator.

  3. To verify the validity of the data, the output data of the analog-to-digital converter is compared with the value of the next lowest gain channel. This value must be within the specified range of values from the next channel.

  4. A low-speed analog-to-digital converter is used to indicate that it is out of overrange.

  It should also be noted that analog-to-digital converters may saturate at input voltages that are higher than the overrange voltage. It is advantageous to delay the escape from saturation, which is why it is not necessary to delay the escape from overrange. In the voltage range between overrange and saturation, the analog-to-digital converter can function properly and no recovery time is required. In the practiced embodiment, the analog-digital overrange indicator is used as a saturation indicator, and unnecessary delays may be introduced. This unnecessary delay rarely occurs and is not a technically significant delay.

  The inventor also contemplates the use of a digital-to-analog converter to trim the reference voltage of the analog-to-digital converter in order to perform gain trimming. This method is used to extend the range of user gain control and is different from channel matching.

  The inventor also contemplates the use of preamplifiers for intermediate and high gain channels that do not distort the source signal. This approach is a preferred approach for constructing or utilizing an amplifier with at least 20 volt peak output range with very low noise performance. The approach described above is also preferred for hybrid designs that use an attenuator step at the input, but the dynamic range of this approach is not very wide. However, in terms of a low cost market, a hybrid design is preferred in some cases.

  The foregoing has described various technical problems associated with saturated circuit devices, ie, analog-to-digital converters that exhibit overrange. Following the introduction to the basic problem, several alternative solutions that are other embodiments of the present invention are described.

In normal operating conditions, channel gains for the circuits identified in parentheses below can be applied.
Channel A gain ^* 32 ≒ Channel B gain [Figure 7]
Channel B gain ^* 32 ≒ Channel C gain [Figure 7]

  When a channel saturates, it is indicated by the overflow output signal of that channel's analog-to-digital converter, which allows the channel selection logic 137 to select the best channel to receive the signal. As already explained, the best channel is the channel with the highest gain and no overflow. Channel A, channel B, and channel C are in order from the smallest gain to the largest gain. See Figures 8b, 8c, 8d and 8e.

  For very fast slew rate signals, such as the leading edge of a pulse generator pulse, the leading edge is too fast for all three channel amplifiers to saturate substantially simultaneously, so either Everything is not necessarily true.

Analog-to-digital converters do not saturate immediately due to amplifier and filter slew rate limitations, and all three channels move toward saturation at substantially the same rate. If a sample is taken from the A / D while the output of the A / D is slewing towards their final value, an incorrect reading will be recorded. For example, if all three channels are at about 1/2 full scale (corresponding to 2FFFC A / D output value at (HEX)), they do not correspond to the correct input amplitude. Readings for channels that do not indicate overflow are as follows:
Channel A = 2FFF, indicating -5V input Channel B = 2FFF, indicating -0.15V input Channel C = 2FFF, indicating -0.005V input

  Therefore, the embodiment shown in FIGS. 8b and 8c will select channel C because channel C is the channel with the highest gain and which has not (yet) overflowed. The channel reading above indicates that channel A is below -5V, so a -0.005V signal (assumed to be the input of channel C) will be shown on the display, Is not accurate.

  As shown in FIGS. 8d and 8e, alternative embodiments need not use an overflow output signal from any of the analog-to-digital converters 132, 134, and 136. Instead, absolute value comparators 801, 802, and 803, respectively, are used to indicate that the predetermined number matches the digital output data of the individual analog-to-digital converters. Absolute value comparators 801, 802 and 803 provide an output signal to channel selection logic 137 when the respective predetermined number is matched. The absolute value comparator 801 provides the output signal to the exponent generator 139. Note that the performance of this embodiment can also be achieved by using only absolute value comparators 801 and 802 for channels A and B, respectively.

  The main advantage of this “absolute value comparator” method is that the digital output signal of the analog-to-digital converter of the channel can be correlated with the level of the signal at any point along the input signal path. Can be used to detect any significant signal level within the full scale of the analog-to-digital converter and within the measurement resolution of the converter. The saturation of the amplifier in the input signal path is an example of an important signal level.

  Referring to FIG. 10, the following logic is true when processing extremely fast signal edges (ie, high slew rates). It should be understood that the values shown below are 14-bit signed integers.

  a) If [channel A> = 100] or [channel A <= 3EFF], then the channel B and channel C amplifiers will probably be overdriven.

  b) If [Channel B> = 100] or [Channel B <= 3EFF], the channel C amplifier will probably be overdriven.

  By using the logics a) and b) above and incorporating the following rules into the channel selection logic 137 with the following priorities, the problem of selecting the wrong channel can be prevented.

  a) If [Channel A> = 100] or [Channel A <= 3EFF], use data from channel A. That is, channel A has priority over channel B.

  b) If [Channel B> = 100] or [Channel B <= 3EFF], use data from Channel B. That is, channel B has priority over channel A.

  c) When [Channel A <100 and> 3EFF] and [Channel B <100 and> 3EFF], the data from channel C is used. That is, channel C has priority over channels A and B.

  Note that the hex values used above, and the hex values used in FIG. 10, are chosen as examples and are not necessarily the values used in the actual embodiment. I want.

  In FIG. 8d, the channel mixer 135 ′ is further indicated by a dashed line and is used as an alternative to the MUX 135. Channel mixer 135 'mixes the output of two of the three A / D converters that have the highest gain and are not saturated to minimize the effects of unwanted signals between channels Is functioning.

  FIG. 11 is approximately equivalent to the circuitry and signals contained within the channel mixer 135 ', but only a portion of channels A and B are shown, in order to be compatible with the inputs required for the RAM 141. In some cases, more output circuits must be added.

  As used herein, “mixed” means combined or related, and thus individual components or boundaries are not easily distinguished. Thus, the channel mixer 135 ′ is a device that obtains output values from two adjacent A / D converter channels and calculates a compromise value as its output. Ratio control is required to control the ratio of the two inputs used.

  FIG. 11 shows details of the ratio control circuit.

In this embodiment, the ratio control value is limited to a range of 0 to 1.
(Input A) ^* Ratio + (Input B) ^* (1-Ratio) = Output

  To simplify the circuit, the ratio control can be further limited in some cases to a small set of discrete values that do not include 0 and / or 1. The numbers 0 and 1 produce exactly the same output as one or the other input. Several other circuits can handle this condition.

  A very simple mixer assembled from two adders and three multiplexers can support the following ratio values: 0, 0.25, 0.5, 0.75 and 1. This divides the channel selection specificity into four individual specificities, each 1/4 in size.

  Therefore, the channel selection logic 137 shown in FIG. 8d selects the active channel according to the amplitude of the input signal 19a shown in FIG. If this system is used in an application that generates input signal amplitudes that are very close to the threshold at which the system will switch channels, the system will change channels so that the gain, frequency response and / or phase of the two channels In some cases, it may be observed that small jumps or glitches appear in the output because they are not accurately matched. This will appear as a sudden rise or fall in output signal amplitude.

  Referring to FIG. 8d, the channel with a small gain is channel A, and the channel with a large gain is channel B. Mixer 1111 (FIG. 11) determines how close channel B approaches saturation, depending on the outputs of absolute value comparators 1102 and 1108 (FIG. 11) contained within channel mixer 135 ′ (FIG. 8d). Is measuring. As the input signal 19a (FIG. 7) increases, channel B approaches the preset value of the saturation and absolute value comparator 1108. When the preset value of the absolute value comparator 1108 is reached, the mixing function is started in the channel mixer 135 ′ that mixes the data from the A / D converter 134 and the data from the A / D converter 132. . The mixing function is variable or has the step of weighting the two data sources from the individual A / D converters. As channel B approaches saturation, the mix-weighting ratio is changed, thereby making channel A more heavily weighted and channel B lighter. As an example, the mixing ratio starts with a small input signal 19a (Figure 7) amplitude where channel B is 100% and channel A is 0%, and when channel B approaches saturation, mixing is 50% for channel B, channel A changes to 50%. When channel B is saturated, the mixing is 100% for channel A and 0% for channel B. The mixing ratio can be derived from channel A or B or a combination thereof. The mixing ratio can be changed in several steps or can be adjusted smoothly in proportion to the channel signal amplitude.

  The use of the channel mixer 135 ′ reduces the likelihood that the operator will observe the voltage threshold of the input signal 19a (FIG. 7) that separates channel A and channel B operations. This mixing function can be used for all channel transition points. This method can be used in combination with any other method of controlling channel selection.

  FIG. 8h shows the output sample data and overflow (OF) of analog-to-digital converters 132, 134 and 136 to provide an overflow signal for additional clock cycles, thereby responding before the output sample data is provided to MUX 135. It provides another solution for adding a delay element to the signal. Although not shown in the figure, multiple additional clock cycles can be used. This delay prevents the channel selection logic 137 from selecting a channel until the overflow signal has sufficient time to respond, thereby preventing the problems caused by the fast slew rate input signal already described. Is done.

  In each channel, an overflow signal and a delayed overflow signal are provided to the OR gate for the following reasons.

  a) to turn on the overflow signal without delay so that the overflow signal occurs before the MUX135 is provided with the analog-to-digital converter output sample data; and

  b) To delay the turn-off of the overflow signal in order to synchronize with the delayed sample data provided at the input of the MUX135 when returning from the overflow condition.

  Note that for this alternative embodiment, it is possible to use delays other than one clock cycle.

  This method is implemented by inserting a data delay of one sample clock cycle between each of the digital signal outputs of analog-to-digital converters 132, 134 and 136 and the input to MUX 135. A data delay of one sample clock is also inserted between the overflow signal of each analog-to-digital converter and the input to the OR gate. The output of channel A OR gate 809 is provided to the input of exponent generator 139. The outputs of channel B and C OR gates 812 and 815 are provided to channel selection logic 137, respectively.

  Note that the performance of this alternative embodiment can also be achieved by using delays for channels B and C only.

  The inventor also contemplates a method that uses only a variable gain mechanism, such as a variable gain amplifier, in the analog signal path of an individual channel to substantially match the gain of the individual channel to a predetermined level. Yes. The gain level will be set to a predetermined level by the calibration procedure. The predetermined level contemplated for this embodiment is a level that ensures that the gain scaling between channels A, B and C is as accurate as possible. The figures associated with this alternative embodiment are not shown.

  In the above description, reference is made to the baseline corrector 148 shown in FIG. 8c. As described below, digital DC offset adjustment can be performed at any output of the analog-to-digital converter instead of adjustment at the combined output shown in FIG. 8c. Therefore, the following will now be described with reference to FIGS. 8e, 8f and 8g.

  a) The baseline correction system (BLCS) 804 shown in FIG. 8f is the same as the items 146 to 150 shown in FIG. 8e.

  b) The configuration of each of the baseline correction systems (BLCS) 805, 806 and 807 for channels A, B and C is the same as that of BLCS 804. BLCS 805, 806 and 807 are re-drawn versions of BLCS 804 and are intended to improve the appearance of FIG. 8g.

  c) As shown in FIG. 8g, BLCS 805, 806 and 807 are inserted between the digital signal output of analog-to-digital converters 132, 134 and 136 and the input to MUX 135.

  With further reference to FIG. 8g, the outputs of A / D converters 132, 134 and 136 are provided to BLCS 805, 806 and 807 during period 10c shown in FIG. Sample points from period 10c are in a relatively "quiet" area in time, i.e., an area that occurs before the pulse generator emits a pulse and after there is a substantial amplitude ultrasound response signal Therefore, the baseline is monitored using these sample points. In this embodiment, each of BLCS 805, 806, and 807 calculates an average using 256 sample points, although a different number of sample points can be used. Multiplexers in BLCS805, 806 or 807 can be enabled by their respective control signals (ME), thereby providing individual BLCS outputs to baseline corrector block input B, as shown in Figure 8f can do. Input B is then subtracted from the outputs of A / D converters 132, 134 and 136, thereby removing the baseline error. The registers included in BLCS 805, 806 and 807 are not shown in the figure, but are intended to allow the use of alternative baseline compensation values generated by software algorithms or hardware devices.

  The inventor has also achieved the advantages of the present invention as shown in FIG. 9 and described below, in particular, one signal path A / D converter with one or more gain reading A / D conversions. Alternative embodiments are contemplated that can be utilized in conjunction with a power supply and automatic gain control (AGC) circuitry to thereby achieve a wide dynamic range by determining and controlling the gain of the system. Although not shown in FIG. 9, the input signal 10b shown in FIG. 1 is connected to the input 200 shown in FIG.

  According to one aspect of this alternative embodiment, the system gain is calculated using the data recovery device in the acquisition logic block 210 so that the appropriate signal amplitude is displayed on the display or as an input to other devices. Provided. The acquisition logic block 210 can be placed in the FPGA 140 shown in FIG. 7, and the circuit on its left side can be replaced by substantially the entire FIG. Some circuitry within the FPGA 140 can be modified or removed as needed for each alternative embodiment.

  According to another aspect of this alternative embodiment, for each sample point, the system gain is calculated using the output value of signal A / D converter 209 along with the output values of gain reading A / D converters 225 and 226. The The sample rate is substantially the same and is synchronized with the A / D converters 209, 225 and 226. The accuracy of the system gain calculation is substantially determined by the accuracy of the gain calibration system, the transfer characteristics of the multiplier, and the accuracy of the three A / D converters. The inventor contemplates that calibration for zero multiplication (discussed later) and DC offset nulling may be necessary for each channel.

  As can further be seen from FIG. 9, the circuit of this alternative embodiment consists of four parallel input gain channels 201, 205, 207 and 211, each of which outputs four gain control multipliers 202, 206, Provided for one of 208 and 212 respectively. The outputs of these gain control multipliers are provided to an adder 203 comprising an amplifier 204, an A / D converter 209 and finally an acquisition logic 210 at the subsequent stage. AGC circuit 227 receives inputs from monitor signals 213, 214, 215 and 216 and provides output gain control signals 217, 218, 219 and 220 to multipliers 202, 206, 208 and 212, respectively. The inventor recognizes that the number of channels can be 5 or more, or 3 or less, depending on the dynamic range required for the application to which this alternative embodiment is applied. ing.

  Prevention of undesirable effects of signal saturation that can occur at different locations along the signal path is a critical aspect of this alternative embodiment. The signal path begins with input 200 and ends with input to A / D converter 209. In this embodiment, any signal in the signal path that begins with the output of preamplifiers 201, 205, 207, and 211 has an absolute value greater than 1 volt is considered a saturated signal. The following three conditions can cause a saturated signal to be present in the signal path.

  1. The absolute value of the amplitude of the input signal 200 is larger than 10V peak.

  2. The absolute value of the amplitude of the input signal 200 is 10 volts peak or less, but it is sufficient for the output of the preamplifier 205, 207 or 211 to be higher than 1 volt.

  3. The absolute value of the amplitude of the input signal 200 is 10V peak or less, but the sum of the outputs of the multipliers 202, 206, 208 and 212 is the signal at the input of the A / D converter 209 at the output of the adder 203. Is large enough to saturate.

  With respect to condition 1, many flaw detector inspection procedures require a pulse generator signal with a peak amplitude magnitude much greater than 10V to be displayed on the display, thus saturating the signal path to the pulse generator signal. It is not the purpose of this alternative embodiment to prevent signal saturation along the signal path.

  With respect to condition 2, this alternative embodiment uses the AGC circuit 227 to provide the saturated output signals of the preamplifiers 205, 207, and 211 by setting the gain control signals 218, 219, and 220 to substantially zero. Means are provided for substantially preventing passage through the gain multipliers 206, 208 and 212. The inventor has recognized that commercially available multiplier components do not have perfect performance characteristics. Thus, multipliers 206, 208, and 212 need not provide infinite attenuation associated with theoretical zero multiplication. What is needed for multipliers 206, 208 and 212 provides enough attenuation to maintain the maximum peak amplitude of the saturation signal below a level that would undesirably affect the input signal to A / D converter 209. Just to do. The maximum allowable saturation signal level can be established, for example, from recognized industry standards such as EN12668-1: 2000 for flaw detector equipment. It is worth mentioning that the outputs of multipliers 206, 208 and 212 are summed, so the calculation of the maximum allowable saturation signal level must be taken into account.

  With respect to condition 3, this alternative embodiment includes the use of the AGC circuit 227 so that the outputs of multipliers 202, 206, 208 and 212 are summed by adder 203 and amplified by +15 dB amplifier 204. Means are provided to ensure that the output is sufficiently small so as to prevent a signal exceeding 1 V from occurring at the input to the A / D converter 209 after being generated.

  According to another aspect of this alternative embodiment, channels A, B, C, and D must have substantially the same propagation delay to prevent total output distortion, It must also have a frequency response up to and including the input of adder 203.

  According to another aspect of this alternative embodiment, the gains of the individual channels are the multiplier multiplicand signal gain A, gain B, gain C and gain shown in FIG. 9 as items 217, 218, 219 and 220, respectively. Controlled by D. The automatic gain control circuit 227 monitors the output of each gain amplifier by the monitor signals 216, 215, 214 and 213, and adjusts the gain accordingly. The gains of multipliers 202, 206, 208 and 212 are controlled in such a way that the gain transitions smoothly from one multiplier to the other, which can cause sudden distortion that can cause signal distortion or glitches. Gain change is prevented.

  According to another aspect of this alternative embodiment, the preamplifier 205, 207 or 211 uses the clamping circuit already described in the present invention shown in FIG. There is no distortion. Each of the clamping circuits prevents distortion of the input signal 200 by maintaining a constant input impedance for the preamplifiers 205, 207 and 211.

  According to another aspect of this alternative embodiment, A / D converters 225 and 226 are sampling the summed gain signals provided by summers 223 and 224, respectively. Gain signals 217 and 219 are each divided by 1/10 to scale them to match the sensitivity of gain signals 218 and 220, respectively.

  According to another aspect of this alternative embodiment, when the signal amplitude at input 200 is approximately zero, the gain monitor signals 213, 214, 215, and 216 also have an approximately zero amplitude so that the automatic gain control circuit 227 Increase the gain signals 217, 218, 219 and 220 to their maximum gain value of 1 volt. As the signal amplitude at input 200 increases, the multiplier with a non-zero gain multiplicand gradually changes so that the gain between channels transitions smoothly before reaching saturation. When the D_Monitor signal 213 reaches a predetermined amplitude just before saturation due to the amplitude of the input 200, the automatic gain control circuit 227 sets the gain D220 to zero to prevent the signal from being saturated. Prevents passage through the vessel 212 and substantially saturates the signal. When the gain D is set to zero, the input 200 will pass through channels A, B and C until the C_Monitor signal 214 reaches a predetermined amplitude just before saturation, which is explained above. An automatic gain control process for channel D is initiated for channel C. As the signal amplitude at input 200 continues to increase, this process is now performed for channel B, then for channel A, and finally through the saturated signals channels B, C and D. Is substantially prevented.

  Since the gain adjustment must be performed before the input signal 200 reaches an amplitude that would result in an unacceptable signal, the response time of the AGC circuit 227 is the maximum allowable rate of change of the input signal 200. Established. If this alternative embodiment must be operated with a signal having a time rate of change faster than the response time of the AGC circuit 227, the outputs of the preamplifiers 201, 205, 207 and 211 and the multipliers 202, 206, 208 and 212 A delay circuit is introduced between the input and the input. Monitor signals 216, 215, 214 and 213 are connected to respective inputs of the delay circuit. This delay circuit provides a time delay that is longer than the response time of the AGC circuit 227. In order not to cause unacceptable signal distortion, the relative propagation delay error and frequency response error between the delay circuits of the individual channels must be minimized.

  The inventor recognizes that the objectives of this alternative embodiment can be achieved using the control parameters and sequence of the automatic gain control circuit 227 implemented in a manner other than that described in the above embodiment. Yes. The inventor has also recognized that with respect to gain control, these other embodiments can be used to achieve substantially the same end result.

  Throughout the specification and claims, reference is made to “echo” signals. As will be appreciated by those skilled in the art, in a particular environment or application, the transmitter and receiver components of transducer 12 are physically separated and the receiver is placed on the opposite side of the object under test. Is done. Thus, the term “echo” as used herein also relates to and encompasses embodiments in which so-called echo signals pass through the object under test.

  Thus, for the present invention, in connection with embodiments in which flaw detection is performed using a single transducer element operating exclusively based on the echo principle and / or processing ultrasound passing through a substance Explained exclusively with reference to the transmitter / receiver pair. However, it should be noted that the present invention is equally applicable to flaw detection equipment that uses an array of multiple transducer elements, such as an ultrasonic phasing array probe. In the case of a single element ultrasonic transducer, the response signals of the individual transducer elements of the phasing ultrasonic probe used for reception are received by the receiver for conditioning and subsequent digitization by an analog-to-digital converter. Provided at the input of the channel. In other words, the reference to “transducer” in the claims is also considered to relate to an ultrasonic phasing array type probe. Such an array of transducers is considered to be identical or at least equivalent to a single element transducer. U.S. Pat. Nos. 4,497,210 and 6,789,427, the contents of which are incorporated herein by reference, describe or reference the structure of such an ultrasonic phasing device.

  Although the present invention has been described in connection with specific embodiments of the present invention, many other variations and modifications and other uses will become apparent to those skilled in the art. Accordingly, the invention is preferably not limited by the specific disclosure herein, but only by the claims.

It is a block diagram which shows the basic structure of an ultrasonic inspection apparatus. FIG. 2 is a basic waveform diagram of the device shown in FIG. It is a waveform diagram which shows the trailing edge characteristic of an ultrasonic pulse. It is the block diagram which compared the waveform display and the failure position in a target object side by side. FIG. 5 is a diagram showing a continuation of FIG. It is a circuit block diagram of the embodiment by the prior art of an ultrasonic inspection apparatus. 1 is a circuit diagram of a thoroughly digitized embodiment of an ultrasonic inspection apparatus according to the present invention. FIG. FIG. 6 is another block diagram of another embodiment according to the present invention. FIG. 6 is another block diagram of another embodiment according to the present invention. FIG. 8b corresponds to FIG. 8b, simply with digital DC offset compensation. FIG. 9 is a diagram corresponding to FIG. 8b in which an absolute value comparator is used instead of the overflow indicator. FIG. 8b is a diagram corresponding to FIG. 8b, using an absolute value comparator instead of an overflow indicator and further adding a digital baseline correction. FIG. 8b corresponds to FIG. 8b, with baseline correction added to individual channels. FIG. 8b corresponds to FIG. 8b, with baseline correction added to individual channels. FIG. 8b corresponds to FIG. 8b with a delay circuit for processing a fast slewing input signal. FIG. 8 is a circuit block diagram of an alternative embodiment of the front end section whose outline is shown in FIG. FIG. 9 is a signal diagram utilized to explain a particular concept that can be applied to the operation of the circuit shown in FIGS. 8d, 8e and 8h. FIG. 8d is a block diagram of the mixing circuit associated with FIG. 8d.

Explanation of symbols

2d, 14b, 14d scratch
6d back wall echo gate
6e Ideal TVG curve
6f, 6h gain
6g Instantaneous slope (gain change rate)
6m Time interval for changing gain
7a Settling time
Approximate dotted line showing improvement of trailing edge of transmitted pulse by 7c HPF
10 Ultrasonic transceiver unit
10a Electric pulse signal (ultrasonic pulse)
10b Electric echo signal (wound echo)
10ab zero baseline
10at trailing edge of transmitted pulse
11 Amplified signal (echo signal, ultrasonic echo pulse)
11a Bottom surface echo (back wall echo)
11b wound echo
12 Probe or transducer
12a Trigger pulse
13 Signal cable
13a, 19a, 19b Converter output (input signal)
14 Target object
14a Bottom surface of target object (back surface, back wall)
14c Front surface of target object
16 signal processing devices
18 Display unit (waveform display)
20, 22, 94 Gain calibrator
24, 26, 29, 46, 67, 92, 114a switch
28, 30, 90, 122, 204 amplifier
31 Output of switch 29
32, 34, 36 Attenuator
40, 42, 44, 86 Variable gain amplifier (VGA)
48 busbar
50, 52, 54, 56, 58, 60, 62, 64 High-pass filter
66 Switching network
70, 72, 74, 76, 78, 80, 82, 84 Low-pass filter
100 100 MHz 10-bit analog-to-digital (A / D) converter
102 Real-time sample data control and storage circuit
104 Measurement gate detection and compensation circuit
106, 140 Rewritable gate array (FPGA)
110 Digital Signal Processor and Control
110, 112, 122 Preamplifier (buffer amplifier)
111a, 111b, 113 clamp circuit
112a, 122a, 126a, 128a DC signal
116, 118, 120 Frequency response trim and filter block (filter, frequency response trim and filter circuit)
116a, 118a, 120a Frequency response adjustment control signal
126, 128, 130 differential amplifier driver
131 100MHz oscillator block
132, 134, 136 A / D converter
132OUT, 134OUT, 136OUT 3-channel A / D converter circuit output
135 Digital multiplexing circuit
137 channel selection logic
139 Exponential generator circuit
141 RAM
142 Control and storage blocks
143 Floating point converter (floating point converter)
145 Final output of the present invention
145a Signed integer signal
146 Time-varying gain
146 Baseline capture block
147 Multiplexer
147a Signal that passed through the multiplexer
148 Baseline correction block
149 Signals that control the multiplexer
150 registers
152 Measurement gate detection and combined A-scan compression circuit
160 DSP
200 inputs
201, 205, 207, 211 Gain channel (preamplifier)
202, 206, 208, 212 Gain control multiplier
203, 223, 224 adder
209 Signal A / D converter
210 Collection logical block
213 Monitor signal (D_Monitor signal)
214 Monitor signal (C_Monitor signal)
215, 216 Monitor signal
217, 218, 219 Output gain control signal
220 Output gain control signal (Gain D)
225, 226 Gain reading A / D converter
227 AGC circuit (automatic gain control circuit)
801, 802, 803, 1102, 1108 Absolute value comparator
804, 805, 806, 807 Baseline correction system (BLCS)
809, 812, 815 OR gate
1111 Mixer
A channel (minimum gain channel)
B channel (intermediate gain channel)
C channel (maximum gain channel)
S Trigger signal To Additional pulse interval

Claims (65)

An object inspection system,
A transmit and receive section for generating a test signal and receiving a response echo signal;
A transform that converts the test signal into an ultrasound signal, applies the ultrasound signal to a target object to be tested, receives an ultrasound echo signal, and generates the echo signal for the transmit and receive sections And
A signal processing circuit coupled to the transmit and receive sections for receiving and processing the echo signal, each scaling the echo signal to a different degree, and each analog-to-digital converter comprising: A signal processing circuit comprising at least three signal processing channels individually having;
A selection circuit that selects an output of an analog-to-digital converter that provides maximum amplification of the echo signal without overflowing.   The system of claim 1, comprising a display for displaying a scanning signal representing the echo signal generated by the signal processing circuit.   The system of claim 1, further comprising a respective frequency filter on at least one of the plurality of signal channels.   The system of claim 1, further comprising a respective frequency trim circuit for at least one of the plurality of signal processing channels, wherein the frequency responses of the filters are matched to each other by the respective frequency trim circuit.   Comprising at least first, second and third signal channels, each comprising first, second and third preamplifiers, wherein said first, second and third preamplifiers respectively The system of claim 1, wherein the system provides first, second and third scaled outputs.   6. The system of claim 5, wherein the output of the second preamplifier is provided as an input to the third preamplifier.   6. The system of claim 5, wherein each DC offset adjustment circuit is present in at least one of the plurality of signal processing channels.   6. The system of claim 5, wherein each channel comprises a respective differential amplifier driver.   9. The system of claim 8, wherein at least one of the plurality of amplifier drivers comprises a direct current offset adjustment circuit.   The outputs of the first, second and third preamplifiers are such that the second output is greater than the first output and the third output is greater than the second output. 6. The system of claim 5, made.   First, second and third analog-to-digital converters each having a respective clock input, said clock input being adapted to compensate for signal path delays of the individual channels, 6. The system of claim 5, wherein the system is synchronized with each other by phase adjustment between the rising edge and the rising clock edge.   6. The system of claim 5, comprising a clamping circuit for the preamplifier.   Each of the analog-to-digital converters has a respective overflow output, and the selection circuit receives the respective overflow output and provides an output of the analog-to-digital converter that provides maximum amplification without overflowing. 6. The system of claim 5, comprising channel selection logic for selecting.   14. The system of claim 13, further comprising an exponent generator for scaling the output of a selected analog-to-digital converter output and storing the scaled output in a random access memory.   6. The system of claim 5, comprising a display.   The system of claim 3, wherein the filter is an anti-aliasing filter.   6. The system according to claim 5, further comprising a DC offset circuit that applies digital DC offset correction at a signal position located subsequent to the selection circuit.   The DC offset circuit comprises a baseline capture circuit for generating a correction signal, coupled to at least one of the first, second and third analog-to-digital converters; and 18. The system of claim 17, comprising a baseline corrector capable of subtracting the correction signal from an output signal derived from one of the second and third analog-to-digital converters.   12. The system of claim 11, comprising a FIFO circuit capable of delaying one clock input relative to other clock inputs by a selectable integer number of clock cycles.   A delayed output from one or more of the first, second, and third preamplifiers in a manner that allows the outputs from the first, second, and third preamplifiers to be synchronized. 6. The system of claim 5, comprising an analog signal delay module that performs the withdrawal of.   21. The system of claim 20, wherein the analog signal delay module comprises a delay line with a plurality of taps, and a desired tap is selected by a switch to obtain a desired delay.   21. The system of claim 20, wherein the analog signal delay module comprises a delay filter element that can be switched in and out of the signal path as needed.   21. The system of claim 20, wherein the analog signal delay module comprises an adjustable variable controlled by a voltage control component responsive to a digital to analog converter.   The system of claim 1, wherein the selection circuit is coupled to a respective overflow signal provided by an individual converter of the plurality of analog-to-digital converters.   The selection circuit is coupled to a plurality of absolute value comparators respectively coupled to individual converters of the plurality of analog to digital converters, each of the absolute value comparators being its respective analog to digital converter. And the selection circuit is responsive to the absolute value comparator and one or more of the analog-to-digital converters result in incorrect readings. The system of claim 1, wherein the system is pre-determined as to whether it tends to go.   A respective baseline correction system coupled to one or more individual converters of the analog-to-digital converter, wherein each of the baseline correction systems is coupled to a multiplexer, and the channel selected by the multiplexer is processed The system of claim 1, wherein: Providing a test signal to the transducer to generate an ultrasonic signal that can propagate through and reflect in the target object to be tested;
Receiving an ultrasonic echo signal and generating an echo signal to be processed;
Using the echo signals scaled to different degrees in the individual processing channels and subsequently converted to digital outputs in the individual processing channels using respective analog-to-digital converters, at least 3 Processing the echo signal in two signal processing channels;
Selecting an output from an analog-to-digital converter that provides maximum amplification of the echo signal without overflowing.   28. The method of claim 27, comprising adjusting the respective sample times of the individual analog-to-digital converters to compensate for time skew sources, including signal propagation delays within the individual signal channels.   28. The method of claim 27, comprising preventing saturation of a preamplifier input stage coupled to a channel to prevent signal distortion from affecting inputs to other channels.   28. The method of claim 27, comprising trimming the frequency response of each of at least one of these channels to have the three channels have a substantially matched frequency response.   28. The method of claim 27, comprising detecting a channel overflow condition of one or more of the plurality of channels having a higher gain.   28. The method of claim 27, comprising combining the output of the analog to digital converter into a continuous output stream.   28. The method of claim 27, comprising removing signal offset errors of individual signal channels by injecting a DC signal from a digital-to-analog converter at various points in the analog signal path.   Changing the reference voltage that can be applied to the analog-to-digital converter in an individual signal channel to adjust the full-scale range of the analog-to-digital converter using the digital-to-analog converter. 28. The method of claim 27, further comprising:   28. adjusting a rising edge arrangement of a clock input to the analog-to-digital converter to ensure that each of the analog-to-digital converters samples the echo signal at the same point. The method described in 1.   28. The method of claim 27, comprising scaling the magnitude of the digital output data obtained from the analog-to-digital converter in different channels to the same reference as the respective gain level of the analog-to-digital converter. An object inspection system,
A transmit and receive section for generating a test signal and receiving a response echo signal;
A transducer that converts a test signal into an ultrasonic signal, applies the ultrasonic signal to a target object to be tested, receives an ultrasonic echo signal, and generates the echo signal for the transmit and receive sections When,
A signal processing circuit coupled to the transmit and receive sections for receiving and processing the echo signal, each comprising at least one preamplifier that scales the echo signal to different degrees A signal processing circuit with two signal processing channels;
An analog-to-digital converter coupled to the preamplifier through an amplifier circuit, wherein only at least one unsaturated output of the plurality of preamplifiers passes to the analog-to-digital converter. A combined analog-to-digital converter;
Selected to detect the magnitude of the output of the preamplifier coupled to the output of the preamplifier and to ensure that the unsaturated output is provided to the analog-to-digital converter And an automatic gain control circuit capable of providing a gain setting value to the multiplier circuit.   38. The system of claim 37, comprising acquisition logic coupled to the analog-to-digital converter for receiving an output from the analog-to-digital converter and receiving an additional output derived from the automatic gain control circuit. .   40. The system of claim 38, wherein the additional output is generated by at least one analog to digital converter provided between the acquisition logic circuit and the automatic gain control circuit. An object inspection system,
A transmit and receive section for generating a test signal and receiving a response echo signal;
A transform that converts the test signal into an ultrasound signal, applies the ultrasound signal to a target object to be tested, receives an ultrasound echo signal, and generates the echo signal for the transmit and receive sections And
A signal processing circuit coupled to the transmit and receive sections for receiving and processing the echo signal, each scaling the echo signal to a different degree, and each analog-to-digital converter comprising: A signal processing circuit comprising at least two signal processing channels individually having;
A selection circuit that selects the output of the analog-to-digital converter that provides maximum amplification of the echo signal without overflow;
An object inspection system comprising: a channel mixer operable to mix the output of the analog-to-digital converter in response to the selection circuit, thereby generating a mixed analog-to-digital output.   The selection circuit is coupled to a plurality of absolute value comparators respectively coupled to individual converters of the plurality of analog to digital converters, each of the absolute value comparators being its respective analog to digital converter. And the selection circuit is responsive to the absolute value comparator and one or more of the analog-to-digital converters result in incorrect readings. 41. The system of claim 40, wherein the system is pre-determined if it tends to head.   Each of the analog-to-digital converters has a respective overflow output, and the selection circuit receives the respective overflow output and provides an output of the analog-to-digital converter that provides maximum amplification without overflowing. 41. The system of claim 40, comprising channel selection logic for selecting.   41. The system of claim 40, further comprising a respective frequency trim circuit for at least one of the plurality of signal processing channels, wherein the respective frequency trim circuits match filter frequency responses to each other.   First and second analog-to-digital converters each having a respective clock input, wherein the clock input compensates for the signal path delay of the individual channels and the rising clock edge and rising clock of the clock input 41. The system of claim 40, wherein the systems are synchronized with each other by phase adjustment between edges.   41. The system of claim 40, further comprising an exponent generator for scaling the output of a selected analog-to-digital converter output and storing the scaled output in a random access memory.   A DC offset circuit for applying a digital DC offset correction at a signal position located at a subsequent stage of the selection circuit, wherein the DC offset circuit is at least one of the first or second analog-digital converters A base line capture circuit for generating a correction signal coupled to and deducting the correction signal from an output signal derived from one of the first or second analog-to-digital converters 41. The system of claim 40, comprising a baseline corrector capable of.   At least first and second signal channels, each having first and second preamplifiers, respectively, wherein the first and second preamplifiers are respectively first and second scaled outputs of the echo signal 41. The system of claim 40, wherein the analog signal delay module comprises a delay line with a plurality of taps, and a desired tap is selected by a switch to obtain a desired delay. Providing a test signal to the transducer to generate an ultrasonic signal that can propagate through and reflect in the target object to be tested;
Receiving an ultrasonic echo signal and generating an echo signal to be processed;
Using said echo signals scaled to different degrees in individual processing channels and subsequently converted to digital outputs in individual processing channels using respective analog-to-digital converters, at least 2 Processing the echo signal in two signal processing channels;
Selecting an output from an analog-to-digital converter that provides maximum amplification of the echo signal without overflowing;
Mixing the output of the analog-to-digital converter in response to the selecting step to produce a mixed analog-to-digital output.   49. The method of claim 48, comprising adjusting the respective sample times of the individual analog-to-digital converters to compensate for time skew sources, including signal propagation delays within the individual signal channels.   49. The method of claim 48, comprising preventing saturation of a preamplifier input stage coupled to a channel to prevent signal distortion from affecting inputs to other channels.   49. The method of claim 48, comprising trimming the frequency response of each of at least one of these channels to have the three channels have a substantially matched frequency response.   49. The method of claim 48, comprising detecting a channel overflow condition of one or more channels of the plurality of higher gain channels.   49. The method of claim 48, comprising removing signal offset errors of individual signal channels by injecting a DC signal from the digital-to-analog converter at various points in the analog signal path.   Changing the reference voltage that can be applied to the analog-to-digital converter in an individual signal channel to adjust the full-scale range of the analog-to-digital converter using the digital-to-analog converter. 49. The method of claim 48, further comprising:   49. Adjusting a rising edge placement of a clock input to the analog-to-digital converter to ensure that each of the analog-to-digital converters samples the echo signal at the same point. The method described in 1.   49. The method of claim 48, comprising scaling the magnitude of the digital output data obtained from the analog-to-digital converters of different channels to the same reference as the respective gain levels of the analog-to-digital converters. An object inspection system,
A transmit and receive section for generating a test signal and receiving a response echo signal;
A transform that converts the test signal into an ultrasound signal, applies the ultrasound signal to a target object to be tested, receives an ultrasound echo signal, and generates the echo signal for the transmit and receive sections And
A signal processing circuit coupled to the transmit and receive sections for receiving and processing the echo signal, each scaling the echo signal to a different degree, and each analog-to-digital converter comprising: A signal processing circuit comprising at least two signal processing channels individually having;
A selection circuit that selects the output of the analog-to-digital converter that provides maximum amplification of the echo signal without overflow;
Delaying the output of at least one of the plurality of analog-to-digital converters so that the analog-to-digital converter responds to the leading edge of a fast slewing input signal prior to processing of the output by the selection circuit An object inspection system comprising a delay circuit capable of   58. The system of claim 57, wherein the delay circuit provides a delay that is a multiple of a clock period coupled to the system.   59. The system of claim 58, wherein the delay circuit further delays a respective overflow output of the analog to digital converter. An object inspection system,
A transmit and receive section for generating a test signal and receiving a response echo signal;
A transform that converts the test signal into an ultrasound signal, applies the ultrasound signal to a target object to be tested, receives an ultrasound echo signal, and generates the echo signal for the transmit and receive sections And
A signal processing circuit coupled to the transmit and receive sections for receiving and processing the echo signal, each scaling the echo signal to a different degree, and each analog-to-digital converter comprising: A signal processing circuit comprising at least two signal processing channels individually having;
A selection circuit that selects the output of the analog-to-digital converter that provides maximum amplification of the echo signal without overflow;
An object inspection system comprising: a delay circuit that freezes selection of an output of the overflowed analog-to-digital converter until the overflowed analog-to-digital converter recovers from a saturated state. An object inspection system,
A transmit and receive section for generating a test signal and receiving a response echo signal;
A transform that converts the test signal into an ultrasound signal, applies the ultrasound signal to a target object to be tested, receives an ultrasound echo signal, and generates the echo signal for the transmit and receive sections And
A signal processing circuit coupled to the transmit and receive sections for receiving and processing the echo signal, each scaling the echo signal to a different degree, and each analog-to-digital converter comprising: A signal processing circuit comprising at least two signal processing channels individually having;
A selection circuit that selects the output of the analog-to-digital converter that provides maximum amplification of the echo signal without overflow;
An object inspection system comprising: a respective frequency trim circuit for at least one of the plurality of signal processing channels, wherein the frequency trim circuit matches the frequency response of the channel to each other by the respective frequency trim circuit. An object inspection system,
A transmit and receive section for generating a test signal and receiving a response echo signal;
A transform that converts the test signal into an ultrasound signal, applies the ultrasound signal to a target object to be tested, receives an ultrasound echo signal, and generates the echo signal for the transmit and receive sections And
A signal processing circuit coupled to the transmit and receive sections for receiving and processing the echo signal, each scaling the echo signal to a different degree, and each analog-to-digital converter comprising: A signal processing circuit comprising at least two signal processing channels individually having;
A selection circuit that selects the output of the analog-to-digital converter that provides maximum amplification of the echo signal without overflow;
A preamplifier coupled to the individual channels;
An anti-saturation circuit coupled to the individual pre-amplifier to prevent saturation of the respective input stage of the individual pre-amplifier, thereby preventing the distortion of the signal from affecting the input to other channels; Object inspection system with An object inspection system,
A transmit and receive section for generating a test signal and receiving a response echo signal;
A transform that converts the test signal into an ultrasound signal, applies the ultrasound signal to a target object to be tested, receives an ultrasound echo signal, and generates the echo signal for the transmit and receive sections And
A signal processing circuit coupled to the transmit and receive sections for receiving and processing the echo signal, each scaling the echo signal to a different degree, and each analog-to-digital converter comprising: A signal processing circuit comprising at least two signal processing channels individually having;
A selection circuit that selects the output of the analog-to-digital converter that provides maximum amplification of the echo signal without overflow;
An object inspection system comprising: a reference voltage circuit that can be applied to each of the analog-to-digital converters in individual signal channels to adjust the full-scale range of the analog-to-digital converters.   64. The system of claim 63, wherein the reference voltage circuit comprises a respective digital to analog converter coupled to a respective individual analog to digital converter. Providing a test signal to the transducer to generate an ultrasonic signal that can propagate through and reflect in the target object to be tested;
Receiving an ultrasonic echo signal and generating an echo signal to be processed;
Using said echo signals scaled to different degrees in individual processing channels and subsequently converted to digital outputs in individual processing channels using respective analog-to-digital converters, at least 2 Processing the echo signal in two signal processing channels;
Selecting an output from an analog-to-digital converter that provides maximum amplification of the echo signal without overflowing;
Enabling a full dynamic range processing of the sample data of the echo signal every sample clock cycle in a way that the sampled data can be represented in a linear or logarithmic scale.

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