JP2009301451A - Serial communication controller - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a serial communication controller which has a 16550-compatible function and is rapidly accessible to a register map. <P>SOLUTION: The serial communication controller for performing read/write access to a plurality of registers on the basis of an address to be applied from a host is provided with a batch processing circuit for simultaneously performing access to the plurality of registers on the basis of the address assigned from the host. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

The present invention relates to a built-in serial communication controller mainly used in various manufacturing apparatuses, and in particular, has a function compatible with 16550 (one of IC chips used for communication such as a serial port of a computer) and internally. This is to improve so that the set register can be accessed at high speed.

Generally, a PLC (programmable logic controller) or the like is adopted as an embedded serial communication controller used in various manufacturing apparatuses, and a register map compatible with 16550 is used for a register used in such a serial communication controller. Is often used. Here, 16550 is a communication controller manufactured by National Semiconductor, and is an IC chip that is an industry standard.

In addition, such a serial communication controller is required to be compatible with Ethernet (registered trademark) communication and multi-channel serial communication. At this time, a read or write request is made via an interface for communication. The internal registers need to be accessed as soon as possible.

As a prior art document of such a serial communication controller, for example, the following Patent Document 1 is known, and as a prior art document of an embedded controller, for example, Non-Patent Document 1 is known.

JP 09-319702 A

Kojiya Matsuoka and three others, “Remote OME function of FA-MA using the Internet”, Yokogawa Technical Journal, Yokogawa Electric Corporation, 2002, Vol. 4, p. 123-126

Hereinafter, a conventional serial communication controller will be described with reference to FIG. As described above, since a register map compatible with a 16550 is often set for a register installed in a controller for serial communication, a register control method will be described using an appropriate method.

FIG. 4 is a block diagram showing the configuration of the 16550 register / map compatible register in the serial communication controller 1. In FIG. 4, a host 10 is a peripheral device such as a temperature controller (hereinafter referred to as “temperature controller”), and outputs encoded data to the serial communication controller 1.

The address decode circuit 20 is a decode circuit of an address given from the host address line LA, decodes an address (A2, A1, A0) designated by the host 10 and sends it to each register 40, 50, 60 in the subsequent stage. Any one of the select signals S40, S50, and S60 to be output is generated.

The data line selection / direction definition circuit 30 connects the host data line LD (32 bits wide) on the host 10 side and the register data lines LRD40, LRD50, LRD60 (8 bits) on the registers 40, 50, 60 side. Circuit.

The data line selection / direction definition circuit 30 defines the direction of data connection according to the contents of the host control line LC (read / write signal), and from each register 40, 50, 60 to the host 10 when reading data. When data is written, a signal is passed from the host 10 to each of the registers 40, 50 and 60.

  Here, for example, if the register 40 is configured to be compatible with 16550, its register map is as shown in FIG. In this figure, the register names are defined as RBR, THR, DLL,..., Respectively, and are configured in units of 8 bits (0-7).

This register map becomes active when the select signal S40 output from the address decode circuit 20 is valid (for example, “1” is valid / “0” is invalid), while the read signal or write signal is sent from the host 10. It is given via the host control line LC.

  Note that the configuration of the registers 50 and 60 is the same as that of the register 40 (including the configuration of the register map), except that it operates with the select signals S50 and S60, respectively, so that the description thereof is omitted.

  Next, the operation of the serial communication controller 1 in FIG. 4 will be described. First, the case where the host 10 reads the contents of a specific register (for example, the register 40) will be described. The host 10 outputs the address of the register 40 to be read to the address decode circuit 20 via the host address line LA and asserts a read signal via the host control line LC.

The address decode circuit 20 asserts the select signal S40 of the register 40 that matches the address input via the host address line LA. As a result, the register 40 outputs the contents of the register via the register / data line LRD40.

Reading the contents of the registers 50 and 60 is the same as the above operation.

Next, a case where the host 10 side writes to a specific register (for example, register 40) will be described. The host 10 outputs the address of the register 40 to be written to the address decode circuit 20 via the host address line LA and asserts a write signal via the host control line LC.

The address decode circuit 20 asserts the select signal S40 of the register 40 that matches the address input via the host address line LA. As a result, the register 40 stores data via the register / data line LRD40.

The same operation is performed when the contents of the registers 50 and 60 are written.

  Next, a detailed flow of reception processing will be described with reference to the register map of FIG. First, as a first access, when a read signal is input via the host control line LC, a line status register LSR (Line Status Register) 72 is read, and the status is set in this register LSR. Is confirmed.

  That is, the presence of received data is confirmed by referring to the data ready DR 73 in the LSR 72 “0” bit (for example, “1” has data / “0” has no data). If no reception data exists, this reception process is terminated.

  Next, referring to DR73, when there is received data ("0" bit is "1"), overrun OE74 in the "1" bit of LSR72, framing error in the "2" bit Check the bit contents of FE75 etc. to make sure there are no errors.

  If there is no error here, the process proceeds to the next second access. The second access is an access to the register of the receiver buffer register RBR71, and data to be actually read (1 byte: RD0 to RD7) is read from the register RBR1.

As described above, the conventional access process is a two-stage process including the first access and the second access as described above. That is, even a simple reception process requires at least two access processes.

When the serial communication controller reads the received data, the serial communication controller confirms the contents of the LSR 72 again, and thereafter repeats these access operations.

As described above, in the conventional serial communication controller, one register is accessed by one access, and necessary registers are sequentially accessed from the second access to perform read and write operations.

However, in the conventional serial communication controller, as described with reference to the register map of FIG. 5, only one register can be accessed in one access, and the access size is in units of bytes. The speed was fixed, and it was difficult to achieve higher speeds.

In the example of FIG. 5, in the case of simple reception processing, two accesses are sufficient. However, since it is actually necessary to see other statuses, this requires this and further time is required for control. Sometimes it becomes.

On the other hand, if the access size is simply changed to word (word) or long (long) or the like, unnecessary data is acquired depending on the access procedure, and it may not be possible to increase the speed. Furthermore, if the register map is rearranged to the original, compatibility with the upper application used conventionally is lost.

Further, since there are a plurality of types of programs for controlling the serial communication controller, it is difficult to newly determine an optimum register map so as to correspond to all of them.

The present invention has been made in consideration of these problems, and an object of the present invention is to provide a serial communication controller having a 16550 compatible function and capable of accessing a register map at high speed.

The present invention for solving such problems is as follows.
(1) In a serial communication controller that performs read / write access to a plurality of registers based on an address given by a host,
A serial communication controller comprising a batch processing circuit that simultaneously accesses a plurality of the registers based on an address given from the host.
(2) In a serial communication controller that performs read / write access to a plurality of registers based on an address given by a host,
An address registration register comprising a set address register for storing addresses of a plurality of the registers to be accessed simultaneously based on an address given from the host;
A registered address decoding circuit comprising a fast access register that outputs a register select signal based on the contents stored in the set address register by access from the host;
A serial communication controller, comprising: a selector for controlling switching in response to a signal indicating whether to access the registers individually or simultaneously to access a plurality of registers from the host.
(3) The serial communication controller according to claim 1, wherein the host accesses the registered address decoding circuit in a word system or a long format.

  The present invention has the following effects. Since the batch processing circuit for accessing a plurality of registers simultaneously is provided, the host can access the registers of the serial communication controller at high speed.

Hereinafter, a configuration example of a serial communication controller according to the present invention will be described with reference to FIG. However, the same reference numerals are given to the same configuration as the conventional one, and the description is omitted.

The batch processing circuit 100 includes a registration address / decoding circuit 110 and an address registration register 120, and is used when accessing the registers 40, 50, 60 in a unit.

The address registration register 120 is a set address register and collectively stores addresses (A3, A2, A1, A0) of registers accessed from the host 10.

Specifically, the address registration register 120 includes set address registers SAR1, SAR2, SAR3, and SAR4 shown in FIGS. , 50, 60,... Can be stored, and read / write from the host 10 side is also possible.

Here, the outline of FIGS. 2 and 3 will be described. FIG. 2 shows the definition of interrupt priority, and FIG. 3 shows an example of bit allocation of specific registers (registers 40, 50, 60) corresponding to the definition of interrupt priority.

In FIG. 2, the rows SAR1, SAR2, SAR3, and SAR4 in which the offset address Offset is the area Y, that is, “0 * 10” to “0 * 17” are address maps in which the registered addresses are newly added in the present invention. The upper region X is an address map similar to the conventional one.

Among the rows in the added area Y, the registers SAR1, SAR2, SAR3, and SAR4 are set in the address registration register 120, and the remaining rows, that is, fast access registers (FAST Access Registers) FAR1, FAR2, FAR3, and so on. The FAR 4 is set in a registered address / decode circuit 110 described later. When the registers FAR1 to 4 are accessed, the registered address / decode circuit 110 operates. This operation will be described later.

FIG. 3 shows a specific bit allocation example of the register corresponding to the definition of the interrupt priority, and a specific bit allocation example of the fast access registers (FAR1, FAR2, FAR3, FAR4). Indicates.

The registers FAR1, FAR2, FAR3, and FAR4 in this example map the register contents in the conventional register area shown in FIG. 2 corresponding to the designation of the registers SAR1, SAR2, SAR3, and SAR4. The registered address / decode circuit 110 can change the registration of the address map by access from the host.

The selector 200 is based on “register 1 to N select signal after decoding by registered address” input from the batch processing circuit 100 and “conventional compatible register 1 to N select signal” input from the address decoding circuit 20. The conventional method described with reference to FIG. 4 is switched, or the registers 40, 50, 60 are collectively accessed.

Regarding the switching of the selector 200, that is, the switching between “register 1 to N select signal after decoding by registered address” and “conventional compatible register 1 to N select signal”, the host address (A3, A2) given from the host 10 is used. , A1, A0), the switching is controlled by the address A3.

That is, when the registers are accessed together, the register select signal is output based on the contents of the decoded registers 1 to N output from the batch processing circuit 100, and the conventional method as described above is used. In response to this, a register select signal is output based on the decode signal from the address decode circuit 20.

Next, the operation of FIG. 1 will be described. First, when the batch processing circuit 100 is not used for access, the operation is the same as the conventional one. In this case, the selector 200 outputs one of the select signals S400, S500, and S600 based on the address decode circuit 20.

Next, the high-speed operation according to the present invention that accesses a plurality of registers collectively will be described. First, as a setting, the addresses of registers to be collectively accessed are set in the address registration register SAR 120 of the batch processing circuit 100 by an instruction from the host 10 side.

After this setting, the registered address / decode circuit FAR110 is accessed from the host 10 in a word or long manner. As a result, the registered address decoding circuit FAR110 operates and outputs a register select signal registered in the address registration register SAR120.

According to the example of FIG. 3, the register select signal S400, S500, S600 and another register select signal (not shown) are output in addition to these signals.

The selector 200 selects the select signals to the plurality of registers 40, 50, 60,... Based on the “register 1-N select signal after decoding by the registered address” output from the registered address / decode circuit 110 in this way. S400, S500, S600,... Are output.

As described above, the registers 40, 50, 60,... Receive the register select signals S400, S500, S600,... And the read signal or write signal input via the host control line LC. By doing so, since each operates independently, a maximum of four can operate simultaneously (since the host data line LC is 32 bits).

Next, specific setting examples of the registers 40, 50, and 60 will be described with reference to FIGS. As the settings of the set address registers SAR1, SAR2, SAR3, and SAR4 in the address registration register 120, the address of the register RBR (address “0 * 00” shown in FIG. 2) in SAR1 and the address of the register IER in SAR2 (FIG. 2) 2), the register LSR (address “0 * 05” shown in FIG. 2) is set in SAR3, and the register MSR (address “0 * 06” shown in FIG. 2) is set in SAR4.

These addresses “0 * 00”, “0 * 01”, “0 * 05”, and “0 * 06” are realized by bit allocation of addresses (A2, A1, A0) in FIG. An example of the specific bit value is as shown in FIG.

In this state, the registers FAR1, FAR2, FAR3, and FAR4 in the registered address decoding circuit 110 are read-accessed by the long method or the word method, so that the four registers 40, 50, 60,. At the same time, register select signals S400, S500, S600,.

That is, the contents of the register RBR (address “0 * 00”) shown in FIG. 2 are set in the register SAR1, and the register FAR1 is read / accessed, whereby the register select signal S400 is output and the contents of the register 40 are read. Is read (FIG. 3A).

Similarly, the contents of the IER (address “0 * 01”) shown in FIG. 2 are set in the register SAR2, and the register FAR2 is read / accessed to output the register select signal S500, and the contents of the register 50 are read. 2 (FIG. 3B), the contents of the LSR (address “0 * 05”) shown in FIG. 2 are sequentially set in the register SAR3, and the register FAR3 is read / accessed, whereby the register select signal S600 is set. Will be output.

As described above, the register select signals S400, S500, and S600 are simultaneously applied to the registers 40, 50, and 60, so that a plurality of registers can be accessed simultaneously.

The registers 40, 50, 60,... Are simultaneously output to the 8-bit register 1 data line LRD40, the register 2 data line LRD50, the register 3 data line 60,. / Direction definition circuit 30 outputs 32 bits wide to host 10 at the same time.

  As described above, since the plurality of registers can be accessed at once, the control speed of the serial communication controller from the host 10 is quadrupled.

  An application example of the present invention will be described. In the example of FIG. 1, three registers (registers 40, 50, 60) are prepared. However, by increasing the number, it is possible to realize further speedup. For example, if eight registers are prepared, the processing speed can be realized up to eight times faster than the conventional one. Further, in the example of FIG. 1, the case of read access has been described, but the same control can be realized for write access.

It is a block diagram of the serial communication controller of this invention. It is a table showing the definition of interrupt priority. It is a bit allocation example of an interrupt register. It is a control block diagram of a 16550 register map compatible register. It is an example of a register map of a 16550 compatible serial controller.

Explanation of symbols

2 Serial communication controller 10 Host 20 Address decode circuit 30 2 Data line selection / direction definition circuit 40 Register 1
50 Register 2
60 register N
100 Batch Processing Circuit 110 Registered Address / Decode Circuit 120 Address Registration Register 200 Selector

Claims (3)

In a serial communication controller that performs read / write access to multiple registers based on the address given by the host,
A serial communication controller comprising a batch processing circuit that simultaneously accesses a plurality of the registers based on an address given from the host. In a serial communication controller that performs read / write access to multiple registers based on the address given by the host,
An address registration register comprising a set address register for storing addresses of a plurality of the registers to be accessed simultaneously based on an address given from the host;
A registered address decoding circuit comprising a fast access register that outputs a register select signal based on the contents stored in the set address register by access from the host;
A serial communication controller, comprising: a selector for controlling switching in response to a signal indicating whether to access the registers individually or simultaneously to access a plurality of registers from the host. 2. The serial communication controller according to claim 1, wherein the host accesses the registered address decoding circuit in a word system or a long format.

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