JP2008198148A - Programmable controller - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem that it takes time to update IO data so that a scan time can not be shortened because an IO module reads data from all IO modules regardless of whether data obtained from the outside is updated in a programmable controller which successively performs program execution and IO data update processing and repeats scanning. <P>SOLUTION: A bit with a different bus is allocated in each IO module, when data obtained from the outside is updated during one scanning, the bit is set to "0" and a CPU module issues an inquiry cycle for reading the allocated bit before IO data update processing, specifies an IO module in which data is updated to read only the specified IO module. Since the number of times for reading IO modules can be reduced, a time needed for updating IO data can be shortened so that a scan time can be shortened. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a programmable controller of a repetitive calculation method using a stored program, and relates to a programmable controller capable of speeding up an IO data update process.

  FIG. 4 shows the configuration of the programmable controller. The programmable controller is composed of a CPU module 10 for executing a program stored therein, IO modules 11 and 12 having IO channels for input / output to / from the outside, and high-function IO modules 13 and 14. These modules are connected by a bus 15. In some cases, a high-function IO module is not included.

  Like the IO modules 11 and 12, the high-function IO modules 13 and 14 have IO channels that perform input and output with the outside, and are modules that have an arithmetic function therein. Hereinafter, it is assumed that the IO module includes a high-function IO module.

  FIG. 5 shows the operation of the programmable controller. The programmable controller alternately repeats a program execution process for executing a program stored therein and an IO data update process for reading data from the IO modules 11 to 14 and writing data to these modules. The program execution process and the subsequent IO data update process are collectively called scan. The programmable controller repeatedly executes this scan. That is, the IO data update process is always performed after the program execution process.

  FIG. 6 shows the configuration of the IO data update table. 6, 20a to 20n are IO module numbers, which correspond to the IO modules 11 to 14 in FIG. 21a to 21n are IO channel numbers, which are provided corresponding to the IO channels built in the IO module 21b. Although not shown, IO channel numbers other than 20b are also provided with IO channel numbers corresponding to the built-in IO channels.

  The IO module numbers 20a to 20n and the IO channel numbers 21a to 21n are unique numbers, and the program executed by the CPU module 10 accesses the IO modules and the IO channels using the unique numbers. For example, in the input data update process, the CPU module 10 reads data from the IO modules 11 to 14 via the bus 15 and writes this data in the memory inside the CPU module 10.

  All IO modules and IO channels that may be accessed by a program executed by the CPU module 10 are registered in this IO data update table. The CPU module 10 performs an update process for all the IO modules and IO channels registered in the IO data update table in the IO data update process.

  FIG. 7 shows the internal configuration of the CPU module 10. In FIG. 7, 30 is a CPU, 31 is a memory, 32 is a bus interface, and 15 is a bus connecting the CPU module 10 and the IO modules 11 to 14. The CPU 30 executes the program to perform the IO data update process. The memory 31 stores an IO data update table and IO data.

  In the program execution process, the CPU 30 reads IO data from the memory 31, performs an update process on the IO data, and writes the IO data again in the memory 31. In this update process, the CPU updates only the necessary bits, but handles 8-bit or 16-bit data at once according to the memory configuration. In the IO data update process, the CPU 30 reads IO data from the IO modules 11 to 14 via the bus interface 32 and writes it to the memory 31. Also, the updated IO data is read from the memory 31, and this IO data is written to the IO modules 11-14.

JP 2005-174042 A

  However, such a programmable controller has the following problems. The CPU module 10 could not know in advance whether the data of the IO modules 11 to 14 has been updated. Therefore, in the IO data update process, the CPU module 10 performs the read process on the IO data of all the IO modules regardless of whether or not the data is actually updated.

  In general, the reading and writing processes via the bus 15 are considerably slower than the reading and writing processes for the memory 31 in the CPU module 10. For this reason, if the number of transfer processes via the bus 15 increases, it takes time for the IO data update process, resulting in a problem that the efficiency of the CPU decreases and the scan time becomes long.

  Further, in a programmable controller having a multi-CPU configuration in which a plurality of CPU modules are connected to the bus 15, the usage rate of the bus 15 is high because a plurality of CPUs access the bus 15, and a wait for using this bus is required. There is also a problem that the time is increased, the efficiency of the CPU is further lowered, and the scanning time is lengthened.

  Therefore, an object of the present invention is to reduce the number of times of reading from the IO module by reducing the read processing of IO data that has not been updated, and to reduce the usage rate of the bus to which the IO module is connected, An object of the present invention is to provide a programmable controller that can shorten the scan time.

In order to solve such a problem, the invention according to claim 1 of the present invention,
In a programmable controller in which a plurality of modules are connected via a bus and repeatedly execute a scan including a program execution process and a subsequent IO data update process.
While collecting data from outside,
A data holding unit for holding the collected data during one scan;
The data held in the data holding unit and the collected data are input, the data is compared, and a comparison unit that outputs a signal indicating whether or not they match,
A bus interface that communicates with other devices connected to the bus and determines the state of the assigned bit based on the output of the comparison unit when inquired;
An IO module comprising:
The program execution process and the IO data update process are executed, different bits of the bus are allocated to the connected IO modules, and an inquiry is made before the IO data update process is performed. A CPU module that identifies the IO module whose data collected based on it is changed, and reads the data of the identified IO module;
Is provided. Since the data of the IO module whose data has not been updated is not read, the scan time can be shortened.

The invention according to claim 2 is the invention according to claim 1,
In the inquiry, the IO module does not return a response, and the CPU module ends the inquiry cycle after a predetermined time. The access time can be shortened.

The invention according to claim 3 is the invention according to claim 1 or claim 2,
The inquiry cycle is distinguished from other cycles by signals on the control line and / or address line of the bus. It can be easily distinguished from other cycles.

The invention according to claim 4 is the invention according to any one of claims 1 to 3,
The IO module is divided into a plurality of groups, bits are assigned to distinguish these groups, and bits are assigned to distinguish IO modules within each group. The bit allocated to distinguish the IO module in the group to which the self belongs is enabled when the IO module in the group to which the self belongs is inquired. It is. More IO modules than the number of usable bits can be handled.

The invention according to claim 5 is the invention according to claim 4,
The group is further divided into subgroups. The number of IO modules that can be handled can be further increased.

The invention according to claim 6 is the invention according to claim 4 or claim 5,
A plurality of CPU modules that can become bus masters are provided, and these CPU modules make inquiries only to IO modules related to themselves. The number of inquiry cycles can be reduced.

The invention described in claim 7
In a programmable controller in which a plurality of modules are connected via a bus and repeatedly execute a scan including a program execution process and a subsequent IO data update process.
While collecting data from outside,
A data holding unit for holding the collected data during one scan;
The data held in the data holding unit and the collected data are input, the data is compared, and a comparison unit that outputs a signal indicating whether or not they match,
A bus interface that communicates with other devices connected to the bus and determines the state of the assigned bit based on the output of the comparison unit when the bus is free;
An IO module comprising:
Executes the program execution process and IO data update process, assigns different bits of the bus to the connected IO modules, and reads data composed of bits output by the IO module when the bus is free A CPU module that identifies an IO module whose collected data has been changed based on the read data, and reads the data of the identified IO module;
Is provided. The scan time can be shortened and the inquiry cycle can be eliminated.

The invention according to claim 8 is the invention according to any one of claims 1 to 7,
In addition to data lines, address lines are also used as the allocated bits. The number of IO modules that can be handled at a time can be increased.

As is apparent from the above description, the present invention has the following effects.
According to the first, second, third, fourth, fifth, sixth, seventh and eighth aspects of the invention, different bits of the bus are assigned to the IO module, and the IO module is updated with data fetched from outside during one scan. Sometimes this bit is changed, and the CPU module reads the change flag data composed of the assigned bit in the inquiry cycle before the IO data update process, and reads the data only from the IO module whose data has been updated. I did it.

  Since data is not read from an IO module whose data has not been updated, the number of reads from the IO module can be reduced. For this reason, the IO data update processing time can be shortened, and the scan time can be shortened. Further, since the number of memory accesses is reduced when the reading operation from the IO module is reduced, the scanning time can be further reduced.

  In addition, the number of IO modules that can be handled can be increased by dividing the IO modules into groups and assigning bits indicating whether the data is updated for each group. Furthermore, if a bit indicating whether data is updated is transmitted to the CPU module when the bus is free, an inquiry cycle can be eliminated, and the scan time can be further reduced. is there.

  Hereinafter, the present invention will be described in detail with reference to the drawings. FIG. 1 is a configuration diagram of an IO module built in a programmable controller according to the present invention. Note that elements not related to the invention are omitted. In FIG. 1, reference numeral 40 denotes a field-side interface, to which field devices 41a to 41n are connected via a field bus (not shown). The field devices 41 a to 41 n exchange data via the field side interface 40. A data holding unit 42 temporarily holds data acquired from the field devices 41a to 41n. This data is updated every scan.

  Reference numeral 43 denotes a comparison unit to which data stored in the data holding unit 42 and output data of the field side interface 40 are input. The comparison unit 43 compares these data and outputs the result. The data holding unit 42 stores data at the time when the CPU module previously read data. Therefore, the output of the comparison unit 43 indicates whether or not the data acquired via the field-side interface 40 has been changed since the previous CPU module read the data.

  Reference numeral 44 denotes a bus interface, to which the output of the comparison unit 43 is input. The bus interface 44 has a function of interfacing with the bus 15 similarly to the bus interface 32 of FIG. 7, but also has a function of creating change flag data from the output of the comparison unit 43.

  The change flag data is data indicating whether or not the data of the IO module has been changed, and different bits of the data line of the bus 15 are assigned to each IO module. The CPU module 10 assigns different bits to the connected IO modules when the programmable controller starts operating. The bus interface 44 sets the bit assigned to the IO module to which the bus interface 44 belongs to “0” if the comparison result of the comparison unit 43 is “changed”, and “1” if the bit is not changed. To. All unassigned bits are set to high impedance.

  If all the data lines of the bus 15 are pulled up with resistors, the change flag data is a low level only for the bit corresponding to the IO module whose data has been changed, and the bit for which the data of the corresponding IO module has not been changed. , And a bit to which no IO module is assigned goes high. Therefore, only by referring to the change flag data, the CPU module can know which IO module data has been changed.

  FIG. 2 is a flowchart showing the operation of the programmable controller according to this embodiment. In addition, the description which is not related to the present invention is omitted. In FIG. 2, the CPU module assigns different bits to the connected IO module in step (P2-1). As a result, the bus interface in each IO module sets the bits other than the assigned bits to high impedance, and reflects the output of the comparison unit 43 in the assigned bits.

  Next, in step (P2-2), the CPU module issues an inquiry cycle and reads the change flag data. Then, the IO module whose data has been changed is specified from the change flag data read in step (P2-3), and the change flag data is cleared in step (P2-4). That is, all bits are set to “1”.

  In step (P2-5), a transfer cycle is issued to the identified IO module, and data is read. Data of the IO module corresponding to the bit that is “1” in the change flag data is not read. In step (P-6), the process waits until the next scan and returns to step (P2-2).

  In this embodiment, since an inquiry cycle is added, the number of bus cycles increases, but the number of reads from the IO module decreases, resulting in a decrease in the number of bus accesses and a reduction in scan time. In particular, the effect is increased when there are many IO modules to be used.

  Since the “inquiry cycle” in which the CPU module reads the change flag data is not intended for a specific IO module, the IO module that has received the “inquiry cycle” does not output a response signal. The CPU module does not expect a response signal and ends this cycle after a certain time. Whether or not it is an “inquiry cycle” is discriminated by using a control line and an address line (whichever is sufficient) of the bus 15.

  When the number of connected IO modules is large and cannot correspond one-to-one to the bits of the data line of the bus 15, a plurality of change flag data are used. This embodiment will be described with reference to FIG. In this embodiment, it is assumed that the number of connected IO modules is 12 (M1 to M12) and the number of bits of the change flag data is 4.

  In this embodiment, four change flag data are used. The IO modules M1 to M12 are divided into three groups (M1 to M4, M5 to M8, and M9 to M12), and each bit of one of the change flag data (change flag data 1) is assigned to the group. That is, group 1 (M1 to M4) is assigned to bit 0, group 2 (M5 to M8) is assigned to bit 1, and group 3 (M9 to M12) is assigned to bit 2.

  Then, different change flag data is assigned to each group, and different bits are assigned to the IO modules in each group. In FIG. 3, bit 0 is assigned to M1, M5, and M9, bit 1 is assigned to M2, M6, and M10, bit 2 is assigned to M3, M7, and M11, and bit 3 is assigned to M4, M8, and M12.

  The CPU module first queries the change flag data 1. If all the bits of this data are “1”, the data of all the IO modules are not changed, so that reading is not performed. If there is a bit that is “0”, the change flag data of the group corresponding to that bit is read, the IO module whose data has been changed is specified, and only the data of that IO module is read. In this way, when the data of all the IO modules has not been changed, only the change flag data 1 needs to be read, so that the number of inquiry cycles can be reduced.

  It is possible to use three change flag data and assign the IO modules of M1 to M12 to the bits of these data in order, but in this case, it is not known whether the data has been changed unless all three change flag data are read. Therefore, when the number of IO modules whose data is changed is small or when the data is concentrated on a specific IO module, the number of times of reading the change flag data can be reduced by the assignment shown in FIG.

  If the number of IO modules is large and cannot be accommodated by the assignment shown in FIG. 3, the group may be further divided into subgroups, and change flag data may be assigned to the subgroups. When a plurality of change flag data is used, the data is distinguished by the address line. If there is an unused address line, the bit of the IO module can be assigned to the address line. In this way, the number of IO modules that can be confirmed by one inquiry can be increased.

  In addition, when a plurality of CPU modules serving as bus masters are used and IO modules are grouped as shown in FIG. 3, each CPU module performs an inquiry cycle only for change flag data related to the IO modules that it accesses. If issued, the number of inquiry cycles can be reduced.

  Furthermore, in these embodiments, the change flag data indicating the IO module changed in the inquiry cycle is read, but whether or not the data of the IO module is changed when the bus 15 is not used. Data may be transmitted to the CPU module. In this way, the inquiry cycle can be eliminated, and the speed can be further increased.

It is a block diagram which shows one Example of this invention. It is a flowchart which shows operation | movement of one Example of this invention. It is a figure which shows bit allocation of change flag data. It is a block diagram of a programmable controller. It is a figure which shows operation | movement of a programmable controller. It is a block diagram of IO data update table. It is a block diagram of a CPU module.

Explanation of symbols

10 CPU module 11, 12 IO module 13, 14 High function IO module 15 Bus 20a-20n IO module number 21a-21n IO channel number 30 CPU
31 Memory 32, 44 Bus interface 40 Field side interface 41a-41n Field device 42 Data holding part 43 Comparison part

Claims (8)

In a programmable controller in which a plurality of modules are connected via a bus and repeatedly execute a scan including a program execution process and a subsequent IO data update process.
While collecting data from outside,
A data holding unit for holding the collected data during one scan;
The data held in the data holding unit and the collected data are input, the data is compared, and a comparison unit that outputs a signal indicating whether or not they match,
A bus interface that communicates with other devices connected to the bus and determines the state of the assigned bit based on the output of the comparison unit when inquired;
An IO module comprising:
The program execution process and the IO data update process are executed, different bits of the bus are allocated to the connected IO modules, and an inquiry is made before the IO data update process is performed. A CPU module that identifies the IO module whose data collected based on it is changed, and reads the data of the identified IO module;
A programmable controller comprising:   2. The programmable controller according to claim 1, wherein the IO module does not return a response to the inquiry, and the CPU module ends the inquiry cycle after a predetermined time.   3. The programmable controller according to claim 1, wherein the inquiry cycle is distinguished from other cycles by a signal on a control line and / or an address line of the bus.   The IO module is divided into a plurality of groups, bits are assigned to distinguish these groups, and bits are assigned to distinguish IO modules within each group. The allocated bit is enabled to distinguish the I / O module, and when querying the IO module in the group to which the self belongs, the allocated bit is enabled to distinguish the IO module in the group. The programmable controller according to any one of claims 1 to 3, wherein:   The programmable controller according to claim 4, wherein the group is further divided into subgroups.   6. The programmable according to claim 4, further comprising a plurality of CPU modules capable of becoming a bus master, wherein these CPU modules make an inquiry only to an IO module related to the CPU module. controller. In a programmable controller in which a plurality of modules are connected via a bus and repeatedly execute a scan including a program execution process and a subsequent IO data update process.
While collecting data from outside,
A data holding unit for holding the collected data during one scan;
The data held in the data holding unit and the collected data are input, the data is compared, and a comparison unit that outputs a signal indicating whether or not they match,
A bus interface that communicates with other devices connected to the bus and determines the state of the assigned bit based on the output of the comparison unit when the bus is free;
An IO module comprising:
Executes the program execution process and IO data update process, assigns different bits of the bus to the connected IO modules, and reads data composed of bits output by the IO module when the bus is free A CPU module that identifies an IO module whose collected data has been changed based on the read data, and reads the data of the identified IO module;
A programmable controller comprising:   8. The programmable controller according to claim 1, wherein an address line is also used in addition to a data line as the assigned bit.

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