JP2009296271A - Latch circuit and a/d converter - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a latch circuit and an A/D converter which can secure a bandwidth, reduce an area and power of subsequent stage circuits, and obtain a high accuracy and a high-speed operation. <P>SOLUTION: Latch circuits 130-1 to 130-5 have a plurality of input transistor pairs converting a plurality of different differential input voltage signals into differential currents to be outputted, and include a circuit in which transistors NT131 to NT133 are connected to a first terminal (drain end) of NT134 to NT136 so that a positive electrode polarity/negative polarity of the differential current signals are alternately synthesized and transition portions of the differential input voltage signals are synthesized to generate one folding differential voltage signal. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a latch circuit and an A / D converter.

The A / D converter compares an analog signal input in the comparison operation circuit with a plurality of reference potentials, and performs conversion into a digital code according to the resolution of the reference potential.
This comparison operation circuit requires a circuit array corresponding to the number of reference potentials, and the number of circuits increases as the resolution becomes finer.

An A / D converter that employs a gray binary conversion system has been proposed (see, for example, Patent Document 1).
The A / D converter disclosed in Patent Document 1 requires an extra circuit such as a majority circuit for countermeasures against bubble errors when operating at high speed.
For this reason, an A / D converter for application that requires high resolution and high speed operation has a problem in that the area and power are large.

Therefore, a folding method is known as an existing A / D converter method that can reduce the number of circuits and reduce the area and power (see, for example, Patent Document 2).
This folding method is known to be able to reduce the number of circuits and reduce the area and power by folding analog signals.
In addition, the folding method has a circuit configuration almost the same as that of a so-called flash method, and is suitable for high-speed operation. Therefore, the folding method is suitable for applications that require high speed and high resolution.

  FIG. 1 is a diagram schematically illustrating a main configuration of a general folding A / D converter.

  The A / D converter 1 includes a reference potential comparison calculator unit (preamplifier unit, hereinafter referred to as preamplifier unit) 2, a folding amplifier unit 3, and a latch unit 4.

  The preamplifier unit 2 includes a plurality of preamplifiers 2-1 to 2-5 and 2a-1 to 2a-5 arranged in parallel to the input of the analog signal AIN.

  Each of the preamplifiers 2-1 to 2-5, 2a-1 to 2a-5 compares the analog signal AIN with different reference potentials REF1 to REF5 and REF1a to REF5a, and the result is a differential output signal VIP1, VIN1 to VIN1a. ~ Output as VIP5a and VIN5a.

  The folding amplifier unit 3 includes a plurality of folding amplifiers 3-1 and 3-2.

  The folding amplifier 3-1 receives the differential output signals VIP 1, VIN 1 to VIP 5, VIN 5 from the plurality of preamplifiers 2-1 to 2-5 and alternately loops back and overlaps these signals to produce a folded differential output waveform S 3. -1 is generated.

  The folding amplifier 3-2 receives the differential output signals VIP1a, VIN1a to VIP5a, and VIN5a from the plurality of preamplifiers 2-1a to 2-5a, and folds these output signals alternately to superimpose and overlap them. -2 is generated.

FIG. 2 is a circuit diagram illustrating a configuration example of the folding amplifier.
The folding amplifiers 3-1 and 3-2 have the same configuration, and FIG. 2 shows a configuration corresponding to the folding amplifier 3-1.

  The folding amplifier 3-1 has differential pair circuits 31 to 35, load resistance elements R1 and R2, and nodes ND31 and ND32.

The differential pair circuit 31 includes n-channel MOS (NMOS) transistors NT11 and NT12 having sources connected to each other, and an NMOS transistor NT13 as a tail current source connected between a connection point between the sources and a reference potential VSS. have.
One differential output signal VIP1 from the preamplifier 2-1 is supplied to the gate of the NMOS transistor NT11, and the other differential output signal VIN1 is supplied to the gate of the NMOS transistor NT12. Then, the bias voltage VBIAD is supplied to the gate of the NMOS transistor NT13.

The differential pair circuit 32 includes NMOS transistors NT21 and NT22 having sources connected to each other, and an NMOS transistor NT23 serving as a tail current source connected between a connection point between the sources and a reference potential VSS. .
One differential output signal VIP2 from the preamplifier 2-2 is supplied to the gate of the NMOS transistor NT21, and the other differential output signal VIN2 is supplied to the gate of the NMOS transistor NT22. The bias voltage VBIAD is supplied to the gate of the NMOS transistor NT23.

The differential pair circuit 33 includes NMOS transistors NT31 and NT32 having sources connected to each other, and an NMOS transistor NT33 as a tail current source connected between a connection point between the sources and a reference potential VSS. .
One differential output signal VIP3 from the preamplifier 2-3 is supplied to the gate of the NMOS transistor NT31, and the other differential output signal VIN3 is supplied to the gate of the NMOS transistor NT32. The bias voltage VBIAD is supplied to the gate of the NMOS transistor NT33.

The differential pair circuit 34 includes NMOS transistors NT51 and NT52 having sources connected to each other, and an NMOS transistor NT53 as a tail current source connected between a connection point between the sources and a reference potential VSS. .
One differential output signal VIP4 from the preamplifier 2-4 is supplied to the gate of the NMOS transistor NT51, and the other differential output signal VIN4 is supplied to the gate of the NMOS transistor NT42. The bias voltage VBIAD is supplied to the gate of the NMOD transistor NT43.

The differential pair circuit 35 includes NMOS transistors NT51 and NT52 having sources connected to each other, and an NMOS transistor NT53 as a tail current source connected between a connection point between the sources and a reference potential VSS. .
One differential output signal VIP5 from the preamplifier 2-5 is supplied to the gate of the NMOS transistor NT51, and the other differential output signal VIN5 is supplied to the gate of the NMOS transistor NT52. The bias voltage VBIAD is supplied to the gate of the NMOS transistor NT53.

  The drain of the positive polarity NMOS transistor NT11 of the differential pair circuit 31, then the drain of the negative polarity NMOS transistor NT22 of the differential pair circuit 32, then the drain of the positive polarity NMOS transistor NT31 of the differential pair circuit 33, The drain of the negative NMOS transistor NT42 of the dynamic pair circuit 34 and the drain of the positive NMOS transistor NT51 of the differential pair circuit 35 are connected in common to the node ND31.

  The drain of the negative-polarity NMOS transistor NT12 of the differential pair circuit 31, the drain of the positive-polarity NMOS transistor NT21 of the differential pair circuit 32, the drain of the negative-polarity NMOS transistor NT32 of the differential pair circuit 33, and the next difference The drain of the positive polarity NMOS transistor NT41 of the dynamic pair circuit 34 and the drain of the negative polarity NMOS transistor NT52 of the differential pair circuit 35 are connected in common to the node ND32.

The resistor element R1 is connected between the power supply potential VDD and the node ND31, and the connection point between the node ND31 and one end of the resistor element R1 is connected to the output node TVON of the return signal VON.
A resistance element R2 is connected between the power supply potential VDD and the node ND32. A connection point between the node ND32 and one end of the resistance element R2 is connected to an output node TVOP of the return signal VOP.

The folding A / D converter 1 having such a configuration includes folding amplifiers 3-1 and 3-2 for folding an analog signal.
In the loopback amplifiers 3-1 and 3-2, as described above, the positive and negative electrodes of the differential output are alternately connected, and the output voltages VOP and VON are generated by the load resistors R1 and R2.

  FIG. 3 is a diagram showing the relationship between the differential voltage input signal (differential output signal from the preamplifier) to each differential pair circuit of the folded amplifier and the folded differential voltage output.

As shown in FIG. 3, in the folding A / D converter 1, the differential pair circuits 31 to 35 of the folding amplifiers 3-1 and 3-2 receive differential output signals from a plurality of preamplifiers. Then, a folded differential output waveform is generated by alternately folding the signals.
JP-A-11-88174 Japanese Examined Patent Publication No. 7-61018 Japanese Patent No. 3836144

However, a plurality of the drain terminals of the input transistors of the differential pair are connected to the output nodes TVOP and TVON through the nodes ND31 and ND32 by the amount of the folding amplifiers 3-1 and 3-2 described above.
For this reason, the capacitance component seen at the output node increases, and the band is limited by the capacitance and the load resistance elements R1 and R2. Therefore, the area and power increase for high-speed operation.

In particular, in the case of the folding method, unlike the flash method, a large amplitude response greatly affects the signal band, so it is difficult to earn a band.
The reason will be described below.

FIG. 4 is a diagram schematically showing functional blocks and response waveforms of a flash A / D converter.
In FIG. 4, appropriate portions are cut out for the sake of explanation, and in order to facilitate understanding, the same functions as those in FIG. 1 are denoted by the same reference numerals.
In FIG. 4, the input signal and the output waveform of each circuit are shown in differential notation.

  The preamplifiers 2-1 to 2-3 compare the input analog signal AIN with the reference potentials REF1, REF2, and REF3, and output differential signals VO1, VO2, and VO3 as shown in the figure.

A broken line in FIG. 4 indicates a DC response, and a solid line indicates a transient response.
When the input signal AIN crosses the reference potential REF, a signal is output so that the difference signal component is inverted between positive and negative.

The latches 4-1 to 4-3 in the subsequent stage determine 0 when the input differential signal is negative and 1 when the input differential signal is positive, and output the digital signal as a digital code.
Here, when the input signal transitions from REF1 to REF3 at a certain speed, the latch output VO6 needs to be inverted from 0 to 1.
The certain speed of the input signal is the maximum input signal band required for the A / D converter.
At this time, the output VO3 of the preamplifier 2-3 is questioned about settling when the response transitions between large amplitude response ≧ small amplitude response.
Therefore, the band design in the normal flash method is performed mainly by focusing on the response of transition from the large amplitude to the small amplitude.

  FIG. 5 is a diagram schematically showing input / output responses of a general folding A / D converter.

As shown in FIG. 5, in the folding system, the folding amplifier 3-1 receives the outputs of the plurality of preamplifiers 2-1 to 2-3, and outputs one folding waveform VO10 (see Patent Document 3).
This folded A / D converter is configured so as to have shifted transition portions in which differential output signals from preamplifiers do not overlap each other, as disclosed in Patent Document 3.
Thus, it is important for the satisfactory accuracy and linearity of the A / D converter to input the signal to the folding amplifier.
In order to satisfy this condition, all of the plurality of preamplifiers connected to the folding amplifier need to be sufficiently settled.

Therefore, as in the case of the folding method described above, when the transition of the input signal from the reference potential REF1 to the reference potential REF3 at a certain speed is considered, the output VO9 of the preamplifier 2-3 has a response of large amplitude response ≧ small amplitude response. Settling when asked.
The output VO7 of the preamplifier 2-1 and the output VO8 of the preamplifier 2-2 need to be settled when the response transitions from large amplitude response ≧ small amplitude response ≧ large amplitude response.

Therefore, the band design in the folding method is performed by focusing on the response from large amplitude to small amplitude and then to large amplitude.
This is why it is difficult for the folding method to gain bandwidth.
For this reason, in the folding method, the band for generating the folded signal becomes a problem, and the area and power increase.

  An object of the present invention is to provide a latch circuit and an A / D converter that can secure a band, can reduce the area and power of a subsequent circuit, and can realize high-precision and high-speed operation.

  The latch circuit according to the first aspect of the present invention has a plurality of input transistor pairs for converting a plurality of different input differential voltage signals into a difference current and outputting the difference current, and the positive and negative electrodes of each difference current signal are synthesized alternately. As described above, the first terminal of each of the transistors is connected, and a circuit for synthesizing transition portions of the input differential voltage signals to generate one folded difference voltage signal is included.

  An A / D converter according to a second aspect of the present invention includes a plurality of reference potential comparison arithmetic units that compare input analog signals and different reference voltages and output different differential voltage signals, and the plurality of reference potentials. A plurality of different differential voltage signals output from the comparator and receiving a plurality of different differential voltages, converting the differential currents into differential currents, and outputting the difference currents. The circuit has a plurality of input transistor pairs that convert and output the plurality of different input differential voltage signals to output differential currents, and the positive and negative electrodes of each of the differential current signals are alternately synthesized. A first terminal of each transistor is connected, and a circuit for synthesizing a transition portion of each input differential voltage signal to generate one folded difference voltage signal is included.

  Preferably, the latch circuit includes a first input circuit having a plurality of input transistors on one side of the plurality of input transistor pairs and a second input having a plurality of input transistors on the other side of the plurality of input transistor pairs. A circuit, the connection node, a first output node connected to a power supply, a second output node connected to the power supply, and a current source element connected between the connection node and a reference potential, In the first input circuit, the first terminals of the plurality of input transistors on one side are connected in common, the connection point is connected to the first output node, and the second terminals of the plurality of input transistors on the one side. Are connected in common, the connection point is connected to the connection node, and the control terminals of the plurality of input transistors on one side receive positive and negative signals among a plurality of different input differential voltage signals. The second input circuits are connected to each other, the first terminals of the plurality of input transistors on the other side are connected in common, the connection point is connected to the second output node, and the plurality of inputs on the other side. The second terminals of the transistors are connected in common, the connection point is connected to the connection node, and a plurality of different input differentials supplied to the first input circuit are connected to the control terminals of the plurality of input transistors on the other side. Negative and positive signals that are paired with voltage signals are alternately supplied.

  Preferably, the latch circuit includes a first switch forming the current source element, a second switch connected between the first output node and the power source, and between the second output node and the power source. A first switch, and the second switch and the third switch are complementarily turned on and off.

  Preferably, a second latch circuit for converting the signal amplitude to a logic level is arranged after each latch circuit.

  According to the present invention, it is possible to secure a bandwidth, reduce the area and power of the subsequent circuit, and realize high-precision and high-speed operation.

  Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

FIG. 6 is a diagram illustrating a configuration example of a folding type A / D converter employing the latch circuit according to the embodiment of the present invention.
FIG. 6 shows a 4-bit A / D converter as an example.

As shown in FIG. 6, the A / D converter 100 includes a reference potential generation unit 110, a preamplifier unit 120, a first latch unit 130, a majority circuit unit 140, a second latch circuit unit 150, a D-type flip-flop (FF). ) Unit 160, encoder 170, and upper bit converter 180.
The A / D converter 100 includes inverters INV1 to INV5.
In the following description, the latch circuit is simply referred to as a latch.

The reference potential generation unit 110 is configured by a resistor ladder (not shown) connected in series between the power supply potential VDD and the reference potential VSS, for example.
The reference potential generation unit 110 generates a plurality (15 in this embodiment) of reference potentials RF101 to RF1015 and supplies the reference potentials to the corresponding preamplifiers of the preamplifier unit 120.

  The preamplifier unit 120 includes a plurality of preamplifiers 120-1 to 120-15 that are arranged in parallel with respect to the input of the analog signal AIN 100 and serve as reference potential comparison calculators that compare the analog signal AIN 100 with different reference potentials.

  The preamplifier 120-1 compares the analog signal AIN100 with the reference potential REF101 generated by the reference potential generation unit 110, and outputs the result to the latch unit 130 as differential output signals VIP101 and VIN101.

  The preamplifier 120-2 compares the analog signal AIN100 with the reference potential REF102 generated by the reference potential generation unit 110, and outputs the result to the latch unit 130 as differential output signals VIP102 and VIN102.

  The preamplifier 120-3 compares the analog signal AIN100 with the reference potential REF103 generated by the reference potential generation unit 110, and outputs the result to the latch circuit unit 130 as differential output signals VIP103 and VIN103.

  The preamplifier 120-4 compares the analog signal AIN100 with the reference potential REF104 generated by the reference potential generation unit 110, and outputs the result to the latch unit 130 as differential output signals VIP104 and VIN104.

  The preamplifier 120-5 compares the analog signal AIN100 with the reference potential REF105 generated by the reference potential generation unit 110, and outputs the result to the latch unit 130 as differential output signals VIP105 and VIN105.

  The preamplifier 120-6 compares the analog signal AIN100 with the reference potential REF106 generated by the reference potential generation unit 110, and outputs the result to the latch unit 130 as differential output signals VIP106 and VIN106.

  The preamplifier 120-7 compares the analog signal AIN100 with the reference potential REF107 generated by the reference potential generation unit 110, and outputs the result to the latch unit 130 as differential output signals VIP107 and VIN107.

  The preamplifier 120-8 compares the analog signal AIN100 with the reference potential REF108 generated by the reference potential generation unit 110, and outputs the result to the latch unit 130 as differential output signals VIP108 and VIN108.

  The preamplifier 120-9 compares the analog signal AIN100 with the reference potential REF109 generated by the reference potential generation unit 110, and outputs the result to the latch unit 130 as differential output signals VIP109 and VIN109.

  The preamplifier 120-10 compares the analog signal AIN100 with the reference potential REF1010 generated by the reference potential generation unit 110, and outputs the result to the latch unit 130 as differential output signals VIP1010 and VIN1010.

  The preamplifier 120-11 compares the analog signal AIN100 with the reference potential REF1011 generated by the reference potential generation unit 110, and outputs the result to the latch unit 130 as differential output signals VIP1011 and VIN1011.

  The preamplifier 120-12 compares the analog signal AIN100 with the reference potential REF1012 generated by the reference potential generation unit 110, and outputs the result to the latch unit 130 as the differential output signals VIP1012 and VIN1012.

  The preamplifier 120-13 compares the analog signal AIN100 with the reference potential REF1013 generated by the reference potential generation unit 110, and outputs the result to the latch unit 130 as a differential output signal VIP1013 and VIN1013.

  The preamplifier 120-14 compares the analog signal AIN 100 with the reference potential REF 1014 generated by the reference potential generation unit 110, and outputs the result as a differential output signal VIP 1014 and VIN 1014 to the latch unit 130.

  The preamplifier 120-15 compares the analog signal AIN100 with the reference potential REF1015 generated by the reference potential generation unit 110, and outputs the result to the latch unit 130 as a differential output signal VIP1015, VIN1015.

The first latch unit 130 includes a plurality of folding latches 130-1 to 130-5.
Each folding latch 130-1 to 130-5 has a plurality of input transistor pairs that convert a plurality of different input differential voltage signals into differential currents and output them, and the positive and negative electrodes of each differential current signal are alternately synthesized. As shown, the first terminal of the transistor, for example, (drain end) is connected.
The folding latch circuits 130-1 to 130-5 synthesize the transition portions of the input differential voltage signals to generate one folding difference voltage signal.

Folding latch 130-1 receives differential output signals VIP101 and VIN101 of preamplifier 120-1, differential output signals VIP106 and VIN106 of preamplifier 120-6, and differential output signals VIP1011 and VIN1011 of preamplifier 120-11.
The folding latch 130-1 combines the transition portions of these input differential voltage signals to generate one folding difference voltage signal VON 131, VOP 131 and outputs it to the majority circuit section 140.

Folding latch 130-2 receives differential output signals VIP102 and VIN102 of preamplifier 120-2, differential output signals VIP107 and VIN107 of preamplifier 120-7, and differential output signals VIP1012 and VIN1012 of preamplifier 120-12.
The folding latch 130-2 combines the transition portions of these input differential voltage signals to generate one folding difference voltage signals VON 132 and VOP 132, and outputs them to the majority circuit section 140.

The folding latch 130-3 receives the differential output signals VIP103 and VIN103 of the preamplifier 120-3, the differential output signals VIP108 and VIN108 of the preamplifier 120-8, and the differential output signals VIP1013 and VIN1013 of the preamplifier 120-13.
The folding latch 130-3 combines the transition portions of these input differential voltage signals to generate one folding difference voltage signal VON 133, VOP 133 and outputs it to the majority circuit section 140.

Folding latch 130-4 receives differential output signals VIP104 and VIN104 of preamplifier 120-4, differential output signals VIP109 and VIN109 of preamplifier 120-9, and differential output signals VIP1014 and VIN1014 of preamplifier 120-14.
The folding latch 130-4 combines the transition portions of these input differential voltage signals to generate one folding difference voltage signal VON 134, VOP 134 and outputs it to the majority circuit section 140.

Folding latch 130-5 receives differential output signals VIP105 and VIN105 of preamplifier 120-5, differential output signals VIP1010 and VIN1010 of preamplifier 120-10, and differential output signals VIP1015 and VIN1015 of preamplifier 120-15.
The folding latch 130-5 combines the transition portions of these input differential voltage signals to generate one folding difference voltage signals VON 135 and VOP 135, and outputs them to the majority circuit section 140.

FIG. 7 is a circuit diagram illustrating a configuration example of the folding latch of the first latch unit according to the present embodiment.
The folding latches 130-1 to 130-5 have the same configuration, and FIG. 7 shows a configuration corresponding to the first latch.

  The folding latch 130 (-1) includes a first input circuit 131, a second input circuit 132, a first switch 133, a second switch 134, a third switch 135, a first output node ND131, a second output node ND132, and a connection. A node ND133 is included.

  The first input circuit 131 includes NMOS transistors NT131, NT132, NT133, and nodes ND134, ND135.

The drains (first terminals) of the NMOS transistors NT131, NT132, NT133 are commonly connected to the node ND134, and their sources (second terminals) are commonly connected to the node ND135.
The node ND134 is connected to the output node ND131, and the node ND135 is connected to the connection node ND133.
The positive output (one) differential output signal VIP101 from the preamplifier 120-1 is supplied to the gate (control terminal) of the NMOS transistor NT131.
The negative output (VIN) differential output signal VIN106 from the preamplifier 120-6 is supplied to the gate of the NMOS transistor NT132.
The positive output (one) differential output signal VIP1011 from the preamplifier 120-11 is supplied to the gate of the NMOS transistor NT133.

  The second input circuit 132 includes NMOS transistors NT134, NT135, NT136, and nodes ND136, ND137.

The drains (first terminals) of the NMOS transistors NT134, NT135, NT136 are commonly connected to the node ND136, and their sources (second terminals) are commonly connected to the node ND137.
The node ND136 is connected to the output node ND132, and the node ND137 is connected to the connection node ND133.
A negative output (the other) differential output signal VIN101 from the preamplifier 120-1 is supplied to the gate (control terminal) of the NMOS transistor NT134.
The positive output (one) differential output signal VIP106 from the preamplifier 120-6 is supplied to the gate of the NMOS transistor NT135.
The differential output signal VIN1011 on the negative side (the other side) from the preamplifier 120-11 is supplied to the gate of the NMOS transistor NT136.

The first switch 133 is connected between the reference potential VSS and the node ND133, and is turned on / off according to the level of the clock VCK.
In the present embodiment, the first switch 133 is formed by an NMOS transistor NT137 as a current source element.
The drain of the NMOS transistor NT137 is connected to the node ND135 of the first input circuit 131 and the node ND137 of the second input circuit 132 through the connection node ND133.
The source of the NMOS transistor NT137 is connected to the reference potential VSS.
The gate of the NMOS transistor NT137 is connected to the supply line of the clock VCK.
The NMOS transistor 137 forming the first switch 133 functions as a current source for the first input circuit 131 and the second input circuit 132 when the clock VCK is at a high level.

The second switch 134 is connected between the power supply potential VDD and the first output node ND131, and is turned on / off according to the level of the clock VCK.
In the present embodiment, the second switch 134 is formed by a PMOS transistor PT131.
The source of the PMOS transistor PT131 is connected to the power supply potential VDD, and the drain is connected to the first output node ND131.
The gate of the PMOS transistor PT131 is connected to the supply line of the clock VCK.
The PMOS transistor 131 forming the second switch 134 functions as a precharge circuit for the first input circuit 131 when the clock VCK is at a high level.

The third switch 135 is connected between the power supply potential VDD and the second output node ND132, and is turned on / off according to the level of the clock VCK.
In the present embodiment, the third switch 135 is formed by a PMOS transistor PT132.
The source of the PMOS transistor PT132 is connected to the power supply potential VDD, and the drain is connected to the second output node ND132.
The gate of the PMOS transistor PT132 is connected to the supply line of the clock VCK.
The PMOS transistor 132 forming the third switch 135 functions as a precharge circuit for the second input circuit 132 when the clock VCK is at a high level.

In the present embodiment, the first switch 133, the second switch 134, and the third switch 135 are complementarily turned on and off according to the level of the clock VCK.
The clock VCK is supplied to each of the latches 130-1 to 130-5 via, for example, inverters INV1 and INV2.
The operation of the latch 130 having such a configuration will be described in detail later.

  The majority circuit unit 140 includes a plurality of majority circuits 140-1 to 140-5 provided corresponding to the respective latches 130-1 to 130-5 of the first latch unit 130 for measures against bubble errors.

The majority circuit 140-1 performs majority processing based on a signal obtained by inverting the output signal of the preceding latch 130-1, the output signal of the latch 130-2, and the output signal of the latch 130-5 by the inverter INV3. The result is output to the second latch unit 150.
Specifically, the majority decision circuit 140-1 is supplied with the folding difference voltage signals VON131 and VOP131 from the latch 130-1, and is supplied with the folding difference voltage signals VON132 and VOP132 from the latch 130-2.
The majority circuit 140-1 is supplied with a signal obtained by inverting the folding difference voltage signals VON135 and VOP135 by the latch 130-5 by the inverter INV3.

The majority circuit 140-2 performs majority processing based on the output signal of the latch 130-1 in the previous stage, the output signal of the latch 130-2, and the output signal of the latch 130-3, and the result is sent to the second latch unit 150. Output.
More specifically, the majority circuit 140-2 is supplied with the folding difference voltage signals VON131 and VOP131 from the latch 130-1, and is supplied with the folding difference voltage signals VON132 and VOP132 from the latch 130-2.
Further, the majority circuit 140-2 is supplied with the folding difference voltage signals VON133 and VOP133 by the latch 130-3.

The majority circuit 140-3 performs majority processing based on the output signal of the previous latch 130-2, the output signal of the latch 130-3, and the output signal of the latch 130-4, and the result is sent to the second latch unit 150. Output.
Specifically, the majority circuit 140-3 is supplied with the folding difference voltage signals VON132 and VOP132 from the latch 130-2, and is supplied with the folding difference voltage signals VON133 and VOP133 from the latch 130-3.
Further, the majority circuit 140-3 is supplied with the folding difference voltage signals VON134 and VOP134 from the latch 130-4.

The majority circuit 140-4 performs majority processing based on the output signal of the latch 130-3 in the previous stage, the output signal of the latch 130-4, and the output signal of the latch 130-5, and the result is sent to the second latch unit 150. Output.
More specifically, the majority circuit 140-4 is supplied with the folding difference voltage signals VON134 and VOP134 from the latch 130-4, and is supplied with the folding difference voltage signals VON134 and VOP134 from the latch 130-4.
Further, the majority circuit 140-4 is supplied with the folding difference voltage signals VON135 and VOP135 from the latch 130-5.

The majority circuit 140-5 performs majority processing based on the output signal of the previous latch 130-4, the output signal of the latch 130-5, and the signal obtained by inverting the output signal of the latch 130-1 by the inverter INV4. The result is output to the second latch unit 150.
More specifically, the majority circuit 140-5 is supplied with the folding difference voltage signals VON134 and VOP134 from the latch 130-4, and is supplied with the folding difference voltage signals VON135 and VOP135 from the latch 130-5.
The majority circuit 140-5 is supplied with a signal obtained by inverting the folded difference voltage signals VON131 and VOP131 by the latch 130-1 by the inverter INV4.

  The second latch unit 150 receives the output signals of the majority circuits 140-1 to 140-5 in the previous stage, secures the setup time of each signal, and amplifies (converts) the signal amplitude to a logic level. -1 to 150-5.

  The latch 150-1 receives the output signal of the majority circuit 140-1 in the preceding stage, ensures the setup time of the signal, amplifies the signal amplitude to a logic level, and outputs the amplified signal to the D-type FF unit 160.

  The latch 150-2 receives the output signal of the majority circuit 140-2 in the previous stage, secures the setup time of the signal, amplifies the signal amplitude to a logic level, and outputs it to the D-type FF unit 160.

  The latch 150-3 receives the output signal of the majority circuit 140-3 in the previous stage, secures the setup time of the signal, amplifies the signal amplitude to a logic level, and outputs the amplified signal to the D-type FF unit 160.

  The latch 150-4 receives the output signal of the majority circuit 140-4 in the previous stage, secures the setup time of the signal, amplifies the signal amplitude to a logic level, and outputs it to the D-type FF unit 160.

  The latch 150-5 receives the output signal of the majority circuit 140-5 in the previous stage, secures the setup time of the signal, amplifies the signal amplitude to a logic level, and outputs it to the D-type FF unit 160.

FIG. 8 is a circuit diagram showing a configuration example of the latch of the second latch unit according to the present embodiment.
The second latches 150-1 to 150-5 have the same configuration, and FIG. 8 shows a configuration corresponding to the second latch 150-1.

The latch 150 (-1) includes inverters 151 and 152, a switch 153, and a node ND151.
The latch 150 is configured by cross-coupling the inputs and outputs of the inverter 151 and the inverter 152.

  Inverter 151 includes PMOS transistor PT151, NMOS transistors NT151 and NT152, and nodes ND152 and ND153.

In the inverter 151, the source of the PMOS transistor PT151 is connected to the node ND151, the drain is connected to the drains of the NMOS transistors NT151 and NT152, and an output node ND153 of the inverter 151 is formed by these connection points.
The gate of the PMOS transistor PT151 and the gate of the NMOS transistor NT151 are connected, and an input node ND152 of the inverter 151 is formed by the connection point.
The sources of the NMOS transistors NT151 and NT152 are connected to the reference potential VSS.
The gate of the NMOS transistor NT152 is supplied with the differential voltage signal VIP having a positive side.

  Inverter 152 includes PMOS transistor PT152, NMOS transistors NT153 and NT154, and nodes ND154 and ND155.

In the inverter 152, the source of the PMOS transistor PT152 is connected to the node ND151, the drain is connected to the drains of the NMOS transistors NT153 and NT154, and an output node ND155 of the inverter 152 is formed by these connection points.
The gate of the PMOS transistor PT152 and the gate of the NMOS transistor NT153 are connected, and an output node ND153 of the inverter 152 is formed by the connection point.
The sources of the NMOS transistors NT153 and NT154 are connected to the reference potential VSS.
Then, the differential voltage signal VIP having the negative electrode side supplied to the gate of the NMOS transistor NT154 is supplied.

  The input node ND152 of the inverter 151 and the output node ND155 of the inverter 153 are connected, and the input node ND154 of the inverter 152 and the output node ND155 of the inverter 151 are connected.

The switch 153 is connected between the node ND151 and the power supply potential VDD, and is turned on and off by the inverted clock XCLK of the clock VCK.
In this embodiment, the switch 153 is configured by a PMOS transistor PT153.
The source of the PMOS transistor PT153 is connected to the power supply potential VDD, the drain name is connected to the G node ND151, and the gate is connected to the supply line of the inverted clock XVCK.
The inverted clock XVCK is supplied by inverting the level of the clock VCK by the inverter INV1.

In the latch 150-1 having such a configuration, when the inverted clock XVCK is supplied at a low level, the PMOS transistor PT153 is turned on.
In this state, for example, when the signal VIP is supplied at a high level and the signal VIN is supplied at a low level, the NMOS transistor NT152 of the inverter 151 is turned on and the NMOS transistor NT154 of the inverter 152 is turned off.
As a result, the node potential is discharged so that output node ND153 of inverter 151 is at reference potential VSS level, for example, ground potential GND.
As a result, the input node ND154 of the inverter 152 becomes the ground potential (low level), the PMOS transistor PT152 is turned on, and the NMOS transistor NT153 is held in the off state.
As a result, the differential voltage signal VOP is output at a high level. On the other hand, the differential voltage signal VON is output at a low level.
As the output node ND155 becomes high level, the PMOS transistor PT151 of the inverter 151 is held in the off state, and the NMOS transistor NT151 is held in the on state. As a result, the node ND153 is stably held at the low level.

Similarly, when the inverted clock XVCK is supplied at a low level, the PMOS transistor PT153 is turned on.
In this state, for example, when the signal VIP is supplied at a low level and the signal VIN is supplied at a high level, the NMOS transistor NT152 of the inverter 151 is turned off and the NMOS transistor NT154 of the inverter 152 is turned on.
As a result, the node potential is discharged such that output node ND155 of inverter 152 is at reference potential VSS level, for example, ground potential GND.
As a result, the input node ND152 of the inverter 151 becomes the ground potential (low level), the PMOS transistor PT151 is turned on, and the NMOS transistor NT151 is held in the off state.
As a result, the differential voltage signal VON is output at a high level. On the other hand, the differential voltage signal VOP is output at a low level.
As the output node ND153 becomes high level, the PMOS transistor PT152 of the inverter 152 is held in the off state, and the NMOS transistor NT153 is held in the on state. As a result, the node ND155 is stably held at the low level.

The D-type FF unit 160 temporarily holds the outputs of the latches 150-1 to 150-5 and outputs them to the encoder 170.
The D-type FF unit 160 includes exclusive OR gates (EXOR) 160-1 to 160-5.

  The EXOR 160-1 takes the exclusive OR of the output of the latch 150-1 and the output of the latch 150-2 and outputs the result to the encoder 170.

  The EXOR 160-2 takes an exclusive OR of the output of the latch 150-2 and the output of the latch 150-3, and outputs the result to the encoder 170.

  The EXOR 160-3 takes an exclusive OR of the output of the latch 150-3 and the output of the latch 150-4, and outputs the result to the encoder 170.

  The EXOR 160-4 takes an exclusive OR of the output of the latch 150-4 and the output of the latch 150-5, and outputs the result to the encoder 170.

  The EXOR 160-5 takes an exclusive OR of the output of the latch 150-5 and the signal obtained by inverting the output of the latch 150-1 by the inverter INV5, and outputs the result to the encoder 170.

  The encoder 170 encodes the outputs of the EXORs 160-1 to 160-5 and outputs a low-order digital code.

  The bit converter 180 receives a plurality of bits of data through the reference potential generator 110, converts the data into an upper 2-bit digital code, and outputs it.

The configuration and function of the A / D converter 100 according to the present embodiment has been described above.
Next, the operation of the folding latches 150-1 to 150-5 of the second latch unit 150, which is a characteristic part of the A / D converter 100 according to the present embodiment, will be considered.
FIG. 9 shows input / output waveforms of the folding latch of FIG.

When the clock VCK is at a low level, the NMOS transistor NT137 is turned off, the PMOS transistors PT131 and PT132 are turned on, and the output nodes ND131 and ND132 are charged to the power supply voltage VDD and precharged.
When the clock VCK is at a high level, the NMOS transistor NT137 is turned on, the PMOS transistors PT131 and PT132 are turned off, and the positive / negative of the differential amount of the input signal voltage is discriminated. Output negative differential voltage. This operation is a latch operation.

If the input signal voltage of one input transistor (for example, transistor NT131) is VIP, the drain terminal of the input transistor is charged to the power supply voltage VDD during the latch operation and operates in the saturation region.
Therefore, the input transistor passes a current value (IDS) obtained by the transconductance (gm) expressed below and the input signal voltage VIP (reference: on analog integrated circuit design technology for Baifukan system LSI).

[Equation 1]
gm = μ · Cox · W / L · (VGS−VT) (Formula 1)
IDS = gm · VIP (Formula 2)

  Here, μ represents electron mobility, Cox represents gate oxide film capacitance per unit area, W represents gate width, L represents gate length, VGS represents gate-source voltage, and VT represents threshold voltage. ing.

In the folding latch 130-1 (to -5), the input transistors NT131, NT132, NT133 of the first input circuit 131 and the input transistors NT134, NT135, NT136 of the second input circuit 132 form an input transistor pair.
Specifically, three input transistor pairs are formed by the input transistor NT131 and the input transistor NT134, the input transistor NT132 and the input transistor NT135, and the input transistor NT133 and the input transistor NT136.

During the latch operation, these three input transistor pairs receive the voltage output of the preamplifier which is the reference potential comparison calculator in the previous stage, and flow currents I1 to I1 and I1 ′ to 3 ′, respectively.
Therefore, the output voltages VOP and VON generated at the output nodes ND131 and ND132 are expressed as follows.

[Equation 2]
VON = VDD− (I1 + I2 + I3) · dt / C (formula 3)
VOP = VDD− (I1 ′ + I2 ′ + I3 ′) · dt / C (formula 4)

Here, VDD indicates the power supply voltage, C indicates the load capacity of the output node, and dt indicates the transition time after the clock VCK becomes high level.
Substituting (Equation.2) into (Equation.3) and (Equation.4), and obtaining the difference, it is as follows.

[Equation 3]
VOP−VON = gm · (ΔI1 + ΔI2 + ΔI3) · dt / C (formula 5)

  However, the input transistors have the same size, and ΔI1 = I1−I1 ′, ΔI2 = I2−I2 ′, and ΔI3 = I3−I3 ′.

Here, in the same manner as in the folding method embodiment (for example, Patent Document 3: Japanese Patent No. 3836144), the input signal of the latch is set so that the transition part of the folding signal is obtained mainly from only the transition part of one preamplifier output signal. Suppose that it was generated.
At this time, in the folding latch 130-1, as shown in FIG. 9, if the transition unit 201 occurs in, for example, the VIP 101 and the VIN 102, the following holds.

[Equation 4]
VIP106 = VIP1011 (formula 6)
VIN106 = VIN1011 (Expression 7)

In addition, the input signal is connected to the input transistor NT131 positively (VIP101), the input transistor NT132 is negatively input (VIN106), and the input transistor NT133 is alternately connected positively and negatively to the positive input signal VIP1011. The drain side is connected.
Therefore, the following equation is established.

[Equation 5]
I2 ′ = I3 (Formula 8)
I2 = I3 ′ (Formula 9)

  Substituting these two equations into (Equation .5) gives the following.

[Equation 6]
VOP−VON = gm · ΔI1 · dt / C (formula 10)

  Similarly, as shown in FIG. 9, when the preamplifier output transition sections 202 and 203 are VIP 106 and VIN 106, and VIP 1011 and VIN 1011, the following occurs.

[Equation 7]
VOP−VON = −gm · ΔI 2 · dt / C (Formula 11)
VOP−VON = gm · ΔI3 · dt / C (Formula 12)

In this way, only a transition of one preamplifier output appears in the output of the latch.
Here, when the transition unit is VIP106 or VIN106, the input differential voltage is connected with the polarity being inverted, so that the sign is inverted as in (Equation .11).
From the above equations, the folding signals VOP and VON as shown in FIG. 9 are output.
For example, latches 150-1 to 15-5 configured as shown in FIG. 8 are used in the subsequent stage to amplify the signal amplitude to a logic level.

Further, if there are five input transistors of the folding latch, it will be folded back 5 times, and if it is 7, it will be folded back 7 times.
Thus, the folded waveform can be generated by the latch operation without using the folded amplifier.
Further, since this circuit does not have a load resistance, it operates at a very high speed as compared with the folded AMP.
According to the present embodiment, it is possible to generate a folding signal without increasing the area and power.

As described above, in the A / D converter 100 according to this embodiment, the folding latches 130-1 to 130-5 are arranged at the subsequent stage of the preamplifiers 120-1 to 120-15.
Further, the A / D converter 100 includes majority circuits 140-1 to 140-5 at the subsequent stage of the folding latch to prevent bubble errors, and further latches 150-1 to 150 to realize high-speed operation. -5 is provided to ensure setup time.

FIG. 10 is a diagram showing a configuration example of a flash type 4-bit A / D converter shown as a comparative example of the A / D converter of FIG.
In the flash type 4-bit A / D converter 100A, the first latch unit, the majority circuit, the second latch unit, and the D-type FF require the same number of elements as the number of preamplifiers.
On the other hand, in the present embodiment, as described above, the folding latches 130-1 to 130-5 are arranged at the subsequent stage of the preamplifiers 120-1 to 120-15. As a result, the signal is folded by the folding latch, and the number of circuits after the folding can be reduced in the same manner as a general folding A / D converter.
Furthermore, since no folding amplifier is used, a high-speed and high-resolution A / D converter can be realized without increasing the area and power.
As described above, in the present embodiment, by folding the signal using the folding latch, the area / power of the subsequent circuit can be reduced, and an A / D converter with high accuracy and high speed operation can be realized.

It is a figure which shows typically the principal part structure of the A / D converter of a general folding system. It is a circuit diagram which shows the structural example of a folding amplifier. It is a figure which shows the relationship between the difference voltage input signal (differential output signal from a preamplifier) to each differential pair circuit of a folding amplifier, and a folding difference voltage output. It is a figure which shows typically the functional block and response waveform of an A / D converter of a flash system. It is a figure which shows typically the input-output response of the A / D converter of a general folding system. It is a figure which shows the structural example of the A / D converter of a folding system which employ | adopted the latch circuit which concerns on embodiment of this invention. It is a circuit diagram which shows the structural example of the folding latch of the 1st latch part which concerns on this embodiment. It is a circuit diagram which shows the structural example of the latch of the 2nd latch part which concerns on this embodiment. It is a figure which shows the input-output waveform of the folding | turning latch of FIG. It is a figure which shows the structural example of the flash | flush system 4 bit A / D converter shown as a comparative example of the A / D converter of FIG.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 100 ... A / D converter, 110 ... Reference potential generation part, 120 ... Preamplifier part, 130 ... First latch circuit part, 140 ... Majority circuit part, 150 ... Second Latch unit, 160... D-type flip-flop unit group, 170... Encoder, 180.

Claims (7)

It has a plurality of input transistor pairs that convert a plurality of different input differential voltage signals into differential currents and output them,
The first terminals of the transistors are connected so that the positive and negative electrodes of the difference current signals are alternately combined, and the transition portions of the input differential voltage signals are combined to generate one folded difference voltage signal. Latch circuit including circuit. A first input circuit having a plurality of input transistors on one side of the plurality of input transistor pairs;
A second input circuit having a plurality of input transistors on the other side of the plurality of input transistor pairs;
The above connection node;
A first output node connected to a power source;
A second output node connected to the power supply;
A current source element connected between the connection node and the reference potential,
The first input circuit includes:
The first terminals of the plurality of input transistors on the one side are connected in common, and the connection point is connected to the first output node,
The second terminals of the plurality of input transistors on one side are connected in common, and the connection point is connected to the connection node;
Positive and negative signals among a plurality of different input differential voltage signals are alternately supplied to the control terminals of the plurality of input transistors on the one side,
The second input circuit is
The first terminals of the plurality of input transistors on the other side are connected in common, and the connection point is connected to the second output node,
The second terminals of the plurality of input transistors on the other side are connected in common, the connection point is connected to the connection node,
2. The negative and positive signals paired with a plurality of different input differential voltage signals supplied to the first input circuit are alternately supplied to the control terminals of the plurality of input transistors on the other side. Latch circuit. A first switch forming the current source element;
A second switch connected between the first output node and a power source;
A third switch connected between the second output node and a power source,
The latch circuit according to claim 2, wherein the first switch, the second switch, and the third switch are complementarily turned on and off. A plurality of reference potential comparators that compare the input analog signal and different reference voltages and output different differential voltage signals;
A plurality of latch circuits that receive a plurality of different differential voltages out of a plurality of different differential voltage signals output from the plurality of reference potential comparison arithmetic units, convert the differential currents into differential currents, and output the differential currents. And
Each of the latch circuits is
A plurality of input transistor pairs that convert and output the differential currents that output the plurality of different input differential voltage signals;
The first terminals of the transistors are connected so that the positive and negative electrodes of the difference current signals are alternately combined, and the transition portions of the input differential voltage signals are combined to generate one folded difference voltage signal. A / D converter including a circuit. The latch circuit is
A first input circuit having a plurality of input transistors on one side of the plurality of input transistor pairs;
A second input circuit having a plurality of input transistors on the other side of the plurality of input transistor pairs;
The above connection node;
A first output node connected to a power source;
A second output node connected to the power supply;
A current source element connected between the connection node and the reference potential,
The first input circuit includes:
The first terminals of the plurality of input transistors on the one side are connected in common, and the connection point is connected to the first output node,
The second terminals of the plurality of input transistors on one side are connected in common, and the connection point is connected to the connection node;
Positive and negative signals among a plurality of different input differential voltage signals are alternately supplied to the control terminals of the plurality of input transistors on the one side,
The second input circuit is
The first terminals of the plurality of input transistors on the other side are connected in common, and the connection point is connected to the second output node,
The second terminals of the plurality of input transistors on the other side are connected in common, the connection point is connected to the connection node,
5. The negative and positive signals paired with a plurality of different input differential voltage signals supplied to the first input circuit are alternately supplied to the control terminals of the plurality of input transistors on the other side. A / D converter. The latch circuit is
A first switch forming the current source element;
A second switch connected between the first output node and a power source;
A third switch connected between the second output node and a power source,
The A / D converter according to claim 5, wherein the first switch, the second switch, and the third switch are complementarily turned on and off. The A / D converter according to any one of claims 4 to 6, wherein a second latch circuit that converts a signal amplitude to a logic level is arranged at a subsequent stage of each latch circuit.

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