JP2013187695A - Comparator and ad converter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a comparator and an AD converter that are capable of reducing kickback noise, which is a factor of degradation of comparison accuracy, and therefore is capable of reducing power consumption.SOLUTION: A comparator includes: at least one input differential pair that makes comparison between an input signal voltage and a reference voltage in synchronization with a clock at the time of a comparison operation; and a bias connection part for connecting an output side terminal of the input differential pair to a bias power supply in synchronization with the clock at the time of a reset operation. The input differential pair performs the comparison operation when the clock is in one phase, and performs the resetting when the clock is in the other phase. The bias connection part connects the output side terminal of the input differential pair to the bias power supply in synchronization with the clock in the other phase and disconnects the output side terminal of the input differential pair from the bias power supply in synchronization with the clock in the one phase. A bias voltage by the bias power supply is set at an intermediate voltage between an upper limit and a lower limit of the reference voltage.

Description

  The present technology relates to a clock-synchronized comparator and an AD converter using the same, which are applied to a receiver in wireless communication, an audio device, a medical instrument, and the like.

  FIG. 1 is a circuit diagram showing a dynamic comparator that operates in synchronization with a general clock and does not consume a steady current.

  1 includes n-channel MOS (NMOS) transistors M1 to M5, p-channel MOS (PMOS) transistors M6 to M11, voltage input terminals TVI1 and TVI2, clock input terminals TCK1 to TCK3, and output terminals TVO1 and TVO2. Have.

The sources of the transistors M2 and M3 are connected to each other, the connection point is connected to the drain of the transistor M1, and the source of the transistor M1 is connected to the reference potential VSS (for example, ground GND).
The drain of the transistor M2 is connected to the source of the transistor M4, and a node ND1 is formed by the connection point. The drain of the transistor M3 is connected to the source of the transistor M5, and a node ND2 is formed by the connection point.
The gate of the transistor M1 is connected to the clock input terminal TCK1, the gate of the transistor M2 is connected to the voltage input terminal TVI1 of the input signal voltage Vin, and the gate of the transistor M3 is connected to the voltage input terminal TVI2 of the reference voltage Vref.

The drain of the transistor M4 is connected to the drain of the transistor M6, and a node ND3 is formed by the connection point. The drain of the transistor M5 is connected to the drain of the transistor MT7, and a node ND4 is formed by the connection point. The sources of the transistors M6 and M7 are connected to the supply line of the power supply voltage VDD.
The gate of the transistor M4 and the gate of the transistor M6 are connected to the node ND4. The gate of the transistor M5 and the gate of the transistor M7 are connected to the node ND3.
The node ND3 is connected to the output terminal TVO1 of the negative phase side voltage Voutm, and the node ND4 is connected to the output terminal TVO2 of the positive phase side voltage Voutp.

The source of the transistor M8 is connected to the supply line of the power supply voltage VDD, and the drain is connected to the node ND3. The source of the transistor M9 is connected to the supply line of the power supply voltage VDD, and the drain is connected to the node ND4.
The source of the transistor M10 is connected to the supply line of the power supply voltage VDD, and the drain is connected to the node ND1. The source of the transistor M11 is connected to the supply line of the power supply voltage VDD, and the drain is connected to the node ND2.
The gates of the transistors M8 and M10 are connected to the clock input terminal TCK2, and the gates of the transistors M9 and M11 are connected to the clock input terminal TCK3.

The comparator 1 having such a configuration has an input differential pair DFP1 including transistors M2 and M3 for comparing the input signal voltage Vin, which is two input voltages, with the reference voltage Vref.
Further, the comparator 1 includes a latch LTC1 as a waveform shaping unit formed by the transistors M4 to M7 and a switch group including the transistors M1 and M8 to M11 for swinging the output voltage to the logic level.

The basic operation of the comparator 1 is synchronized with the two-phase clock CK. When the clock CK is at a high level (H), the transistor M1 is turned on and the transistors M10 and M11 are turned off to perform a comparison operation.
When the clock CK is at a low level (L), the transistor M1 is turned off, the transistors M10 and M11 are turned on, and a reset operation is performed.
At reset, the drain terminals of the input differential pair are all connected to the supply line of the power supply voltage VDD so that the previous comparison result does not affect the next comparison result.

  This type of comparator is applied to an analog-digital (AD) converter (see, for example, Patent Document 1).

JP 2007-318457 A

However, the comparator has the following disadvantages.
Each time the comparison operation and the reset operation are switched, the drain terminals of the transistors M2 and M3 constituting the input differential pair vary greatly. Under the influence, charge is discharged to the input signal voltage Vin and the reference voltage Vref through the two voltage input terminals TVI1 and TVI2 through the parasitic capacitance between the gate and the drain.
This is kickback noise, and the input voltage is contaminated, which may cause an error in the comparison result.

Regarding the voltage input terminal TVI1 of the input signal voltage Vin, a buffer that also functions as an anti-aliasing filter is usually inserted in front of the comparator, or a sufficiently large sampling capacity is prepared to reduce the influence of kickback noise. ing.
On the other hand, the influence of the voltage input terminal TVI2 of the reference voltage Vref is more conspicuous, and since the reference voltage is usually generated by a resistor ladder, the time constant is limited by the input capacitance of the comparator and the resistance value of the ladder, so kickback An error occurs in the reference voltage due to noise.
If this error is to be eliminated, it is necessary to lower the resistance value of the ladder, resulting in an increase in power consumption.

A flash AD converter will be described as one application example of the comparator.
In this case, 80 to 90% of the power consumption is consumed by the reference voltage Vref generation circuit including the resistance ladder. Therefore, reducing the ladder resistance as a measure for kickback noise directly reduces the power consumption of the entire AD converter. It will increase.

  It is an object of the present technology to provide a comparator and an AD converter that can reduce kickback noise, which is a factor that deteriorates comparison accuracy, and can reduce power consumption.

  The comparator according to the first aspect of the present technology includes at least one input differential pair that compares an input signal voltage and a reference voltage in synchronization with a clock during a comparison operation, and the above input in synchronization with a clock during a reset operation. A bias connection for connecting the output side terminals of the differential pair to a bias power supply, and the input differential pair performs a comparison operation when the clock is in one phase and is reset when the clock is in the other phase. The bias connection unit connects an output side terminal of the input differential pair to a bias power source in synchronization with the clock of the other phase, and the input differential pair in synchronization with the clock of the one phase. The output side terminal is disconnected from the bias power source, and the bias voltage by the bias power source is set to an intermediate voltage between the upper limit value and the lower limit value of the reference voltage.

  An AD converter according to a second aspect of the present technology includes at least one comparator that compares an input signal voltage with a reference voltage, and includes an analog-digital (AD) conversion block that converts an input analog signal into a digital signal. The comparator includes at least one input differential pair that compares an input signal voltage with a reference voltage in synchronization with a clock during a comparison operation, and an output side of the input differential pair in synchronization with a clock during a reset operation. A bias connection for connecting a terminal to a bias power source, and the input differential pair performs a comparison operation when the clock is in one phase, and performs a reset operation when the clock is in the other phase. The output terminal of the input differential pair is connected to a bias power supply in synchronization with the clock of the other phase, and the output of the input differential pair is synchronized with the clock of the one phase. Disconnect the positive terminal from the bias power supply, a bias voltage by the bias power source is set to an intermediate voltage between the upper and lower limits of the reference voltage.

  According to the present technology, it is possible to reduce kickback noise, which is a factor that deteriorates the comparison accuracy, and it is possible to reduce power consumption.

It is a circuit diagram showing a dynamic comparator which operates in synchronization with a general clock and does not consume a steady current. It is a circuit diagram which shows the structural example of the comparator which concerns on this embodiment. It is a figure which shows typically the influence of the kickback current in the comparator which concerns on this embodiment, and the comparator of FIG. 1 which is a comparative example. It is a figure which shows the structural example of the AD converter which can apply the comparator which concerns on this embodiment. FIG. 5 is a circuit diagram illustrating a configuration example of a 5-bit binary search circuit in FIG. 4. FIG. 6 is a circuit diagram illustrating a configuration example of a 4-input comparator in FIG. 5. It is a circuit diagram which shows the structural example of a resistance ladder.

Hereinafter, embodiments of the present technology will be described with reference to the drawings.
The description will be given in the following order.
1. 1. Configuration example of comparator Configuration example of AD converter

<1. First Embodiment>
FIG. 2 is a circuit diagram illustrating a configuration example of the comparator according to the present embodiment.

The comparator 100 according to the present embodiment includes NMOS transistors M101 to M105 and M110 to M113, PMOS transistors M106 to M109, and voltage input terminals TVI101 and TVI102.
The comparator 100 has clock input terminals TCK101 to TCK104, reverse phase clock input terminals TXC101 and TXC102, and output terminals TVO101 and TVO102. The comparator 100 includes intermediate voltage input terminals TVb101 and TVb102, and first to sixth nodes ND101 to ND106.

A differential pair transistor of the input differential pair DFP101 is formed by the transistors M102 and M103, and a comparison switch unit is formed by the transistor M101.
Further, a bias connection portion is formed by the transistors M112 and M113.
The transistor M110 and M111 form a connection disconnect switch unit.
A latch LTC101 as a waveform shaping unit is formed by the transistors M104 to M107.

In the present embodiment, the supply line of the power supply voltage VDD corresponds to the first power supply potential, and the reference potential VSS corresponds to the second power supply potential. However, the first power supply potential and the second power supply potential may be reversed.
In this embodiment, the comparison operation is performed when the clock CK is in one phase (rising, first level, for example, high level), and reset is performed when the clock CK is in the other phase (falling, second level, or low level). . However, one phase and the other phase of the clock CK may be reversed.

The sources of the transistors M102 and M103 forming the differential pair transistor are connected to each other, the connection point is connected to the drain of the transistor M101, and the source of the transistor M101 is connected to the reference potential VSS (for example, ground GND).
The drain of the transistor M102 is connected to the source of the transistor M110, and a first node ND101 is formed by the connection point. The drain of the transistor M103 is connected to the source of the transistor M111, and the connection point forms a second node ND102.
The gate of the transistor M101 is connected to the clock input terminal TCK101, and the gate of the transistor M102 is connected to the voltage input terminal TVI101 for the input signal voltage Vin. The gate of the transistor M103 is connected to the voltage input terminal TVI102 of the reference voltage Vvef.

The drain of the transistor M110 is connected to the source of the transistor M104, and a fifth node ND105 is formed by the connection point. The drain of the transistor M111 is connected to the source of the transistor M105, and a sixth node ND106 is formed by the connection point.
The drain of the transistor M112 is connected to the input terminal TVb101 of the bias voltage Vb, which is an intermediate voltage, and the source is connected to the first node ND101. The drain of the transistor M113 is connected to the input terminal TVb102 of the bias voltage Vb, and the source is connected to the second node ND102.
The gate of the transistor M110 and the gate of the transistor M111 are connected to the clock input terminal TCK102.
The gate of the transistor M112 is connected to the input terminal TXC101 of the reverse phase clock xCK of the clock CK, and the gate of the transistor M113 is connected to the input terminal TXC102 of the reverse phase clock xCK.

  Here, the intermediate voltage that defines the bias voltage Vb refers to a voltage between the upper limit value Vrefp and the lower limit value Vrefm (intermediate value) of the reference voltage Vref that is not at the power supply or ground level.

The drain of the transistor M104 is connected to the drain of the transistor M106, and the connection point forms the third node ND103. The drain of the transistor M105 is connected to the drain of the transistor M107, and the connection point forms a fourth node ND104. The sources of the transistors M106 and M107 are connected to the supply line of the power supply voltage VDD.

The gate of the transistor M104 and the gate of the transistor M106 are connected to the fourth node ND104. The gate of the transistor M105 and the gate of the transistor M107 are connected to the third node ND103.
The third node ND103 is connected to the output terminal TVO101 of the negative phase side voltage Voutm, and the fourth node ND104 is connected to the output terminal TVO102 of the positive phase side voltage Voutp.

The source of the transistor M108 is connected to the supply line of the power supply voltage VDD, and the drain is connected to the third node ND103. The source of the transistor M109 is connected to the supply line of the power supply voltage VDD, and the drain is connected to the fourth node ND104.
The gate of the transistor M108 is connected to the clock input terminal TCK103, and the gate of the transistor M109 is connected to the clock input terminal TCK104.

The comparator 100 having such a configuration includes an input differential pair DFP101 composed of transistors M102 and M103 for comparing the input signal voltage Vin, which is two input voltages, with the reference voltage Vref.
Further, the comparator 100 includes a latch LTC101 formed by the transistors M104 to M107 and a switch group including the transistors M101 and M108 to M113 for swinging the output voltage to the logic level.

The basic operation of the comparator 101 operates in synchronization with the two-phase clock CK.
Here, the first phase of the clock CK is at a high level (H), and the second phase is at a low level (L).
When the clock CK is at a high level (H), the comparator 100 performs the comparison operation by turning on the transistors M101, M110, and M111 and turning off the transistors M108, M109, M112, and M113.
When the clock CK is at a low level (L), the transistors M101, M110, and M111 are turned off, the transistors M108, M109, M112, and M113 are turned on, and a reset operation is performed.
At reset, the drain terminals of the input differential pair are all connected to the supply line of the bias voltage Vb, which is an intermediate voltage, so that the previous comparison result does not affect the next comparison result.

Here, the characteristics of the comparator 100 according to the present embodiment will be described using the comparator 1 of FIG. 1 as a comparative example.
FIG. 3 is a diagram schematically illustrating the influence of the kickback current in the comparator according to the present embodiment and the comparator of FIG. 1 which is a comparative example.
In FIG. 3, this circuit is the comparator 100 according to this embodiment, and the comparison circuit is the comparator 1 in FIG. 1.

The difference between the comparator 100 of the present technology and the comparator 1 of FIG. 1 is basically the holding voltage of the drain terminal of the input differential pair DFP at the time of reset.
In other words, the comparator 100 eliminates the transistors (M10 and M11 in FIG. 1) that connect the drain terminals of the input differential pair DFP to the power supply, and instead switches to fix to the appropriate bias voltage (Vb) instead of the power supply. A mechanism (M110 to M113 in FIG. 2) is added.
In the comparator 1 of FIG. 1, the drain terminal of the input differential pair DFP is fixed to the power supply voltage VDD at the time of reset. In this case, when the normal operation is shifted from there, the power supply potential changes to the ground potential.
In the comparator 100 according to the present technology, the change is gradual from the bias voltage Vb to the ground potential, so that kickback noise caused by a change from reset to normal operation is reduced.
Similarly, when shifting from normal operation to reset, the amount of change in voltage can be kept small, so that kickback noise is reduced.

<2. Configuration example of AD converter>
FIG. 4 is a diagram illustrating a configuration example of an AD converter to which the comparator according to the present embodiment can be applied.

4 includes a track and hold circuit (T / H) 210 and a reference voltage generation circuit (Bias) 220 for sampling the differential input voltages Vinp and Vinm.
The AD converter 200 includes a 5-bit binary search circuit 230 that is an actual AD conversion block.
The AD converter 200 converts the input analog signal into a 5-bit digital value.

  The reference voltage generation circuit 220 generates the reference voltages Vref, 1 to Vref, 31 using a normal band gap reference circuit, a buffer, a resistance ladder, and the like.

FIG. 5 is a circuit diagram showing a configuration example of the 5-bit binary search circuit in FIG.
FIG. 6 is a circuit diagram showing a configuration example of the 4-input comparator in FIG.

The comparator 100A shown in FIG. 6 has four inputs in consideration of the removal of common-mode noise and power supply voltage fluctuation, but the present technology is used just like the case of the two-input comparator 100 shown in FIG.
In FIG. 6, the same components as those in FIG. 2 are denoted by the same reference numerals for easy understanding.
The comparator 100A in FIG. 6 has a positive-phase side input differential pair DFP101p formed by transistors M102p and M103p, and a reverse (negative) -phase side input differential pair DFP101m formed by transistors M102m and M103m.
Further, in the comparator 100A, PMOS transistors M114, M115, M116, and M118, and NMOS transistors M117 and M119 are added to the configuration of FIG.

In the positive phase side input differential pair DFP101p, the positive phase side input signal voltage Vinp is supplied to the gate of one transistor M102p of the differential pair transistor, and the positive phase side reference voltage Vrefp is supplied to the gate of the other transistor M103p. The
The drain of the M transistor 102p is connected to the first node ND101, and the drain of the transistor M103p is connected to the second node ND102.

In the reverse side input differential pair DFP101m, the negative phase side input signal voltage Vinm is supplied to the gate of one transistor M102m of the differential pair transistor, and the negative phase side reference voltage Vrefm is supplied to the gate of the other transistor M103m. .
The drain of the transistor M102m is connected to the second node ND102, and the drain of the transistor M103m is connected to the first node ND101.

The source of the transistor M114 is connected to the supply line of the power supply voltage VDD, the drain is connected to the fifth node ND105, and the gate is connected to the clock input terminal TCK103.
The source of the transistor M115 is connected to the supply line of the power supply voltage VDD, the drain is connected to the sixth node ND106, and the gate is connected to the clock input terminal TCK104.
Transistors M114 and M115 form a power connection.
As described above, the comparator 100A in FIG. 6 connects the fifth node ND105 and the sixth node ND106 to the supply line of the power supply voltage VDD so that the comparison result does not affect the next comparison result at the time of reset. Is done.
In this case, since the transistors M110 and M111 as switches are off, kickback noise is not generated.

The source of the transistor M116 is connected to the supply line of the power supply voltage VDD, the drain is connected to the drain of the transistor M117, and the connection point is connected to the output terminal VTO102.
The source of the transistor M117 is connected to the reference potential VSS, and the gates of the transistors M116 and M117 are connected to the third node ND103.
Thus, the output buffer BF101 is formed by the transistors M116 and M117.

The source of the transistor M118 is connected to the supply line of the power supply voltage VDD, the drain is connected to the drain of the transistor M119, and the connection point is connected to the output terminal VTO101.
The source of the transistor M119 is connected to the reference potential VSS, and the gates of the transistors M118 and M119 are connected to the fourth node ND104.
Thus, the output buffer BF102 is formed by the transistors M118 and M119.

A binary search type AD converter requires the same number of comparators as the flash type (2 ^B -1 if the number of output bits is B).
However, in the 5-bit binary search circuit 230, since the output result of the previous-stage comparator is the clock signal of the next-stage comparator group, only the minimum number of comparators necessary for AD conversion are activated and low power consumption is possible. It has the characteristic of being.

In the n-bit (n−5 in this embodiment) binary search circuit 230, 2 ⁿ⁻¹ comparators Comp are arranged in each of n stages.
In the 5-bit binary search circuit 230, one comparator Comp1,1 is arranged in the first stage. The comparators Comp1,1 are supplied with reference voltages Vref, 16, Vref, 16, output voltages Vtp and Vtm of the T / H 210, and a clock CK. The comparator Comp1,1 outputs the voltages V11p and V11m to the next stage.

Two comparators Comp2,1 and Comp2,2 are arranged in the second stage.
The comparator Comp2,1 is supplied with the reference voltages Vref, 8, Vref, 24, the output voltages Vtp, Vtm of the T / H 210, and the output voltage V11p of the first stage as a clock. The comparator Comp2,1 outputs the voltages V21p and V21m to the next stage.
The comparators Comp2, 2 are supplied with the reference voltages Vref, 8, Vref, 24, the output voltages Vtp, Vtm of the T / H 210, and the output voltage V11m of the first stage as a clock. Comparators Comp2, 2 output voltages V22p and V22m to the next stage.

In the third stage, four comparators Comp3,1, Comp3,2, Comp3,3, Comp3,4 are arranged.
The comparator Comp3,1 is supplied with the reference voltages Vref, 4, Vref, 28, the output voltages Vtp, Vtm of the T / H 210, and the output voltage V21p of the previous stage as a clock. The comparator Comp3,1 outputs the voltages V31p and V31m to the next stage.
The comparators Comp3, 2 are supplied with the reference voltages Vref, 12, Vref, 20, the output voltages Vtp, Vtm of the T / H 210, and the output voltage V21m of the previous stage as a clock. The comparator Comp3,2 outputs the voltages V32p and V32m to the next stage.
The comparators Comp3, 3 are supplied with the reference voltages Vref, 12, Vref, 20, the output voltages Vtp, Vtm of the T / H 210, and the output voltage V22p of the previous stage as a clock. Comparators Comp3, 3 output voltages V33p and V33m to the next stage.
The comparators Comp 3 and 4 are supplied with the reference voltages Vref, 4, Vref, 28, the output voltages Vtp and Vtm of the T / H 210, and the output voltage V22m of the previous stage as a clock. Comparators Comp3 and 4 output voltages V34p and V34m to the next stage.

Similarly, eight comparators Comp4,1, Comp4,2, Comp4,3, Comp4,4, Comp4,5, Comp4,6, Comp4,7, Comp4,8 are arranged in the fourth stage.
In the fifth stage, 16 comparators Comp5,1, Comp5,2, Comp5,3, Comp5,4, Comp5,5, Comp5,6, Comp5,7, Comp5,8, Comp5,9, Comp5,10, Comp5 , 11, Comp5, 12, Comp5, 13, Comp5, 14, Comp5, 15, Comp5, 16 are arranged.

In the 5-bit binary search circuit 230, the output voltages Vtp and Vtm of the T / H 210 are supplied to all the comparators as an operation.
The clock CK is input to only one of the comparators Comp1,1 in the front row (first stage), and the output result of the comparator in the front row is obtained by raising the clock. The positive phase output voltage V1p becomes the output MSB to the AD converter 200.
Next, for example, when the voltage V11p is at a high level, the comparator Comp2,1 performs the second bit conversion.
At this time, since the negative phase output voltage V11m of the comparator Comp1,1 is at a low level, the comparator Comp2,2 does not operate and both the voltages V22p and V22m are fixed at a low level.
The output of the second bit of the AD converter 200 is obtained by taking the logical sum of the positive phase output voltages of the comparators Compp2,1 and Comp2,2.
In the same manner, lower bit conversion is performed asynchronously with the clock. I bit of the AD conversion result similarly I-th comparator positive-phase output voltage ^{(VI1p, VI2p ... VI2 I p} ) is obtained by ORing.

In the binary search type AD converter 200, when the clock is supplied to the first comparator for determining the MSB, the bits are determined in a manner that is asynchronous with the clock.
The operation timing of the comparator at the previous stage and the operation timing of the comparator at the next stage are only a delay of one stage of the comparator, and if the reference is not sufficiently settled between them, an error will occur in the comparison result. It is easy to receive.

In a normal design, in order to reduce this error, a large current is passed through the bias bias to keep the impedance of the reference voltage for AD conversion low. However, the kickback noise itself is reduced by using the comparator of the present technology. be able to.
Therefore, the power consumption of the Bias block (reference voltage generation circuit) can be dramatically reduced.
The comparator of the present technology is characterized in that the input differential pair is connected to an appropriate bias voltage Vb at the time of resetting. This voltage is also obtained from a resistor ladder that generates a reference voltage for the AD converter as shown in FIG. be able to.
Here, V _BGR is obtained by buffering the output of the band gap reference circuit. In this way, when the bias voltage Vb is made with the same resistance ladder as the reference voltage, kickback noise is generated for Vb when the operation state of the comparator changes.
If this kickback noise is Ikickback in FIG. 7, the reference voltage can be expressed as follows.

That is, the influence of kickback noise on the bias voltage Vb can be completely canceled by setting R ₁ = R ₂ (Vb is an intermediate voltage between the positive phase and negative phase reference voltages).

As described above, according to the present embodiment, the following effects can be obtained.
As a result of reducing kickback noise, which is a factor that degrades the comparison accuracy of comparator circuits applied to AD converters applied to audio equipment, medical measuring instruments, and other receivers in wireless communications, the result is AD. The power consumption of the converter itself can be reduced.

In addition, this technique can take the following structures.
(1) at least one input differential pair that compares an input signal voltage with a reference voltage in synchronization with a clock during a comparison operation;
A bias connection unit that connects the output side terminal of the input differential pair to a bias power source in synchronization with a clock during a reset operation;
The input differential pair is
Compare operation is performed when the clock is in one phase, reset is performed in the other phase,
The bias connection is
The output side terminal of the input differential pair is connected to the bias power supply in synchronization with the clock of the other phase, and the output side terminal of the input differential pair is disconnected from the bias power supply in synchronization with the clock of the one phase. ,
The bias voltage by the bias power supply is
A comparator that is set to an intermediate voltage between the upper and lower limits of the reference voltage.
(2) A waveform which is connected between the first power supply potential and the output side terminal of the input differential pair, and which shapes and outputs the signal voltage of the comparison result output to the output side terminal during the comparison operation. Shaping section;
It is connected between the output side terminal of the input differential pair and the input side of the waveform shaping unit, and the output side terminal of the input differential pair is connected to the waveform shaping unit in synchronization with the clock of the one phase. The comparator according to (1), further including: a connection disconnecting switch unit that connects and disconnects the output side terminal of the input differential pair and the waveform shaping unit in synchronization with the clock of the other phase.
(3) Connected between the first power supply potential and the connection node of the connection disconnection switch section for disconnecting from the waveform shaping section, and connecting the connection node to the first power supply in synchronization with the clock of the other phase. A comparator connected to the potential, and a power supply connection section that disconnects the connection node from the first power supply potential in synchronization with the clock of the one phase.
(4) The input differential pair is
At least one differential pair transistor formed by two transistors whose sources are connected to each other and that compares an input signal voltage input to each gate with a reference voltage;
The differential pair transistor is connected between the connection point between the sources and the second power supply potential, and the clock is synchronized with the clock of the one phase and the connection point between the sources and the first power supply potential. And a comparison switch unit that enables comparison operation by connecting
The drain which is the output side terminal of one of the two differential pair transistors is connected to the first node, and the drain which is the output side terminal of the other transistor is connected to the second node,
The bias connection is
A switch connected to the bias power source, the first node, and the bias power source and the second node, and connecting the first node and the second node to the bias power source in synchronization with the clock of the other phase The comparator according to any one of (1) to (3).
(5) The input signal voltage and the reference voltage include a positive phase side voltage and a negative phase side voltage,
The input differential pair is
A positive-phase differential pair transistor;
A negative phase side differential pair transistor, and including the positive phase side differential pair transistor,
The positive phase side input signal voltage is supplied to the gate of one transistor, the positive phase side reference voltage is supplied to the gate of the other transistor, the drain of the one transistor is connected to the first node, and the other node The drain of the transistor is connected to the second node;
The negative phase side differential pair transistor is
The negative phase side input signal voltage is supplied to the gate of one transistor, the negative phase side reference voltage is supplied to the gate of the other transistor, the drain of the one transistor is connected to the second node, and the other node The comparator according to (4), wherein a drain of the transistor is connected to the first node.
(6) An analog-digital (AD) conversion block that includes at least one comparator that compares an input signal voltage with a reference voltage and converts an input analog signal into a digital signal;
The comparator is
At least one input differential pair for comparing the input signal voltage and the reference voltage in synchronization with the clock during the comparison operation;
A bias connection unit that connects the output side terminal of the input differential pair to a bias power source in synchronization with a clock during a reset operation;
The input differential pair is
Compare operation is performed when the clock is in one phase, reset is performed in the other phase,
The bias connection is
The output side terminal of the input differential pair is connected to the bias power supply in synchronization with the clock of the other phase, and the output side terminal of the input differential pair is disconnected from the bias power supply in synchronization with the clock of the one phase. ,
The bias voltage by the bias power supply is
An AD converter set to an intermediate voltage between the upper limit value and the lower limit value of the reference voltage.
(7) The comparator is
A waveform shaping unit that is connected between the first power supply potential and the output side terminal of the input differential pair, and that shapes and outputs the signal voltage of the comparison result output to the output side terminal during the comparison operation; ,
It is connected between the output side terminal of the input differential pair and the input side of the waveform shaping unit, and the output side terminal of the input differential pair is connected to the waveform shaping unit in synchronization with the clock of the one phase. The AD converter according to (6), further including a connection disconnecting switch unit that connects and disconnects the output side terminal of the input differential pair and the waveform shaping unit in synchronization with the clock of the other phase.
(8) The comparator is
Connected between the first power supply potential and the connection node of the connection disconnection switch section that disconnects from the waveform shaping section, and connects the connection node to the first power supply potential in synchronization with the clock of the other phase. And a power supply connection section that disconnects the connection node from the first power supply potential in synchronization with the clock of the one phase. The AD converter according to (7).
(9) The input differential pair of the comparator is
At least one differential pair transistor formed by two transistors whose sources are connected to each other and that compares an input signal voltage input to each gate with a reference voltage;
The differential pair transistor is connected between the connection point between the sources and the second power supply potential, and the clock is synchronized with the clock of the one phase and the connection point between the sources and the first power supply potential. And a comparison switch unit that enables comparison operation by connecting
The drain which is the output side terminal of one of the two differential pair transistors is connected to the first node, and the drain which is the output side terminal of the other transistor is connected to the second node,
The bias connection is
A switch connected to the bias power source, the first node, and the bias power source and the second node, and connecting the first node and the second node to the bias power source in synchronization with the clock of the other phase The AD converter according to any one of (6) to (8).
(10) The input signal voltage and the reference voltage include a positive phase side voltage and a negative phase side voltage,
The input differential pair of the comparator is
A positive-phase differential pair transistor;
A negative phase side differential pair transistor, and including the positive phase side differential pair transistor,
The positive phase side input signal voltage is supplied to the gate of one transistor, the positive phase side reference voltage is supplied to the gate of the other transistor, the drain of the one transistor is connected to the first node, and the other node The drain of the transistor is connected to the second node;
The negative phase side differential pair transistor is
The negative phase side input signal voltage is supplied to the gate of one transistor, the negative phase side reference voltage is supplied to the gate of the other transistor, the drain of the one transistor is connected to the second node, and the other node The AD converter according to (9), wherein a drain of the transistor is connected to the first node.
(11) The AD conversion block is
A binary search AD conversion configuration in which a plurality of comparators are arranged in n stages;
Each stage has 2 ^n-1 comparators,
The AD converter according to any one of (6) to (10), wherein the result of the comparator of the previous stage becomes a clock of the comparator group of the next stage.

  DESCRIPTION OF SYMBOLS 100 ... Comparator, M101-M105, M110-M113 ... NMOS transistor, M106-M109 ... PMOS transistor, DFP101 ... Input differential pair, Vb ... Bias voltage, 200 ... AD conversion 210 ... track and hold circuit (T / H), 220 ... reference voltage generation circuit (Bias), 230 ... 5-bit binary search circuit.

Claims (11)

At least one input differential pair for comparing the input signal voltage and the reference voltage in synchronization with the clock during the comparison operation;
A bias connection unit that connects the output side terminal of the input differential pair to a bias power source in synchronization with a clock during a reset operation;
The input differential pair is
Compare operation is performed when the clock is in one phase, reset is performed in the other phase,
The bias connection is
The output side terminal of the input differential pair is connected to the bias power supply in synchronization with the clock of the other phase, and the output side terminal of the input differential pair is disconnected from the bias power supply in synchronization with the clock of the one phase. ,
The bias voltage by the bias power supply is
A comparator that is set to an intermediate voltage between the upper and lower limits of the reference voltage. A waveform shaping unit that is connected between the first power supply potential and the output side terminal of the input differential pair, and that shapes and outputs the signal voltage of the comparison result output to the output side terminal during the comparison operation; ,
It is connected between the output side terminal of the input differential pair and the input side of the waveform shaping unit, and the output side terminal of the input differential pair is connected to the waveform shaping unit in synchronization with the clock of the one phase. The comparator according to claim 1, further comprising: a connection disconnecting switch unit that connects and disconnects the output side terminal of the input differential pair and the waveform shaping unit in synchronization with the clock of the other phase. Connected between the first power supply potential and the connection node of the connection disconnection switch section that disconnects from the waveform shaping section, and connects the connection node to the first power supply potential in synchronization with the clock of the other phase. The power supply connection part which isolate | separates the said connection node from the said 1st power supply potential synchronizing with the clock of said one phase, The comparator of Claim 2. The input differential pair is
At least one differential pair transistor formed by two transistors whose sources are connected to each other and that compares an input signal voltage input to each gate with a reference voltage;
The differential pair transistor is connected between the connection point between the sources and the second power supply potential, and the clock is synchronized with the clock of the one phase and the connection point between the sources and the first power supply potential. And a comparison switch unit that enables comparison operation by connecting
The drain which is the output side terminal of one of the two differential pair transistors is connected to the first node, and the drain which is the output side terminal of the other transistor is connected to the second node,
The bias connection is
A switch connected to the bias power source, the first node, and the bias power source and the second node, and connecting the first node and the second node to the bias power source in synchronization with the clock of the other phase The comparator according to claim 1. The input signal voltage and the reference voltage include a positive phase side voltage and a negative phase side voltage,
The input differential pair is
A positive-phase differential pair transistor;
A negative phase side differential pair transistor, and including the positive phase side differential pair transistor,
The positive phase side input signal voltage is supplied to the gate of one transistor, the positive phase side reference voltage is supplied to the gate of the other transistor, the drain of the one transistor is connected to the first node, and the other node The drain of the transistor is connected to the second node;
The negative phase side differential pair transistor is
The negative phase side input signal voltage is supplied to the gate of one transistor, the negative phase side reference voltage is supplied to the gate of the other transistor, the drain of the one transistor is connected to the second node, and the other node The comparator according to claim 4, wherein a drain of the transistor is connected to the first node. An analog-to-digital (AD) conversion block that includes at least one comparator that compares an input signal voltage with a reference voltage and converts an input analog signal to a digital signal;
The comparator is
At least one input differential pair for comparing the input signal voltage and the reference voltage in synchronization with the clock during the comparison operation;
A bias connection unit that connects the output side terminal of the input differential pair to a bias power source in synchronization with a clock during a reset operation;
The input differential pair is
Compare operation is performed when the clock is in one phase, reset is performed in the other phase,
The bias connection is
The output side terminal of the input differential pair is connected to the bias power supply in synchronization with the clock of the other phase, and the output side terminal of the input differential pair is disconnected from the bias power supply in synchronization with the clock of the one phase. ,
The bias voltage by the bias power supply is
An AD converter set to an intermediate voltage between the upper limit value and the lower limit value of the reference voltage. The comparator is
A waveform shaping unit that is connected between the first power supply potential and the output side terminal of the input differential pair, and that shapes and outputs the signal voltage of the comparison result output to the output side terminal during the comparison operation; ,
It is connected between the output side terminal of the input differential pair and the input side of the waveform shaping unit, and the output side terminal of the input differential pair is connected to the waveform shaping unit in synchronization with the clock of the one phase. The AD converter according to claim 6, further comprising: a connection disconnecting switch unit that connects and disconnects the output side terminal of the input differential pair and the waveform shaping unit in synchronization with the clock of the other phase. The comparator is
Connected between the first power supply potential and the connection node of the connection disconnection switch section that disconnects from the waveform shaping section, and connects the connection node to the first power supply potential in synchronization with the clock of the other phase. The AD converter according to claim 7, further comprising: a power supply connection section that disconnects the connection node from the first power supply potential in synchronization with the clock of the one phase. The input differential pair of the comparator is
At least one differential pair transistor formed by two transistors whose sources are connected to each other and that compares an input signal voltage input to each gate with a reference voltage;
The differential pair transistor is connected between the connection point between the sources and the second power supply potential, and the clock is synchronized with the clock of the one phase and the connection point between the sources and the first power supply potential. And a comparison switch unit that enables comparison operation by connecting
The drain which is the output side terminal of one of the two differential pair transistors is connected to the first node, and the drain which is the output side terminal of the other transistor is connected to the second node,
The bias connection is
A switch connected to the bias power source, the first node, and the bias power source and the second node, and connecting the first node and the second node to the bias power source in synchronization with the clock of the other phase The AD converter according to claim 6, including a unit. The input signal voltage and the reference voltage include a positive phase side voltage and a negative phase side voltage,
The input differential pair of the comparator is
A positive-phase differential pair transistor;
A negative phase side differential pair transistor, and including the positive phase side differential pair transistor,
The positive phase side input signal voltage is supplied to the gate of one transistor, the positive phase side reference voltage is supplied to the gate of the other transistor, the drain of the one transistor is connected to the first node, and the other node The drain of the transistor is connected to the second node;
The negative phase side differential pair transistor is
The negative phase side input signal voltage is supplied to the gate of one transistor, the negative phase side reference voltage is supplied to the gate of the other transistor, the drain of the one transistor is connected to the second node, and the other node The AD converter according to claim 9, wherein a drain of the transistor is connected to the first node. The AD conversion block is
A binary search AD conversion configuration in which a plurality of comparators are arranged in n stages;
Each stage has 2 ^n-1 comparators,
The AD converter according to claim 6, wherein a result of the preceding comparator becomes a clock of a comparator group of the next stage.

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