JP2009290064A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device which can minimize its height-directional size and can reduce its cost. <P>SOLUTION: In the semiconductor device, a second semiconductor chip 17 is bonded to a top surface 38A of a semiconductor integrated circuit 38 and to the upper portion of a first metal wire 15 for electrically connecting a first semiconductor chip 15 with a wiring substrate 11 via a bonding member 18. Also, a third semiconductor chip 21 is bonded to a top surface 42A of a semiconductor integrated circuit 42 and to the upper portion of a second metal wire 19 for electrically connecting a second semiconductor chip 17 to the wiring substrate 11 via a bonding member 22. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor device, and more particularly, to a semiconductor device including a plurality of semiconductor chips stacked on a wiring board.

  As a conventional semiconductor device, there is a semiconductor device (see FIG. 1) configured by stacking a plurality of semiconductor chips on a wiring board.

  FIG. 1 is a cross-sectional view of a conventional semiconductor device.

  Referring to FIG. 1, a conventional semiconductor device 200 includes a wiring board 201, a first semiconductor chip 203, a spacer 204, a second semiconductor chip 205, a spacer 207, and a third semiconductor chip 208. And a sealing resin 209.

  The wiring board 201 includes a wiring board main body 215 and pads 217 to 219. As the wiring board main body 215, for example, a multilayer wiring structure having a plurality of stacked insulating layers and vias and wirings provided in the plurality of insulating layers can be used. The pads 217 to 219 are provided on the upper surface 215A of the wiring board body 215. The pads 217 to 219 are electrically connected to the wiring board main body 215.

  The first semiconductor chip 203 is provided on a chip body 225 in which a semiconductor integrated circuit (not shown) is formed on a semiconductor substrate (not shown), and is electrically connected to the semiconductor integrated circuit. And a plurality of electrode pads 226. The first semiconductor chip 203 is bonded to the upper surface 215A of the wiring board main body 215 by an adhesive film 227 provided on the lower surface 225A of the chip main body 225 (specifically, the back surface of the semiconductor substrate). The chip body 225 is rectangular in plan view.

The plurality of electrode pads 226 are provided on the upper surface 225B side of the chip body. The plurality of electrode pads 226 are arranged in the vicinity of two opposing sides of the chip body 225 so as to form one row. That is, the plurality of electrode pads 226 are arranged so as to constitute two opposing rows. The electrode pad 226 is electrically connected to the pad 217 via the metal wire 231. As a result, the first semiconductor chip 203 is electrically connected to the wiring board 201. As the first semiconductor chip 203, for example, a semiconductor chip for memory can be used. The height _{J 1} metal wire 231 when based on the upper surface 225B of the chip body 225 may be, for example, to 130 .mu.m.

  The spacer 204 is bonded to the upper surface 225 </ b> B of the chip body 225 with an adhesive film 233. The spacer 204 is a member for disposing the second semiconductor chip 205 and the adhesive film 237 above the metal wire 231 so that the metal wire 231 does not contact the second semiconductor chip 205 and the adhesive film 237. As the spacer 204, for example, a silicon substrate can be used. The thickness of the spacer 204 can be set to 150 μm, for example.

  The second semiconductor chip 205 is provided on the chip body 235 having a semiconductor integrated circuit (not shown) formed on a semiconductor substrate (not shown), and is electrically connected to the semiconductor integrated circuit. And a plurality of electrode pads 236. The second semiconductor chip 205 is bonded to the upper surface 204A of the spacer 204 by an adhesive film 237 provided on the lower surface 235A of the chip body 235 (specifically, the back surface of the semiconductor substrate). The chip body 235 is rectangular in plan view. The plurality of electrode pads 236 are provided on the upper surface 235 </ b> B side of the chip body 235.

The plurality of electrode pads 236 are arranged in the vicinity of two opposing sides of the chip body 235 so as to form one row. That is, the plurality of electrode pads 236 are arranged so as to constitute two opposing rows. The electrode pad 236 is electrically connected to the pad 218 via the metal wire 241. As a result, the second semiconductor chip 205 is electrically connected to the wiring board 201. As the second semiconductor chip 205, for example, a semiconductor chip for memory can be used. The height _{J 2} of the metal wires 241 when based on the upper surface 235B of the chip body 235 may be, for example, to 130 .mu.m.

  The spacer 207 is bonded to the upper surface 235 </ b> B of the chip body 235 by an adhesive film 243. The spacer 207 is a member for disposing the third semiconductor chip 208 and the adhesive film 247 above the metal wire 241 so that the metal wire 241 does not contact the third semiconductor chip 208 and the adhesive film 247. As the spacer 207, for example, a silicon substrate can be used. The thickness of the spacer 207 can be set to 150 μm, for example.

  The third semiconductor chip 208 is provided on the chip body 245 having a semiconductor integrated circuit (not shown) formed on a semiconductor substrate (not shown), and is electrically connected to the semiconductor integrated circuit. And a plurality of electrode pads 246. The third semiconductor chip 208 is bonded to the upper surface 207A of the spacer 207 by an adhesive film 247 provided on the lower surface 245A of the chip body 245 (specifically, the back surface of the semiconductor substrate). The chip body 245 has a square shape in plan view.

The plurality of electrode pads 246 are provided on the upper surface 245 </ b> B side of the chip body 245. The plurality of electrode pads 246 are arranged in the vicinity of two opposing sides of the chip body 245 so as to form one row. That is, the plurality of electrode pads 246 are arranged so as to constitute two opposing rows. The electrode pad 246 is electrically connected to the pad 219 via the metal wire 251. Thereby, the third semiconductor chip 208 is electrically connected to the wiring board 201. As the third semiconductor chip 208, for example, a memory semiconductor chip can be used. The height _{J 3} of the metal wire 251 when based on the upper surface 245B of the chip body 245 may be, for example, to 130 .mu.m.

The sealing resin 209 covers the first to third semiconductor chips 203, 205, 208, the spacers 204, 207, the metal wires 231, 241, 251 and the pads 217-219, and the upper surface 215A of the wiring board body 215. Is provided. The sealing resin 209 is a resin for sealing the first to third semiconductor chips 203, 205, 208, the spacers 204, 207, and the metal wires 231, 241, 251 (see, for example, Patent Document 1). ).
JP 2002-261233 A

  However, in the conventional semiconductor device 200, since the first to third semiconductor chips 203, 205, and 208 are stacked via the spacers 204 and 207, there is a problem that the size in the height direction of the semiconductor device 200 cannot be reduced. there were.

  Further, the use of the spacers 204 and 207 has a problem that the cost of the semiconductor device 200 increases.

  Accordingly, the present invention has been made in view of the above-described problems, and an object of the present invention is to provide a semiconductor device capable of reducing the size in the height direction of the semiconductor device and reducing the cost.

  According to one aspect of the present invention, a wiring board, a first semiconductor chip body that is square in plan view and is bonded to the upper surface of the wiring board, and a main surface of the first semiconductor chip body, A first semiconductor chip having a first electrode pad electrically connected to the wiring substrate via a first metal wire; a second semiconductor chip body having a square shape in plan view; A second semiconductor chip provided on the main surface of the semiconductor chip body 2 and having a second electrode pad electrically connected to the wiring board via a second metal wire; A third semiconductor chip body, and a third electrode pad provided on the main surface of the third semiconductor chip body and electrically connected to the wiring board via a third metal wire. A third semiconductor chip having A semiconductor device in which the second and third semiconductor chips are arranged above one semiconductor chip, the second semiconductor in a portion located on the opposite side of the main surface of the second semiconductor chip body The chip body is bonded to the upper part of the first metal wire and the main surface of the first semiconductor chip body, and the main surface of the third semiconductor chip body and the upper surface of the wiring board are substantially parallel. As described above, the third semiconductor chip main body in a portion located on the opposite side of the main surface of the third semiconductor chip main body, the upper portion of the second metal wire and the main surface of the second semiconductor chip main body. A semiconductor device characterized in that the semiconductor device is adhered to is provided.

  According to the present invention, the portion of the second semiconductor chip body located on the opposite side of the main surface of the second semiconductor chip body is placed on the upper portion of the first metal wire and the main surface of the first semiconductor chip body. The third semiconductor chip in a portion located on the opposite side of the main surface of the third semiconductor chip body so that the main surface of the third semiconductor chip body and the upper surface of the wiring board are substantially parallel to each other while being bonded The main body is bonded to the upper portion of the second metal wire and the main surface of the second semiconductor chip main body, so that the first to third semiconductor chips are stacked on the wiring board, and the first spacer is used to form the first semiconductor chip. Compared with the case where the first to third semiconductor chips are stacked, the size of the semiconductor device in the height direction can be reduced.

  Further, since the spacer is not necessary, the cost of the semiconductor device can be reduced.

  According to the present invention, the size of the semiconductor device in the height direction can be reduced, and the cost of the semiconductor device can be reduced.

  Next, embodiments of the present invention will be described with reference to the drawings.

(First embodiment)
FIG. 2 is a cross-sectional view of the semiconductor device according to the first embodiment of the present invention. In FIG. 2, the X and X directions indicate directions orthogonal to the arrangement direction of the plurality of electrode pads 39, 43, and 48 (Y and Y directions shown in FIG. 3 described later).

  Referring to FIG. 2, the semiconductor device 10 according to the first embodiment includes a wiring board 11, a first semiconductor chip 13, adhesive members 14, 18, 22, a first metal wire 15, 2 semiconductor chip 17, second metal wire 19, third semiconductor chip 21, third metal wire 24, and sealing resin 26.

  The wiring board 11 includes a wiring board main body 31 and pads 33 to 35. As the wiring board body 31, for example, a plurality of laminated insulating layers (not shown), vias and wirings (both not shown) provided in the plurality of insulating layers, and electrical connection to the vias and wirings A multilayer wiring structure (for example, a build-up structure) having an external connection pad (not shown) can be used. The external connection pads are pads that are electrically connected to a mounting board such as a mother board, and are provided on the lower surface 31B side of the wiring board body 31.

  The pads 33 to 35 are provided on the upper surface 31 </ b> A of the wiring board main body 31. The pads 33 to 35 are electrically connected to vias, wirings, and external connection pads provided in the wiring board main body 31.

  FIG. 3 is a plan view of the semiconductor device shown in FIG. In FIG. 3, the X and X directions indicate directions orthogonal to the Y and Y directions, and the Y and Y directions indicate the arrangement directions of the plurality of electrode pads 39, 43, and 48, respectively. In FIG. 3, the same components as those of the semiconductor device 10 of the first embodiment are denoted by the same reference numerals. Further, in FIG. 3, illustration of the sealing resin 26 is omitted for convenience of explanation.

  2 and 3, the first semiconductor chip 13 includes a semiconductor substrate 37 and a semiconductor integrated circuit 38 that constitute the first semiconductor chip body, a plurality of electrode pads 39 (first electrode pads), and the like. Have The semiconductor substrate 37 is rectangular in plan view. The semiconductor substrate 37 is bonded to the upper surface 31 </ b> A of the wiring substrate body 31 by the bonding member 14 bonded to the back surface 37 </ b> B of the semiconductor substrate 37. Thus, the first semiconductor chip 13 is bonded to the upper surface 31A of the wiring board body 31. As the semiconductor substrate 37, for example, a silicon substrate can be used.

  The semiconductor integrated circuit 38 is formed on the surface 37 </ b> A side of the semiconductor substrate 37. The semiconductor integrated circuit 38 is rectangular in plan view. The semiconductor integrated circuit 38 includes a diffusion layer, an insulating layer, a via, a wiring, and the like (not shown).

  The plurality of electrode pads 39 are provided on the upper surface 38A (the main surface of the first semiconductor chip body) of the semiconductor integrated circuit 38. The plurality of electrode pads 39 are arranged so as to form one column in the vicinity of two opposing sides of the semiconductor integrated circuit 38. That is, the plurality of electrode pads 39 are arranged so as to constitute two opposing rows. The electrode pad 39 is electrically connected to the pad 33 via the first metal wire 15. Thereby, the first semiconductor chip 13 is electrically connected to the wiring board 11. For example, a memory semiconductor chip can be used as the first semiconductor chip 13. Further, the thickness of the first semiconductor chip 13 can be set to, for example, 50 μm to 100 μm.

  The adhesive member 14 is provided between the wiring board main body 31 and the semiconductor substrate 37. One surface of the connection member 14 is in contact with the upper surface 31 </ b> A of the wiring substrate body 31, and the other surface is in contact with the back surface 37 </ b> B of the semiconductor substrate 37. The bonding member 14 is a member for bonding the first semiconductor chip 13 to the upper surface 31 </ b> A of the wiring board main body 31. As the adhesive member 14, for example, a die attach film can be used. When a die attach film is used as the adhesive member 14, the thickness of the adhesive member 14 can be set to 20 μm to 30 μm, for example.

The first metal wire 15 has one end connected to the electrode pad 39 and the other end connected to the pad 33. The first metal wire 15 can be formed by, for example, a wire bonding apparatus. The height H ₁ of the first metal wire 15 with respect to the upper surface 38A of the semiconductor integrated circuit 38 is the height J ₁ , J _{2 of} the metal wires 231, 241, 251 provided in the conventional semiconductor device 200. It is set to be lower than J _3.

Thus, by making the height H ₁ of the first metal wire 15 lower than the heights J ₁ , J ₂ , J _{3 of} the metal wires 231, 241, 251 provided in the conventional semiconductor device 200, The upper part of the first metal wire 15 can support the second semiconductor chip 17 via the adhesive member 18 disposed so as to be in contact with a part of the upper surface 38A of the semiconductor integrated circuit 38. As a result, the second semiconductor chip 17 can be stacked on the first semiconductor chip 13 without using the spacers 204 and 207 (see FIG. 1), so that the size of the semiconductor device 10 in the height direction can be reduced. It can be downsized.

The height H1 of the _first metal wire 15 may be set in the range of 50 μm to ₁₀₀ μm, for example. If the height H _{1 of} the first metal wire 15 is higher than 100 μm, it is difficult to stably support the second semiconductor chip 17. In addition, it is difficult in the manufacturing process to stably form the first metal wire 15 such that the height H1 of the _first metal wire 15 is lower than 50 μm (specifically, the performance of the wire bonding apparatus). Difficult).

  As a material of the first metal wire 15, for example, Au or Cu can be used. When Au is used as the material of the first metal wire 15, the diameter of the first metal wire 15 can be set to, for example, 15 μm to 25 μm. In addition, when Cu is used as the material of the first metal wire 15, the diameter of the first metal wire 15 can be set to 15 μm to 25 μm, for example.

  The second semiconductor chip 17 includes a semiconductor substrate 41 and a semiconductor integrated circuit 42 that form a second semiconductor chip body, and a plurality of electrode pads 43 (second electrode pads). The semiconductor substrate 41 is rectangular in plan view. As the semiconductor substrate 41, for example, a silicon substrate can be used. An adhesive member 18 is provided on the back surface 41 </ b> B of the semiconductor substrate 41. The semiconductor substrate 41 is arranged so that a part thereof protrudes to the right side of the first semiconductor chip 13 shown in FIGS. The semiconductor substrate 41 has an upper surface 38A of the semiconductor integrated circuit 38 and an upper portion of the first metal wire 15 connected to the electrode pads 39 arranged in the right column of FIGS. It is glued to.

  As a result, the second semiconductor chip 17 is placed above the first semiconductor chip 13 and the first metal wire 15 with the upper surface 42A of the semiconductor integrated circuit 42 inclined with respect to the upper surface 31A of the wiring board body 31. Are stacked. In this way, by stacking the second semiconductor chip 17 on top of the first semiconductor chip 13 and the first metal wire 15, the semiconductor integrated circuit 38 and the adhesive member are formed in a state where the sealing resin 26 is not formed. A first gap A is formed between the first gap 18 and the second gap 18.

  The outer shape of the semiconductor substrate 41 is configured to be substantially equal to the outer shape of the semiconductor substrate 37 or larger than the outer shape of the semiconductor substrate 37.

  As described above, the outer shape of the semiconductor substrate 41 is substantially equal to the outer shape of the semiconductor substrate 37 or larger than the outer shape of the semiconductor substrate 37, so that the first semiconductor chip 13 and the first metal wire 15 are placed above the first semiconductor wire 13. Two semiconductor chips 17 can be mounted. In the present embodiment, as shown in FIG. 3, the following description is given by taking as an example the case where the outer shape of the semiconductor substrate 41 is larger than the outer shape of the semiconductor substrate 37.

  The semiconductor integrated circuit 42 is formed on the surface 41 </ b> A side of the semiconductor substrate 41. The semiconductor integrated circuit 42 is rectangular in plan view. The semiconductor integrated circuit 42 includes a diffusion layer, an insulating layer, a via, a wiring, and the like (not shown).

  The plurality of electrode pads 43 are provided on the upper surface 42 </ b> A side of the semiconductor integrated circuit 42 and are electrically connected to the semiconductor integrated circuit 42. The plurality of electrode pads 43 are arranged so as to form one column in the vicinity of two opposing sides of the semiconductor integrated circuit 42. That is, the plurality of electrode pads 43 are arranged so as to constitute two opposing rows. The electrode pad 43 is electrically connected to the pad 34 via the second metal wire 19. As a result, the second semiconductor chip 17 is electrically connected to the wiring board 11. As the second semiconductor chip 17, for example, a memory semiconductor chip can be used. The thickness of the second semiconductor chip 17 can be set to 100 μm to 150 μm, for example.

  The second semiconductor chip 17 configured as described above has the first semiconductor chip 13 and the first semiconductor chip 13 so that the arrangement direction of the electrode pads 43 and the arrangement direction of the electrode pads 39 are substantially parallel in a plan view. The metal wire 19 is bonded to the upper part.

  As described above, in the state in plan view, the second direction is arranged above the first semiconductor chip 13 and the first metal wire 19 so that the arrangement direction of the electrode pads 43 and the arrangement direction of the electrode pads 39 are substantially parallel. By bonding the semiconductor chip 17, the third semiconductor chip 21 can be stacked on the second semiconductor chip 17.

  The adhesive member 18 is provided on the back surface 41 </ b> B of the semiconductor substrate 41. The adhesive member 14 is formed on the upper surface 38A of the semiconductor integrated circuit 38 and the upper portion of the first metal wire 15 connected to the electrode pad 39 arranged in the right column shown in FIGS. It is a member for adhering the chip 17. For example, a die attach film can be used as the adhesive member 18. When a die attach film is used as the adhesive member 18, the thickness of the adhesive member 18 can be set to 20 μm to 30 μm, for example.

The second metal wire 19 has one end connected to the electrode pad 43 and the other end connected to the pad 34. The second metal wire 19 can be formed by, for example, a wire bonding apparatus. The height H ₂ of the second metal wire 19 with respect to the upper surface 42A of the semiconductor integrated circuit 42 is the height J ₁ , J _{2 of} the metal wires 231, 241, 251 provided in the conventional semiconductor device 200. It is set to be lower than J _3.

Thus, by making the height H ₂ of the second metal wire 19 lower than the heights J ₁ , J ₂ , J _{3 of} the metal wires 231, 241, 251 provided in the conventional semiconductor device 200, The upper part of the second metal wire 19 can support the third semiconductor chip 21 via the adhesive member 22 disposed so as to be in contact with a part of the upper surface 42A of the semiconductor integrated circuit 42. Accordingly, the third semiconductor chip 21 can be stacked on the second semiconductor chip 17 without using the spacers 204 and 207 (see FIG. 1), and thus the size of the semiconductor device 10 in the height direction can be reduced. It can be downsized.

The height H2 of the _second metal wire 19 may be set in the range of 50 μm to 100 μm, for example. If the height H _{2 of} the second metal wire 19 is higher than 100 μm, it is difficult to stably support the third semiconductor chip 21. In addition, it is difficult in the manufacturing process to stably form the second metal wire 19 so that the height H2 of the _second metal wire 19 is lower than 50 μm (specifically, the performance of the wire bonding apparatus). It is difficult.

  As a material of the second metal wire 19, for example, Au or Cu can be used. When Au is used as the material of the second metal wire 19, the diameter of the second metal wire 19 can be set to, for example, 15 μm to 25 μm. Further, when Cu is used as the material of the second metal wire 19, the diameter of the second metal wire 19 can be set to, for example, 15 μm to 25 μm.

  The third semiconductor chip 21 includes a semiconductor substrate 46 and a semiconductor integrated circuit 47 constituting a third semiconductor chip body, and a plurality of electrode pads 48 (third electrode pads). The semiconductor substrate 46 is rectangular in plan view. The adhesive member 22 is provided on the back surface 46 </ b> B of the semiconductor substrate 46. The semiconductor substrate 46 is arranged so that a part thereof protrudes to the left side of the second semiconductor chip 17 shown in FIGS. The semiconductor substrate 46 is connected to the upper surface 38A of the semiconductor integrated circuit 38 and the upper part of the second metal wire 19 connected to the electrode pads 43 arranged in the left column shown in FIGS. It is glued to.

  As a result, the third semiconductor chip 21 has the second semiconductor chip 17 and the second metal wire 19 so that the upper surface 47A of the semiconductor integrated circuit 47 is substantially parallel to the upper surface 31A of the wiring board body 31. Stacked on top. As described above, the third semiconductor chip 21 is stacked on the second semiconductor chip 17 and the second metal wire 19 to stack the semiconductor integrated circuit 42 and the adhesive member in a state where the sealing resin 26 is not formed. A second gap B is formed between

  As described above, the third surface is formed on the upper surface 42A of the semiconductor integrated circuit 42 and the upper portion of the second metal wire 19 so that the upper surface 47A of the semiconductor integrated circuit 47 is substantially parallel to the upper surface 31A of the wiring board body 31. By bonding the semiconductor chip 21, another semiconductor chip can be further stacked on the third semiconductor chip 21.

  The outer shape of the semiconductor substrate 46 is configured to be substantially the same as the outer shape of the semiconductor substrate 41 or larger than the outer shape of the semiconductor substrate 41.

  As described above, the outer shape of the semiconductor substrate 46 is substantially equal to the outer shape of the semiconductor substrate 41 or larger than the outer shape of the semiconductor substrate 41, so that the second semiconductor chip 19 and the second metal wire 19 are placed above the second semiconductor chip 19. 3 semiconductor chips 21 can be bonded. In the present embodiment, as shown in FIG. 3, the following description is given by taking as an example the case where the outer shape of the semiconductor substrate 46 is larger than the outer shape of the semiconductor substrate 41.

  The semiconductor integrated circuit 47 is formed on the surface 46 </ b> A side of the semiconductor substrate 46. The semiconductor integrated circuit 47 is rectangular in plan view. The semiconductor integrated circuit 47 includes a diffusion layer, an insulating layer, a via, a wiring, and the like (not shown).

  The plurality of electrode pads 48 are provided on the upper surface 47 A side of the semiconductor integrated circuit 47 and are electrically connected to the semiconductor integrated circuit 47. The plurality of electrode pads 48 are arranged in the vicinity of two opposing sides of the semiconductor integrated circuit 47 so as to form one column. That is, the plurality of electrode pads 48 are arranged so as to constitute two opposing rows. The electrode pad 48 is electrically connected to the pad 35 via the third metal wire 24. Thereby, the third semiconductor chip 21 is electrically connected to the wiring board 11. As the third semiconductor chip 21, for example, a semiconductor chip for memory can be used. The thickness of the third semiconductor chip 21 can be set to 100 μm to 150 μm, for example.

  The third semiconductor chip 21 configured as described above has the second semiconductor chip 17 and the second semiconductor chip 17 so that the arrangement direction of the electrode pads 48 and the arrangement direction of the electrode pads 39 and 43 are substantially parallel in a plan view. It is bonded to the upper part of the second metal wire 19.

  As described above, in a plan view, the arrangement direction of the electrode pad 48 and the arrangement direction of the electrode pads 39 and 43 are substantially above the second semiconductor chip 17 and the second metal wire 19 so as to be parallel to each other. By bonding the third semiconductor chip 21, another semiconductor chip can be stacked on the third semiconductor chip 21.

The third metal wire 24 has one end connected to the electrode pad 48 and the other end connected to the pad 35. The third metal wire 24 can be formed by, for example, a wire bonding apparatus. The height H ₃ of the third metal wire 24 with respect to the upper surface 47A of the semiconductor integrated circuit 47 is the height J ₁ , J _{2 of} the metal wires 231, 241, 251 provided in the conventional semiconductor device 200. It is set to be lower than J _3.

In this way, by making the height H ₃ of the third metal wire 24 lower than the heights J ₁ , J ₂ , J _{3 of} the metal wires 231, 241, 251 provided in the conventional semiconductor device 200, Since the other semiconductor chip 17 placed on the third semiconductor chip 21 can be supported by the upper part of the third metal wire 24, the size of the semiconductor device 10 in the height direction is reduced. be able to.

The height H ₃ of the third metal wire 24 may be set in the range of 50 μm to 100 μm, for example. When the height H3 of the _third metal wire 24 is higher than 100 μm, when another semiconductor chip (not shown) is stacked on the third semiconductor chip 21, the other semiconductor chip is stably supported. It becomes difficult. In addition, it is difficult in the manufacturing process to stably form the third metal wire 24 so that the height H3 of the _third metal wire 24 is lower than 50 μm (specifically, the performance of the wire bonding apparatus). Difficult).

  As a material of the third metal wire 24, for example, Au or Cu can be used. When Au is used as the material of the third metal wire 24, the diameter of the third metal wire 24 can be set to 15 μm to 25 μm, for example. In addition, when Cu is used as the material of the third metal wire 24, the diameter of the third metal wire 24 can be set to, for example, 15 μm to 25 μm.

  The sealing resin 26 covers the top surface of the wiring board main body 31 so as to cover the first to third semiconductor chips 13, 17, 21, the first to third metal wires 15, 19, 24, and the pads 33 to 35. 31A is provided. The sealing resin 26 is a resin for sealing the first to third semiconductor chips 13, 17, 21 and the first to third metal wires 15, 19, 24. As the sealing resin 26, for example, a mold resin (specifically, for example, a thermoplastic epoxy resin) can be used.

  According to the semiconductor device of the present embodiment, the second semiconductor chip 17 is electrically connected to the upper surface 38A of the semiconductor integrated circuit 38 and the first semiconductor chip 15 and the wiring board 11 through the adhesive member 18. The third semiconductor chip 21 is bonded to the upper portion of the first metal wire 15, and the upper surface 42 A of the semiconductor integrated circuit 42 and the second semiconductor chip 17 and the wiring substrate 11 are electrically connected via the bonding member 22. The first to third semiconductor chips 13, 17, and 21 can be stacked without using a spacer by adhering to the upper portion of the second metal wire 19 to be connected to the semiconductor device 10. The size in the height direction can be reduced, and the cost of the semiconductor device 10 can be reduced.

  The third semiconductor chip 21 is disposed on the upper surface 42A of the semiconductor integrated circuit 42 and the second metal wire 19 so that the upper surface 47A of the semiconductor integrated circuit 47 is substantially parallel to the upper surface 31A of the wiring board body 31. By adhering, another semiconductor chip can be further stacked on the third semiconductor chip 21.

  4 to 14 are views showing a manufacturing process of the semiconductor device according to the first embodiment of the invention. 4 to 14, the same components as those of the semiconductor device 10 according to the first embodiment are denoted by the same reference numerals.

  A method for manufacturing the semiconductor device 10 according to the first embodiment will be described with reference to FIGS. First, in the process shown in FIG. 4, the wiring board 11 having the wiring board body 31 and the pads 33 to 35 is formed by a known method. As the wiring board body 31, for example, a plurality of laminated insulating layers (not shown), vias and wirings (both not shown) provided in the plurality of insulating layers, and electrical connection to the vias and wirings A multilayer wiring structure (for example, a build-up structure) having an external connection pad (not shown) can be used.

  Next, in the step shown in FIG. 5, the first semiconductor chip 13 having the adhesive member 14 formed on the back surface 37 </ b> B of the semiconductor substrate 37 is prepared, and the first upper surface 31 </ b> A of the wiring board body 31 is interposed via the adhesive member 14. The semiconductor chip 13 is adhered.

  The first semiconductor chip 13 has a semiconductor substrate 37, a semiconductor integrated circuit 38, and a plurality of electrode pads arranged on the upper surface 38A of the semiconductor integrated circuit 38 so as to constitute two opposing rows. For example, a memory semiconductor chip can be used as the first semiconductor chip 13. As the adhesive member 14, for example, a die attach film can be used. When using a die attach film as the adhesive member 14, the thickness of the adhesive member 14 can be 20 micrometers-30 micrometers, for example.

Next, in the step shown in FIG. 6, the first metal wire 15 having one end connected to the electrode pad 39 and the other end connected to the pad 33 is formed. The first metal wire 15 can be formed by, for example, a wire bonding apparatus. The height H1 of the _first metal wire 15 with respect to the upper surface 38A of the semiconductor integrated circuit 38 may be set within a range of 50 μm to ₁₀₀ μm, for example.

Thus, by setting the height H ₁ of the first metal wire 15 to 50 μm to ₁₀₀ μm, the second semiconductor chip 17 bonded to the upper part of the first metal wire 15 and the upper surface 38A of the semiconductor integrated circuit 38. Can be stably supported.

When the height H1 of the _first metal wire 15 is higher than 100 μm, the first metal wire 15 is deformed by the weight of the second semiconductor chip 17 on which the adhesive member 18 is formed. It becomes difficult to stably support the formed second semiconductor chip 17. In addition, it is difficult in the manufacturing process to stably form the first metal wire 15 such that the height H1 of the _first metal wire 15 is lower than 50 μm (specifically, the performance of the wire bonding apparatus). Difficult).

  As a material of the first metal wire 15, for example, Au or Cu can be used. When Au is used as the material of the first metal wire 15, the diameter of the first metal wire 15 can be set to, for example, 15 μm to 25 μm. In addition, when Cu is used as the material of the first metal wire 15, the diameter of the first metal wire 15 can be set to 15 μm to 25 μm, for example.

  Next, in the process shown in FIG. 7, the second semiconductor chip 17 having the adhesive member 18 formed on the back surface 41 </ b> B of the semiconductor substrate 41 is prepared, and the upper surface 38 </ b> A of the semiconductor integrated circuit 38 is connected to the one side via the adhesive member 18. The second semiconductor is connected to the upper part of the first metal wire 15 connected to the electrode pad 39 arranged in this column (in the case of the present embodiment, the electrode pad 39 arranged in the right column shown in FIG. 7). The chip 17 is bonded. As a result, the upper surface 42A of the semiconductor integrated circuit 42 is inclined with respect to the upper surface 31A of the wiring board main body 31, and a first gap A is formed between the first semiconductor chip 13 and the adhesive member 18.

  The second semiconductor chip 17 has a semiconductor substrate 41, a semiconductor integrated circuit 42, and a plurality of electrode pads 43 arranged on the upper surface 42A of the semiconductor integrated circuit 42 so as to constitute two opposing rows. As the second semiconductor chip 17, for example, a memory semiconductor chip can be used. As the adhesive member 18, for example, a die attach film can be used. When using a die attach film as the adhesive member 18, the thickness of the adhesive member 18 can be 20 micrometers-30 micrometers, for example.

Next, in the step shown in FIG. 8, the second metal wire 19 having one end connected to the electrode pad 43 and the other end connected to the pad 34 is formed. The second metal wire 19 can be formed by, for example, a wire bonding apparatus. The height H2 of the _second metal wire 19 with respect to the upper surface 42A of the semiconductor integrated circuit 42 may be set within a range of 50 μm to 100 μm, for example.

Thus, the third semiconductor chip 21 bonded to the upper part of the second metal wire 19 and the upper surface 42A of the semiconductor integrated circuit 42 by setting the height H2 of the _second metal wire 19 to 50 μm to 100 μm. Can be stably supported.

When the height H2 of the _second metal wire 19 is higher than 100 μm, the second metal wire 19 is deformed by the weight of the third semiconductor chip 21 on which the adhesive member 22 is formed. It becomes difficult to stably support the formed third semiconductor chip 21. In addition, it is difficult in the manufacturing process to stably form the second metal wire 19 so that the height H2 of the _second metal wire 19 is lower than 50 μm (specifically, the performance of the wire bonding apparatus). Difficult).

  As a material of the second metal wire 19, for example, Au or Cu can be used. When Au is used as the material of the second metal wire 19, the diameter of the second metal wire 19 can be set to, for example, 15 μm to 25 μm. Further, when Cu is used as the material of the second metal wire 19, the diameter of the second metal wire 19 can be set to, for example, 15 μm to 25 μm.

  Next, in the process shown in FIG. 9, the third semiconductor chip 21 having the adhesive member 22 formed on the back surface 46 </ b> B of the semiconductor substrate 46 is prepared, and then the upper surface 47 </ b> A of the semiconductor integrated circuit 47 is replaced with the upper surface 31 </ b> A of the wiring substrate body 31. And the electrode pad 43 arranged in one row through the adhesive member 22 (in the case of the present embodiment, in the left column shown in FIG. 9). The third semiconductor chip 21 is bonded to the upper part of the second metal wire 19 connected to the arranged electrode pads 43). As a result, a second gap B is formed between the second semiconductor chip 17 and the adhesive member 22.

  The third semiconductor chip 21 has a semiconductor substrate 46, a semiconductor integrated circuit 47, and a plurality of electrode pads 48 arranged on the surface 46A of the semiconductor integrated circuit 46 so as to constitute two opposing rows. As the third semiconductor chip 21, for example, a semiconductor chip for memory can be used. For example, a die attach film can be used as the adhesive member 22. When a die attach film is used as the adhesive member 22, the thickness of the adhesive member 22 can be set to, for example, 20 μm to 30 μm.

Next, in the step shown in FIG. 10, a third metal wire 24 is formed in which one end is connected to the electrode pad 48 and the other end is connected to the pad 35. The third metal wire 24 can be formed by, for example, a wire bonding apparatus. The height H ₃ of the third metal wire 24 with respect to the upper surface 47A of the semiconductor integrated circuit 47 may be set within a range of 50 μm to 100 μm, for example.

In this way, when another semiconductor chip (not shown) is stacked on the third semiconductor chip 21 by setting the height H3 of the _third metal wire 24 to 50 μm to 100 μm, the third metal wire The upper part 24 and the upper surface 47A of the semiconductor integrated circuit 47 can stably support other semiconductor chips, and can improve the mounting density of the semiconductor device 10.

If the height H3 of the _third metal wire 24 is higher than 100 μm, the third metal wire 24 is deformed by the weight of the other semiconductor chip, so that it is difficult to stably support the other semiconductor chip. Become. In addition, it is difficult in the manufacturing process to stably form the third metal wire 24 so that the height H3 of the _third metal wire 24 is lower than 50 μm (specifically, the wire bonding apparatus includes Difficult in terms of performance).

  As a material of the third metal wire 24, for example, Au or Cu can be used. When Au is used as the material of the third metal wire 24, the diameter of the third metal wire 24 can be set to 15 μm to 25 μm, for example. In addition, when Cu is used as the material of the third metal wire 24, the diameter of the third metal wire 24 can be set to, for example, 15 μm to 25 μm.

  Next, in the step shown in FIG. 11, a liquid resin 58 is prepared in the concave portion 56 of the mold 55. The recess 56 has a shape corresponding to the shape of the sealing resin 26 (see FIG. 2). The liquid resin 58 is a resin that becomes the sealing resin 26 by being cured. For example, the liquid resin 58 heats the mold 55, puts a powdered mold resin (for example, a thermoplastic epoxy resin) into the recessed portion 56 of the heated mold 55, and heats the powdered mold resin. It is formed by melting. When a thermoplastic epoxy resin is used as the powder mold resin, the mold 55 can be heated to 180 ° C., for example. In the present embodiment, the following description will be given by taking as an example a case where a thermoplastic epoxy resin is used as the powdery mold resin.

  Next, in the step shown in FIG. 12, the first to third semiconductor chips 13, 17, 21 and the first to third metal wires 15, 19, 24 are immersed in the concave portion 56 filled with the liquid resin 58. As described above, the structure shown in FIG. Thus, the upper surface 31A of the wiring board body 31 and the pads 33 to 35 are covered with the liquid resin 58, and the first and second gaps A and B are filled with the liquid resin 58.

  In this way, the liquid resin 58 is formed in the concave portion 56 of the mold 55, and the first to third semiconductor chips 13, 17, 21 and the first to third metal wires 15, 19, 24 are sealed with the sealing resin 26. The first to third semiconductor chips 13 are immersed in the liquid resin 58 serving as the base material of the first and third semiconductor chips 13 without changing the relative positional relationship between the stacked first to third semiconductor chips 13, 17, and 21. , 17, 21, the first to third metal wires 15, 19, 24, the first gap A, and the second gap B can be sealed.

  Next, in the step shown in FIG. 13, the mold 55 is cooled to cure the liquid resin 58 shown in FIG. 12, and the first to third semiconductor chips 13, 17, 21, first to third A sealing resin 26 that seals the metal wires 15, 19, 24, the first gap A, the second gap B, the upper surface 31 A of the wiring board body 31, and the pads 33 to 35 is formed.

  Next, in the step shown in FIG. 14, the wiring substrate 11 on which the sealing resin 26 is formed is removed from the mold 55. Thereby, the semiconductor device 10 of the first embodiment is manufactured.

  According to the manufacturing method of the semiconductor device of the present embodiment, the upper surface 38A of the semiconductor integrated circuit 38 and the electrode pads 39 arranged in one row via the adhesive member 18 (in the case of the present embodiment, FIG. The second semiconductor chip 17 is bonded to the upper part of the first metal wire 15 connected to the electrode pads 39) arranged in the right column shown in FIG. The semiconductor chip 17 and the wiring board 11 are electrically connected, and then the semiconductor integrated circuit 47 is interposed via the adhesive member 22 so that the upper surface 47A of the semiconductor integrated circuit 47 and the upper surface 31A of the wiring board body 31 are substantially parallel. The second metal wire 19 connected to the upper surface 42A of the circuit 42 and the electrode pads 43 arranged in one row (in the present embodiment, the electrode pads 43 arranged in the left row shown in FIG. 9). On top of the third The conductor chip 21 is bonded, and then the third semiconductor chip 24 and the wiring board 11 are electrically connected by the third metal wire 24, so that the first on the wiring board 11 without using a spacer. Since the third to third semiconductor chips 13, 17, and 21 can be stacked, the size of the semiconductor device 10 in the height direction can be reduced, and the cost of the semiconductor device 10 can be reduced.

  In addition, since the spacer is not necessary, a process for forming the spacer is not necessary, and the manufacturing cost of the semiconductor device 10 can be reduced.

  Further, a liquid resin 58 is formed in the recess 56 of the mold 55, and then the first to third semiconductor chips 13, 17, 21 and the first to third metal wires 15, 19, 24 are replaced with the liquid resin 58. The first to third semiconductor chips are formed without changing the relative positional relationship of the stacked first to third semiconductor chips 13, 17, and 21 by forming the sealing resin 26 by immersing them in the substrate. 13, 17, 21, the first to third metal wires 15, 19, 24, the first gap A, the second gap B, the upper surface 31A of the wiring board body 31, and the pads 33 to 35 are accurately sealed. can do.

  FIG. 15 is a cross-sectional view of a semiconductor device according to a first variation of the first embodiment of the present invention. In FIG. 15, the same components as those of the semiconductor device 10 of the first embodiment are denoted by the same reference numerals.

  Referring to FIG. 15, the semiconductor device 60 of the first modification example of the first embodiment is further provided with first and second support members 61 and 62 in addition to the configuration of the semiconductor device 10 of the first embodiment. The configuration is the same as that of the semiconductor device 10 except that is provided.

  The first support member 61 is provided on the upper surface 38A of the semiconductor integrated circuit 38 corresponding to the first gap A. The first support member 61 is a member for supporting the second semiconductor chip 17 via the adhesive member 18. The height of the first support member 61 is set to a height that makes contact with the upper surface of the first metal wire 15 and the lower surface 18A of the adhesive member 18 bonded to the upper surface 38A of the semiconductor integrated circuit 38.

  As described above, the upper surface 38A of the semiconductor integrated circuit 38 corresponding to the first gap A, the lower surface 18A of the adhesive member 18 bonded to the upper portion of the first metal wire 15 and the upper surface 38A of the semiconductor integrated circuit 38, By providing the first support member 61 in contact, the second semiconductor chip 17 can be supported by the first metal wire 15 and the first support member 61 via the adhesive member 18. The second semiconductor chip 17 can be stably supported.

  As a material of the first support member 61, for example, resin, silicon, or the like can be used. The cross-sectional shape of the first support member 61 can be, for example, a semicircular shape.

  The second support member 62 is provided on the upper surface 42 </ b> A of the semiconductor integrated circuit 42 corresponding to the second gap B. The second support member 62 is a member for supporting the third semiconductor chip 21 via the adhesive member 22. The height of the second support member 62 is set to be in contact with the upper surface of the second metal wire 19 and the lower surface 22A of the adhesive member 22 bonded to the upper surface 42A of the semiconductor integrated circuit 42.

  As described above, the upper surface 42A of the semiconductor integrated circuit 42 corresponding to the second gap B, the lower surface 22A of the adhesive member 22 bonded to the upper portion of the second metal wire 19 and the upper surface 42A of the semiconductor integrated circuit 42, and By providing the second support member 62 in contact, the third semiconductor chip 21 can be supported by the second metal wire 19 and the second support member 62 via the adhesive member 22. The third semiconductor chip 21 can be stably supported.

  As a material of the second support member 62, for example, resin, silicon, or the like can be used. The cross-sectional shape of the second support member 62 can be, for example, a semicircular shape.

  According to the semiconductor device of the first modified example of the present embodiment, the upper surface 38A of the semiconductor integrated circuit 38 corresponding to the first gap A, the upper portion of the first metal wire 15 and the upper surface of the semiconductor integrated circuit 38. The first support member 61 that contacts the adhesive member 18 bonded to 38A is provided, and the upper portion of the second metal wire 19 and the semiconductor are formed on the upper surface 42A of the semiconductor integrated circuit 42 corresponding to the second gap B. By providing the second support member 62 that contacts the adhesive member 22 bonded to the upper surface 42A of the integrated circuit 42, the second and third semiconductor chips 17 and 21 can be stably supported.

  The semiconductor device 60 according to the first modification of the present embodiment can obtain the same effects as those of the semiconductor device 10 according to the first embodiment.

  In the first modification of the present embodiment, the case where the cross-sectional shapes of the first and second support members 61 and 62 are semicircular has been described as an example, but the first and second support members are described. The shapes of 61 and 62 are not limited to this.

  FIG. 16 is a cross-sectional view of a semiconductor device according to a second modification of the first embodiment of the present invention. In FIG. 16, the same components as those of the semiconductor device 60 according to the first modification of the first embodiment are denoted by the same reference numerals.

  Referring to FIG. 16, the semiconductor device 65 of the second modification example of the first embodiment is provided with first and second supports provided in the semiconductor device 60 of the first modification example of the first embodiment. The structure is the same as that of the semiconductor device 60 except that the first and second support members 66 and 67 are provided instead of the members 61 and 62.

  The first support member 66 is provided on the upper surface 38 </ b> A of the semiconductor integrated circuit 38 at a portion corresponding to the first gap A. The first support member 66 is a member for supporting the second semiconductor chip 17 provided with the adhesive member 18 by making contact with the lower surface 18A of the adhesive member 18. The first support member 66 has a height such that the lower surface 18 </ b> A of the adhesive member 18 and the upper portion of the first metal wire 15 do not contact each other. That is, the second semiconductor chip 17 on which the adhesive member 18 is formed is supported by the upper surface 38A of the semiconductor integrated circuit 38 and the first support member 66.

  As a material of the first support member 66, for example, resin, silicon, or the like can be used. The cross-sectional shape of the first support member 66 can be, for example, a semicircular shape.

  The second support member 67 is provided on the upper surface 42 </ b> A of the semiconductor integrated circuit 42 at a portion corresponding to the second gap B. The second support member 67 is a member for supporting the third semiconductor chip 21 provided with the adhesive member 22 by contacting the lower surface 22A of the adhesive member 22. The height of the second support member 67 is set such that the lower surface 22 </ b> A of the adhesive member 22 does not contact the upper portion of the second metal wire 19. That is, the third semiconductor chip 21 on which the adhesive member 22 is formed is supported by the upper surface 42A of the semiconductor integrated circuit 42 and the second support member 67.

  As a material of the second support member 67, for example, resin, silicon, or the like can be used. The cross-sectional shape of the second support member 67 can be, for example, a semicircular shape.

  According to the semiconductor device of the second modified example of the present embodiment, the first support member 66 that contacts the lower surface 18A of the adhesive member 18 on the upper surface 38A of the semiconductor integrated circuit 38 corresponding to the first gap A. And the height of the first support member 66 is set so that the lower surface 18A of the adhesive member 18 and the upper portion of the first metal wire 15 do not come into contact with each other, and the portion corresponding to the second gap B is provided. A second support member 67 that contacts the lower surface 22A of the adhesive member 22 is provided on the upper surface 42A of the semiconductor integrated circuit 42, and the height of the second support member 67 is set to the lower surface 22A of the adhesive member 22 and the second metal wire 19. The first to third semiconductor chips 203, 205, and 21 are stacked using the spacers 204 and 207 by stacking the first to third semiconductor chips 13, 17, and 21 so as not to contact the upper part of Load 208 Proof as compared with the conventional semiconductor device 200 (see FIG. 1), the height direction size of the semiconductor device 65 can be miniaturized.

(Second Embodiment)
FIG. 17 is a cross-sectional view of a semiconductor device according to the second embodiment of the present invention. In FIG. 17, the same components as those of the semiconductor device 10 of the first embodiment are denoted by the same reference numerals.

  Referring to FIG. 17, in the semiconductor device 70 of the second embodiment, a wiring board 71 is provided instead of the wiring board 11 provided in the semiconductor device 10 of the first embodiment, and a fourth semiconductor is further provided. A chip 73, adhesive members 74 and 78, a fourth metal wire 75, a fifth semiconductor chip 77 and a fifth metal wire 79 are provided, and the first to fifth semiconductor chips 13, 17, 21, 73 and 77 are provided. In addition, the configuration is the same as that of the semiconductor device 10 except that the sealing resin 26 is formed so as to seal the first to fifth metal wires 15, 19, 24, 75, and 79.

  The wiring board 71 is configured in the same manner as the wiring board 11 except that pads 80 and 81 are further provided in the configuration of the wiring board 11 provided in the semiconductor device 10 of the first embodiment.

  The pad 80 is provided on the upper surface 31 </ b> A of the wiring board body 31. The pad 80 is electrically connected to the fourth semiconductor chip 73 via the fourth metal wire 75. The pad 81 is provided on the upper surface 31 </ b> A of the wiring board body 31. The pad 81 is electrically connected to the fifth semiconductor chip 77 via the fifth metal wire 79.

  The fourth semiconductor chip 73 includes a semiconductor substrate 82 and a semiconductor integrated circuit 83 constituting a fourth semiconductor chip body, and a plurality of electrode pads 84 (fourth electrode pads). The semiconductor substrate 82 is rectangular in plan view. An adhesive member 74 is provided on the back surface 82 </ b> B of the semiconductor substrate 82. As the semiconductor substrate 82, for example, a silicon substrate can be used.

  The semiconductor substrate 82 is rectangular in plan view. An adhesive member 74 is provided on the back surface 82 </ b> B of the semiconductor substrate 82. The semiconductor substrate 82 is arranged so that a part thereof protrudes to the right side of the third semiconductor chip 21 shown in FIG. The semiconductor substrate 82 has an upper surface 47A of the semiconductor integrated circuit 47 and an electrode pad 48 arranged in one column (in the case of the present embodiment, arranged in the right column shown in FIG. 17) via the adhesive member 74. It is bonded to the upper part of the third metal wire 24 connected to the electrode pad 48).

  As a result, the fourth semiconductor chip 73 is formed on the third semiconductor chip 21 and the third metal wire 24 with the upper surface 83A of the semiconductor integrated circuit 83 inclined with respect to the upper surface 31A of the wiring board body 31. Are stacked. In this way, by stacking the fourth semiconductor chip 73 on the third semiconductor chip 21 and the third metal wire 24, the semiconductor integrated circuit 47 and the adhesive member are formed in a state where the sealing resin 26 is not formed. A third gap C is formed between the second gap 74 and the second gap 74.

  The outer shape of the semiconductor substrate 82 is configured to be approximately equal to the outer shape of the semiconductor substrate 46 or larger than the outer shape of the semiconductor substrate 37.

  As described above, by making the outer shape of the semiconductor substrate 82 substantially equal to or larger than the outer shape of the semiconductor substrate 46, the third semiconductor chip 21 and the third metal wire 24 are placed above the third semiconductor wire 21. 4 semiconductor chips 73 can be bonded. In the present embodiment, the following description is given by taking as an example the case where the outer shape of the semiconductor substrate 82 is larger than the outer shape of the semiconductor substrate 46.

  The semiconductor integrated circuit 83 is formed on the surface 82 A side of the semiconductor substrate 82. The semiconductor integrated circuit 83 is rectangular in plan view. The semiconductor integrated circuit 83 includes a diffusion layer, an insulating layer, a via, a wiring, and the like (not shown).

  The plurality of electrode pads 84 are provided on the upper surface 83 </ b> A side of the semiconductor integrated circuit 83 and are electrically connected to the semiconductor integrated circuit 83. The plurality of electrode pads 84 are arranged so as to form one column in the vicinity of two opposing sides of the semiconductor integrated circuit 83. That is, the plurality of electrode pads 84 are arranged so as to constitute two opposing rows. The electrode pad 84 is electrically connected to the pad 80 via the fourth metal wire 75. As a result, the fourth semiconductor chip 73 is electrically connected to the wiring board 11. As the fourth semiconductor chip 73, for example, a semiconductor chip for memory can be used. The thickness of the fourth semiconductor chip 73 can be set to 100 μm to 150 μm, for example.

  The fourth semiconductor chip 73 configured as described above has the third semiconductor chip 73 so that the arrangement direction of the electrode pads 84 is substantially parallel to the arrangement direction of the electrode pads 39, 43, and 48 in a plan view. 21 and the upper part of the third metal wire 24.

  As described above, the third semiconductor chip 21 and the third metal wire 24 are arranged so that the arrangement direction of the electrode pads 84 and the arrangement direction of the electrode pads 39, 43, 48 are substantially parallel in a plan view. The fifth semiconductor chip 77 can be stacked on the fourth semiconductor chip 73 by bonding the fourth semiconductor chip 73 to the upper part.

  The adhesive member 74 is provided on the back surface 82 </ b> B of the semiconductor substrate 82. The adhesive member 74 is connected to the upper surface 47A of the semiconductor integrated circuit 47 and the electrode pads 48 arranged in one row (in the present embodiment, the electrode pads 48 arranged in the right row shown in FIG. 17). This is a member for adhering the fourth semiconductor chip 73 to the upper part of the third metal wire 24. As the adhesive member 74, for example, a die attach film can be used. When a die attach film is used as the adhesive member 74, the thickness of the adhesive member 74 can be set to 20 μm to 30 μm, for example.

The fourth metal wire 75 has one end connected to the electrode pad 84 and the other end connected to the pad 80. The fourth metal wire 75 can be formed by, for example, a wire bonding apparatus. The height H ₄ of the fourth metal wire 75 with respect to the upper surface 83 A of the semiconductor integrated circuit 83 is the height J ₁ , J _{2 of} the metal wires 231, 282, 251 provided in the conventional semiconductor device 200. It is set to be lower than J _3.

Thus, by making the height H ₄ of the fourth metal wire 75 lower than the heights J ₁ , J ₂ , J _{3 of} the metal wires 231, 282, 251 provided in the conventional semiconductor device 200, The fifth semiconductor chip 77 can be supported by the upper portion of the fourth metal wire 75 via the adhesive member 78 disposed so as to be in contact with a part of the upper surface 83A of the semiconductor integrated circuit 83. As a result, the fifth semiconductor chip 77 can be stacked on the fourth semiconductor chip 73 without using the spacers 204 and 207 (see FIG. 1), so the size of the semiconductor device 70 in the height direction can be reduced. It can be downsized.

The height H ₄ of the fourth metal wire 75 may be set in the range of 50 μm to 100 μm, for example. If the height H _{4 of} the fourth metal wire 75 is higher than 100 μm, it is difficult to stably support the fourth semiconductor chip 73 on which the adhesive member 74 is formed. Further, in the fourth height H ₄ of the metal wire 75 to be stably formed a fourth metal wire 75 to be lower than 50μm are manufacturing process difficult (specifically, the performance of the wire bonding apparatus Difficult).

  As a material of the fourth metal wire 75, for example, Au, Cu, or the like can be used. When Au is used as the material of the fourth metal wire 75, the diameter of the fourth metal wire 75 can be, for example, 15 μm to 25 μm. When Cu is used as the material of the fourth metal wire 75, the diameter of the fourth metal wire 75 can be set to, for example, 15 μm to 25 μm.

  The fifth semiconductor chip 77 includes a semiconductor substrate 87 and a semiconductor integrated circuit 88 that constitute a fifth semiconductor chip body, and a plurality of electrode pads 89 (fifth electrode pads). The semiconductor substrate 87 is rectangular in plan view. An adhesive member 78 is provided on the lower surface 87 </ b> B of the semiconductor substrate 87. As the semiconductor substrate 87, for example, a silicon substrate can be used.

  The semiconductor substrate 87 is arranged so that a part thereof protrudes to the left side of the fourth semiconductor chip 73 shown in FIG. The semiconductor substrate 87 has an upper surface 83A of the semiconductor integrated circuit 83 and an electrode pad 84 disposed in one column (in the case of the present embodiment, disposed in the left column shown in FIG. 17) via the adhesive member 78. It is bonded to the upper part of the fourth metal wire 75 connected to the electrode pad 84).

  Thus, the fifth semiconductor chip 73 is arranged in one row with the upper surface 83A of the semiconductor integrated circuit 83 so that the upper surface 88A of the semiconductor integrated circuit 88 is substantially parallel to the upper surface 31A of the wiring board body 31. It adheres to the electrode pad 84 formed.

  Thus, the fifth semiconductor is formed on the upper surface 83A of the semiconductor integrated circuit 83 and the upper portion of the fourth metal wire 75 so that the upper surface 88A of the semiconductor integrated circuit 88 is substantially parallel to the upper surface 31A of the wiring board body 31. By bonding the chip 77, another semiconductor chip can be further stacked on the fifth semiconductor chip 77.

  As described above, the semiconductor integrated circuit 83 is formed in a state where the sealing resin 26 is not formed by bonding the fifth semiconductor chip 77 on the fourth semiconductor chip 73 and the fourth metal wire 75. A fourth gap D is formed between the adhesive member 78 and the adhesive member 78.

  The outer shape of the semiconductor substrate 87 is configured to be substantially equal to or larger than the outer shape of the semiconductor substrate 82.

  As described above, the outer shape of the semiconductor substrate 87 is substantially equal to the outer shape of the semiconductor substrate 82 or larger than the outer shape of the semiconductor substrate 82, so that the fourth semiconductor chip 73 and the fourth metal wire 75 are placed above the fourth semiconductor wire 73. 5 semiconductor chips 77 can be bonded. In the present embodiment, the following description is given by taking as an example the case where the outer shape of the semiconductor substrate 87 is larger than the outer shape of the semiconductor substrate 82.

  The semiconductor integrated circuit 88 is formed on the upper surface 87 </ b> A side of the semiconductor substrate 87. The semiconductor integrated circuit 88 is rectangular in plan view. The semiconductor integrated circuit 88 includes a diffusion layer, an insulating layer, a via, a wiring, and the like (not shown).

  The plurality of electrode pads 89 are provided on the upper surface 88 </ b> A side of the semiconductor integrated circuit 88 and are electrically connected to the semiconductor integrated circuit 88. The plurality of electrode pads 89 are arranged in the vicinity of two opposite sides of the semiconductor integrated circuit 88 so as to form one column. That is, the plurality of electrode pads 89 are arranged so as to constitute two opposing rows. The electrode pad 89 is electrically connected to the pad 81 through the fifth metal wire 79. As a result, the fifth semiconductor chip 77 is electrically connected to the wiring board 11. As the fifth semiconductor chip 77, for example, a semiconductor chip for memory can be used. Further, the thickness of the fifth semiconductor chip 77 can be set to, for example, 100 μm to 150 μm.

  The fifth semiconductor chip 77 configured as described above has a fourth semiconductor chip 77 so that the arrangement direction of the electrode pads 89 and the arrangement direction of the electrode pads 39, 43, 48, and 84 are substantially parallel in a plan view. The semiconductor chip 73 and the fourth metal wire 75 are bonded to the upper part.

  As described above, the fourth semiconductor chip 73 and the fourth metal wire are arranged so that the arrangement direction of the electrode pads 89 and the arrangement direction of the electrode pads 39, 43, 48, 84 are substantially parallel in a plan view. By adhering the fifth semiconductor chip 77 to the upper part of 75, another semiconductor chip can be stacked on the fifth semiconductor chip 77.

  The adhesive member 78 is provided on the lower surface 87 </ b> B of the semiconductor substrate 87. The adhesive member 78 is connected to the upper surface 83A of the semiconductor integrated circuit 83 and the electrode pads 84 arranged in one column (in this embodiment, the electrode pads 84 arranged in the left column shown in FIG. 17). This is a member for adhering the fifth semiconductor chip 77 to the upper portion of the fourth metal wire 75. As the adhesive member 78, for example, a die attach film can be used. When a die attach film is used as the adhesive member 78, the thickness of the adhesive member 78 can be set to 20 μm to 30 μm, for example.

The fifth metal wire 79 has one end connected to the electrode pad 89 and the other end connected to the pad 81. The fifth metal wire 79 can be formed by, for example, a wire bonding apparatus. The height H ₅ of the fifth metal wire 79 with respect to the upper surface 88 A of the semiconductor integrated circuit 88 is the height J ₁ , J _{2 of} the metal wires 231, 282, 251 provided in the conventional semiconductor device 200. It is set to be lower than J _3.

Thus, by making the height H ₅ of the fifth metal wire 79 lower than the heights J ₁ , J ₂ , J _{3 of} the metal wires 231, 282, 251 provided in the conventional semiconductor device 200, Since the upper portion 88A of the fifth metal wire 75 and the upper surface 88A of the semiconductor integrated circuit 88 can support another semiconductor chip (not shown) without using a spacer, the height direction of the semiconductor device 70 is increased. Can be reduced in size.

The height _{H 5} of the fifth metal wire 79, for example, may be set in the range of 50 .mu.m to 100 .mu.m. If the height H _{5 of} the fifth metal wire 79 is higher than 100 μm, it is difficult to stably support other semiconductor chips stacked on the fifth semiconductor chip 77. Further, in the fifth to the height H ₅ of the metal wire 79 is lower than 50μm to a fifth metal wire 79 formed stably in the manufacturing process difficult (specifically, the performance of the wire bonding apparatus Difficult).

  As a material of the fifth metal wire 79, for example, Au or Cu can be used. When Au is used as the material of the fifth metal wire 79, the diameter of the fifth metal wire 79 can be set to 15 μm to 25 μm, for example. When Cu is used as the material of the fifth metal wire 79, the diameter of the fifth metal wire 79 can be set to, for example, 15 μm to 25 μm.

  According to the semiconductor device of the present embodiment, the fourth semiconductor chip 73 is mounted on the first to third semiconductor chips 13, 17, and 21 stacked on the wiring substrate 11 via the adhesive member 74. The upper surface 47A of the integrated circuit 47 and the upper portion of the third metal wire 24 that electrically connects the third semiconductor chip 21 and the wiring board 11 are adhered, and the fifth semiconductor chip 77 is interposed via an adhesive member 78. Are bonded to the upper surface 83A of the semiconductor integrated circuit 83 and the upper portion of the fourth metal wire 75 that electrically connects the fourth semiconductor chip 73 and the wiring substrate 11, without using spacers. Since the fifth semiconductor chips 13, 17, 21, 73, 77 can be stacked, the size of the semiconductor device 70 in the height direction can be reduced, and the semiconductor It is possible to reduce the cost of the location 70.

  Further, the fifth semiconductor chip 77 is placed on the upper surface 83A of the semiconductor integrated circuit 83 and the upper portion of the fourth metal wire 75 so that the upper surface 88A of the semiconductor integrated circuit 88 is substantially parallel to the upper surface 31A of the wiring board body 31. By adhering to, another semiconductor chip can be further stacked on the fifth semiconductor chip 77.

  The semiconductor device 70 of the present embodiment can be formed by the same method as the semiconductor device 10 of the first embodiment, and is the same as the manufacturing method of the semiconductor device 10 of the first embodiment. Effects can be obtained.

  FIG. 18 is a cross-sectional view of a semiconductor device according to a first modification of the second embodiment of the present invention. In FIG. 18, the same components as those of the semiconductor device 70 of the second embodiment are denoted by the same reference numerals.

  Referring to FIG. 18, a semiconductor device 95 according to the first modification of the second embodiment further includes first to fourth support members 61 and 62 in addition to the configuration of the semiconductor device 70 according to the second embodiment. , 96, and 97 except that the second semiconductor device 70 is configured.

  The first support member 61 is provided on the upper surface 38A of the semiconductor integrated circuit 38 corresponding to the first gap A. The upper portion of the first support member 61 is in contact with the lower surface 18 </ b> A of the adhesive member 18 bonded to the first metal wire 15. The first support member 61 is a member for supporting the second semiconductor chip 17 via the adhesive member 18.

  The second support member 62 is provided on the upper surface 42 </ b> A of the semiconductor integrated circuit 42 corresponding to the second gap B. The upper part of the second support member 62 is in contact with the lower surface 22 </ b> A of the adhesive member 22 bonded to the second metal wire 19. The second support member 62 is a member for supporting the third semiconductor chip 21 via the adhesive member 22.

  The third support member 96 is provided on the upper surface 47 </ b> A of the semiconductor integrated circuit 47 corresponding to the third gap C. The upper part of the third support member 96 is in contact with the lower surface 74 </ b> A of the adhesive member 74 bonded to the third metal wire 24.

  The height of the third support member 96 is set to a height at which the third support member 96 comes into contact with the upper surface of the third metal wire 24 and the lower surface 74A of the adhesive member 74 bonded to the upper surface 47A of the semiconductor integrated circuit 47. Thereby, the upper part of the third support member 96 is in contact with the lower surface 74 </ b> A of the adhesive member 74. The third support member 96 is a member for supporting the fourth semiconductor chip 73 via the adhesive member 74.

  As described above, the upper surface 47A of the semiconductor integrated circuit 47 corresponding to the third gap C is supported on the adhesive member 74 bonded to the upper portion of the third metal wire 24 and the upper surface 47A of the semiconductor integrated circuit 47. By providing the third support member 96, the fourth semiconductor chip 73 can be stably supported via the adhesive member 74.

  As a material of the third support member 96, for example, resin, silicon, or the like can be used. The cross-sectional shape of the third support member 96 can be, for example, a semicircular shape.

  The fourth support member 97 is provided on the upper surface 83 </ b> A of the semiconductor integrated circuit 83 in a portion corresponding to the fourth gap D. The upper part of the fourth support member 97 is in contact with the lower surface 78 </ b> A of the adhesive member 78.

  The height of the fourth support member 97 is set to be in contact with the upper surface of the fourth metal wire 75 and the lower surface 78A of the adhesive member 78 bonded to the upper surface 83A of the semiconductor integrated circuit 83. Thereby, the upper part of the fourth support member 97 is in contact with the upper part of the fourth metal wire 24 and the lower surface 78A of the adhesive member 78. The fourth support member 97 is a member for supporting the fifth semiconductor chip 77 through the adhesive member 78.

  As described above, the upper surface 83A of the semiconductor integrated circuit 83 corresponding to the fourth gap D is supported by the upper portion of the fourth metal wire 75 and the adhesive member 78 bonded to the upper surface 83A of the semiconductor integrated circuit 83. By providing the fourth support member 97, the fifth semiconductor chip 77 can be stably supported via the adhesive member 78.

  As a material of the fourth support member 97, for example, resin, silicon, or the like can be used. The cross-sectional shape of the fourth support member 97 can be, for example, a semicircular shape.

  According to the semiconductor device of the first modification of the present embodiment, the adhesive member 18 bonded to the upper surface 38A of the semiconductor integrated circuit 38 in the portion corresponding to the first gap A is bonded to the upper portion of the first metal wire 15. The first support member 61 that supports the second metal wire 19 is supported on the upper surface 42A of the semiconductor integrated circuit 42 corresponding to the second gap B. The third support member 62 is provided to support the bonding member 74 bonded to the upper portion of the third metal wire 24 on the upper surface 47A of the semiconductor integrated circuit 47 corresponding to the third gap C. 96 is provided, and a fourth support member 97 that supports the adhesive member 78 bonded to the upper part of the fourth metal wire 75 is provided on the upper surface 83A of the semiconductor integrated circuit 83 corresponding to the fourth gap D. The first semiconductor chip The second to fifth semiconductor chips 17,21,73,77 stacked on top 13 can be stably reliably supported.

  FIG. 19 is a cross-sectional view of a semiconductor device according to a second modification of the second embodiment of the present invention. In FIG. 19, the same components as those of the semiconductor device 70 of the second embodiment are denoted by the same reference numerals.

  Referring to FIG. 19, the semiconductor device 100 according to the second modification of the second embodiment is further configured by the first to fourth support members 66 and 67 in addition to the configuration of the semiconductor device 70 according to the second embodiment. , 101, 102 except that the second semiconductor device 70 is configured.

  The first support member 66 is provided on the upper surface 38 </ b> A of the semiconductor integrated circuit 38 at a portion corresponding to the first gap A. The first support member 66 is a member for supporting the second semiconductor chip 17 via the adhesive member 18 by contacting the lower surface 18A of the adhesive member 18. The height of the first support member 66 is set such that the lower surface 18A of the adhesive member 18 and the upper portion of the first metal wire 15 do not contact each other. That is, the second semiconductor chip 17 is supported by the upper surface 38 </ b> A of the semiconductor integrated circuit 38 and the first support member 66 through the adhesive member 18.

  The second support member 67 is provided on the upper surface 42 </ b> A of the semiconductor integrated circuit 42 at a portion corresponding to the second gap B. The second support member 67 is a member for supporting the third semiconductor chip 21 via the adhesive member 22 by contacting the lower surface 22A of the adhesive member 22. The height of the second support member 67 is set such that the lower surface 22 </ b> A of the adhesive member 22 does not contact the upper portion of the second metal wire 19. That is, the third semiconductor chip 21 is supported by the upper surface 42 </ b> A of the semiconductor integrated circuit 42 and the second support member 67 through the adhesive member 22.

  The third support member 101 is provided on the upper surface 47 </ b> A of the semiconductor integrated circuit 47 corresponding to the third gap C. The third support member 101 is a member for supporting the fourth semiconductor chip 73 via the adhesive member 74 by contacting the lower surface 74 </ b> A of the adhesive member 74. The height of the third support member 101 is set such that the lower surface 74A of the adhesive member 74 and the upper portion of the third metal wire 24 do not contact each other. That is, the fourth semiconductor chip 73 is supported by the upper surface 47 A of the semiconductor integrated circuit 47 and the third support member 101 via the adhesive member 74.

  The fourth support member 102 is provided on the upper surface 83 </ b> A of the semiconductor integrated circuit 83 corresponding to the fourth gap D. The fourth support member 102 is a member for supporting the fifth semiconductor chip 77 through the adhesive member 78 by contacting the lower surface 78A of the adhesive member 78. The height of the fourth support member 102 is set such that the lower surface 78A of the adhesive member 78 and the upper portion of the fourth metal wire 75 do not contact each other. That is, the fifth semiconductor chip 77 is supported by the upper surface 83 </ b> A of the semiconductor integrated circuit 83 and the fourth support member 102 via the adhesive member 78.

  As a material of the first to fourth support members 66, 67, 101, 102 having the above-described configuration, for example, resin, silicon, or the like can be used. The cross-sectional shape of the first to fourth support members 66, 67, 101, 102 can be, for example, a semicircular shape.

  According to the semiconductor device of the second modification of the present embodiment, the adhesive member 18 is supported on the upper surface 38A of the semiconductor integrated circuit 38 corresponding to the first gap A, and the lower surface 18A of the adhesive member 18 is A first support member 66 having a height that does not contact the upper portion of the first metal wire 15 is provided, and the adhesive member 22 is attached to the upper surface 42A of the semiconductor integrated circuit 42 corresponding to the second gap B. A second support member 67 is provided which is supported and height is set such that the lower surface 22A of the adhesive member 22 and the upper portion of the second metal wire 17 do not contact each other, and a portion of the semiconductor integrated portion corresponding to the third gap C is provided. The upper surface 47A of the circuit 47 is provided with a third support member 101 that supports the adhesive member 74 and has a height that prevents the lower surface 74A of the adhesive member 74 from contacting the upper portion of the third metal wire 24. 4 gap D A fourth support that supports the adhesive member 78 on the upper surface 83A of the corresponding portion of the semiconductor integrated circuit 83 and has a height that prevents the lower surface 78A of the adhesive member 78 and the upper portion of the fourth metal wire 75 from contacting each other. By providing the member 102 and stacking the second to fifth semiconductor chips 17, 21, 73, 77 on the first semiconductor chip 13, the first to fifth semiconductor chips 13 are used using the spacers 204, 207. , 17, 21, 73, 77, the size in the height direction of the semiconductor device 100 can be reduced.

  The preferred embodiments of the present invention have been described in detail above, but the present invention is not limited to such specific embodiments, and within the scope of the present invention described in the claims, Various modifications and changes are possible.

  The present invention can be applied to a semiconductor device including a plurality of semiconductor chips stacked on a wiring board.

It is sectional drawing of the conventional semiconductor device. 1 is a cross-sectional view of a semiconductor device according to a first embodiment of the present invention. FIG. 3 is a plan view of the semiconductor device shown in FIG. 2. FIG. 6 is a diagram (part 1) illustrating a manufacturing process of the semiconductor device according to the first embodiment of the invention; FIG. 8 is a diagram (part 2) for illustrating a manufacturing step of the semiconductor device according to the first embodiment of the present invention; It is FIG. (The 3) which shows the manufacturing process of the semiconductor device which concerns on the 1st Embodiment of this invention. FIG. 4 is a diagram (part 4) illustrating a manufacturing step of the semiconductor device according to the first embodiment of the present invention; It is FIG. (5) which shows the manufacturing process of the semiconductor device which concerns on the 1st Embodiment of this invention. It is FIG. (6) which shows the manufacturing process of the semiconductor device which concerns on the 1st Embodiment of this invention. It is FIG. (The 7) which shows the manufacturing process of the semiconductor device which concerns on the 1st Embodiment of this invention. It is FIG. (The 8) which shows the manufacturing process of the semiconductor device which concerns on the 1st Embodiment of this invention. It is FIG. (9) which shows the manufacturing process of the semiconductor device which concerns on the 1st Embodiment of this invention. It is FIG. (10) which shows the manufacturing process of the semiconductor device which concerns on the 1st Embodiment of this invention. It is FIG. (11) which shows the manufacturing process of the semiconductor device which concerns on the 1st Embodiment of this invention. It is sectional drawing of the semiconductor device which concerns on the 1st modification of the 1st Embodiment of this invention. It is sectional drawing of the semiconductor device which concerns on the 2nd modification of the 1st Embodiment of this invention. It is sectional drawing of the semiconductor device which concerns on the 2nd Embodiment of this invention. It is sectional drawing of the semiconductor device which concerns on the 1st modification of the 2nd Embodiment of this invention. It is sectional drawing of the semiconductor device which concerns on the 2nd modification of the 2nd Embodiment of this invention.

Explanation of symbols

10, 60, 65, 70, 95, 100 Semiconductor device 11, 71 Wiring board 13 First semiconductor chip 14, 18, 22, 74, 78 Adhesive member 15 First metal wire 17 Second semiconductor chip 18A, 22A , 31B, 74A, 78A, 82B, 87B Lower surface 19 Second metal wire 21 Third semiconductor chip 24 Third metal wire 26 Sealing resin 31 Wiring board body 31A, 38A, 42A, 47A, 83A, 87A, 88A Upper surface 33 to 35, 80, 81 Pad 37, 41, 46, 82, 87 Semiconductor substrate 37A, 41A, 46A, 82A, 87A Front surface 37B, 41B, 46B, 82B, 87B Back surface 38, 42, 47, 83, 88 Semiconductor Integrated circuit 39, 43, 48, 84, 89 Electrode pad 55 Die 56 Recess 58 Liquid resin 61, 6 First support member 62, 67 Second support member 73 Fourth semiconductor chip 75 Fourth metal wire 77 Fifth semiconductor chip 79 Fifth metal wire 96, 101 Third support member 97, 102 Fourth Support member A first gap B second gap C third gap D fourth gap H ₁ , H ₂ , H ₃ , H ₄ , H ₅ height

Claims (11)

A wiring board;
A first semiconductor chip body that is square in plan view and is bonded to the upper surface of the wiring board; and provided on a main surface of the first semiconductor chip body; and the wiring board via a first metal wire A first semiconductor chip having a first electrode pad electrically connected;
A second semiconductor chip body having a square shape in plan view; and a second semiconductor chip body provided on a main surface of the second semiconductor chip body and electrically connected to the wiring board via a second metal wire A second semiconductor chip having an electrode pad;
A third semiconductor chip body having a square shape in plan view and a third semiconductor chip provided on the main surface of the third semiconductor chip body and electrically connected to the wiring board via a third metal wire A third semiconductor chip having an electrode pad,
A semiconductor device in which the second and third semiconductor chips are disposed above the first semiconductor chip,
The portion of the second semiconductor chip body located on the opposite side of the main surface of the second semiconductor chip body is bonded to the upper portion of the first metal wire and the main surface of the first semiconductor chip body. With
The portion of the third semiconductor chip located on the opposite side of the main surface of the third semiconductor chip body so that the main surface of the third semiconductor chip body and the upper surface of the wiring substrate are substantially parallel to each other. A semiconductor device characterized in that a main body is bonded to an upper portion of the second metal wire and a main surface of the second semiconductor chip main body. The first electrode pads are arranged so as to form one row on two opposite sides of the first semiconductor chip body, and the second electrode pads are arranged on the second semiconductor chip body. The third electrode pads are arranged to form one row on the two opposite sides of the third semiconductor chip body, respectively. And
In a state where the first to third semiconductor chips stacked on the wiring board are viewed in plan, the first to third electrode pads are arranged so that the arrangement directions of the first to third electrode pads are substantially parallel to each other. 2. The semiconductor device according to claim 1, wherein the semiconductor chips are stacked. The outer shape of the second semiconductor chip body is substantially equal to the outer shape of the first semiconductor chip body or larger than the outer shape of the first semiconductor chip body,
The outer shape of the third semiconductor chip body is substantially equal to the outer shape of the second semiconductor chip body or larger than the outer shape of the second semiconductor chip body. Semiconductor device. A first gap is formed between the first semiconductor chip and the second semiconductor chip,
4. The device according to claim 1, wherein a first support member that supports the second semiconductor chip is provided on the first semiconductor chip in a portion corresponding to the first gap. 5. The semiconductor device according to 1. A second gap is formed between the second semiconductor chip and the third semiconductor chip,
5. The device according to claim 1, wherein a second support member that supports the third semiconductor chip is provided on the second semiconductor chip in a portion corresponding to the second gap. The semiconductor device according to 1.   The sealing resin for sealing the first to third semiconductor chips and the first to third metal wires is provided on the upper surface of the wiring board. A semiconductor device according to claim 1. A fourth semiconductor chip body having a square shape in plan view; a fourth semiconductor chip body provided on the main surface of the fourth semiconductor chip body; and electrically connected to the wiring board via a fourth metal wire A fourth semiconductor chip having electrode pads;
A fifth semiconductor chip body having a square shape in plan view, and a fifth semiconductor chip provided on the main surface of the fifth semiconductor chip body and electrically connected to the wiring board via a fifth metal wire A fifth semiconductor chip having an electrode pad,
The portion of the fourth semiconductor chip body located on the opposite side of the main surface of the fourth semiconductor chip body is bonded to the upper part of the third metal wire and the main surface of the third semiconductor chip body. With
The portion of the fifth semiconductor chip located on the opposite side of the main surface of the fifth semiconductor chip body so that the main surface of the fifth semiconductor chip body and the upper surface of the wiring board are substantially parallel to each other. The semiconductor device according to claim 1, wherein a main body is bonded to an upper portion of the fourth metal wire and a main surface of the fourth semiconductor chip main body. The fourth electrode pads are arranged so as to form one row on two opposite sides of the fourth semiconductor chip body, and the fifth electrode pads are arranged on the fifth semiconductor chip body. Are arranged so as to form one row on each of two opposite sides of
In the state where the first to fifth semiconductor chips stacked on the wiring substrate are viewed in plan, the fourth and fifth electrodes are arranged so that the arrangement directions of the first to fifth electrode pads are substantially parallel to each other. 8. The semiconductor device according to claim 7, wherein the semiconductor chips are stacked. The outer shape of the fourth semiconductor chip body is substantially equal to the outer shape of the third semiconductor chip body or larger than the outer shape of the third semiconductor chip body,
9. The outer shape of the fifth semiconductor chip body is substantially equal to or larger than the outer shape of the fourth semiconductor chip body. Semiconductor device. A third gap is formed between the third semiconductor chip and the fourth semiconductor chip,
The third support member for supporting the fourth semiconductor chip is provided on the third semiconductor chip at a portion corresponding to the third gap, wherein the third support member is provided. The semiconductor device according to 1. A fourth gap is formed between the fourth semiconductor chip and the fifth semiconductor chip,
11. The fourth support member for supporting the fifth semiconductor chip is provided on the fourth semiconductor chip in a portion corresponding to the fourth gap. The semiconductor device according to 1.

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