JP2009283862A - Thin film transistor and production method therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To densely dispose the thin-film transistors (TFT) of a thin-film transistor circuit comprising a thin and light image display apparatus or a flexible electronic apparatus, and to reduce the production cost by employing a small number of production steps. <P>SOLUTION: After patterning first layer electrodes of the thin-film transistor by a coating method, a dropping method or a printing method, second layer electrodes are formed by a coating method, a dropping method or a printing method with the second layer electrodes positioned corresponding to the first layer electrodes. The second layer electrodes are disposed so that a separated state of projection images of the first layer electrode shapes is achieved, while using a light shielding mask in an exposing step. For example, in the case the thin-film transistors are disposed parallel with each other, the projection images of the electrodes to the principal plane of a translucent substrate have an embodiment with the second layer electrodes disposed so as to be surrounded by the first layer electrodes or an embodiment with a part of the first layer electrodes projected so as to be separated from the second layer electrode arrangement. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a thin film transistor (hereinafter referred to as TFT) device and a method for manufacturing the same.

  As a prior art, there is an example of a TFT using an organic semiconductor layer, which is disclosed in, for example, Japanese Patent Application Laid-Open No. 2007-088001 (Patent Document 1). In this example, a coating drop printing technique is used for manufacturing a TFT, and an active matrix image display device to which it is applied can be formed.

  As a second example, there is an example of an organic semiconductor layer using an anodic oxide film, which is disclosed in, for example, Japanese Patent Application Laid-Open No. 2004-152959 (Patent Document 2). Also in this example, an array of organic TFTs on a flexible substrate and an image display device using the same can be formed.

JP 2007-088001 JP 2004-152959 A

  Future technologies include thin, lightweight, impact-resistant, portable, and storable display devices, cards with authentication functions, image display devices that are mounted on curved surfaces, and electronic labels with integrated circuits. Realization of a so-called flexible electronic device such as a type matrix sensor is expected. These devices are devices having a relatively large area of several centimeters to several tens of centimeters or more, or devices that are used by being added to cards or labels that have been conventionally produced by printing. It is necessary to reduce the manufacturing cost per hit.

  As a transistor substrate technology for realizing these devices, there is an organic TFT which is the first example, and these organic TFTs are formed by a coating drop printing technique or a mask vapor deposition technique. However, these technologies are inferior in processing accuracy and alignment accuracy compared to conventional photolithography technology. Therefore, with such a technique, it is difficult to achieve fine processing, high performance, low power consumption, and high functionality with a manufacturing method that reduces manufacturing costs on a flexible substrate.

  In the organic TFT as the second example, vacuum technology or photolithography technology is used for manufacturing, but it is difficult to simplify the manufacturing process and reduce manufacturing cost.

The gist of the present invention is as follows.
As a structure of the TFT, there are a bottom gate structure in which the gate electrode is below the semiconductor layer and a top gate structure in which the gate electrode is above the semiconductor layer with reference to a light-transmitting substrate for TFT. In any structure, the conductor layer other than the formation of the first layer electrode (that is, the gate electrode or the source / drain electrode) is patterned by coating, dropping, or printing technique. At this time, a so-called self-alignment technique in which the alignment of the source / drain electrode is aligned with the gate electrode or the alignment of the gate electrode is aligned with the source / drain electrode by using exposure from the back surface of the TFT substrate. Thus, a TFT is formed.

  In the present invention, the following shape is taken with respect to the projected image of the gate electrode or the source / drain electrode onto the TFT substrate surface. In the following description of the present application, the arrangement relationship of the gate electrode or the source / drain electrode and the electrode conductor layer (so-called dummy electrode) formed in the same process is the same unless otherwise specified. It means the relationship in the projected image of the electrode and each dummy electrode on the TFT substrate surface, that is, the relationship in a plan view.

  The present invention relates to the relationship between the arrangement of the gate electrode and the source / drain electrode on the substrate surface in the TFT and the relationship between the planar shape, and more specifically, the gate electrode and the source / drain electrode, and The present invention relates to the arrangement of the conductor layers for each electrode formed in the same process as the gate electrode and the source / drain electrode and the mutual relationship between the planar shapes. Even if the conductor layer does not serve as a specific electrode, it contributes to how densely the TFT gate electrode and source / drain electrode are arranged depending on how and how each conductor layer shape is arranged. I can do it. In this sense, the terms “gate electrode” and “source / drain electrode” are used to mean the conductor layer for each electrode including the dummy gate electrode and the dummy source / drain electrode unless otherwise specified. Needless to say, the roles of the gate electrode and the source / drain electrode or the dummy gate electrode and the dummy source / drain electrode are left to the design based on the inventive concept of the present invention.

  The term “source / drain electrode” means a source or drain electrode. Which role is to be played is required to be named by the circuit in which the TFT operates. As the physical configuration, since they are in a mutually interchangeable relationship, they will be referred to as source / drain electrodes in this specification.

  When this self-alignment technique is used for a bottom-gate TFT, the source / drain electrodes are arranged by using the planar shape of the gate electrode as a light-shielding mask for exposure and then separating. At this time, (1) when the TFTs are arranged on the matrix as in the TFT array, the source / drain electrodes are arranged so as to be surrounded by the gate electrodes. (2) When the TFTs are arranged in one direction in a circuit such as a logic gate, a part of the gate electrode for separation protrudes from the arrangement of the source / drain electrodes. It is the first main form of the present invention that the gate electrode and the source / drain electrode are arranged in this manner with respect to the TFT having the bottom gate structure.

  When this self-alignment technique is used for a TFT having a top gate structure, the arrangement of the gate electrode is performed by forming and separating the planar shape of the source / drain electrode as a light shielding mask for exposure. At this time, (1) when the TFTs are arranged on the matrix as in the TFT array, the arrangement of the gate electrodes or the source / drain electrodes of the TFTs is an arrangement surrounded by the source / drain electrodes. (2) In a circuit such as a logic gate, when TFTs are arranged in one direction, a part of the source / drain electrodes for separation is projected depending on the arrangement of the gate electrodes. It is the second main form of the present invention that the gate electrode and the source / drain electrode are arranged in this manner with respect to the TFT having the top gate structure.

  Further, by using this self-alignment technique and TFT electrode arrangement technique, the arrangement interval of the source / drain electrodes or the arrangement interval of the gate electrodes of the adjacent first and second TFTs is determined by a coating method, a dropping method or a printing method. It is possible to provide a thin film transistor device that is closer than the arrangement interval determined by the processing accuracy and the alignment accuracy.

The summary of the method of manufacturing the thin film transistor device is as follows.
(1) In the case of the bottom gate structure, first, a gate electrode is patterned on a light-transmitting substrate for TFT, and a gate insulating film is formed thereon. Subsequent steps, two methods are conceivable. That is, the first is to expose the back surface of the transparent substrate while using the gate electrode as a light shielding mask to pattern the source / drain electrode so that the position of the source / drain electrode is aligned with the gate electrode. It is a method of forming. Alternatively, after the gate insulating film is formed and the semiconductor layer is formed, the gate electrode is used as a light shielding mask and exposed from the back surface of the transparent substrate, so that the position of the source / drain electrode is changed to the gate. This is a method of patterning in alignment with the electrodes.

The point is that, in any of the above methods, when performing the backside exposure, a gate electrode serving as a light shielding mask is arranged between the arrangements of the source / drain electrodes of the plurality of TFTs. The electrode arrangement is characterized in that the gate electrode is partially protruded from the source / drain electrode. Furthermore, it is of course possible to form a pattern using the above-described electrode arrangements, that is, the arrangement in which the gate electrode surrounds the source / drain electrode and the arrangement in which the gate electrode partially protrudes from the source / drain electrode. It is.
(2) In the case of the top gate structure, first, a semiconductor layer is formed after patterning a source / drain electrode on a light-transmitting substrate for TFT, or a source / drain electrode is formed after forming a semiconductor layer. Pattern. At this stage, two methods are also conceivable, details of which will be described later.

  Thereafter, a gate insulating film is formed, and patterning is performed by aligning the position of the gate electrode with the source / drain electrode by exposing from the back surface of the transparent substrate while using the source / drain electrode as a light shielding mask.

  The point is that, in any of the above methods, when performing this backside exposure, a source / drain electrode serving as a light shielding mask is arranged between the gate electrode arrangements of a plurality of TFTs, and the source / drain electrode is a gate electrode or a source electrode. The electrode arrangement is characterized by surrounding the / drain electrode, or by arranging the source / drain electrode partially protruding from the gate electrode. Further, a pattern using the above-described electrode arrangements, that is, the arrangement in which the source / drain electrodes surround the gate electrode or the source / drain electrodes, or the arrangement in which the source / drain electrodes partially protrude from the gate electrode is configured. Of course, it is also possible.

  According to the present invention, the arrangement of each electrode in the entire device can be made very dense while using the coating printing method and aligning the positional relationship between the gate electrode and the source / drain electrode in a plurality of arranged TFTs. I can do it.

Example 1
The first embodiment is an example in which a bottom gate TFT is formed by a self-alignment technique. In this example, since the gate electrode is finely processed and the source / drain electrode is patterned in a region without the gate electrode, it is higher than the processing size and alignment accuracy limited by coating, dripping or printing, and the TFT arrangement pitch. Processing with accuracy is possible. Therefore, the pixel pitch of the active matrix image display device, the arrangement pitch of the NOR and NAND logic gate TFTs can be reduced, the overlap capacity of the TFT gate electrode and the source / drain electrode, and the channel The gate capacity can be minimized and the channel length can be the minimum feature size of the initial gate microfabrication. By these means, a high-definition image display device and a high-performance / low-power-consumption / high-functional circuit configuration can be achieved by a simple and cost-effective coating or dropping or printing method.

[Example of thin film transistor device and basic manufacturing process]
A first embodiment of the present invention will be described with reference to FIGS. This embodiment is an example of a TFT pixel circuit array of an active matrix image display device and a thin film transistor device configured with a NOR or NAND logic circuit. As a specific configuration example, for example, it is a thin and light, and can be used even when bent to a radius of curvature of about 1 cm or less, and on a flexible plastic substrate by a coating printing method using a self-alignment technique. An organic TFT having a bottom gate structure to be formed was taken as an example. A TFT circuit represented by such an example has high performance and low power consumption, and thus can provide various functions and systems.

  First, a basic manufacturing process will be described. 6 to 10 show the cross-sectional structure of the device in the order of the TFT manufacturing process. In this example, a TFT is formed by a self-alignment technique using so-called back exposure. The organic semiconductor layer TFT can be formed directly on a plastic substrate with low heat resistance by using, for example, a coating printing method and setting all process temperatures to 200 ° C. or lower. The semiconductor layer is translucent to the exposure light. Therefore, it is possible to take a partially modified manufacturing process which will be described later.

  First, as shown in FIG. 6, a gate electrode material is provided on a transparent plastic substrate 50, and a gate electrode 51 is formed by a direct exposure technique that does not require a mask. At this time, the width of the gate electrode 51 is formed with the minimum processing size, but in this embodiment, it is about 4 μm to 5 μm, for example. Here, as another method, it is also possible to use a lithography technique using a photomask only for patterning in this step. Also, for example, a printing technique capable of patterning of 4 μm to 5 μm, such as reverse offset printing, can be used.

Next, a coating type gate insulating film 52 such as a coating type SiO ₂ film or an organic polymer insulating film is applied. Thereafter, a photosensitive self-assembled monomolecular film (Self-Assemble-Monolayer, hereinafter referred to as SAM film) 53 having a water repellent function is applied. Here, a water-repellent resist film may be used instead of the SAM film.

Next, as shown in FIG. 7, post-processing related to exposure and photolithography is performed from the back surface of the transparent substrate 50.
At this time, the gate electrode 51 serves as a light shielding mask, the water-repellent group remains in the photosensitive SAM film 53 above the gate electrode 51, and the water-repellent group is detached from the photosensitive SAM film 53 in the other region, so that the hydrophilic region 54.

  As shown in FIG. 8, a source / drain electrode 55 is selectively applied by a print patterning technique using a metal ink such as Au, Ag, or Cu. At this time, since the SAM film 53 has water repellency, the metal ink material is not applied on the SAM film 53. Therefore, the position of the source / drain 55 is self-aligned with the gate electrode 51, and the overlap of both electrodes can be suppressed.

  As shown in FIG. 9, after the SAM film 53 is removed by a method such as overall exposure, an organic semiconductor film 56 such as a coating type pentacene is selectively applied by a coating method, a dropping method, or a printing method.

  Finally, as shown in FIG. 10, a protective film 57 made of, for example, an organic polymer material is applied, and a desired region is selectively opened. A wiring layer 58 is formed by a printing patterning method, and this opening is used to connect a gate electrode and a source / drain electrode and other electrodes necessary for circuit formation. Thus, a thin film transistor device constituted by a TFT circuit is completed. The protective film 57 can be formed selectively by, for example, a printing patterning method.

As described above, here, the following method can be used for forming the source / drain electrodes by the self-alignment method by the backside exposure. FIG. 11 to FIG. 15 are sectional views of the apparatus in the order of the manufacturing process according to this method. Reference numerals in the figure are the same as those in FIGS. That is, as shown in FIG. 11, the gate electrode 51 is formed on the transparent plastic substrate 50. As described above, a coating type gate insulating film 52 such as a coating type SiO ₂ film or an organic polymer insulating film is applied. Next, a semiconductor film 56 is formed on the gate insulating film 52 (FIG. 12). Thereafter, a conductor layer for the source / drain electrodes is formed and exposed from the back surface of the transparent substrate 50 (FIG. 13). At this time, the semiconductor film is translucent, the gate electrode 51 serves as a light-shielding mask, the position of the source / drain electrode is self-aligned with the gate electrode 51, and the overlap of both electrodes can be suppressed. Thereafter, as in the previous examples, a protective film 57 made of, for example, an organic polymer material is applied, and a desired region is selectively opened. It is also possible to selectively form the wiring layer 58 by a printing patterning method (FIG. 14), thus forming a so-called top contact TFT.

  The plastic substrate 50 used in this embodiment can be a plastic substrate such as polyethylene terephthalate, polyethylene naphthalate, polycarbonate, polyimide, polyethersulfone, but is not limited to the plastic substrate in this embodiment. Absent. As the electrode wiring materials 51, 55, 58, metal ink such as Ag ink, Au ink, Cu ink, conductive organic material such as PEDOT, transparent electrode material, and the like are possible. As the coating printing method, for example, a normal printing method such as an ink jet method, an offset printing method, an electrophotographic method, a dispenser method, or a plating method can be used. As the gate insulating film 52, a coating-type high dielectric constant metal oxide film can be used in addition to the material of the present embodiment. The coating type organic semiconductor material 56 can be pentacene or a derivative thereof, a low molecular organic material such as porphyrin, or a high molecular organic material such as P3HT (polythiophene) or F8T2 (polyfluorenethiophene copolymer). is there. Further, it can be formed by coating, for example, coating type Si, coating type amorphous oxide semiconductor, or the like.

  A specific example in which TFTs formed by this manufacturing method are arranged is shown in FIG. In this embodiment, the thinnest region of the gate electrode 1 uses a direct exposure technique that does not use a mask. In this embodiment, this region has a width of 4 μm to 5 μm, for example. Since all other patterning uses a coating printing method, the processing dimension accuracy and alignment accuracy are, for example, 20 μm or more.

  Here, main reference numerals in the drawings will be described. Reference numeral 1 is a gate electrode, 2a and 2b are source / drain electrodes, 3 is a semiconductor layer, 4 is a contact hole, and 5a and 5b are wirings. In the example of FIG. 1, the source / drain electrode conductor layer 2b is formed of the same layer as the layer 2a. Therefore, the source / drain electrode conductor layer 2b is an actual source / drain electrode role. It is a so-called “dummy electrode” that does not play. The conductive layer for the gate electrode is the same, and does not play the role of the actual gate electrode, but the layer formed of the same layer is referred to as a dummy gate electrode as described above. In addition, 1a, 2a-1, and 2a-2 illustrated the gate electrode and source / drain electrode corresponding to individual TFT. Reference numerals 3a, 3b, 3c and 3d denote channels of four arranged TFTs. In the plan view of FIG. 1, the region where the semiconductor layer 3 and the gate electrode 1 intersect is the active region of the gate insulating field effect TFT. In FIG. 1, four TFTs are arranged. Specifically, for example, a region where the gate electrode 1a intersects the semiconductor layer 3a is a channel. Source / drain electrodes 2a-1 and 2a-2 are arranged on both sides of the channel. In FIG. 1, only the TFT of 3a is illustrated and described in detail.

  Since a source / drain electrode and a source / drain electrode conductor layer (that is, a dummy electrode) are formed in a region other than the gate electrode 1, the source / drain electrode 2 a is disposed so as to be surrounded by the gate electrode 1. When patterning the source / drain electrode, the source / drain electrode is also formed outside the region surrounded by the gate electrode 1 as shown in FIG. Material 2b is applied. However, as described above, the source / drain electrode material is not applied to the region of the gate electrode 1 because the source / drain electrode is formed by the self-alignment method by backside exposure using the gate electrode as a light shielding mask. Thus, the source / drain electrode 2a and the dummy source / drain electrode 2b are electrically separated. Gate electrode 1 and source / drain electrode 2a are connected to upper wirings 5a and 5b through contact holes, respectively, and a circuit is configured by connecting these wirings. With such an arrangement, as shown in FIG. 1, the arrangement intervals of the source / drain electrodes of different TFTs can be arranged closer than the intervals considering the processing dimensional accuracy and alignment accuracy of coating printing. .

  A region where the selectively coated semiconductor layer 3 and the gate electrode 1 intersect is a channel region. Since the width of the gate electrode in this region is 4 μm to 5 μm, which is the minimum processing size, the processing accuracy is 20 μm. Even if the source / drain electrodes are patterned by the printing method described above, a TFT having a channel length of 4 μm to 5 μm is possible.

  Furthermore, since the gate electrode 1 and the source / drain electrode 2a are formed by the self-alignment technique, there is no overlap. Further, since the semiconductor layer 3 does not protrude from the source / drain-in electrode 2a, the width of the semiconductor layer 3 is equal to the channel width. In this way, the area where the source / drain electrode 2a and the semiconductor layer 3 are added together with the area of the gate electrode 1 intersects with the area of the area where carriers involved in channel electrical conduction are induced by the gate electrode. , Can be equal. As a result, the gate parasitic capacitance is almost zero except for the gate capacitance necessary for inducing channel conduction carriers, realizing the minimum gate parasitic capacitance and enabling high-speed performance.

[Example of thin film transistor device in which TFTs are arranged in a matrix]
Next, an example in which the TFT of this example is applied to a pixel circuit of an active matrix organic EL image display device is shown in FIGS. 2A and 2B. FIG. 2A is a plan view of three pixels, and FIG. 2B is a circuit diagram of a part of the pixel matrix, showing a circuit of 3 × 3 pixels. The source / drain electrodes of the switching TFT 16 are 12a and 12b, the gate electrode is 11a, and the semiconductor layer is 13a. The source / drain electrode 12a is connected to the drain wiring 15a through the contact hole 14, and constitutes a drain line 15c in the circuit diagram. The gate electrode 11a is common with the gate electrode of the switching TFT of the adjacent pixel, and constitutes a gate line 11c in the circuit diagram. The source / drain electrodes of a TFT 17 that drives an organic light emitting diode (hereinafter referred to as OLED) 18 are 12c and 12d, the gate electrode is 11b, and the semiconductor layer is 13b. The source / drain electrode 12b of the TFT 16 and the gate electrode 11b of the TFT 17 are connected via the internal wiring 15b, and the source / drain electrode 12c of the TFT 17 is connected to the OLED via the internal wiring. The source / drain electrode 12d of the TFT 17 is a common electrode with an adjacent pixel, and constitutes a wiring 12e in the circuit diagram.

  In this way, by using the self-alignment technique, the source / drain electrodes are separated by the gate electrode, and the electrode having the characteristics such that the source / drain electrode is surrounded by the gate electrode is used. The arrangement interval can be arranged closer than the interval considering the processing dimension accuracy and alignment accuracy of coating printing. As a result, it is possible to improve the definition of the image display device. In this embodiment, the resolution is about 100 ppi or higher despite the processing dimensional accuracy and alignment accuracy of the coating printing method being about 20 μm or more. A fine image display device can be realized. In addition, since the TFT has the minimum gate parasitic capacitance as well as the minimum processing dimension of the channel length of 4 μm to 5 μm, high-speed display performance can also be realized.

[Example of thin film transistor device in which TFTs are arranged in a matrix]
Next, an example in which the TFT of this example is applied to a pixel circuit of an active matrix image display device is shown in FIGS. 3A and 3B. Here, the display device is, for example, a liquid crystal display device or an electrophoretic display device having a memory property. 3A is a plan view of three pixels, and FIG. 3B is a circuit diagram of a part of a pixel matrix, showing a circuit for 3 × 3 pixels.

  The switching TFT 26 has a source / drain electrode 22, a gate electrode 21 a, and a semiconductor layer 23. The source / drain electrode 22 is connected to the drain wiring 25a through the contact hole 24 and constitutes a drain line 25c in the circuit diagram. The gate electrode 21a is in common with the gate electrode of the switching TFT of the adjacent pixel, and constitutes a gate line 21b in the circuit diagram. This TFT is connected to the display device 27 via the internal wiring 25b. Here, the display device 27 is, for example, a liquid crystal display device or an electrophoretic display device having a memory property.

  In this way, by using the self-alignment technique, the source / drain electrodes are separated by the gate electrode, and the electrode having the characteristics such that the source / drain electrode is surrounded by the gate electrode is used. The arrangement interval can be arranged closer than the interval considering the processing dimension accuracy and alignment accuracy of coating printing. As a result, it is possible to improve the definition of the image display device. In this embodiment, the resolution is about 100 ppi or higher despite the processing dimensional accuracy and alignment accuracy of the coating printing method being about 20 μm or more. A fine image display device can be realized. In addition, since the TFT has the minimum gate parasitic capacitance as well as the minimum processing dimension of the channel length of 4 μm to 5 μm, high-speed display performance can also be realized.

[Example of thin film transistor device using TFT in logic circuit]
Next, an example in which this TFT is applied to a 2-input NOR logic circuit is shown in FIGS. 4A and 4B. 4A is a plan view of one stage of the NOR circuit, and FIG. 4B is a circuit diagram showing two stages. The source / drain electrodes of the driving TFT 36 and the load TFT 37 are 32a, the gate electrode is 31a, the opening region of the contact hole 34 of the gate electrode is 31b, and the semiconductor layer is 33. Each electrode is connected to the internal wiring 35a and the power supply wiring 35b via the contact hole 34, and constitutes a logic circuit. The signal of the output OUT is connected to the next-stage inputs IN1 and IN2 through the internal wiring 35a, and performs a logical operation.

  Thus, using the self-alignment technique, the source / drain electrode is separated by the gate electrode, and the source / drain electrode is surrounded by the gate electrode, or a part of the gate electrode 31a is the source / drain electrode 32a, 32b. In order to arrange the electrodes having more protruding features, the arrangement intervals of adjacent source / drain electrodes can be arranged closer than the intervals considering the processing dimensional accuracy and alignment accuracy of coating printing.

  When patterning the source / drain electrode, the source / drain electrode material 32b is applied to the outside of the region surrounded by the gate electrode 31a in order to perform patterning by a coating printing method with low processing dimensional accuracy and alignment accuracy. Since the source / drain electrode material is not applied to the region of the gate electrode, the electrode 32a and the electrode conductor layer 32b are electrically separated. As a result, the area of the logic circuit can be reduced. In addition, since the TFT has the minimum gate parasitic capacitance at the same time as the minimum processing dimension of the channel length of 4 μm to 5 μm, high-speed logic operation performance with low power consumption can also be realized.

[Example of thin film transistor device using TFT in 2-input logic circuit]
Next, an example in which the TFT of this example is applied to a 2-input NAND logic circuit is shown in FIGS. 5A and 5B. 5A is a plan view of one stage of the NAND circuit, and FIG. 5B is a circuit diagram showing two stages. The source / drain electrodes of the driving TFT 46 and the load TFT 47 are 42a, the gate electrode is 41a, the contact hole 44 opening region of the gate electrode is 41b, and the semiconductor layer is 43. Each electrode is connected to the internal wiring 45a and the power supply wiring 45b through the contact hole 44 to constitute a logic circuit. The signal of the output OUT is connected to the next-stage inputs IN1 and IN2 through the internal wiring 45a, and performs a logical operation.

  Thus, using the self-alignment technique, the source / drain electrode is separated by the gate electrode, and the source / drain electrode is surrounded by the gate electrode, or a part of the gate electrode 41a is the source / drain electrode 42a, 42b. In order to make the electrode arrangement with more prominent features, the arrangement intervals of adjacent source / drain electrodes can be arranged closer than the intervals considering the processing dimension accuracy and alignment accuracy of coating printing.

  When patterning the source / drain electrode, the source / drain electrode material 42b is applied to the outside of the region surrounded by the gate electrode 41a in order to perform patterning by a coating printing method with low processing dimensional accuracy and alignment accuracy. Since the source / drain electrode material is not applied to the region of the gate electrode, the electrode 42a and the electrode conductor layer 42b are electrically separated. As a result, the area of the logic circuit can be reduced. In addition, since the TFT has the minimum gate parasitic capacitance at the same time as the minimum processing dimension of the channel length of 4 μm to 5 μm, high-speed logic operation performance with low power consumption can also be realized.

In the embodiments of these logic circuits, the TFT channel length is patterned to be about 4 μm to 5 μm, for example, and a semiconductor material in which the field effect mobility of the TFT is 1 cm ² / Vs or more is used to minimize the gate parasitic capacitance. By doing so, for example, the operation delay time per stage of one input no-load inverter is reduced to about 5 ns or less, and for example, the oscillation frequency of a ring oscillator in which no-load inverters are connected in multiple stages operates at about 50 WHz or more. It is possible to make it. In addition, by using direct exposure without using a mask, the pattern length of the gate electrode is further reduced to shorten the channel length, and it can be applied to various circuits other than this embodiment, thereby achieving higher speed and multifunctionality. It is also possible to realize circuit operation.

(Example 2)
The second embodiment is an example in which a top gate TFT is formed by a self-alignment technique. In this example, since the source / drain electrode is finely processed and the gate electrode is patterned in a region without the source / drain electrode, the processing dimensions and alignment accuracy limited by the coating, dripping or printing method, and the TFT arrangement pitch are used. Processing with high accuracy becomes possible. Therefore, the pixel pitch of the active matrix image display device and the arrangement pitch of NOR and NAND logic gate TFTs can be reduced. Further, the overlap capacity of the TFT gate electrode and the source / drain electrode and the gate capacity of the channel can be minimized, and the channel length can be set to the minimum processing dimension of the first gate microfabrication. By these means, a high-definition image display device and a high-performance / low-power-consumption / high-functional circuit configuration can be achieved by a simple and cost-effective coating or dropping or printing method.

[Example of thin film transistor device and its basic manufacturing method]
A second embodiment of the present invention will be described with reference to FIGS. 16A to 25. This embodiment is an example of a TFT pixel circuit array of an active matrix image display device and a thin film transistor device configured with a NOR or NAND logic circuit. As a specific configuration example, for example, a thin and lightweight coating printing method using a self-alignment technique on a flexible plastic substrate that can be used even when the radius of curvature is around 1 cm or less. An organic TFT with a top gate structure formed in the above was taken as an example. A TFT circuit represented by such an example has high performance and low power consumption, and thus can provide various functions and systems.

  First, a basic manufacturing process will be described. 21 to 25 show the cross-sectional structure of the device in the order of the TFT manufacturing process. In this example, a TFT is formed by a self-alignment technique using so-called back exposure. This organic semiconductor TFT can be directly formed on a plastic substrate with low heat resistance by using, for example, a coating printing method and setting all process temperatures to 200 ° C. or lower. The semiconductor layer is translucent to the exposure light.

  First, as shown in FIG. 21, a source / drain electrode material is provided on a transparent (translucent) plastic substrate 110, and the source / drain electrode 111 is patterned by a direct exposure technique that does not require a mask. At this time, the distance between the source / drain electrodes 111 is formed with a minimum processing size, but in this embodiment, it is about 4 μm to 5 μm, for example. Here, as another method, it is also possible to use a lithography technique using a photomask only for patterning in this step. Further, for example, a printing technique capable of patterning of 4 μm to 5 μm, such as reverse offset printing, can be used.

  Next, as shown in FIG. 22, an organic semiconductor film 112 such as coating-type pentacene is selectively applied by a coating method, a dropping method, a printing method, or the like.

Next, as shown in FIG. 23, for example, a coating type gate insulating film 113 such as a coating type SiO ₂ film or an organic polymer insulating film is applied, and subsequently a water repellent resist film 114 is applied. Then, it exposes from the back surface of the transparent substrate 110, and also develops. At this time, the source / drain electrode 111 serves as a light shielding mask. Therefore, the water-repellent resist film 114 above the source / drain electrode 111 remains, and the water-repellent resist film in other regions is removed. Here, instead of the water-repellent resist film, a photosensitive SAM film can be used as in the first embodiment.

  Next, as shown in FIG. 24, a metal ink such as Au, Ag, or Cu, for example, is selectively poured into the groove surrounded by the resist by a coating printing patterning technique to form the gate electrode 115. At this time, the trench surrounded by the resist corresponds to the gate electrode region 63a of FIG. 16, and a wide gate electrode region 63b for opening the contact hole 64 is connected to the groove. Since the region 63b functions as an ink reservoir when the metal ink is poured, the metal ink can be efficiently poured into the gate electrode groove 63a. Further, since the resist film 114 has water repellency, the metal ink material is not applied on the water repellent resist film 114. Therefore, the position of the gate electrode 115 is self-aligned with the source / drain electrode 111, and the overlap of both electrodes can be suppressed.

  Finally, as shown in FIG. 25, after removing the water-repellent resist film 114, a protective film 116 made of, for example, an organic polymer material is applied to selectively open a desired region. A wiring layer 117 is formed by a printing patterning method, and a gate electrode and a source / drain electrode are connected and other electrodes necessary for circuit formation are connected to complete a thin film transistor device constituted by a TFT circuit. The protective film 116 can be selectively applied by, for example, a printing patterning method.

  As described above, in the case of the top gate structure, first, in addition to patterning the source / drain electrodes after forming the semiconductor layer on the light-transmitting substrate for TFT, the source / drain is formed after forming the semiconductor layer. A method of patterning the drain electrode is also conceivable. The second method is shown in FIGS. First, the semiconductor layer 112 is formed on the translucent substrate 110 (FIG. 27), and the source / drain electrode 111 is formed thereon (FIG. 27). Next, a gate insulating film 113 is formed, and a water repellent resist film 114 is formed thereon. Then, exposure is performed from the back (FIG. 28). A gate electrode 115 is formed at the selectively removed portion (FIG. 24). Finally, the protective film 116 and the wiring 117 are formed as before.

  The plastic substrate 110 used in this embodiment can be a plastic substrate such as polyethylene terephthalate, polyethylene naphthalate, polycarbonate, polyimide, polyethersulfone, but is not limited to the plastic substrate exemplified in this embodiment. Not a thing. As the electrode wiring materials 111, 115, 117, metal ink such as Ag ink, Au ink, Cu ink, conductive organic material such as PEDOT, transparent electrode material, and the like are possible. As the coating printing method, for example, a normal printing method such as an ink jet method, an offset printing method, an electrophotographic method, a dispenser method, or a plating method can be used. As the gate insulating film 113, other than the material of this embodiment, a coating type high dielectric constant metal oxide film or the like can be used. The coated organic semiconductor material 112 can be pentacene or a derivative thereof, a low molecular organic material such as porphyrin, or a high molecular organic material such as P3HT (polythiophene) or F8T2 (polyfluorenethiophene copolymer). is there. Further, for example, a coating type Si or a coating type amorphous oxide semiconductor which can be formed by coating can be used.

  An example in which TFTs formed by this manufacturing method are arranged is shown in FIG. In the present embodiment, the narrowest distance between the source / drain electrodes 61a is the minimum processing dimension when using a direct exposure technique that does not use a mask. In this embodiment, the width is, for example, 4 to 5 μm. Since all other patterning uses a coating printing method, the processing dimension accuracy and alignment accuracy are, for example, 20 μm or more.

  Here, main reference numerals in the drawings will be described. Reference numerals 61a and 61b are source / drain electrodes and source / drain electrode conductor layers (ie, dummy source / drain electrodes), 62 is a semiconductor layer, 63a and 63b are gate electrodes, 63c is a conductor layer for gate electrodes, and 64 Are contact holes, and 65a and 65b are wirings. The region where the semiconductor layer intersects with the gate electrode is configured as a TFT channel as in the previous examples.

  In this example, the gate electrode is formed in a region other than the source / drain electrode 61a and the gate electrode separation dummy source / drain electrode 61b in accordance with the manufacturing method. For this reason, the gate electrodes 63a and 63b and the source / drain electrode 61a are arranged so as to be surrounded by the source / drain electrode 61a and the dummy source / drain electrode 61b. When patterning the gate electrode, the gate electrode material 63c is applied to the outside of the region surrounded by the dummy source / drain electrode 61b because the patterning is performed by a coating printing method with low processing dimensional accuracy and alignment accuracy. Since the gate electrode material is not applied to the / drain electrode region, the electrodes 63b and 63c are electrically separated. The source / drain electrode 61a and the gate electrode 63b are connected to upper wirings 65a and 65b through contact holes, respectively, and a circuit is configured by connecting these wirings.

  With such an arrangement, as shown in FIG. 16, different arrangement intervals between the source / drain electrodes and the gate of the TFT are arranged closer than the intervals considering the processing dimension accuracy and alignment accuracy of coating printing. be able to. Another feature of the pattern arrangement is that the wide gate electrode region 63b is connected to the narrow gate electrode region 63a. In the manufacturing process illustrated in FIG. 24, a groove surrounded by a resist is formed in these regions 63a and 63b. When metal ink is poured into this groove, the wide gate electrode groove 63b acts as an ink reservoir. In addition, the metal ink can be efficiently poured into the narrow gate electrode groove 63a.

  A region where the selectively coated semiconductor layer 62 and the gate electrode 63a intersect is a channel region. Since the distance between the source / drain electrodes in this region is the minimum processing size of 4 to 5 μm, the channel length TFT of 4 μm to 5 μm becomes possible. Furthermore, since the gate electrode is patterned by a printing method with processing accuracy and alignment accuracy of 20 μm or more because it is formed by a self-alignment technique, there is no overlap between the gate electrode 63a and the source / drain electrode 61a. Further, since the semiconductor layer 62 does not protrude from the source drain electrode 61a, the width of the semiconductor layer 62 is equal to the channel width. In this way, the area where the region where the source / drain electrode 61a and the semiconductor layer 62 are combined and the region of the gate electrode 63a intersects is the area of the region where carriers involved in channel electrical conduction are induced by the gate electrode. And can be made equal. As a result, the gate parasitic capacitance is almost zero except for the gate capacitance necessary for inducing channel conduction carriers, realizing the minimum gate parasitic capacitance and enabling high-speed performance.

[Application Example of Active Matrix Organic EL Image Display Device to Pixel Circuit]
Next, an example in which the TFT of this example is applied to a pixel circuit of an active matrix organic EL image display device is shown in FIGS. 17A and 17B. FIG. 17A is a plan view for three pixels, and FIG. 17B is a circuit diagram of a part of a pixel matrix, showing a circuit for 3 × 3 pixels. The source / drain electrodes of the switching TFT 76 are 71a and 71b, the gate electrode is 73a, and the semiconductor layer is 72a. The source / drain electrode 71a is connected to the drain wiring 75a through the contact hole 74, and constitutes a drain line 75c in the circuit diagram. The gate electrode 73a is in common with the gate electrode of the switching TFT of the adjacent pixel, and constitutes a gate line 73c in the circuit diagram. The source / drain electrodes of the TFT 77 that drives the OLED 78 are 71c and 71d, the gate electrode is 73b, and the semiconductor layer is 72b. The source / drain electrode 71b of the TFT 76 and the gate electrode 73b of the TFT 77 are connected via the internal wiring 75b, and the source / drain electrode 71c of the TFT 77 is connected to the OLED via the internal wiring. The source / drain electrode 71d of the TFT 77 is a common electrode with an adjacent pixel, and constitutes a wiring 71e in the circuit diagram.

  In this way, by using the self-alignment technique, the gate electrode is separated by the source / drain electrode, and the gate electrode is surrounded by the source / drain electrode or the source / drain electrode is surrounded by the gate electrode. In order to achieve the arrangement, the arrangement intervals of the adjacent pixel circuit configuration TFTs can be arranged closer than the intervals considering the processing dimensional accuracy and alignment accuracy of coating printing. As a result, it is possible to improve the definition of the image display device. In this embodiment, the resolution is about 100 ppi or higher despite the processing dimensional accuracy and alignment accuracy of the coating printing method being about 20 μm or more. A fine image display device can be realized. In addition, since the TFT has the minimum gate parasitic capacitance as well as the minimum processing dimension of the channel length of 4 μm to 5 μm, high-speed display performance can also be realized. Another feature of the pattern arrangement is that a wide gate electrode region is connected to a narrow gate electrode region. In the manufacturing process illustrated in FIG. 24, a groove surrounded by a resist is formed in these regions. When metal ink is poured into this groove, the wide gate electrode groove acts as an ink reservoir, and a narrow gate is formed. Metal ink can be efficiently poured into the electrode grooves.

[Example applied to pixel circuit of active matrix image display device]
Next, an example in which this TFT is applied to a pixel circuit of an active matrix image display device is shown in FIGS. 18A and 18B. Here, the display device is, for example, a liquid crystal display device or an electrophoretic display device having a memory property. FIG. 18A is a plan view of three pixels, and FIG. 18B is a circuit diagram of a part of the pixel matrix, showing a circuit of 3 × 3 pixels. The switching TFT 86 has a source / drain electrode of 81, a gate electrode of 83a, and a semiconductor layer of 82. The source / drain electrode 81-1 is connected to the drain wiring 85 a through the contact hole 84 to constitute a drain line 85 c in the circuit diagram. The gate electrode 83a is in common with the gate electrode of the switching TFT of the adjacent pixel, and constitutes a gate line 83b in the circuit diagram. The other source / drain electrode 81 -2 of this TFT is connected to the display device 87 via the internal wiring 85b. Here, the display device 87 is, for example, a liquid crystal display device or an electrophoretic display device having a memory property. Since the gate electrode is separated by the source / drain electrode using the self-alignment technique in this way, the TFT has a minimum processing dimension of 4 μm to 5 μm and at the same time, the TFT has a minimum gate parasitic capacitance. High-speed display performance can be realized. As a feature of the pattern arrangement, a wide gate electrode region is connected to a narrow gate electrode region. In the manufacturing process illustrated in FIG. 19, a groove surrounded by a resist is formed in these regions. When metal ink is poured into this groove, the wide gate electrode groove acts as an ink reservoir, and a narrow gate is formed. Metal ink can be efficiently poured into the electrode grooves.

[Example applied to 2-input NOR logic circuit]
Next, an example in which the TFT of this example is applied to a 2-input NOR logic circuit is shown in FIGS. 19A and 19B. FIG. 19A is a plan view of one stage of the NOR circuit, and FIG. 19B is a circuit diagram showing two stages. The source / drain electrodes of the driving TFTs 96-1, 96-2 and the load TFT 97 are 91a (91a-1, 91a-2, 91a-3), and the gate electrodes are 93a (93a-1, 93a-2, 93a). -3), and the semiconductor layer is 92. Each electrode is connected to the internal wiring 95a and the power supply wiring 95b through the contact hole 94 to form a logic circuit. The signal of the output OUT is connected to the next-stage inputs IN1 and IN2 via the internal wiring 95a, and performs a logical operation. Thus, using the self-alignment technique, the gate electrode is separated by the source / drain electrode, and the feature that the gate electrode is surrounded by the source / drain electrode, or the portion 91b of the source / drain electrode protrudes from the gate electrode 93a. In order to obtain the arrangement of the electrodes having the above characteristics, the arrangement intervals of the adjacent gate electrodes can be arranged closer than the intervals considering the processing dimensional accuracy and alignment accuracy of coating printing. When patterning the gate electrode, since the patterning is performed by a coating printing method with low processing dimensional accuracy and alignment accuracy, the gate electrode material 93b is also provided outside the region surrounded by the source / drain electrode 91b and the thin source / drain electrode 91b. However, since the gate electrode material is not applied to the source / drain electrode region, the electrodes 93a and 93b are electrically separated. As a result, the area of the logic circuit can be reduced. In addition, since the TFT has the minimum gate parasitic capacitance at the same time as the minimum processing dimension of the channel length of 4 μm to 5 μm, high-speed logic operation performance with low power consumption can also be realized. Another feature of the pattern arrangement is that a wide gate electrode region is connected to a narrow gate electrode region. In the manufacturing process illustrated in FIG. 24, a groove surrounded by a resist is formed in these regions. When metal ink is poured into this groove, the wide gate electrode groove acts as an ink reservoir, and a narrow gate is formed. Metal ink can be efficiently poured into the electrode grooves.

[Example applied to 2-input NAND logic circuit]
Next, an example in which the TFT of this example is applied to a 2-input NAND logic circuit is shown in FIG. 20A is a plan view of one stage of the NAND circuit, and FIG. 20B is a circuit diagram showing two stages. The source / drain electrodes of the driving TFTs 106-1 and 106-2 and the load TFT 107 are 101a, the gate electrode is 103a, and the semiconductor layer is 102. Each electrode is connected to the internal wiring 105a and the power supply wiring 105b through the contact hole 104 to form a logic circuit. The signal of the output OUT is connected to the next-stage inputs IN1 and IN2 through the internal wiring 105a, and performs a logical operation. Thus, using the self-alignment technique, the gate electrode is separated by the source / drain electrode, and the feature that the gate electrode is surrounded by the source / drain electrode, or the portion 101b of the source / drain electrode protrudes from the gate electrode 103a. In order to obtain the arrangement of the electrodes having the above characteristics, the arrangement intervals of the adjacent gate electrodes can be arranged closer than the intervals considering the processing dimensional accuracy and alignment accuracy of coating printing. When patterning the gate electrode, the gate electrode material 103b is applied to the outside of the region surrounded by the source / drain electrodes because the patterning is performed by a coating printing method with low processing dimensional accuracy and alignment accuracy. Since the gate electrode material is not applied to the electrode region, the electrodes 103a and 103b are electrically separated. As a result, the area of the logic circuit can be reduced. In addition, since the TFT has the minimum gate parasitic capacitance at the same time as the minimum processing dimension of the channel length of 4 μm to 5 μm, high-speed logic operation performance with low power consumption can also be realized. Another feature of the pattern arrangement is that a wide gate electrode region is connected to a narrow gate electrode region. In the manufacturing process illustrated in FIG. 19, a groove surrounded by a resist is formed in these regions. When metal ink is poured into this groove, the wide gate electrode groove acts as an ink reservoir, and a narrow gate is formed. Metal ink can be efficiently poured into the electrode grooves.

In the embodiments of these logic circuits, the TFT channel length is patterned to be about 4 μm to 5 μm as an example, and a semiconductor material having a field effect mobility of 1 cm ² / Vs or more in this example is used. By minimizing the capacity, for example, the operation delay time per stage of one input no-load inverter is reduced to about 5 ns or less, and for example, the oscillation frequency of a ring oscillator in which no-load inverters are connected in multiple stages is reduced to about It is possible to operate at about 50 MHz or higher. Furthermore, by using direct exposure without using a mask, the patterning interval of the source / drain electrodes is further reduced to shorten the channel length. It is also possible to realize functional circuit operation.

The effects obtained by Examples 1 and 2 are as follows. The manufacturing method using the coating drop printing technique and the mask vapor deposition technique is inferior in processing accuracy and alignment accuracy compared to the conventional photolithography technology, and it is difficult to achieve fine processing, high performance, low power consumption, and high functionality. . In addition, when vacuum technology or photolithography technology is used for manufacturing, it is difficult to simplify the manufacturing process and reduce manufacturing cost. In these examples, microfabrication such as direct exposure is used for the first electrode patterning, and all others are applied printing manufacturing methods, and the self-aligned manufacturing method is adopted, so that the manufacturing process is simplified and facilitated. , Miniaturization, high definition, and circuit area reduction. Further, it is possible to provide a high performance and low power consumption TFT circuit device capable of avoiding a decrease in alignment accuracy, which is generally a problem in a coating printing patterning method, and having a small overlap capacity between a gate and a source / drain. Is possible. By application of this device, as called electronic book, can be used for reading of reading and color photographic bent like paper, high performance with low power consumption display device, RF-ID (R adio F requency ID high-performance, low-power printed electronic tags, RF-ID and flexible cards with computing functions, RF-ID and electronic product labels with computing functions, wearable flexible Sensors etc. become possible.

  In the embodiments described above, various changes such as materials, patterning dimensions, specifications, manufacturing conditions, and manufacturing methods can be made without departing from the spirit of the present invention. Further, the TFT structure is not limited to these examples. For example, the present invention can be implemented in an active matrix image display device having a large screen using a glass substrate. Also, in these examples, almost all coating and printing methods have been taken as examples of organic TFT manufacturing methods, but are not limited thereto, for example, vacuum film formation such as vapor deposition and sputtering, photolithography / etching, etc. It goes without saying that the effects of the present invention can also be obtained by forming a TFT, an electrode, and a wiring by incorporating a part of these patterning methods.

  As described above in detail, according to the present invention, in particular, a transistor integrated circuit substrate and an active matrix image display device, in particular, a thin film transistor that is excellent in thin and light weight, impact resistance and flexibility and can be manufactured at low cost. An integrated circuit substrate, an image display device, and a manufacturing method thereof can be provided. Furthermore, it is possible to provide an electronic device having a TFT circuit with high performance and low power consumption, in particular, a thin and light image display device and a flexible electronic device with an RF-ID and an arithmetic function. Furthermore, by reducing the number of manufacturing steps of these electronic devices, the manufacturing cost is reduced, and mass production and enlargement by printing are facilitated.

Since the present invention is diverse, its main forms are listed below.
(1) It comprises a plurality of thin film transistors (TFTs),
The TFT is a method in which the semiconductor layer, the gate electrode, and the source / drain electrode are all or part of them selected from the group consisting of a coating method, a dropping method, and a printing method, or a method selected from the above group. Formed by a combined method,
The first and second transistors in the plurality of TFTs are adjacent in the first direction;
The first and third transistors in the plurality of TFTs are adjacent to each other in the second direction, and the relationship of the projection pattern of the TFT gate electrode and the source / drain electrodes on the TFT substrate surface is
A form in which a source / drain electrode of a TFT is surrounded by a gate electrode;
A form in which a source / drain electrode or a gate electrode of a TFT is surrounded by a source / drain electrode different from the source / drain electrode;
The gate electrode of the TFT has at least one form selected from the group of a form in which the gate electrode of the TFT partially protrudes from the source / drain electrode and a form in which the source / drain electrode of the TFT partially protrudes from the gate electrode. A thin film transistor device.
(2) In the preceding paragraph (1),
The thin film transistor device according to claim 1, wherein the first direction and the second direction are perpendicular to each other.
(3) In the preceding paragraph (1),
A thin film transistor device, wherein a channel length of the TFT is a minimum processing dimension.
(4) In the preceding paragraph (1),
The area where the region where the source / drain electrodes of the TFT and the semiconductor layer are combined and the gate electrode region intersects is equal to the area of the region where carriers involved in channel electrical conduction are induced by the gate electrode. Thin film transistor device.
(5) In the preceding paragraph (1),
The thin film transistor device, wherein the semiconductor layer is an organic semiconductor layer.
(6) It comprises a plurality of TFTs,
In the TFT, all or part of the semiconductor layer, the gate electrode, and the source / drain electrode are selected from the group consisting of a coating method, a dropping method, and a printing method, or a method selected from the above group. It is formed by a combined method, and the relationship of the projection pattern of the TFT gate electrode and source / drain electrode onto the TFT substrate surface is as follows:
The arrangement interval of the source / drain electrodes or the arrangement interval of the gate electrodes of the first and second TFTs is larger than the arrangement interval determined by the processing accuracy and alignment accuracy of the coating method, the dropping method, and the printing method. A thin film transistor device having a close region.
(7) In the preceding paragraph (6),
A thin film transistor device, wherein a channel length of the TFT is a minimum processing dimension.
(8) In the preceding paragraph (6),
The area where the region where the source / drain electrodes of the TFT and the semiconductor layer are combined and the gate electrode region intersect is equal to the area of the region where carriers involved in channel electrical conduction are induced by the gate electrode. A thin film transistor device.
(9) In the preceding paragraph (6),
The thin film transistor device, wherein the semiconductor layer is an organic semiconductor layer.
(10) A method of manufacturing a device including a plurality of TFTs,
A gate electrode is formed by patterning on the translucent substrate,
A gate insulating film is formed on this,
By exposing from the back surface of the translucent substrate using the gate electrode as a light shielding mask, the position of the source / drain electrode is determined in alignment with the gate electrode,
Thereafter, a semiconductor layer is formed on the substrate thus prepared,
Alternatively, a gate electrode is formed by patterning on a translucent substrate,
A gate insulating film is formed on this,
A semiconductor layer is formed on the gate insulating film,
Thereafter, from the back surface of the translucent substrate, by exposing while using the gate electrode as a light shielding mask, the position of the source / drain electrode is determined in alignment with the gate electrode,
Because
The relationship of the projection pattern of the gate electrode and the source / drain electrode of the TFT onto the surface of the translucent substrate is as follows:
When performing the backside exposure, a gate electrode serving as a light shielding mask is disposed between the source / drain electrodes of adjacent TFTs,
The thin film transistor characterized in that the gate electrode has at least one form selected from the group of a form surrounding the source / drain electrode and a form in which the gate electrode partially protrudes from the source / drain electrode. Device manufacturing method.
(11) In the preceding paragraph (10),
All or part of the gate electrode, the gate insulating film, the source / drain electrode, and the semiconductor layer film is selected from the group consisting of a coating method, a dropping method, and a printing method, or selected from the above group. A method of manufacturing a thin film transistor device, characterized by being formed by a combination of methods.
(12) In the preceding paragraph (10),
A method of manufacturing a thin film transistor device, wherein a channel length of the TFT is a minimum processing dimension.
(13) In the preceding paragraph (10),
The area where the region where the source / drain electrodes of the TFT and the semiconductor layer are combined and the gate electrode region intersect is equal to the area of the region where carriers involved in channel electrical conduction are induced by the gate electrode. A method for manufacturing a thin film transistor device.
(14) In the preceding paragraph (10),
The method for manufacturing a thin film transistor device, wherein the semiconductor layer is an organic semiconductor layer.
(15) A method for manufacturing a device including a plurality of TFTs,
A source / drain electrode is formed by patterning on a translucent substrate,
After this, a semiconductor layer is formed,
On top of this, a gate insulating film is formed,
Alternatively, a semiconductor layer is formed over the light-transmitting substrate,
Thereafter, source / drain electrodes are formed by patterning,
On top of this, a gate insulating film is formed,
Is done,
Thereafter, the position of the gate electrode is determined in alignment with the source / drain electrode by exposing from the back surface of the translucent substrate while using the source / drain electrode as a light shielding mask. A method for manufacturing a thin film transistor device.
(16) In the preceding paragraph (15),
When exposing from the back surface of the translucent substrate, source / drain electrodes that serve as the light shielding mask are disposed between the gate electrodes of adjacent TFTs,
From the group in which the source / drain electrode surrounds a TFT gate electrode or a source / drain electrode different from the source / drain electrode, or a group in which the source / drain electrode partially protrudes from the gate electrode. A method of manufacturing a thin film transistor device, characterized by having at least one selected form.
(17) In the preceding paragraph (15),
All or part of the source / drain electrode, the semiconductor film, the gate insulating film, and the gate electrode are selected from the group consisting of a coating method, a dropping method, and a printing method, or selected from the above group. A method of manufacturing a thin film transistor device, characterized in that the thin film transistor device is formed by a combination of the above methods.
(18) In the preceding paragraph (15),
A method of manufacturing a thin film transistor device, wherein a channel length of the TFT is a minimum processing dimension.
(19) In the preceding paragraph (15),
The area where the source / drain electrode of the TFT and the semiconductor layer are combined and the area where the gate electrode region intersects is equal to the area of the region where carriers involved in channel electrical conduction are induced by the gate electrode. A method for manufacturing a thin film transistor device.
(20) In the preceding paragraph (15),
The method for manufacturing a thin film transistor device, wherein the semiconductor layer is an organic semiconductor layer.
(21) In the preceding paragraph (17),
The channel length of the TFT and the width of the first gate electrode located on the semiconductor layer are minimum processing dimensions, and the first gate electrode is selected from the group consisting of a coating method, a dropping method, and a printing method Or a combination of methods selected from the above group,
2. A thin film transistor device comprising: a second gate electrode having a width wider than that of the first gate electrode is connected to the first gate electrode, and the second gate electrode is adjacent to a source / drain electrode. Manufacturing method.

1 is a plan view of a thin film transistor device according to a first embodiment. 1 is a plan view of a thin film transistor device according to a first embodiment. 1 is a circuit diagram of a thin film transistor device according to a first embodiment. 1 is a plan view of a thin film transistor device according to a first embodiment. 1 is a circuit diagram of a thin film transistor device according to a first embodiment. 1 is a plan view of a thin film transistor device according to a first embodiment. 1 is a circuit diagram of a thin film transistor device according to a first embodiment. 1 is a plan view of a thin film transistor device according to a first embodiment. 1 is a circuit diagram of a thin film transistor device according to a first embodiment. FIG. 3 is a cross-sectional structure diagram illustrating the order of manufacturing steps of the thin film transistor device according to the first embodiment. FIG. 3 is a cross-sectional structure diagram illustrating the order of manufacturing steps of the thin film transistor device according to the first embodiment. FIG. 3 is a cross-sectional structure diagram illustrating the order of manufacturing steps of the thin film transistor device according to the first embodiment. FIG. 6 is a cross-sectional structure diagram illustrating another manufacturing process of the thin film transistor device according to the first embodiment in the order of the manufacturing processes. FIG. 6 is a cross-sectional structure diagram illustrating another manufacturing process of the thin film transistor device according to the first embodiment in the order of the manufacturing processes. The cross-sectional structure figure shown to the process order of the changed manufacturing process of the thin-film transistor device which is a 1st Example. The cross-section figure which showed the manufacturing process changed of the thin-film transistor apparatus which is a 1st Example in process order. FIG. 6 is a cross-sectional structure diagram illustrating the thin film transistor device according to the first embodiment in the order of changed steps. The cross-section figure which showed the manufacturing process changed of the thin-film transistor apparatus which is a 1st Example in process order. The cross-section figure which showed the manufacturing process changed of the thin-film transistor apparatus which is a 1st Example in process order. The top view of the thin-film transistor apparatus which is a 2nd Example. The top view of the thin-film transistor apparatus which is a 2nd Example. The circuit diagram of the thin-film transistor apparatus which is a 2nd Example. The top view of the thin-film transistor apparatus which is a 2nd Example. The circuit diagram of the thin-film transistor apparatus which is a 2nd Example. The top view of the thin-film transistor apparatus which is a 2nd Example. The circuit diagram of the thin-film transistor apparatus which is a 2nd Example. The top view of the thin-film transistor apparatus which is a 2nd Example. The circuit diagram of the thin-film transistor apparatus which is a 2nd Example. FIG. 6 is a cross-sectional structure diagram illustrating the order of manufacturing steps of a thin film transistor device according to a second embodiment. FIG. 6 is a cross-sectional structure diagram illustrating the order of manufacturing steps of a thin film transistor device according to a second embodiment. FIG. 6 is a cross-sectional structure diagram illustrating the order of manufacturing steps of a thin film transistor device according to a second embodiment. FIG. 6 is a cross-sectional structure diagram illustrating the order of manufacturing steps of a thin film transistor device according to a second embodiment. FIG. 6 is a cross-sectional structure diagram illustrating the order of manufacturing steps of a thin film transistor device according to a second embodiment. The cross-section figure which showed the manufacturing process changed of the thin-film transistor apparatus which is a 2nd Example in process order. The cross-section figure which showed the manufacturing process changed of the thin-film transistor apparatus which is a 2nd Example in process order. The cross-section figure which showed the manufacturing process changed of the thin-film transistor apparatus which is a 2nd Example in process order. The cross-section figure which showed the manufacturing process by which the thin-film transistor device which is a 2nd Example was changed in order of the process. The cross-section figure which showed the manufacturing process by which the thin-film transistor device which is a 2nd Example was changed in order of the process.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Gate electrode, 2a, 2b ... Source / drain electrode, 3 ... Semiconductor layer, 4 ... Contact hole, 5a, 5b ... Wiring 11a, 11b ... Gate electrode, 11c ... Gate electrode line, 12a, 12b, 12c, 12d ... Source / drain electrode, 12e ... drain electrode line, 13a, 13b ... semiconductor layer, 14 ... contact hole, 15a, 15b ... wiring, 15c ... drain line, 16 ... switching TFT, 17 ... driving TFT, 18 ... OLED, 21a ... Gate electrode, 21b ... Gate electrode line, 22 ... Source / drain electrode, 23 ... Semiconductor layer, 24 ... Contact hole, 25a, 25b ... Wiring, 25c ... Drain line, 26 ... Switching TFT, 27 ... Display device, 31a, 31b ... Gate electrodes, 32a, 32b ... Source / drain electrodes, 33 ... Semiconductor layer, 34 Contact hole, 35a, 35b ... wiring, 36 ... driving TFT, 37 ... load TFT, 41a, 41b ... gate electrode, 42a, 42b ... source / drain electrode, 43 ... semiconductor layer, 44 ... contact hole, 45a, 45b ... wiring , 46 ... Driving TFT, 47 ... Load TFT, 50 ... Plastic substrate, 51 ... Gate electrode, 52 ... Gate insulating film, 53 ... Photosensitive SAM film, 54 ... Hydrophilic region, 55 ... Source / drain electrode, 56 ... Semiconductor Layers 57 ... Protective film 58 ... Wiring 61a, 61b Source / drain electrode 62 ... Semiconductor layer 63a 63b 63c Gate electrode 64 Contact hole 65a 65b Wiring 71a 71b 71c 71d, source / drain electrodes, 71e, drain electrode lines, 72a, 72b, semiconductor layers, 73a, 73 ... Gate electrode, 73c ... Gate electrode line, 74 ... Contact hole, 75a, 75b ... Wiring, 75c ... Drain line, 76 ... Switching TFT, 77 ... Drive TFT, 78 ... OLED, 81 ... Source / drain electrode, 82 ... Semiconductor Layer 83a ... gate electrode 83b gate electrode line 84 contact hole 85a 85b wiring 85c drain line 86 switching TFT 87 display device 91a 91b source / drain electrode 92 Semiconductor layer, 93a, 93b ... gate electrode, 94 ... contact hole, 95a, 95b ... wiring, 96 ... driving TFT, 97 ... load TFT, 101a, 101b ... source / drain electrode, 102 ... semiconductor layer, 103a, 103b ... gate Electrode 104 ... Contact hole 105a, 105b ... Wiring , 106 driving TFT, 107 load TFT, 110 plastic substrate, 111 source / drain electrode, 112 semiconductor layer, 113 gate insulating film, 114 water-repellent resist film, 115 gate electrode, 116 protective film 117: Wiring.

Claims (20)

A plurality of thin film transistors (abbreviated as TFT (Thin-Film-Transistor)),
The TFT is a method in which the semiconductor layer, the gate electrode, and the source / drain electrode are all or part of them selected from the group consisting of a coating method, a dropping method, and a printing method, or a method selected from the above group. Formed by a combined method,
The first and second transistors in the plurality of TFTs are adjacent in the first direction;
The first and third transistors in the plurality of TFTs are adjacent to each other in the second direction, and the relationship of the projection pattern of the TFT gate electrode and the source / drain electrodes on the TFT substrate surface is
A form in which a source / drain electrode of a TFT is surrounded by a gate electrode;
A form in which a source / drain electrode or a gate electrode of a TFT is surrounded by a source / drain electrode different from the source / drain electrode;
The gate electrode of the TFT has at least one form selected from the group of a form in which the gate electrode of the TFT partially protrudes from the source / drain electrode and a form in which the source / drain electrode of the TFT partially protrudes from the gate electrode. A thin film transistor device. In claim 1,
The thin film transistor device according to claim 1, wherein the first direction and the second direction are perpendicular to each other. In claim 1,
A thin film transistor device, wherein a channel length of the TFT is a minimum processing dimension. In claim 1,
The area where the region where the source / drain electrodes of the TFT and the semiconductor layer are combined and the gate electrode region intersects is equal to the area of the region where carriers involved in channel electrical conduction are induced by the gate electrode. Thin film transistor device. In claim 1,
The thin film transistor device, wherein the semiconductor layer is an organic semiconductor layer. A plurality of TFTs,
In the TFT, all or part of the semiconductor layer, the gate electrode, and the source / drain electrode are selected from the group consisting of a coating method, a dropping method, and a printing method, or a method selected from the above group. It is formed by a combined method, and the relationship of the projection pattern of the TFT gate electrode and source / drain electrode onto the TFT substrate surface is as follows:
The arrangement interval of the source / drain electrodes or the arrangement interval of the gate electrodes of the first and second TFTs is larger than the arrangement interval determined by the processing accuracy and alignment accuracy of the coating method, the dropping method, and the printing method. A thin film transistor device having a close region. In claim 6,
A thin film transistor device, wherein a channel length of the TFT is a minimum processing dimension. In claim 6,
The area where the region where the source / drain electrodes of the TFT and the semiconductor layer are combined and the gate electrode region intersect is equal to the area of the region where carriers involved in channel electrical conduction are induced by the gate electrode. A thin film transistor device. In claim 6,
The thin film transistor device, wherein the semiconductor layer is an organic semiconductor layer. A method for manufacturing a device having a plurality of TFTs,
A gate electrode is formed by patterning on the translucent substrate,
A gate insulating film is formed on this,
By exposing from the back surface of the translucent substrate using the gate electrode as a light shielding mask, the position of the source / drain electrode is determined in alignment with the gate electrode,
Thereafter, a semiconductor layer is formed on the substrate thus prepared,
Alternatively, a gate electrode is formed by patterning on a translucent substrate,
A gate insulating film is formed on this,
A semiconductor layer is formed on the gate insulating film,
Thereafter, from the back surface of the translucent substrate, by exposing while using the gate electrode as a light shielding mask, the position of the source / drain electrode is determined in alignment with the gate electrode,
Because
The relationship of the projection pattern of the gate electrode and the source / drain electrode of the TFT onto the surface of the translucent substrate is as follows:
When performing the backside exposure, a gate electrode serving as a light shielding mask is disposed between the source / drain electrodes of adjacent TFTs,
The thin film transistor characterized in that the gate electrode has at least one form selected from the group of a form surrounding the source / drain electrode and a form in which the gate electrode partially protrudes from the source / drain electrode. Device manufacturing method. In claim 10,
All or part of the gate electrode, the gate insulating film, the source / drain electrode, and the semiconductor layer film is selected from the group consisting of a coating method, a dropping method, and a printing method, or selected from the above group. A method of manufacturing a thin film transistor device, characterized by being formed by a combination of methods. In claim 10,
A method of manufacturing a thin film transistor device, wherein a channel length of the TFT is a minimum processing dimension. In claim 10,
The area where the region where the source / drain electrodes of the TFT and the semiconductor layer are combined and the gate electrode region intersect is equal to the area of the region where carriers involved in channel electrical conduction are induced by the gate electrode. A method for manufacturing a thin film transistor device. In claim 10,
The method for manufacturing a thin film transistor device, wherein the semiconductor layer is an organic semiconductor layer. A method for manufacturing a device having a plurality of TFTs,
A source / drain electrode is formed by patterning on a translucent substrate,
After this, a semiconductor layer is formed,
On top of this, a gate insulating film is formed,
Alternatively, a semiconductor layer is formed over the light-transmitting substrate,
Thereafter, source / drain electrodes are formed by patterning,
On top of this, a gate insulating film is formed,
Is done,
Thereafter, the position of the gate electrode is determined in alignment with the source / drain electrode by exposing from the back surface of the translucent substrate while using the source / drain electrode as a light shielding mask. A method for manufacturing a thin film transistor device. In claim 15,
When exposing from the back surface of the translucent substrate, source / drain electrodes that serve as the light shielding mask are disposed between the gate electrodes of adjacent TFTs,
From the group in which the source / drain electrode surrounds a TFT gate electrode or a source / drain electrode different from the source / drain electrode, or a group in which the source / drain electrode partially protrudes from the gate electrode. A method of manufacturing a thin film transistor device, characterized by having at least one selected form. In claim 15,
All or part of the source / drain electrode, the semiconductor film, the gate insulating film, and the gate electrode are selected from the group consisting of a coating method, a dropping method, and a printing method, or selected from the above group. A method of manufacturing a thin film transistor device, characterized in that the thin film transistor device is formed by a combination of the above methods. In claim 15,
A method of manufacturing a thin film transistor device, wherein a channel length of the TFT is a minimum processing dimension. In claim 15,
The area where the source / drain electrode of the TFT and the semiconductor layer are combined and the area where the gate electrode region intersects is equal to the area of the region where carriers involved in channel electrical conduction are induced by the gate electrode. A method for manufacturing a thin film transistor device. In claim 15,
The method for manufacturing a thin film transistor device, wherein the semiconductor layer is an organic semiconductor layer.

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