JP2009283855A - Wiring layout method and wiring layout device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a wiring layout method which efficiently reduces wiring resistance in the same node. <P>SOLUTION: The layout method includes the steps of extracting wiring graphic data of the target node from layout patterns of wiring layers, forming a parallel shift region extended by carrying out the parallel shift of the target node wiring so that the number of vertices are not changeable to the extent a design rule is satisfied, extracting a wiring extensible region of the target node from the layout pattern of the wiring layer in which the target node is included, extracting a wiring extension region A3 by carrying out logical OR of the parallel shift region and wiring extensible region, and forming a bunch wiring where the target node wiring is shifted in parallel to the wiring extension region A3. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a layout device for laying out a wiring layer of a semiconductor device having a plurality of wiring layers.

  In recent years, semiconductor integrated circuit devices have been increased in scale and integration, and the amount of design data has increased. Therefore, the work time required for the layout design of the semiconductor integrated circuit device tends to be long, and a technique for shortening the work time is required.

In addition, with the miniaturization of semiconductor integrated circuit devices, multilayering of wiring layers is promoted, and there is concern about an increase in wiring resistance between wirings that become the same node in different wiring layers.
An increase in the wiring resistance causes a voltage drop at the node, and the voltage drop becomes large especially in a portion where a large current flows, which causes a malfunction and cannot be ignored. For this reason, it is necessary to design a layout that reduces the wiring resistance.

  Conventionally, in layout design of semiconductor integrated circuits, automatic generation of contact vias in an environment using a net driven tool is an existing technology, and generated layout data is subjected to various verifications by a layout verification tool.

  Patent Document 1 discloses a layout method in which a wiring having a large delay due to parasitic capacitance is extracted and the wiring width of the wiring is automatically widened in a range in which the distance from other wiring does not violate the design rule.

  In Patent Document 2, a contact via that violates a design rule is detected, the wiring layout related to the contact via is changed, the contact via is removed, or the position of the contact via is moved to violate the rule. A layout method to be solved is disclosed.

Patent Document 3 discloses a layout method in which wiring resistance is reduced by increasing the number of contact vias between wirings that are the same node in two wiring layers adjacent vertically. In addition, the wiring expandable region of the wiring that becomes the same node is calculated by two wiring layers adjacent to each other in the upper and lower directions, a parallel movement line segment is generated in the wiring expandable region, the wiring area is expanded, and a contact via is formed between the wirings. A layout method is disclosed in which the wiring resistance is reduced by arranging as many as possible.
JP-A-8-83847 (FIG. 2) Japanese Patent Laid-Open No. 10-65007 (FIGS. 5 and 6) JP 2008-40678 A

  In order to reduce the wiring resistance between wirings that become the same node in different wiring layers, it is necessary to connect both wirings with more contact vias. For this reason, the wiring area where contact vias can be arranged is maximized. There is a need.

However, Patent Documents 1 and 2 do not disclose a configuration for maximizing the number of contact vias in order to reduce wiring resistance.
Patent Document 3 discloses a layout method that reduces the wiring resistance by increasing the number of contact vias between two wiring layers that are adjacent to each other in the upper and lower wiring layers. There is a point.

  In Patent Document 3, as shown in FIG. 11 to FIG. 21, the wiring resistance of the wiring layer that becomes a common node in two adjacent wiring layers is laid out by laying out a wiring bundle for thickening the wiring in the empty area. The wiring bundles in the X direction and the Y direction are laid out in different wiring layers.

  For this reason, when there is no vacant area for adding a wiring bundle in one layer, the wiring bundle cannot be laid out in the wiring layer, and as a result, the wiring resistance of the node can be reduced. There is a problem that it is not possible.

In addition, when reducing the wiring resistance of the same node across three or more wiring layers, the wiring resistance may not be sufficiently reduced.
In FIG. 14, for example, the wiring LA formed in the first wiring layer is the ground GND, the wiring LBa formed in the second wiring layer is the ground GND, the wiring LBb is a node other than the ground GND, the third layer It is assumed that the wiring LC formed in this wiring layer is the ground GND. Here, when connecting the ground GND node of the first layer to the third layer to reduce the wiring resistance, the contact via that connects the wiring LA and the wiring LC can be generated only between the wiring LBa and each of the wirings LA and LC. It is. Therefore, there is a problem that the reduction of the wiring resistance between the wirings LA and LC becomes insufficient.

  As shown in FIG. 15, when the wiring width is widened to reduce the wiring resistance, the width is widened until the distance from the other node wiring in the same wiring layer becomes the minimum wiring distance set in advance by the normal design rule. Then, the generation of noise due to interference between nodes may be a problem.

  As shown in FIG. 15A, when the wirings 2 and 3 to which the power sources VDD and Vss are supplied are laid out on both sides of the wiring 1 to which the reference voltage Vref is supplied, the wiring resistance of the wirings 2 and 3 is reduced. For this purpose, the wirings 2 and 3 are widened. At this time, as shown in FIG. 15B, if the width between the wiring 1 and the wirings 2 and 3 is widened to the minimum distance set by the design rule, the wiring 1 receives the interference of the power supply noise, and the reference There is a problem that noise is generated in the voltage Vref.

As shown in FIG. 16, when the wiring width is increased in order to reduce the wiring resistance, if the width is increased to cover the element formed on the wafer substrate, the characteristics of the element may be deteriorated.
As shown in FIG. 16A, the pair transistors T1 and T2, the pair resistors R1 and R2, and the high impedance wirings L1 and L2 are formed on the substrate, and the power supply VDD and Vss are supplied to the upper wiring layer. A case where 4 and 5 are laid out will be described.

  In order to reduce the wiring resistance of the wirings 4 and 5, as shown in FIG. 16B, the wirings 4 and 5 are widened to the minimum wiring interval of a normal design rule, and the pair transistors T1 and T2 and the pair resistance R1 , R2 may be widened to a position covering the pair transistors T1 and T2 and the pair resistors R1 and R2 may be interfered by power supply noise, and the characteristics may be degraded.

  In particular, the pair transistors T1 and T2 and the pair resistors R1 and R2 need to have the same characteristics. However, when the pair transistors T1 and T2 and the pair resistors R1 and R2 are not evenly covered with the wires 4 and 5, or the high impedance wires L1 and L2 connected to the pair resistors R1 and R2 are the wires 4 of different nodes. , 5, there is a problem that the characteristics of the pair transistors T1, T2 and the pair resistors R1, R2 are unbalanced.

  As shown in FIG. 17, when the wiring width is widened to reduce the wiring resistance, the wiring of each node is uniformly widened, so that the wiring of the node whose wiring resistance is to be reduced is preferentially widened. It is not possible.

  As shown in FIG. 17, when the wiring 7 of the node having the highest priority for reducing the wiring resistance, the wiring 8 of the next highest node, and the wiring 9 of the other node are laid out in the same wiring layer. If the wiring expandable area has the same conditions for the wirings 7 and 8, the wirings 7 and 8 are expanded with the same expansion width wx. Therefore, there is a problem that the wiring resistance cannot be efficiently reduced according to the priority.

  An object of the present invention is to provide a wiring layout method capable of efficiently reducing the wiring resistance of the same node.

  The purpose is to extract the graphic data of the wiring of the target node from the layout pattern of the wiring layer, and to extend the parallel wiring of the target node by translating so that the number of vertices does not change within the range satisfying the design rule. Wiring by a logical sum of the step of generating a moving region, the step of extracting the wiring expandable region of the target node from the layout pattern of the wiring layer including the target node, and the parallel moving region and the wiring expandable region This is achieved by a wiring layout method comprising a step of extracting an extension region and a step of generating a bundle wiring obtained by translating the wiring of the target node in the wiring extension region.

  In the disclosed wiring layout method, the wiring resistance of the same node can be efficiently reduced.

Hereinafter, an embodiment of the present invention will be described with reference to the drawings.
FIG. 1 is a schematic configuration diagram of a layout apparatus according to the present embodiment. As shown in the figure, the layout device includes a central control device 11, a working area (extraction means) 12, a graphic calculator 13, a graphic generator (via generation means) 14, and a determination processing device 15. ing. The layout device inputs input polygon data 16a stored in a storage device (not shown) such as a magnetic disk device, and outputs / stores the processed polygon data 16b in the same storage device. The layout device displays an image based on the input polygon data 16a and various processing data on a display device (not shown) such as a CRT.

  The input polygon data 16a is automatically created based on circuit information (net list) of a semiconductor integrated circuit device (hereinafter referred to as “LSI”) by an automatic layout tool provided in a general-purpose CAD (Computer Aided Design) device, for example. Data file or format data based thereon. Then, an LSI arrangement / wiring layout pattern is expressed by graphic data of a plurality of layers having at least one pattern graphic (polygon). That is, this data file includes, for example, a coordinate value string that defines the shape, a layer number that defines the layer to be arranged, and its node for a pattern figure corresponding to the wiring of each wiring layer (metal layer) of the LSI. It has information such as text to prescribe. On the other hand, the processed polygon data 16b also has the same information as the input polygon data 16a.

  The central control unit 11 outputs control signals to the graphic calculator 13, the graphic generator 14, and the determination processing device 15 to control them centrally, and processes the input polygon data 16 a read into the working area 12. Further, the processing data generated during the processing operation is temporarily stored in the working area 12, or the processing data is exchanged between the graphic calculator 13 and the graphic generator 14. The final process data stored in the working area 12 is output as processed polygon data 16b.

  The graphic calculator 13 is controlled by a control signal from the central controller 11 and inputs processing data (such as input polygon data 16a) stored in the working area 12 or processing data of the graphic generator 14, Performs logical operation processing (logical product processing, logical sum processing, etc.) of the graphic and shift processing (extension processing, movement processing, deletion processing, etc.) of the graphic. Then, the graphic calculator 13 stores the processing data in the working area 12 or outputs it to the graphic generator 14.

  The graphic generator 14 is controlled by a control signal from the central control unit 11 and inputs processing data stored in the working area 12 or processing data of the graphic calculator 13 to input contact vias and wiring (metal wiring). ) Etc. are generated. The graphic generator 14 stores the processing data in the working area 12 or outputs it to the graphic calculator 13.

  The determination processing device 15 is controlled by each control signal from the central control device 11 and the graphic calculator 13. Then, a control signal is output to the working area 12 to control it, and the input polygon data 16a is stored in the working area 12, and the final processed data stored in the working area 12 is processed as polygon data. 16b is output.

Next, the processing operation of the layout apparatus as described above will be described.
(First processing)
In the first process, in the graphic data of the layout patterns of two wiring layers adjacent to each other vertically, the shape of the pattern forming the same node is maximized within the range allowed by the design rule, and the expanded pattern The maximum number of contact vias is generated within a range satisfying the design rule. Since the processing is the same as that disclosed in FIGS. 11 to 21 of Patent Document 3 by the present applicant, it will not be described in detail here.
(Second processing)
FIG. 2 is a flowchart showing the second processing, and FIGS. 3 and 4 are image examples showing step by step an example of graphic data of each layer corresponding to the processing operation. In the following, each processing step (step) shown in FIG. 2 will be described with reference to specific image examples shown in FIGS. 3 and 4.

  When this process is started, an LSI layout pattern (input polygon data 16a) is first input (step 1). FIG. 3A shows an example of the input pattern data, and the first layer pattern La, which is the lowermost layer, and the second layer pattern Lb, which is the uppermost layer, are input.

  Next, a node name to be checked is added as a target node, and a graphic of the target node is extracted (step 2). Here, a case where the node N1 to which the reference voltage Vref is supplied in the first layer is extracted as a target node is shown. If the area to be processed is large, the area is divided and the process is executed for each area (step 3).

  Next, the area of the pattern in which the area of the pattern of the node N1 extracted in step 2 is maximized is calculated (step 4). That is, as shown in FIG. 3B, the pattern area of the node N1 is enlarged so as to be maximized in a state where the minimum distance from the wiring of another node in the same layer is secured. At this time, the area is enlarged by translation so that the number of vertices of the pattern of the node N1 does not change, and a translation area A1 shown in FIG. 3C is calculated.

Next, from the input layout pattern, a wiring expandable area A2 (a white portion in FIG. 3D) in the first layer including the node N1 is calculated (step 5).
Next, as shown in FIG. 4A, the AND area of the areas A1 and A2 is calculated as a wiring expansion area A3, and the vertical wiring and the horizontal direction of the node N1 (target wiring) are included in the wiring expansion area A3. A large number of wirings (translation line segments) obtained by translating the wirings are generated for each minimum wiring interval of the design rule (step 6).

  At this time, the vertical wiring and the horizontal wiring are connected by increasing the wiring interval outside the bent portion of the target wiring and shortening the wiring interval inside. Further, the unconnected portion X1 shown in FIG. 4A is extended until connected, as shown in FIG. 4B. Further, as shown in FIG. 4A, the short line segment X2 in contact with the outer periphery of the routable area A3 is deleted as shown in FIG. 4B. By such processing, a bundle wiring of the node N1 is generated in the routable area A3.

  Next, orthogonal wires CP1 to CP7 that connect the bundle wires are generated in a direction perpendicular to the bundle wires (step 7). The orthogonal wirings CP1 to CP7 are generated in the order of the orthogonal wirings CP1 to CP7 in order from the bent portion of the bundle wiring and in order from the wider width of the routable area A3.

  Next, it is determined whether or not all the processes in the area, that is, similar processes for the same node of the wiring layer have been completed (step 8). If it is determined that all the processes in the area are not completed, the process returns to step 4 and is repeated until all the processes in the area are completed. On the other hand, when all the processes in the area are completed, the process proceeds to step 9 to determine whether or not the processes for all layers are completed. If it is determined that all layers have not been processed, the processes in steps 4 to 8 are repeated for the same node in different wiring layers.

  If it is determined in step 9 that all layers have been processed, it is determined whether or not all nodes have been processed (step 10). If it is determined that the processing of all the nodes has not been completed, the process proceeds to step 2 to add a new node name, and the processes of steps 4 to 9 are repeated.

When processing of all nodes is completed, final processing data is output as processed polygon data 16b (step 11).
(Third treatment)
The third process is a process for increasing the number of vias connecting each wiring layer in order to reduce the wiring resistance for the same node over three or more wiring layers. FIG. 5 is a flowchart showing the second processing, and FIGS. 6 and 7 are image examples showing step by step an example of graphic data of each layer corresponding to the processing operation.

  In FIG. 5, first, an LSI layout pattern is input (step 21). FIG. 6 shows an example of the input pattern data. The first layer wiring LA which is the lowest layer, the second layer wiring LB which is the intermediate layer, and the third layer wiring LC which is the upper layer are input. Is done.

Here, the wirings LA and LC are the same node, for example, the ground GND, the wiring LB1 is the ground GND, and the wiring LB2 is the other node.
Next, a base layer is defined for each generation layer that newly generates wiring for additionally arranging vias (step 22). Here, the base layer is the wirings LA and LC, and the generation layer is the wiring LB.

Next, target nodes for which vias are to be increased are extracted (step 23). Here, the target node is the ground GND.
Next, the generation layer graphic is extracted from the base layer of the target node, and the AND region of the generation layer from the lower layer and the generation layer from the upper layer is extracted (step 24). That is, in FIG. 7A, the AND portion of the unused area of the first layer wiring LA that is the base layer and the unused area of the second layer that is the generation layer is extracted as the via arrangement candidate area AR1. .

In FIG. 7B, an AND portion of the unused area of the third layer wiring LC that is the base layer and the unused area of the second layer that is the generation layer is extracted as the via arrangement candidate area AR2. .
In FIG. 7C, an AND area of the via arrangement candidate area AR1 and the via arrangement candidate area AR2 is extracted, and a via arrangement possible area AR3 is extracted. The via arrangement area AR3 is an area in which a via extending from the first layer wiring LA to the third layer wiring LC can be generated.

Next, the OR region of the generation layer and the existing layer is extracted as a via installation region (step 25). Here, the via installation area coincides with the via arrangement possible area AR3.
Next, vias are arranged by excluding the via arrangement impossible area defined by the design rule from the via installation area (step 26), and the via area ratio of the via installation area is calculated (step 27).

  Next, whether or not the via area ratio exceeds the threshold value, that is, the vias are efficiently arranged in the via installation region, and the area ratio between the total via area and the via installation region area exceeds the threshold value. (Step 28), if not exceeded, rearrange the vias (step 29) and proceed to step 30. In step 28, if the area ratio exceeds the threshold value, the process proceeds to step 30. In addition, the process of steps 26-29 is a well-known process disclosed by patent document 3. FIG.

  In step 30, it is determined whether or not the processing using all the wiring layers as the base layer is completed. If the processing is not completed, the process proceeds to step 22, and the processing in which a different wiring layer is defined as the base layer is performed. Process according to 22-29.

  If the process using all the wiring layers as the base layer is completed in step 30, the process proceeds to step 31 to determine whether the process is completed for all target nodes. If not completed, the process proceeds to step 23, and the process of extracting a different node as the target node is processed according to steps 23-30.

When the processing of all nodes is completed, final processing data is output as processed polygon data 16b (step 32).
(Fourth process)
The fourth process is a process of widening the wiring width while preventing the generation of noise due to interference between nodes when the wiring width is widened to reduce the wiring resistance. FIG. 8 is a flowchart showing the fourth processing, and FIG. 9 is an image example showing an example of graphic data of each layer corresponding to the processing operation.

  In FIG. 8, first, an LSI layout pattern is input (step 41). Next, a node name to be checked is added, and a graphic of the same node is extracted from the node name (step 42).

  FIG. 9 is a figure extracted in steps 41 and 42, and the wirings 21a and 21b are wirings of the same node. The wiring 21c is a wiring in the same layer as the wirings 21a and 21b and is a wiring of another node, and is a critical net with strict timing. Further, the wiring 22 is higher than the wirings 21a to 21c and has the same node as the wirings 21a and 21b.

  Next, in step 43, a neutral area for crosstalk is added to the critical net of each wiring layer. In FIG. 9, the wiring 21c is a critical net, and a neutralization area NE is set between the wirings 21a and 21b, and this neutralization area NE is excluded from the wiring expandable area.

  When the wirings 22 of different wiring layers intersect the wirings 21c, a predetermined interval is secured between the wirings 21c and the wirings 22. For example, a condition is set such that the wiring layer in which the wiring 21c is generated and the wiring layer in which the wiring 22 is generated are not adjacent to each other. In addition, if the critical net is shielded, a relaxation standard such as permitting an adjacent wiring layer is set. The critical net information for performing these processes is taken together with the polygon data 16a.

Next, the processes of steps 44 to 54 are performed. These processes are the same processes as the first and second processes and the process described in Patent Document 3. That is, the wiring width of the target node is expanded, or a wiring bundle is generated, and further, vias that connect the same node between different wiring layers are increased to reduce the wiring resistance of the target node. Reduce.
(Fifth process)
10 and 11 show the fifth process. In this process, when the wiring width is widened in order to reduce the wiring resistance, a process for preventing the characteristic deterioration of the pair device is performed. FIG. 10 is a flowchart showing the fifth process, and FIG. 11 is an image example showing an example of graphic data of each layer corresponding to the processing operation.

  In FIG. 10, first, an LSI layout pattern is input (step 61). Next, a node name to be checked is added, and a graphic of the same node is extracted from the node name (step 62).

Next, in step 63, another node wiring prohibition area of the pair device is added to the wiring area of each wiring layer.
In FIG. 11, transistors T1 and T2 formed on the wafer substrate are pair transistors, and resistors R1 and R2 are pair resistors. The pair device graphic data and the pair device designation information are supplied from the outside together with the polygon data 16a.

  In step 63, the other node wiring prohibited areas IH1 and IH2 are set in a range covering the pair transistors T1 and T2 and the pair resistors R1 and R2, and wirings of other nodes are provided above the other node wiring prohibited areas IH1 and IH2. Do not generate.

  In FIG. 11, the wiring 23 is a high-impedance wiring. In step 63, another node wiring prohibition area IH3 is set for this wiring 23 as well. In the other-node wiring prohibited area IH3, based on specific node designation information supplied from the outside, an interval between adjacent digital wirings, an interval between adjacent power supply wirings, and an interval between upper and lower layer wirings are set to a predetermined value or more. Set as an area.

Next, steps 64 to 74 are performed. These processes are similar to the fourth process. That is, the wiring width of the target node is expanded, or a wiring bundle is generated, and further, vias that connect the same node between different wiring layers are increased to reduce the wiring resistance of the target node. Reduce.
(Sixth processing)
12 and 13 show the sixth process. This process is a process for efficiently reducing the wiring resistance by preferentially widening the wiring of a node having a high priority for reducing the wiring resistance when the wiring width is widened to reduce the wiring resistance. . FIG. 12 is a flowchart showing the sixth processing, and FIG. 13 is an image example showing an example of graphic data of each layer corresponding to the processing operation.

  In FIG. 12, an LSI layout pattern is first input (step 81). Next, a node name to be checked is added, and a graphic of the same node is extracted from the node name (step 82).

Next, in step 83, a weight for wiring expansion is set in accordance with the additional information held by the priority node, and the processes in and after step 84 are performed based on the weight.
As shown in FIG. 13, in the wiring 24 and the wiring 25 of the first wiring layer LA, the wiring 24 is the first node and the wiring 25 is the second node, and the priority of the first node is high. When the priority of the second node is low, the wiring expandable area A4 between the wirings 24 and 25 is a wiring expansion area of the wiring 24 of the first node. In this case, the priority ratio is set to 100% for the first node and 0% for the second node. However, for example, 70% and 30% may be set.

  When the priority of the wiring 26 of the third node different from the wirings 24 and 25 is lower than that of the first and second nodes, and the first and second nodes cannot be sufficiently expanded in the first wiring layer, the first node The third node wiring 26 laid out in one layer is moved to the second wiring layer LB for layout.

The wiring 27 of the fourth node is laid out in the fourth layer with a high priority for layout in the fourth wiring layer LD.
Additional information for setting priorities of these wirings 24 to 27 is supplied from the outside together with the polygon data 16a.

  Next, processing in steps 84 to 94 is performed. These processes are similar to the fourth process. That is, the wiring width of the target node is expanded, or a wiring bundle is generated, and further, vias that connect the same node between different wiring layers are increased to reduce the wiring resistance of the target node. Reduce.

In the layout apparatus as described above, the following operational effects can be obtained.
(1) In the second process, at each node in the same wiring layer, a bundle wiring can be generated in the wiring expansion region A3 to reduce the wiring resistance of the node.
(2) In the second process, the wiring resistance of the target wiring of the node can be reduced regardless of the routable area of the same node in the adjacent wiring layer.
(3) In the second process, the target wiring is translated to generate a bundle wiring, and further, the orthogonal wirings CP1 to CP7 that connect the bundle wiring in the perpendicular direction are generated, thereby reducing the wiring resistance of the target wiring. A wiring pattern can be easily generated.
(4) In the third process, it is possible to increase the number of vias that connect the wirings of the same node across three or more wiring layers, thereby reducing the wiring resistance.
(5) In the fourth process, the wiring resistance of the target node can be reduced so that interference with the critical net does not occur.
(6) In the fifth process, the wiring resistance can be reduced while setting other node wiring prohibited areas IH1 and IH2 in the upper layer of the pair device to prevent deterioration of the characteristics of the pair device. In addition, the wiring resistance can be reduced at the specific node while preventing the deterioration of the characteristics.
(7) In the sixth process, the priority for reducing the wiring resistance can be set for each node, and the wiring of the node with a higher priority can be preferentially expanded. Accordingly, the wiring resistance can be efficiently reduced.

  The first to sixth processes may be performed independently, but may be performed by appropriately combining the processes. When all of the first to sixth processes are performed, the fourth process to the sixth process are performed, and then the third process, the first process, and the second process are performed in this order. Can be performed efficiently.

The said embodiment can also be implemented in the aspect shown next.
In the third treatment, the generation layer has been described as the second layer, but it may be similarly treated as the first layer or the third layer.

Next, the technical idea that can be grasped from the above embodiment will be added below.
(Appendix 1)
Extracting graphic data of the wiring of the target node from the layout pattern of the wiring layer;
A step of generating an expanded translation area by translating the wiring of the target node so that the number of vertices does not change within a range satisfying a design rule;
Extracting the wiring expandable region of the target node from the layout pattern of the wiring layer including the target node;
Extracting a wiring expansion area by a logical sum of the parallel movement area and a wiring expansion possible area;
Generating a bundle wiring obtained by translating the wiring of the target node in the wiring extension region;
A wiring layout method comprising: generating an orthogonal wiring for connecting the bundle wiring in a direction orthogonal to the bundle wiring.
(Appendix 2)
A step of sequentially selecting any one generation layer from three or more wiring layers and a wiring layer other than the generation layer as a base layer;
Extracting target nodes for increasing vias; and
In each of the base layer and the generation layer, extracting a plurality of via placement candidate areas based on a combination of the base layer and the generation layer by logical sum of unused areas of the wiring of the target node;
Extracting a via placement possible region by a logical sum of the plurality of via placement candidate regions; and
And a step of arranging vias in the via arrangementable region until the area ratio between the total area of the vias and the via arrangementable region is equal to or greater than a threshold value.
(Appendix 3)
Adding a neutralization region for crosstalk to the critical net wiring extracted from the layout pattern of the wiring layer;
Adding another node wiring prohibition region to the wiring layer laid out on the upper layer of the pair device formed on the wafer substrate;
2. The wiring layout method according to claim 1, further comprising at least one step of performing a wiring expansion process with weighting based on priority information added to the target node.
(Appendix 4)
Extracting graphic data of the wiring of the target node from the layout pattern of the wiring layer;
A step of generating an extended translation area by translating the wiring of the target node so that the number of vertices does not change within a range satisfying the design rule;
Extracting the wiring expandable region of the target node from the layout pattern of the wiring layer including the target node;
Extracting a wiring expansion area by a logical sum of the parallel movement area and a wiring expansion possible area;
Generating a bundle wiring obtained by translating the wiring of the target node in the wiring extension region;
Generating an orthogonal wiring for connecting the bundle wiring in a direction orthogonal to the bundle wiring;
A step of sequentially selecting any one generation layer from three or more wiring layers and a wiring layer other than the generation layer as a base layer;
Extracting target nodes for increasing vias; and
In each of the base layer and the generation layer, extracting a plurality of via placement candidate areas based on a combination of the base layer and the generation layer by logical sum of unused areas of the wiring of the target node;
Extracting a via placement possible region by a logical sum of the plurality of via placement candidate regions; and
Arranging the vias in the via-arrangeable region until the area ratio between the total area of the vias and the via-arrangeable region is equal to or greater than a threshold;
Adding a neutralization region for crosstalk to the critical net wiring extracted from the layout pattern of the wiring layer;
Adding another node wiring prohibition region to the wiring layer laid out on the upper layer of the pair device formed on the wafer substrate;
A wiring layout method comprising a step of performing wiring expansion processing with weighting based on priority information added to the target node.
(Appendix 5)
Any one generation layer from three or more wiring layers, and extraction means for sequentially extracting wiring layers other than the generation layer as a base layer;
Extraction means for extracting target nodes for increasing vias;
In each of the base layer and the generation layer, an extraction unit that extracts a plurality of via placement candidate areas based on a combination of the base layer and the generation layer by a logical sum of unused areas of the wiring of the target node;
Extracting means for extracting via placement possible areas by logical sum of the plurality of via placement candidate areas;
A wiring layout apparatus, comprising: a via generation unit configured to generate vias in the via arrangementable region until an area ratio of a total area of vias to the via arrangementable region becomes equal to or greater than a threshold value.
(Appendix 6)
An extraction means for extracting the graphic data of the wiring of the target node from the layout pattern of the wiring layer;
Means for generating a translation region that is expanded by translating the wiring of the target node so that the number of vertices does not change within a range that satisfies a design rule;
Means for extracting a wiring expandable region of the target node from a layout pattern of a wiring layer including the target node;
Means for extracting a wiring expansion area by a logical sum of the parallel movement area and the wiring expansion area;
Means for generating a bundle wiring obtained by translating the wiring of the target node in the wiring extension region;
A wiring layout apparatus comprising: means for generating an orthogonal wiring for connecting the bundle wiring in a direction orthogonal to the bundle wiring.
(Appendix 7)
4. The wiring layout method according to claim 3, further comprising a step of adding another node wiring prohibited area to a wiring layer laid out above a specific node formed on the wafer substrate.
(Appendix 8)
The wiring layout method according to claim 1, further comprising a step of generating an orthogonal wiring for connecting the bundle wiring in a direction orthogonal to the bundle wiring.

It is a block diagram which shows the structure of the layout apparatus which concerns on this invention. It is a flowchart which shows a 2nd process. (A)-(d) is explanatory drawing which shows a 2nd process. (A)-(c) is explanatory drawing which shows a 2nd process. It is a flowchart which shows a 3rd process. It is explanatory drawing which shows a 3rd process. (A)-(c) is explanatory drawing which shows a 3rd process. It is a flowchart which shows a 4th process. It is explanatory drawing which shows a 4th process. It is a flowchart which shows a 5th process. It is explanatory drawing which shows a 5th process. It is a flowchart which shows a 6th process. It is explanatory drawing which shows a 6th process. It is explanatory drawing which shows the conventional process. (A) (b) is explanatory drawing which shows the conventional process. (A) (b) is explanatory drawing which shows the conventional process. It is explanatory drawing which shows the conventional process.

Explanation of symbols

N1 Target node A1 Parallel movement area A2 Wiring extension area A3 Wiring extension area CP1 to CP7 Orthogonal wiring

Claims (5)

Extracting graphic data of the wiring of the target node from the layout pattern of the wiring layer;
A step of generating an expanded translation area by translating the wiring of the target node so that the number of vertices does not change within a range satisfying a design rule;
Extracting the wiring expandable region of the target node from the layout pattern of the wiring layer including the target node;
Extracting a wiring expansion area by a logical sum of the parallel movement area and a wiring expansion possible area;
And a step of generating a bundle wiring obtained by translating the wiring of the target node in the wiring extension area. A step of sequentially selecting any one generation layer from three or more wiring layers and a wiring layer other than the generation layer as a base layer;
Extracting target nodes for increasing vias; and
In each of the base layer and the generation layer, extracting a plurality of via placement candidate areas based on a combination of the base layer and the generation layer by logical sum of unused areas of the wiring of the target node;
Extracting a via placement possible region by a logical sum of the plurality of via placement candidate regions; and
And a step of arranging vias in the via arrangementable region until the area ratio between the total area of the vias and the via arrangementable region is equal to or greater than a threshold value. Adding a neutralization region for crosstalk to the critical net wiring extracted from the layout pattern of the wiring layer;
Adding another node wiring prohibition region to the wiring layer laid out on the upper layer of the pair device formed on the wafer substrate;
2. The wiring layout method according to claim 1, further comprising at least one step of performing a wiring expansion process with weighting based on priority information added to the target node. Extracting graphic data of the wiring of the target node from the layout pattern of the wiring layer;
A step of generating an expanded translation area by translating the wiring of the target node so that the number of vertices does not change within a range satisfying a design rule;
Extracting the wiring expandable region of the target node from the layout pattern of the wiring layer including the target node;
Extracting a wiring expansion area by a logical sum of the parallel movement area and a wiring expansion possible area;
Generating a bundle wiring obtained by translating the wiring of the target node in the wiring extension region;
Generating an orthogonal wiring for connecting the bundle wiring in a direction orthogonal to the bundle wiring;
A step of sequentially selecting any one generation layer from three or more wiring layers and a wiring layer other than the generation layer as a base layer;
Extracting target nodes for increasing vias; and
In each of the base layer and the generation layer, extracting a plurality of via placement candidate areas based on a combination of the base layer and the generation layer by logical sum of unused areas of the wiring of the target node;
Extracting a via placement possible region by a logical sum of the plurality of via placement candidate regions; and
Arranging the vias in the via-arrangeable region until the area ratio between the total area of the vias and the via-arrangeable region is equal to or greater than a threshold;
Adding a neutralization region for crosstalk to the critical net wiring extracted from the layout pattern of the wiring layer;
Adding another node wiring prohibition region to the wiring layer laid out on the upper layer of the pair device formed on the wafer substrate;
A wiring layout method comprising a step of performing wiring expansion processing with weighting based on priority information added to the target node. Any one generation layer from three or more wiring layers, and extraction means for sequentially extracting wiring layers other than the generation layer as a base layer;
Extraction means for extracting target nodes for increasing vias;
In each of the base layer and the generation layer, an extraction unit that extracts a plurality of via placement candidate areas based on a combination of the base layer and the generation layer by logical sum of unused areas of the wiring of the target node;
An extracting means for extracting a via arrangement possible area by a logical sum of the plurality of via arrangement candidate areas;
A wiring layout apparatus comprising: via generation means for generating vias until the area ratio between the total area of vias and the via arrangementable area exceeds a threshold value in the via arrangementable area.

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