JP2009283788A - Method of manufacturing substrate with built-in chip - Google Patents

Method of manufacturing substrate with built-in chip Download PDF

Info

Publication number
JP2009283788A
JP2009283788A JP2008135980A JP2008135980A JP2009283788A JP 2009283788 A JP2009283788 A JP 2009283788A JP 2008135980 A JP2008135980 A JP 2008135980A JP 2008135980 A JP2008135980 A JP 2008135980A JP 2009283788 A JP2009283788 A JP 2009283788A
Authority
JP
Japan
Prior art keywords
multilayer wiring
substrate
metal plate
pads
wiring substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP2008135980A
Other languages
Japanese (ja)
Inventor
Hajime Iizuka
肇 飯塚
Toshio Kobayashi
敏男 小林
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shinko Electric Industries Co Ltd
Original Assignee
Shinko Electric Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinko Electric Industries Co Ltd filed Critical Shinko Electric Industries Co Ltd
Priority to JP2008135980A priority Critical patent/JP2009283788A/en
Publication of JP2009283788A publication Critical patent/JP2009283788A/en
Withdrawn legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector

Abstract

<P>PROBLEM TO BE SOLVED: To solve such a problem of a conventional method of manufacturing a substrate with a built-in chip for performing inspections, such as, continuity tests with a completed substrate with a built-in chip. <P>SOLUTION: After forming a first multi-layer wiring board 12 on one surface side of a first metal plate 10 by a build-up method, the electrical connection between a second pad 20 and a first pad 14 making contact with the first metal plate 10, in correspondence with each of the second pads, is checked by a continuity test between the second pad 20 and the first metal plate 10. Then, the insulation of wiring patterns connected to the first pad 14 is checked by the continuity test between the first pads 14 and 14, that are exposed by peeling the first metal plate 10, after bonding the second metal plate via an insulating layer which covers the entire surface on the other surface side with the first multi-layer wiring board 12. After that, a semiconductor chip is mounted on one board of the first multi-layer wiring board 10 and the second multi-layer wiring board, after performing the continuity test, in a similar manner as to that with respect to the second multi-layer wiring board that is bonded to the first multi-layer wiring board 12. Then, the other board is laminated on the chip-mounting surface of the one board. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

本発明はチップ内蔵基板の製造方法に関し、更に詳細には第１多層配線基板と第２多層配線基板とを、前記第１多層配線基板又は第２多層配線基板に実装したチップを挟み込むように積層して成るチップ内蔵基板の製造方法に関する。   The present invention relates to a method for manufacturing a chip-embedded substrate, and more specifically, a first multilayer wiring substrate and a second multilayer wiring substrate are stacked so as to sandwich a chip mounted on the first multilayer wiring substrate or the second multilayer wiring substrate. It is related with the manufacturing method of the chip | tip built-in board | substrate comprised.

現在、半導体装置を用いた電子機器の高性能化及び小型化に伴って、半導体装置の高密度化及び小型化が要求されている。
このため、下記特許文献１には、図８に示す半導体チップが基板内に埋め込まれたチップ内蔵半導体装置が提案されている。図８に示すチップ内蔵半導体装置は、一面側に他の電子部品が実装されるパッド１０２，１０２・・が設けられた第１多層配線基板１００と、一面側に外部接続端子としてのはんだボールが装着されるパッド２０２，２０２・・が形成された第1多層配線基板２００とが、銅コアはんだボール１０４，１０４によって電気的に接続されている。
かかる第２多層配線基板２００と第１多層配線基板１００との間であって、第２多層配線基板２００の他面側には、半導体チップ２０４が搭載されている。この半導体チップ２０４と第２多層配線基板２００との間には、アンダーフィル剤２０６によって封止され、且つ半導体チップ２０４を含む第２多層配線基板２００と第１多層配線基板１００との間も、封止樹脂１０８によって封止されている。
特開２００８−１０８８５ At present, as electronic devices using semiconductor devices have higher performance and smaller sizes, there is a demand for higher density and smaller size of semiconductor devices.
For this reason, the following Patent Document 1 proposes a chip built-in semiconductor device in which the semiconductor chip shown in FIG. 8 is embedded in a substrate. 8 includes a first multilayer wiring board 100 provided with pads 102, 102,... On which one side is mounted with other electronic components, and solder balls as external connection terminals on one side. Are electrically connected to the first multilayer wiring board 200 on which the pads 202, 202,... To be mounted are formed by the copper core solder balls 104, 104.
A semiconductor chip 204 is mounted between the second multilayer wiring board 200 and the first multilayer wiring board 100 and on the other surface side of the second multilayer wiring board 200. Between the semiconductor chip 204 and the second multilayer wiring substrate 200, the space between the second multilayer wiring substrate 200 and the first multilayer wiring substrate 100 that is sealed with the underfill agent 206 and includes the semiconductor chip 204 is also It is sealed with a sealing resin 108.
JP2008-1085A

図８に示すチップ内蔵基板を製造する際には、図９（ａ）に示す様に、パッド１０２，１０２・・を直接形成した支持板としての銅板１１０の一面側に、ビルドアップ法で形成した第１多層配線基板１００を形成し、第１多層配線基板１００の一面側に銅コアはんだボール１０４，１０４を装着する。
更に、パッド２０２，２０２・・を直接形成した支持板としての銅板２１０の一面側にビルドアップ法で形成した第２多層配線基板２００に、半導体チップ２０４を搭載し且つ半導体チップ２０４と第２多層配線基板２００との間にはアンダーフィル剤２０６を充填する。
次いで、図９（ｂ）に示す様に、第１多層配線基板１００と第２多層配線基板２００とを、半導体チップ２０４を挟み込むように積層する。この際に、第1多層配線基板１００と第２多層配線基板２００とは、第１多層配線基板１００の一面側に装着した銅コアはんだボール１０４，１０４を介して電気的に接続されている。かかる第１多層配線基板１００と第２多層配線基板２００との間は、封止樹脂１０８によって封止する。
次いで、銅板１１０，２１０を剥離し、図９（ｃ）に示す様に、所定形状に切断することによって、図８に示すチップ内蔵基板を得ることができる。 When the chip-embedded substrate shown in FIG. 8 is manufactured, as shown in FIG. 9A, it is formed by a build-up method on one surface side of the copper plate 110 as a support plate on which the pads 102, 102. The first multilayer wiring board 100 is formed, and copper core solder balls 104 and 104 are mounted on one surface side of the first multilayer wiring board 100.
Further, the semiconductor chip 204 is mounted on the second multilayer wiring board 200 formed by the build-up method on one surface side of the copper plate 210 as a support plate on which the pads 202, 202... Are directly formed, and the semiconductor chip 204 and the second multilayer are mounted. An underfill agent 206 is filled between the wiring board 200 and the wiring board 200.
Next, as shown in FIG. 9B, the first multilayer wiring substrate 100 and the second multilayer wiring substrate 200 are stacked so as to sandwich the semiconductor chip 204 therebetween. At this time, the first multilayer wiring board 100 and the second multilayer wiring board 200 are electrically connected via copper core solder balls 104 and 104 mounted on one surface side of the first multilayer wiring board 100. The space between the first multilayer wiring board 100 and the second multilayer wiring board 200 is sealed with a sealing resin 108.
Next, the copper plates 110 and 210 are peeled off and cut into a predetermined shape as shown in FIG. 9C, whereby the chip built-in substrate shown in FIG. 8 can be obtained.

図９に示すチップ内蔵基板の製造方法によれば、支持板としての銅板１１０，２１０の一面側にビルドアップ法によって形成した多層配線基板１００，２００を積層して、反りの発現が抑制できる所定厚さ以上の基板が形成された後、銅板１１０，２１０を剥離している。このため、基板の形成途中で多層配線基板１００，２００に反りが発生することを抑制できる。
しかしながら、図８に示すチップ内蔵基板では、基板内に半導体チップ２０４が内蔵されているため、図９に示す製造方法で得られたチップ内蔵基板の導通試験等の検査において不具合が発生したとき、全体を不良品扱いせざるを得ない。
また、発生した不具合が、多層配線基板１００，２００に原因があるのか、半導体チップ２０４に原因があるのか不明であり、対応策が遅れるおそれがある。
そこで、本発明は、完成したチップ内蔵基板で導通試験等の検査を行う従来のチップ内蔵基板の製造方法の課題を解決し、チップ内蔵基板の製造工程の途中で形成した多層配線基板の導通検査を行うことができるチップ内蔵基板の製造方法を提供することにある。 According to the method for manufacturing a chip-embedded substrate shown in FIG. 9, the multilayer wiring substrates 100 and 200 formed by the build-up method are laminated on one surface side of the copper plates 110 and 210 as support plates, so that the occurrence of warpage can be suppressed. After the substrate having a thickness larger than that is formed, the copper plates 110 and 210 are peeled off. For this reason, it can suppress that the multilayer wiring board 100,200 generate | occur | produces curvature in the middle of formation of a board | substrate.
However, in the chip-embedded substrate shown in FIG. 8, since the semiconductor chip 204 is built in the substrate, when a defect occurs in the inspection such as the continuity test of the chip-embedded substrate obtained by the manufacturing method shown in FIG. The whole must be treated as defective.
In addition, it is unclear whether the problem that has occurred is caused by the multilayer wiring boards 100 and 200 or the semiconductor chip 204, and there is a possibility that countermeasures will be delayed.
Accordingly, the present invention solves the problem of the conventional method for manufacturing a chip-embedded substrate in which a continuity test or the like is inspected on the completed chip-embedded substrate, and conducts a continuity test on a multilayer wiring board formed during the manufacturing process of the chip-embedded substrate Another object of the present invention is to provide a method of manufacturing a chip-embedded substrate that can perform the above process.

本発明者等は、前記課題を解決するには、支持板としての銅板の一面側にビルドアップ法によって形成した多層配線基板の段階で、形成した多層配線基板に導通試験を施すことが有効であると考え検討した結果、本発明に到達した。
すなわち、本発明は、第１多層配線基板と第２多層配線基板とを、前記第１多層配線基板又は第２多層配線基板に実装した半導体チップを挟み込むように積層してチップ内蔵基板を製造する際に、前記第１多層配線基板と第２多層配線基板との各々を、前記基板の各一面側に形成する複数の第１パッドを直接形成した支持板としての第１金属板の一面側に、絶縁層を介して複数の配線を積層するビルドアップ法によって形成した後、前記第１多層配線基板と第２多層配線基板の各々の他面側に、端面が露出する第２パッドの各々と、前記第２パッドの各々と対応し且つ端面が前記第１金属板と接触している前記第１パッドとが、前記基板内に形成された配線パターンを介して電気的に接続されていることを、前記第２パッドと第１金属板との間の導通試験によって確認し、次いで、前記第１多層配線基板と第２多層配線基板の各第２パッドの端面が露出する他面側の全面を被覆する絶縁層を介して第２金属板を接合した後、前記第１金属板を剥離して端面が露出した各第１パッドに接続された配線パターン同士が互いに絶縁されていることを、前記第１パッドの露出した端面間の導通試験によって確認し、その後、前記第１多層配線基板と第２多層配線基板の一方の基板に半導体チップを搭載してから、前記一方の基板のチップ搭載面に他方の基板を積層することを特徴とするチップ内蔵基板の製造方法にある。
かかる本発明において、第１金属板及び第２金属板として、銅板を用いることが好ましい。 In order to solve the above problems, the present inventors are effective to conduct a continuity test on the formed multilayer wiring board at the stage of the multilayer wiring board formed on one side of the copper plate as the support plate by the build-up method. The present invention has been reached as a result of studying it.
That is, the present invention manufactures a chip-embedded substrate by laminating a first multilayer wiring substrate and a second multilayer wiring substrate so as to sandwich a semiconductor chip mounted on the first multilayer wiring substrate or the second multilayer wiring substrate. In this case, each of the first multilayer wiring board and the second multilayer wiring board is provided on one surface side of a first metal plate as a support plate directly formed with a plurality of first pads formed on each surface side of the substrate. Each of the second pads whose end faces are exposed to the other side of each of the first multilayer wiring board and the second multilayer wiring board after being formed by a build-up method in which a plurality of wirings are stacked via an insulating layer. The first pad corresponding to each of the second pads and having an end surface in contact with the first metal plate is electrically connected via a wiring pattern formed in the substrate. Between the second pad and the first metal plate. Next, the second metal plate is bonded through an insulating layer covering the entire surface on the other side where the end faces of the respective second pads of the first multilayer wiring board and the second multilayer wiring board are exposed. Then, it is confirmed by a continuity test between the exposed end surfaces of the first pad that the wiring patterns connected to the first pads whose end surfaces are exposed by peeling off the first metal plate are insulated from each other. Then, after mounting a semiconductor chip on one of the first multilayer wiring substrate and the second multilayer wiring substrate, the other substrate is stacked on the chip mounting surface of the one substrate. The method is for manufacturing a built-in substrate.
In the present invention, it is preferable to use copper plates as the first metal plate and the second metal plate.

また、本発明は、第１多層配線基板と第２多層配線基板とを、前記第１多層配線基板又は第２多層配線基板に実装した半導体チップを挟み込むように積層してチップ内蔵基板を製造する際に、前記第１多層配線基板と第２多層配線基板との各々を、支持板としての金属板の一面側に形成した、前記金属板を形成する金属よりも電気抵抗の大きな金属から成る金属層の露出面に複数の第１パッドを直接形成した後、前記金属層上に絶縁層を介して複数の配線を積層するビルドアップ法によって形成し、前記第１多層配線基板と第２多層配線基板との各々の他面側に端面が露出する第２パッドの各々と、前記第２パッドの各々と対応し且つ前記金属層と端面が接触している前記第１パッドとが、前記基板内に形成された配線パターンを介して電気的に接続されていることを、前記第２パッドと第１金属板との間の導通試験によって確認すると共に、端面が露出する前記第２パッドの各々に接続された配線パターン同士が互いに絶縁されていることを、前記第２パッドの露出した端面間の導通試験によって確認し、次いで、前記第１多層配線基板と第２多層配線基板の一方の基板に半導体チップを搭載した後、前記一方の基板のチップ搭載面に他方の基板を積層することを特徴とするチップ内蔵基板の製造方法でもある。
かかる本発明において、金属層として、金属板よりも薄い金属層を形成することによって、第１パッドと第２パッドとの間の配線パターンが導通していることを確認する導通試験の際に、第１パッドと第２パッドとの間の導通を容易に確認できる。
更に、金属板として、銅板を好適に用いることができ、この銅板の一面側に、ニッケル又はクロムから成る金属層を好適に形成できる。 According to the present invention, a first multilayer wiring board and a second multilayer wiring board are stacked so as to sandwich a semiconductor chip mounted on the first multilayer wiring board or the second multilayer wiring board to manufacture a chip built-in substrate. In this case, each of the first multilayer wiring board and the second multilayer wiring board is formed on one surface side of a metal plate as a support plate, and is made of a metal having a higher electric resistance than the metal forming the metal plate. A plurality of first pads are directly formed on the exposed surface of the layer, and then formed by a build-up method in which a plurality of wirings are stacked on the metal layer via an insulating layer, and the first multilayer wiring board and the second multilayer wiring are formed. Each of the second pads whose end surfaces are exposed on the other surface side of each of the substrates, and each of the first pads corresponding to each of the second pads and in contact with the end surfaces of the metal layer are in the substrate. Electricity through the wiring pattern formed on Is confirmed by a continuity test between the second pad and the first metal plate, and the wiring patterns connected to each of the second pads where the end surfaces are exposed are insulated from each other. Is confirmed by a continuity test between the exposed end surfaces of the second pad, and then a semiconductor chip is mounted on one of the first multilayer wiring substrate and the second multilayer wiring substrate, and then the one substrate is mounted. This is also a method for manufacturing a chip-embedded substrate, in which the other substrate is laminated on the chip mounting surface.
In the present invention, by forming a metal layer thinner than the metal plate as the metal layer, a continuity test is performed to confirm that the wiring pattern between the first pad and the second pad is conductive. The conduction between the first pad and the second pad can be easily confirmed.
Furthermore, a copper plate can be suitably used as the metal plate, and a metal layer made of nickel or chromium can be suitably formed on one side of the copper plate.

本発明では、第１多層配線基板と第２多層配線基板とを、支持体としての金属板の一面側にビルドアップ法によって形成した後、多層配線基板の一面側に金属板を接合した状態での導通試験によって、多層配線基板の一面側に形成した第１パッドと他面側に形成した第２パッドとを電気的に接続する配線パターンが導通されていること、及び第１パッドの各々に接続された配線パターン同士が絶縁されていることを確認できる。
その結果、第１パッドと第２パッドとを電気的に接続する配線パターンの断線や第１パッドの各々に接続された配線パターン同士の短絡が存在する多層配線基板は不良品として排除でき、最終的に得られたチップ内蔵基板の信頼性を向上できる。
また、得られたチップ内蔵基板に不具合が発生した場合も、不具合の発生箇所の特定が容易であるため、その対応策を迅速に取ることができる。 In the present invention, after the first multilayer wiring board and the second multilayer wiring board are formed on one surface side of the metal plate as a support by a build-up method, the metal plate is bonded to the one surface side of the multilayer wiring substrate. In the continuity test, the wiring pattern that electrically connects the first pad formed on one surface side of the multilayer wiring board and the second pad formed on the other surface side is electrically connected, and each of the first pads It can be confirmed that the connected wiring patterns are insulated.
As a result, the multilayer wiring board in which the disconnection of the wiring pattern that electrically connects the first pad and the second pad or the short circuit between the wiring patterns connected to each of the first pads can be eliminated as a defective product. Thus, the reliability of the obtained chip built-in substrate can be improved.
In addition, even when a defect occurs in the obtained chip-embedded substrate, it is easy to identify the location where the defect has occurred, so that countermeasures can be taken quickly.

本発明に係るチップ内蔵基板の製造方法の一例を図１〜図６に示す。先ず、図１（ａ）に示す様に、支持板としての第１金属板１０の一面側に、第１多層配線基板１２をビルドアップ法によって形成する。第１金属板１０としては、厚さ５０μｍ以上の銅板を用いることができ、第１金属板１０の一面側に、第１金属板１０を給電層とする電解めっきによって第１パッド１４，１４・・を形成する。この第１パッド１４は、第１金属板１０側から金層１４ａ、ニッケル層１４ｂ及び銅層１４ｃから成る。
かかる第１パッド１４，１４・・を覆うように形成した樹脂層１６ａに、レーザによって第１パッド１４，１４・・が底面に露出するヴィア穴を形成した後、第１パッド１４，１４・・に各々が接続された銅製の配線パターン１８ａ，１８ａ・・を形成する。
更に、同様にして、配線パターン１８ａ，１８ａ・・上に、樹脂層１６ｂを介して銅製の配線パターン１８ｂ，１８ｂ・・を形成する。配線パターン１８ｂ，１８ｂ・・を覆うソルダーレジスト２２には、配線パターン１８ｂ，１８ｂ・・に接続された第２パッド２０，２０・・が底面に露出する凹部が形成されている。
この様に、第１金属板１０の一面側に形成された第１多層配線基板１２では、第１パッド１４と対応する第２パッド２０とは、配線パターン１８ａ，１８ｂによって電気的に接続されている。
このことを、確認すべく、図１（ｂ）に示す様に、第１パッド１４，１４・・の各々に接続されている第１金属板１０と各第２パッド２０との間の導通試験を行う。
ここで、導通試験を行った第１多層配線基板１２の第２パッドのうち、導通が確認できなかった第２パッドは、対応する第１パッドとの間の配線パターン１８ａ，１８ｂのいずれかで断線している。このため、かかる第１多層配線基板１２は不良品である。 An example of a method for manufacturing a chip-embedded substrate according to the present invention is shown in FIGS. First, as shown in FIG. 1A, a first multilayer wiring board 12 is formed on one surface side of a first metal plate 10 as a support plate by a build-up method. A copper plate having a thickness of 50 μm or more can be used as the first metal plate 10, and the first pads 14, 14... Are formed on one surface side of the first metal plate 10 by electrolytic plating using the first metal plate 10 as a power feeding layer. -Forming. The first pad 14 includes a gold layer 14a, a nickel layer 14b, and a copper layer 14c from the first metal plate 10 side.
In the resin layer 16a formed so as to cover the first pads 14, 14,..., Via holes that expose the first pads 14, 14,. Are made of copper wiring patterns 18a, 18a,.
In the same manner, copper wiring patterns 18b, 18b,... Are formed on the wiring patterns 18a, 18a,. In the solder resist 22 covering the wiring patterns 18b, 18b,..., Recesses are formed in which the second pads 20, 20,... Connected to the wiring patterns 18b, 18b,.
In this way, in the first multilayer wiring board 12 formed on the one surface side of the first metal plate 10, the first pad 14 and the corresponding second pad 20 are electrically connected by the wiring patterns 18a and 18b. Yes.
In order to confirm this, as shown in FIG. 1B, a continuity test between the first metal plate 10 connected to each of the first pads 14, 14... And each second pad 20 is performed. I do.
Here, among the second pads of the first multilayer wiring board 12 subjected to the continuity test, the second pad for which continuity could not be confirmed is one of the wiring patterns 18a and 18b between the corresponding first pads. Disconnected. Therefore, the first multilayer wiring board 12 is a defective product.

次いで、第２パッド２０，２０と第１金属板１０との間の導通が確認された第１多層配線基板１２については、図２（ａ）に示す様に、第１多層配線基板１２の第２パッド２０，２０・・が形成された面側に、絶縁層３２を介して第２金属板３０を接合する。かかる絶縁層３２としては、ドライフィルムレジストを好適に用いることができ、第２金属板３０としては、厚さ５０μｍの銅板を好適に用いることができる。
次いで、図２（ｂ）に示す様に、第１金属板１０をエッチング除去して露出した第１パッド１４，１４・・について、第１パッド１４，１４間の導通試験を行う。かかる導通試験によって、第１パッド１４，１４の各々に接続されている配線パターン１８ａ，１８ｂ同士間では、絶縁されていることを確認する。
ここで、導通試験を行った第１多層配線基板１２の第１パッド１４，１４・・のうち、導通が確認された第１パッド１４，１４では、この第１パッド１４，１４の各々に接続されている配線パターン１８ａ，１８ｂ同士間のいずれかに短絡が存在している。このため、かかる第１多層配線基板１２は不良品である。
この様にして、第１多層配線基板１２について、その第２パッド２０と対応する第１パッド１４とが導通されていること、第１パッド１４，１４・・の各々に接続されている配線パターン１８ａ，１８ｂ同士間が絶縁されている良品であることを確認する。
良品であることが確認された第１多層配線基板１２の第１パッド１４，１４・・の各々には、図２（ｃ）に示す様に、銅コアはんだボール２３を装着する。
尚、銅コアはんだボール２３に代えて、銅コアを含まないはんだボールを用いることができる。 Next, for the first multilayer wiring board 12 in which conduction between the second pads 20 and 20 and the first metal plate 10 is confirmed, as shown in FIG. The second metal plate 30 is bonded to the surface side on which the two pads 20, 20. As the insulating layer 32, a dry film resist can be preferably used, and as the second metal plate 30, a copper plate having a thickness of 50 μm can be preferably used.
Next, as shown in FIG. 2B, a continuity test between the first pads 14 and 14 is performed on the first pads 14 and 14 exposed by removing the first metal plate 10 by etching. The continuity test confirms that the wiring patterns 18a and 18b connected to the first pads 14 and 14 are insulated from each other.
Here, among the first pads 14, 14... Of the first multilayer wiring board 12 subjected to the continuity test, the first pads 14, 14 confirmed to be conductive are connected to each of the first pads 14, 14. There is a short circuit between the wiring patterns 18a and 18b. Therefore, the first multilayer wiring board 12 is a defective product.
In this way, with respect to the first multilayer wiring board 12, the second pad 20 and the corresponding first pad 14 are electrically connected, and the wiring pattern connected to each of the first pads 14, 14. It is confirmed that the non-defective product is insulated between 18a and 18b.
As shown in FIG. 2C, a copper core solder ball 23 is attached to each of the first pads 14, 14,... Of the first multilayer wiring board 12 that has been confirmed to be non-defective.
In place of the copper core solder ball 23, a solder ball not including a copper core can be used.

図２（ｃ）に示す第１多層配線基板１２と接合される第２多層配線基板を製造する際には、図３（ａ）に示す様に、支持板としての第１金属板５０の一面側に第２多層配線基板５２をビルドアップ法によって形成する。第１金属板５０としては、厚さ５０μｍ以上の銅板を用いることができ、第１金属板５０の一面側に、第１金属板５０を給電層とする電解めっきによって第１パッド５４，５４・・を形成する。この第１パッド５４は、第１金属板１０側から金層５４ａ、ニッケル層５４ｂ及び銅層５４ｃから成る。
かかる第１パッド５４，５４・・を覆うように形成した樹脂層５６ａに、レーザによって第１パッド５４，５４・・が底面に露出するヴィア穴を形成した後、第１パッド５４，５４・・に各々が接続された銅製の配線パターン５８ａ，５８ａ・・を形成する。
更に、同様にして、配線パターン５８ａ，５８ａ・・上に、樹脂層５６ｂを介して銅製の配線パターン５８ｂ，５８ｂ・・を形成する。配線パターン５８ｂ，５８ｂ・・を覆うソルダーレジスト６０には、配線パターン５８ｂ、５８ｂに接続された第２パッド６２，６２が底面に露出する凹部が形成されている。
この様に、第１金属板５０の一面側に形成された第２多層配線基板５２では、第１パッド５４と対応する第２パッド６２とは、配線パターン５８ａ，５８ｂによって電気的に接続されている。
このことを、確認すべく、図３（ｂ）に示す様に、第１パッド５４，５４・・の各々に接続されている第１金属板５０と各第２パッド６２との間の導通試験を行う。
ここで、導通試験を行った第２多層配線基板５２の第２パッドのうち、導通が確認できなかった第２パッドは、対応する第１パッドとの間の配線パターン５８ａ，５８ｂのいずれかで断線している。このため、かかる第２多層配線基板５２は不良品である。 When manufacturing the second multilayer wiring board to be joined to the first multilayer wiring board 12 shown in FIG. 2 (c), as shown in FIG. 3 (a), one surface of the first metal plate 50 as a support plate. A second multilayer wiring board 52 is formed on the side by a build-up method. As the first metal plate 50, a copper plate having a thickness of 50 μm or more can be used. On the one surface side of the first metal plate 50, the first pads 54, 54. -Forming. The first pad 54 includes a gold layer 54a, a nickel layer 54b, and a copper layer 54c from the first metal plate 10 side.
In the resin layer 56a formed so as to cover the first pads 54, 54,..., Via holes that expose the first pads 54, 54,. Are formed with copper wiring patterns 58a, 58a,.
Further, similarly, copper wiring patterns 58b, 58b,... Are formed on the wiring patterns 58a, 58a,. In the solder resist 60 covering the wiring patterns 58b, 58b,..., Recesses are formed in which the second pads 62, 62 connected to the wiring patterns 58b, 58b are exposed on the bottom surface.
As described above, in the second multilayer wiring board 52 formed on the one surface side of the first metal plate 50, the first pads 54 and the corresponding second pads 62 are electrically connected by the wiring patterns 58a and 58b. Yes.
In order to confirm this, as shown in FIG. 3B, a continuity test between the first metal plate 50 connected to each of the first pads 54, 54,. I do.
Here, of the second pads of the second multilayer wiring board 52 that have been subjected to the continuity test, the second pad that has not been confirmed to be conductive is one of the wiring patterns 58a and 58b between the corresponding first pad. Disconnected. Therefore, the second multilayer wiring board 52 is a defective product.

次いで、第２パッド６２，６２・・と第１金属板５０との間の導通が確認された第２多層配線基板５２については、図４（ａ）に示す様に、第２多層配線基板５２の第２パッド６２，６２・・が形成された面側に、絶縁層７２を介して第２金属板７０を接合する。かかる絶縁層７２としては、ドライフィルムレジストを好適に用いることができ、第２金属板７０としては、厚さ５０μｍの銅板を好適に用いることができる。
次いで、図４（ｂ）に示す様に、第１金属板５０をエッチング除去して露出した第１パッド５４，５４・・について、第１パッド５４，５４間の導通試験を行う。かかる導通試験によって、第１パッド５４，５４の各々に接続されている配線パターン５８ａ，５８ｂ同士間では、絶縁されていることを確認する。
ここで、導通試験を行った第２多層配線基板５２の第１パッド５４，５４・・のうち、導通が確認された第１パッド５４，５４では、この第１パッド５４，５４の各々に接続されている配線パターン５８ａ，５８ｂ同士間のいずれかに短絡が存在している。このため、かかる第２多層配線基板５２は不良品である。
この様にして、第２多層配線基板５２について、その第２パッド６２と対応する第１パッド５４とが導通されていること、第１パッド５４，５４・・の各々に接続されている配線パターン５８ａ，５８ｂ同士間が絶縁されている良品であることを確認する。
良品であることが確認された第２多層配線基板５２の第１パッド５４，５４・・の各々には、図４（ｃ）に示す様に、半導体チップ８０をフリップチップ方式によって搭載し、半導体チップ８０と第２多層配線基板５２との間隙は、アンダーフィル８２によって充填する。
尚、図４（ｃ）では、第２多層配線基板５２に半導体チップ８０を搭載しているが、第１多層配線基板１２に半導体チップ８０を搭載してもよい。 Next, as for the second multilayer wiring board 52 in which conduction between the second pads 62, 62... And the first metal plate 50 is confirmed, as shown in FIG. The second metal plate 70 is bonded to the surface side on which the second pads 62, 62,. As the insulating layer 72, a dry film resist can be preferably used, and as the second metal plate 70, a copper plate having a thickness of 50 μm can be preferably used.
Next, as shown in FIG. 4B, a continuity test between the first pads 54, 54 is performed on the first pads 54, 54,... Exposed by removing the first metal plate 50 by etching. By such a continuity test, it is confirmed that the wiring patterns 58a and 58b connected to the first pads 54 and 54 are insulated from each other.
Here, among the first pads 54, 54,... Of the second multilayer wiring board 52 subjected to the continuity test, the first pads 54, 54 confirmed to be conductive are connected to the first pads 54, 54, respectively. There is a short circuit between the wiring patterns 58a and 58b. Therefore, the second multilayer wiring board 52 is a defective product.
In this way, with respect to the second multilayer wiring substrate 52, the second pad 62 and the corresponding first pad 54 are electrically connected, and the wiring pattern connected to each of the first pads 54, 54,. It is confirmed that the non-defective product 58a and 58b are insulated from each other.
As shown in FIG. 4 (c), a semiconductor chip 80 is mounted on each of the first pads 54, 54,... Of the second multilayer wiring board 52, which has been confirmed to be non-defective, by a flip chip method. The gap between the chip 80 and the second multilayer wiring board 52 is filled with an underfill 82.
In FIG. 4C, the semiconductor chip 80 is mounted on the second multilayer wiring board 52, but the semiconductor chip 80 may be mounted on the first multilayer wiring board 12.

図１及び図２に示す方法によって得た良品の第１多層配線基板１２と図３及び図４に示す方法によって得た良品の第２多層配線基板５２とを、図５（ａ）に示す様に、銅コアはんだボール２３，２３・・を介して接合する。この際に、第２多層配線基板５２に搭載された半導体チップ８０は、第１多層配線基板１２との間に挟み込まれる。
更に、第１多層配線基板１２と第２多層配線基板５２との間の隙間は、図５（ｂ）に示す様に、封止樹脂８４によって封止される。
次いで、図６（ａ）に示す様に、第１多層配線基板１２に絶縁層３２を介して接合されていた第２金属板３０を剥離した後、図６（ｂ）に示す様に、第２多層配線基板５２に絶縁層７２を介して接合されていた第２金属板７０を剥離する。更に、絶縁層３２，７２を剥離することによって、第２パッド２０，６２が露出する。
この様に、第２金属板３０，７０の各々を剥離しても、第１多層配線基板１２と第２多層配線基板５２とが封止樹脂８４を介して一体に接合された基板は、その剛性が向上されているため、湾曲することを防止できる。
その後、基板を切断して個片化することによって、図６（ｃ）に示すチップ内蔵基板を得ることができる。 A good first multilayer wiring board 12 obtained by the method shown in FIGS. 1 and 2 and a good second multilayer wiring board 52 obtained by the method shown in FIGS. 3 and 4 are shown in FIG. Are joined via copper core solder balls 23, 23. At this time, the semiconductor chip 80 mounted on the second multilayer wiring board 52 is sandwiched between the first multilayer wiring board 12.
Further, the gap between the first multilayer wiring board 12 and the second multilayer wiring board 52 is sealed with a sealing resin 84 as shown in FIG.
Next, as shown in FIG. 6A, after the second metal plate 30 bonded to the first multilayer wiring board 12 via the insulating layer 32 is peeled off, as shown in FIG. The second metal plate 70 bonded to the two multilayer wiring board 52 via the insulating layer 72 is peeled off. Further, the second pads 20 and 62 are exposed by peeling off the insulating layers 32 and 72.
Thus, even if each of the second metal plates 30 and 70 is peeled off, the substrate in which the first multilayer wiring substrate 12 and the second multilayer wiring substrate 52 are integrally bonded via the sealing resin 84 is Since the rigidity is improved, the bending can be prevented.
Thereafter, the substrate is cut into individual pieces, whereby the chip-embedded substrate shown in FIG. 6C can be obtained.

この様にして得られたチップ内蔵基板は、その製造工程において、第１パッド１４（５４）と第２パッド２０（６２）とを電気的に接続する配線パターン１８ａ，１８ｂ（５８ａ，５８ｂ）の断線や第１パッド１４（５４）の各々に接続された配線パターン同士の短絡が存在する多層配線基板は不良品として排除でき、最終的に得られたチップ内蔵基板の信頼性を向上できる。
また、得られたチップ内蔵基板に不具合が発生した場合も、不具合の発生箇所の特定が容易であるため、その対応策を迅速に取ることができる。 The chip-embedded substrate thus obtained has wiring patterns 18a and 18b (58a and 58b) for electrically connecting the first pad 14 (54) and the second pad 20 (62) in the manufacturing process. A multilayer wiring board in which a disconnection or a short circuit between wiring patterns connected to each of the first pads 14 (54) exists can be eliminated as a defective product, and the reliability of the finally obtained chip-embedded substrate can be improved.
In addition, even when a defect occurs in the obtained chip-embedded substrate, it is easy to identify the location where the defect has occurred, so that countermeasures can be taken quickly.

図１〜図６に示す製造方法では、第１多層配線基板１２と第２多層配線基板５２との第１回目の導通試験を、第１多層配線基板１２と第２多層配線基板５２の各一面側に接合されていた第１金属板１０，５０を用いて第１回目の導通試験を実施した後、第１多層配線基板１２と第２多層配線基板５２の各他面側に第２金属板３０，７０を接合し、次いで、第１金属板１０，５０を除去した後、第２金属板３０，７０を用いた第２回目の導通試験を行っている。
この様に、金属板の張り替えを行うことは、チップ内蔵基板の製造工程を複雑化する傾向にある。このため、図７（ａ）に示す様に、支持板としての銅から成る第１金属板１０の一面側に、銅よりも電気抵抗の大きな金属、例えばニッケル又はクロムから成る金属層８６を形成する。かかる金属層８６は、めっき、蒸着又はスパッタによって形成できる。
更に、第１金属板１０に形成した金属層８６上に、複数個の第１パッド１４，１４・・を直接形成する。この第１パッド１４は、図１〜図６に示すものと同一であって、詳細な説明は省略する。
かかる金属層８６上に、図７（ｂ）に示す様に、第１多層配線基板１２をビルドアップ法によって形成する。かかる第１多層配線基板１２の製造方法は、図１（ａ）に示す製造方法と同一であるため、詳細な説明を省略する。 1 to 6, the first continuity test between the first multilayer wiring board 12 and the second multilayer wiring board 52 is performed on each surface of the first multilayer wiring board 12 and the second multilayer wiring board 52. After conducting the first continuity test using the first metal plates 10 and 50 bonded to the side, the second metal plate is formed on each other side of the first multilayer wiring substrate 12 and the second multilayer wiring substrate 52. 30 and 70 are joined, and then the first metal plates 10 and 50 are removed, and then a second continuity test using the second metal plates 30 and 70 is performed.
In this way, the replacement of the metal plate tends to complicate the manufacturing process of the chip-embedded substrate. Therefore, as shown in FIG. 7A, a metal layer 86 made of a metal having a higher electrical resistance than copper, such as nickel or chromium, is formed on one surface side of the first metal plate 10 made of copper as a support plate. To do. Such a metal layer 86 can be formed by plating, vapor deposition, or sputtering.
Further, a plurality of first pads 14 are formed directly on the metal layer 86 formed on the first metal plate 10. The first pad 14 is the same as that shown in FIGS. 1 to 6 and will not be described in detail.
On the metal layer 86, as shown in FIG. 7B, the first multilayer wiring board 12 is formed by a build-up method. Since the manufacturing method of this 1st multilayer wiring board 12 is the same as the manufacturing method shown to Fig.1 (a), detailed description is abbreviate | omitted.

形成した第１多層配線基板１２には、図７（ｃ）に示す様に、第１パッド１４，１４間の導通試験を行う。この際に、第２パッド２０と銅製の配線パターン１８ａ，１８ｂを介して接続されている第１パッド１４が接触している金属層８６は、第１金属板１０を形成する銅よりも電気抵抗の大きなニッケル又はクロムによって形成されており、第１パッド１４，１４間は実質的に絶縁されている状態にある。
従って、第１パッド１４，１４の各々に接続されている配線パターン１８ａ，１８ｂ同士間では、絶縁されていることを確認できる。
また、第２パッド２０と対応する第１パッド１４との間の導通試験も、第１金属板１０を第１多層配線基板１２に接合した状態で行うことができる。すなわち、金属層８６は、その厚み方向の距離が長手方向に比較して著しく短く、厚み方向の電気抵抗値は小さい。このため、第２パッド２０と第１金属板１０との間に印加する電圧を調整することによって、第２パッド２０と第１金属板１０との間を導通でき、第２パッド２０と対応する第１パッド１４との間の導通を確認できる。
図７では、第１多層配線基板１２を形成する際の導通試験について説明したが、第２多層配線基板５２を形成する際の導通試験についても同様に行うことができる。 The formed first multilayer wiring board 12 is subjected to a continuity test between the first pads 14 and 14, as shown in FIG. At this time, the metal layer 86 in contact with the second pad 20 and the first pad 14 connected via the copper wiring patterns 18 a and 18 b has an electric resistance higher than that of the copper forming the first metal plate 10. The first pads 14 and 14 are substantially insulated from each other.
Therefore, it can be confirmed that the wiring patterns 18a and 18b connected to the first pads 14 and 14 are insulated from each other.
Further, the continuity test between the second pad 20 and the corresponding first pad 14 can also be performed in a state where the first metal plate 10 is bonded to the first multilayer wiring board 12. That is, the metal layer 86 has a remarkably short distance in the thickness direction compared to the longitudinal direction, and has a small electric resistance value in the thickness direction. For this reason, by adjusting the voltage applied between the second pad 20 and the first metal plate 10, the second pad 20 and the first metal plate 10 can be electrically connected to each other and correspond to the second pad 20. Conductivity with the first pad 14 can be confirmed.
Although the continuity test when forming the first multilayer wiring board 12 has been described with reference to FIG. 7, the continuity test when forming the second multilayer wiring board 52 can be similarly performed.

本発明に係るチップ内蔵基板の製造工程の一部を説明する工程図である。It is process drawing explaining a part of manufacturing process of the chip | tip built-in board | substrate concerning this invention. 図１に示す製造工程に続く工程の一部を説明する工程図である。It is process drawing explaining a part of process following the manufacturing process shown in FIG. 図２に示す製造工程に続く工程の一部を説明する工程図である。FIG. 3 is a process diagram illustrating part of a process that follows the manufacturing process illustrated in FIG. 2. 図３に示す製造工程に続く工程の一部を説明する工程図である。It is process drawing explaining a part of process following the manufacturing process shown in FIG. 図４に示す製造工程に続く工程の一部を説明する工程図である。It is process drawing explaining a part of process following the manufacturing process shown in FIG. 図５に示す製造工程に続く工程の残部を説明する工程図である。It is process drawing explaining the remainder of the process following the manufacturing process shown in FIG. 本発明に係るチップ内蔵基板の製造方法の他の方法を説明する工程図である。It is process drawing explaining the other method of the manufacturing method of the chip | tip built-in board | substrate concerning this invention. チップ内蔵基板の構成を説明する縦断面図である。It is a longitudinal cross-sectional view explaining the structure of a chip | tip built-in board | substrate. 従来のチップ内蔵基板の製造方法を説明する工程図である。It is process drawing explaining the manufacturing method of the conventional chip | tip built-in board | substrate.

符号の説明Explanation of symbols

１０，５０，３０，７０ 金属板
１２ 第１多層配線基板
１４，２０，５４，６２ パッド
１６ａ，１６ｂ，５６ａ，５６ｂ 樹脂層
１８ａ，１８ｂ，５８ａ，５８ｂ 配線パターン
２２，６０ ソルダーレジスト
２２ 銅コアはんだボール
３２，７２ 絶縁層
５２ 第２多層配線基板
８０ 半導体チップ
８２ アンダーフィル
８４ 封止樹脂
８６ 金属層 10, 50, 30, 70 Metal plate 12 First multilayer wiring board 14, 20, 54, 62 Pads 16a, 16b, 56a, 56b Resin layers 18a, 18b, 58a, 58b Wiring patterns 22, 60 Solder resist 22 Copper core solder Balls 32 and 72 Insulating layer 52 Second multilayer wiring board 80 Semiconductor chip 82 Underfill 84 Sealing resin 86 Metal layer

Claims (5)

第１多層配線基板と第２多層配線基板とを、前記第１多層配線基板又は第２多層配線基板に実装した半導体チップを挟み込むように積層してチップ内蔵基板を製造する際に、
前記第１多層配線基板と第２多層配線基板との各々を、前記基板の各一面側に形成する複数の第１パッドを直接形成した支持板としての第１金属板の一面側に、絶縁層を介して複数の配線を積層するビルドアップ法によって形成した後、
前記第１多層配線基板と第２多層配線基板との各々の他面側に、端面が露出する第２パッドの各々と、前記第２パッドの各々と対応し且つ端面が前記第１金属板と接触している前記第１パッドとが、前記基板内に形成された配線パターンを介して電気的に接続されていることを、前記第２パッドと第１金属板との間の導通試験によって確認し、
次いで、前記第１多層配線基板と第２多層配線基板の各第２パッドの端面が露出する他面側の全面を被覆する絶縁層を介して第２金属板を接合した後、前記第１金属板を剥離して端面が露出した各第１パッドに接続された配線パターン同士が互いに絶縁されていることを、前記第１パッドの露出した端面間の導通試験によって確認し、
その後、前記第１多層配線基板と第２多層配線基板の一方の基板に半導体チップを搭載してから、前記一方の基板のチップ搭載面に他方の基板を積層することを特徴とするチップ内蔵基板の製造方法。 When manufacturing the chip built-in substrate by stacking the first multilayer wiring substrate and the second multilayer wiring substrate so as to sandwich the semiconductor chip mounted on the first multilayer wiring substrate or the second multilayer wiring substrate,
An insulating layer is formed on one surface side of the first metal plate as a support plate in which a plurality of first pads for directly forming each of the first multilayer wiring substrate and the second multilayer wiring substrate is formed on each surface side of the substrate. After forming by a build-up method that stacks multiple wires through
On the other surface side of each of the first multilayer wiring substrate and the second multilayer wiring substrate, each of the second pads whose end surfaces are exposed, each end surface corresponding to each of the second pads and the first metal plate It is confirmed by a continuity test between the second pad and the first metal plate that the contacting first pad is electrically connected via a wiring pattern formed in the substrate. And
Next, after joining a second metal plate via an insulating layer covering the entire surface on the other surface side where the end face of each second pad of the first multilayer wiring substrate and the second multilayer wiring substrate is exposed, the first metal It is confirmed by a continuity test between the exposed end faces of the first pad that the wiring patterns connected to the first pads whose end faces are exposed by peeling the plate are insulated from each other,
Thereafter, a semiconductor chip is mounted on one of the first multilayer wiring substrate and the second multilayer wiring substrate, and then the other substrate is stacked on the chip mounting surface of the one substrate. Manufacturing method. 第１金属板及び第２金属板として、銅板を用いる請求項１記載のチップ内蔵基板の製造方法。   The manufacturing method of the chip | tip built-in board | substrate of Claim 1 which uses a copper plate as a 1st metal plate and a 2nd metal plate. 第１多層配線基板と第２多層配線基板とを、前記第１多層配線基板又は第２多層配線基板に実装した半導体チップを挟み込むように積層してチップ内蔵基板を製造する際に、
前記第１多層配線基板と第２多層配線基板との各々を、支持板としての金属板の一面側に形成した、前記金属板を形成する金属よりも電気抵抗の大きな金属から成る金属層の露出面に複数の第１パッドを直接形成した後、前記金属層上に絶縁層を介して複数の配線を積層するビルドアップ法によって形成し、
前記第１多層配線基板と第２多層配線基板との各々の他面側に端面が露出する第２パッドの各々と、前記第２パッドの各々と対応し且つ前記金属層と端面が接触している前記第１パッドとが、前記基板内に形成された配線パターンを介して電気的に接続されていることを、前記第２パッドと第１金属板との間の導通試験によって確認すると共に、
端面が露出する前記第２パッドの各々に接続された配線パターン同士が互いに絶縁されていることを、前記第２パッドの露出した端面間の導通試験によって確認し、
次いで、前記第１多層配線基板と第２多層配線基板の一方の基板に半導体チップを搭載した後、前記一方の基板のチップ搭載面に他方の基板を積層することを特徴とするチップ内蔵基板の製造方法。 When manufacturing the chip built-in substrate by stacking the first multilayer wiring substrate and the second multilayer wiring substrate so as to sandwich the semiconductor chip mounted on the first multilayer wiring substrate or the second multilayer wiring substrate,
Exposing a metal layer made of a metal having a higher electric resistance than the metal forming the metal plate, wherein each of the first multilayer wiring substrate and the second multilayer wiring substrate is formed on one side of a metal plate as a support plate A plurality of first pads are directly formed on the surface, and then formed by a build-up method in which a plurality of wirings are stacked on the metal layer via an insulating layer,
Each of the second pads whose end faces are exposed on the other side of each of the first multilayer wiring board and the second multilayer wiring board corresponds to each of the second pads, and the metal layer and the end face are in contact with each other. The first pad is confirmed to be electrically connected via a wiring pattern formed in the substrate by a continuity test between the second pad and the first metal plate,
It is confirmed by a continuity test between the exposed end faces of the second pad that the wiring patterns connected to each of the second pads where the end faces are exposed are insulated from each other,
Next, after mounting a semiconductor chip on one of the first multilayer wiring substrate and the second multilayer wiring substrate, the other substrate is stacked on the chip mounting surface of the one substrate. Production method. 金属層として、金属板よりも薄い金属層を形成する請求項３記載のチップ内蔵基板の製造方法。   4. The method for manufacturing a chip built-in substrate according to claim 3, wherein a metal layer thinner than the metal plate is formed as the metal layer. 金属板として、銅板を用い、前記銅板の一面側に、ニッケル又はクロムから成る金属層を形成する請求項３又は請求項４記載のチップ内蔵基板の製造方法。   5. The method for manufacturing a chip-embedded substrate according to claim 3, wherein a copper plate is used as the metal plate, and a metal layer made of nickel or chromium is formed on one surface side of the copper plate.
JP2008135980A 2008-05-23 2008-05-23 Method of manufacturing substrate with built-in chip Withdrawn JP2009283788A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2008135980A JP2009283788A (en) 2008-05-23 2008-05-23 Method of manufacturing substrate with built-in chip

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2008135980A JP2009283788A (en) 2008-05-23 2008-05-23 Method of manufacturing substrate with built-in chip

Publications (1)

Publication Number Publication Date
JP2009283788A true JP2009283788A (en) 2009-12-03

Family

ID=41453913

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2008135980A Withdrawn JP2009283788A (en) 2008-05-23 2008-05-23 Method of manufacturing substrate with built-in chip

Country Status (1)

Country Link
JP (1) JP2009283788A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2017103364A (en) * 2015-12-02 2017-06-08 凸版印刷株式会社 Wiring board laminate, semiconductor device, and method of manufacturing semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2017103364A (en) * 2015-12-02 2017-06-08 凸版印刷株式会社 Wiring board laminate, semiconductor device, and method of manufacturing semiconductor device

Similar Documents

Publication Publication Date Title
JP5010737B2 (en) Printed wiring board
KR100796523B1 (en) Electronic component embedded multilayer printed wiring board and manufacturing method thereof
JP4361826B2 (en) Semiconductor device
US7365416B2 (en) Multi-level semiconductor module and method for fabricating the same
JP5071084B2 (en) Wiring substrate, laminated semiconductor device and laminated semiconductor module using the same
TWI469700B (en) Printed circuit board having buried component and method for manufacturing same
JP4930567B2 (en) Relay board, printed circuit board unit, and relay board manufacturing method
US8120148B2 (en) Package structure with embedded die and method of fabricating the same
JP4070470B2 (en) Multilayer circuit board for semiconductor device, manufacturing method thereof, and semiconductor device
JP2014107552A (en) Multilayer printed circuit board and method of manufacturing the same
JP2009147165A (en) Semiconductor device
WO2017217138A1 (en) Multilayer wiring board for inspection of electronic components
JP2007163327A (en) Semiconductor device, and inspection method of semiconductor device
US9338887B2 (en) Core substrate, manufacturing method thereof, and structure for metal via
KR101489798B1 (en) Wiring board
JP5289880B2 (en) Wiring board
JP5715237B2 (en) Flexible multilayer board
WO2013061500A1 (en) Flexible wiring board and method for manufacturing same
JP4848676B2 (en) Component-embedded substrate, component-embedded module using the component-embedded substrate, and method of manufacturing the component-embedded substrate
TW201138582A (en) Substrate with built-in components, multilayer substrate using the same, and manufacturing method of substrate with built-in components
JP2009283788A (en) Method of manufacturing substrate with built-in chip
JP6999730B2 (en) Metal probe structure and its manufacturing method
JP5515210B2 (en) Component built-in wiring board, method of manufacturing component built-in wiring board
JP4654971B2 (en) Multilayer semiconductor device
JP2003283145A (en) Method of inspecting misregistration of multilayer wiring board

Legal Events

Date Code Title Description
A300 Withdrawal of application because of no request for examination

Free format text: JAPANESE INTERMEDIATE CODE: A300

Effective date: 20110802