JP2009283570A - Semiconductor device and manufacturing method therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To decide the presence or absence of an etching product, without having to directly observe it in a semiconductor device, and to provide a manufacturing method of the device. <P>SOLUTION: The manufacturing method of the semiconductor device is provided with: a process for forming a first conductive film 19; a ferroelectric film 20 and a second conductive film 21 above a silicon substrate 1; a process for patterning the second conductive film 21 and making it to be an upper electrode 21a; a process for patterning the ferroelectric film 20 and making it to be a capacitor dielectric film 20a; a process for etching the first conductive film 19 and making a lower electrode 19a, while a side of the resist pattern 30 is retreated with the resist pattern 30 as a mask; a process for measuring the width of a step face 21x becoming higher than the other region by reflecting the retreat of the resist pattern 30, in an upper face of the upper electrode 20a; and a process for deciding the presence or absence of the etching product stuck to a side of the capacitor dielectric film 20a, based on width C<SB>1</SB>of the step face 21x. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof.

  Flash memories and ferroelectric memories are known as nonvolatile memories that can store information even when the power is turned off.

  Among these, the flash memory has a floating gate embedded in a gate insulating film of an insulated gate field effect transistor (IGFET), and stores information by accumulating charges representing stored information in the floating gate. However, such a flash memory has a drawback that a tunnel current needs to flow through the gate insulating film when writing or erasing information, and a relatively high voltage is required.

  On the other hand, the ferroelectric memory is also called FeRAM (Ferroelectric Random Access Memory), and stores information using the hysteresis characteristic of the ferroelectric film provided in the ferroelectric capacitor. The ferroelectric film is polarized according to the voltage applied between the upper electrode and the lower electrode of the capacitor, and the spontaneous polarization remains even if the voltage is removed. When the polarity of the applied voltage is reversed, this spontaneous polarization is also reversed, and the direction of the spontaneous polarization is made to correspond to “1” and “0”, whereby information is written in the ferroelectric film. FeRAM has the advantage that the voltage required for the writing is lower than that in the flash memory and that writing can be performed at a higher speed than the flash memory.

  As a lower electrode and an upper electrode of a ferroelectric capacitor, a noble metal film or an oxide noble metal film is often used. This is because the orientation of the ferroelectric film is aligned by the action of the orientation of these films, and the ferroelectric properties of the ferroelectric film, such as the amount of residual polarization charge, can be enhanced.

  However, since the noble metal film and the oxidized noble metal film are poor in chemical reactivity, conductive etching products are generated when these films are dry-etched and patterned into electrode shapes. If the etching product adheres to the side surface of the capacitor dielectric film, a leak path between the upper electrode and the lower electrode is formed on the side surface, and the ferroelectric capacitor becomes defective.

  As a method for avoiding such an inconvenience, a method for preventing the adhesion of the etching product to the side surface by tilting the side surface of the ferroelectric capacitor in a tapered manner by patterning the electrode under an etching condition in which the resist pattern recedes. (Patent Document 1).

  In this method, when the etching conditions fluctuate, a predetermined taper shape cannot be obtained, and the risk of etching products adhering to the side surfaces of the capacitor increases. Therefore, it is required to control the etching conditions with high accuracy.

  However, even if it is attempted to control the etching conditions, if the calibration of measuring equipment such as a pressure gauge or mass flow meter attached to the etching apparatus is insufficient, the measured numerical value will deviate from the actual value, which is the target. Etching under etching conditions becomes difficult. In this case, if each measuring instrument is calibrated before etching, the stop time of the etching apparatus becomes long, and mass production of FeRAM becomes inefficient.

  In addition, even when the etching conditions are controlled near the upper or lower limit of the operation guarantee range of the measuring instrument, a divergence is likely to occur between the measured numerical value and the actual value. In order to avoid this, it is conceivable to replace the measuring instrument with a high-precision one, but there are cases where it cannot be replaced depending on the compatibility with the etching apparatus.

  Therefore, in this method, if the ferroelectric capacitor is not actually observed after the etching is finished, it cannot be confirmed that the etching product is not attached to the side surface.

In addition, the technique relevant to this application is also disclosed by patent documents 2-3.
Japanese Patent Laid-Open No. 2002-324852 JP-A-2005-77192 JP 2004-207611 A JP 2006-173579 A

  An object of the present invention is to determine the presence or absence of an etching product without directly observing the etching product in a semiconductor device and a manufacturing method thereof.

  According to one aspect of the following disclosure, a step of forming a first insulating film over a semiconductor substrate, a first conductive film, a ferroelectric film, and a second film on the first insulating film Sequentially forming the conductive film, patterning the second conductive film to form an upper electrode, patterning the ferroelectric film to form a capacitor dielectric film, Forming a resist pattern on the substrate, etching the first conductive film while retreating the side of the resist pattern using the resist pattern as a mask, and forming a lower electrode, and an upper surface of the upper electrode Measuring the width of the stepped surface that is higher than other regions reflecting the recession of the resist pattern, and the capacitor dielectric film during the etching based on the width of the stepped surface On the side of A step of determining the presence or absence of a deposited etching product, and covering the upper electrode, the capacitor dielectric film, and the lower electrode with a second insulating film when it is determined that the etching product is absent A method for manufacturing a semiconductor device.

  Since the width of the step surface formed on the upper electrode depends on process parameters such as a gas flow rate ratio when etching the first conductive film, the value of the process parameter can be estimated by measuring the width of the step surface. . Further, whether or not an etching product adheres to the side surface of the capacitor dielectric film during etching can be determined from a process parameter such as a gas flow rate ratio. Therefore, the presence or absence of an etching product can be determined from the value of the process parameter estimated based on the width of the step surface as described above.

  According to this, the presence or absence of the etching product can be determined without directly observing the side surface of the capacitor dielectric film, and the manufacturing process of the semiconductor device can be simplified.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

  1 to 24 are cross-sectional views of the semiconductor device according to the present embodiment during manufacture. Among these, FIGS. 1 to 14 are cross-sectional views in the direction orthogonal to the word line direction, and FIGS. 15 to 24 are cross-sectional views in the word line direction.

  25 to 28 are plan views of the semiconductor device in the middle of its manufacture.

  This semiconductor device is a planar-type FeRAM and is manufactured as follows.

  First, steps required until a sectional structure shown in FIG.

  First, an element isolation trench is formed in n-type or p-type silicon (semiconductor substrate) 1, and an insulating film such as a silicon oxide film is embedded therein as an element isolation insulating film 2. Such an element isolation structure is called STI (Shallow Trench Isolation). Alternatively, element isolation may be performed by LOCOS (Local Oxidation of Silicon).

  Next, a p-well 3 is formed in the memory cell region of the silicon substrate 1.

  Thereafter, the surface of the active region of the silicon substrate 1 is thermally oxidized to form a thermal oxide film that becomes the gate insulating film 4. Further, a polycrystalline silicon film is formed on the entire upper surface of the silicon substrate 1 and patterned to form the gate electrode 5. On one p-well 3 in the memory cell region, two gate electrodes 5 that are part of the word line are arranged substantially in parallel.

Subsequently, n-type impurity ions are implanted into the p-well 3 on both sides of the gate electrode 5 to form n-type source / drain extensions 6a and 6b. Then, after an insulating film is formed on the entire upper surface of the silicon substrate 1, the insulating film is etched back and left as an insulating sidewall 7 next to the gate electrode 5. As the insulating film, for example, a silicon oxide (SiO ₂ ) film is formed by a CVD method.

  Further, n-type impurities are ion-implanted again into the p-well 3 using the gate electrode 5 and the insulating sidewall 7 as a mask, so that the n-type source / drain regions are formed in the silicon substrate 1 next to the gate electrode 5. 8a and 8b are formed.

  The n-type source / drain region 8b sandwiched between the two gate electrodes 5 functions as a part of the bit line, and the two n-type source / drain regions 8a on both sides of the p-well 3 are the upper part of the capacitor described later. It is electrically connected to the electrode.

  Next, a refractory metal layer such as a cobalt layer is formed on the entire upper surface of the silicon substrate 1 by sputtering. Then, the refractory metal layer is annealed and reacted with silicon to form a refractory metal silicide layer 9 on the surface layer of the n-type source / drain regions 8a and 8b. Thereafter, the refractory metal layer that has not reacted on the element isolation insulating film 2 or the like is removed by wet etching.

  Through the steps so far, the basic structure of the n-type MOS transistor including the gate electrode 5 and the n-type source / drain regions 8a and 8b on the p-well 3 is completed.

  FIG. 25A is a plan view after this process is completed. In the figure, the insulating sidewall 7 and the refractory metal silicide layer 9 are omitted. Further, FIG. 1A corresponds to a cross-sectional view taken along line A1-A1 of FIG.

  Next, as shown in FIG. 1B, a cover insulating film 14 is formed on the entire upper surface of the silicon substrate 1 by the CVD method. The cover insulating film 14 is formed by laminating a silicon oxide film having a thickness of about 20 nm and a silicon nitride (SiN) film having a thickness of about 80 nm in this order from the bottom.

  Further, a silicon oxide film is formed on the cover insulating film 14 as the first interlayer insulating film 15 by the plasma CVD method using TEOS gas, and then the upper surface of the first interlayer insulating film 15 is formed by the CMP method. Polish and flatten. As a result of such polishing, the thickness of the first interlayer insulating film 15 is about 700 nm on the flat surface of the silicon substrate 1.

  Then, the cover insulating film 14 and the first interlayer insulating film 15 are patterned by photolithography and etching to form contact holes 12a and 12b in the n-type source / drain regions 8a and 8b.

  Subsequently, a glue film is formed by sputtering on the inner surfaces of the contact holes 12a and 12b and the upper surface of the first interlayer insulating film 15, and then a tungsten film is formed on the glue film by the CVD method. The contact holes 12a and 12b are completely embedded. As the glue film, for example, a titanium film having a thickness of about 30 nm and a titanium nitride film having a thickness of about 20 nm are formed in this order.

  Then, the excess glue film and the tungsten film on the first interlayer insulating film 15 are removed by polishing by the CMP method, and these films are removed only in the contact holes 12a and 12b by the first conductive plugs 13a, Leave as 13b.

  The diameters of the first conductive plugs 13a and 13b are not particularly limited. In this embodiment, the diameter is about 0.25 μm.

  Since the first conductive plugs 13a and 13b formed in this way are mainly composed of tungsten that is easily oxidized, they are easily oxidized in an oxygen-containing atmosphere and easily cause contact failure.

  Therefore, in the next step, as shown in FIG. 2A, an anti-oxidation insulating film 16 for preventing plug oxidation is formed on the first conductive plugs 13a and 13b and the first interlayer insulating film 15. A silicon oxynitride (SiON) film is formed to a thickness of 100 nm by the CVD method.

  Next, a silicon oxide film having a thickness of about 130 nm is formed as an insulating adhesion film 17 on the oxidation-preventing insulating film 16 by a CVD method.

  Further, an alumina film having a thickness of about 20 nm is formed on the insulating adhesive layer 17 by sputtering, and this is used as a base insulating film 18.

  Next, steps required until a sectional structure shown in FIG.

  First, a platinum film is formed as a first conductive film 19 on the base insulating film 18 by sputtering. The first conductive film 19 is later patterned to become a capacitor lower electrode, and the film thickness is about 150 nm.

The first conductive film 19 is not limited to a platinum film. Instead of platinum, a noble metal such as iridium or a noble metal such as platinum oxide or iridium oxide (IrO ₂ ) may be used as the material of the first conductive film 19.

Further, a PZT (Lead Zirconate Titanate: PbZrTiO ₃ ) film having a thickness of about 140 nm is formed on the first conductive film 19 by sputtering, and this PZT film is used as the ferroelectric film 20.

  In addition to the sputtering method, the ferroelectric film 20 may be formed by a MOCVD (Metal Organic CVD) method or a sol-gel method.

The material of the ferroelectric film 20 is not limited to PZT. The materials include Bi-layered structural compounds such as SrBi ₂ Ta ₂ O ₉ , SrBi ₂ (Ta _x Nb _1-x ) ₂ O ₉ , Bi ₄ Ti ₂ O ₁₂ , and PLZT (Pb _{1 -x} La _x Zr _1-y Ti _y O ₃ ), or other metal oxide ferroelectrics may be employed.

  Here, the PZT formed by the sputtering method is hardly crystallized immediately after the film formation and has poor ferroelectric characteristics. Therefore, RTA (Rapid Thermal Anneal) with a substrate temperature of about 585 ° C. in an oxygen-containing atmosphere is performed for about 90 seconds as crystallization annealing for crystallizing PZT of the ferroelectric film 20. It should be noted that this crystallization annealing is not necessary when the ferroelectric film 20 is formed by the MOCVD method.

  In addition, since the first conductive film 19 is formed on the base insulating film 18 as described above, the orientation of platinum in the first conductive film 19 is better than when the base insulating film 18 is omitted. It has become. Then, by the action of the orientation of the first conductive film 19, the orientation of PZT in the ferroelectric film 20 is made uniform, and the ferroelectric characteristics of the ferroelectric film 20 are improved.

  Further, an iridium oxide film having a thickness of about 250 nm is formed on the ferroelectric film 20 by sputtering, and this iridium oxide film is used as the second conductive film 21.

  The second conductive film 21 is not limited to an iridium oxide film, and a noble metal oxide film such as ruthenium, rhodium, osmium, rhenium, and palladium may be formed as the second conductive film 21.

  Subsequently, as shown in FIGS. 3A and 15A, a titanium nitride film having a thickness of about 20 nm is formed on the second conductive film 21 as a mask material film 22 by sputtering. The mask material film 22 is not particularly limited as long as it has a lower etch rate than the resist. For example, a titanium aluminum nitride (TiNAl) film may be formed as the mask material film 22 instead of the titanium nitride film.

  Further, a photoresist is applied on the mask material film 22, and is exposed and developed to form a first resist pattern 23 having a capacitor upper electrode shape.

  Then, as shown in FIGS. 3B and 15B, the mask material film 22 is dry-etched using the first resist pattern 23 as a mask to form an upper electrode-shaped hard mask 22a. This dry etching is performed using an ICP (Inductively Coupled Plasma) etching apparatus, and a mixed gas of chlorine gas and argon gas is used as an etching gas.

  Next, as shown in FIGS. 4A and 16A, the above-described ICP etching apparatus is continuously used to form the second conductive film 21a using the hard mask 22a and the first resist pattern 23 as a mask. The upper electrode 21a is formed by dry etching.

  Although the etching gas in this dry etching is not particularly limited, in this embodiment, a mixed gas of chlorine and argon is used.

  The first resist pattern 23 exposed to such an etching atmosphere is damaged and its side surface recedes, but since the upper surface of the upper electrode 21a is protected by the hard mask 22a, the upper surface of the upper electrode 21a is etched. Never reach.

  FIG. 25B is a plan view after this process is completed. FIG. 4A corresponds to a cross-sectional view taken along line A2-A2 of FIG. FIG. 16A corresponds to a cross-sectional view taken along line B1-B1 of FIG.

Thereafter, the silicon substrate 1 is immersed in an etching solution made of a mixed solution of hydrogen peroxide (H ₂ O ₂ ) and ammonium hydroxide (NH ₄ OH) to remove the hard mask 22a by wet etching. .

  Subsequently, as shown in FIGS. 4B and 16B, a photoresist is applied to the entire upper surface of the silicon substrate 1, exposed and developed, and a second resist is formed on the upper electrode 21a. A pattern 27 is formed.

  FIG. 26A is a plan view after this process is completed. Note that FIG. 4B corresponds to a cross-sectional view taken along line A3-A3 in FIG. FIG. 16B corresponds to a cross-sectional view taken along line B2-B2 of FIG.

  As shown in FIG. 26A, the planar shape of the second resist pattern 27 is a stripe shape extending in the word line direction, that is, the extending direction of the gate electrode 5, and each of the upper electrodes 21a has its first shape. 2 resist patterns 27.

  Next, as shown in FIGS. 5A and 17A, the ferroelectric film 20 is dry-etched using the second resist pattern 27 as a mask to form a capacitor dielectric film 20a. Similarly to the etching of the second conductive film 21 (FIG. 4A), this dry etching is also performed using an ICP etching apparatus, and a mixed gas of chlorine and argon is used as the etching gas.

  Thereafter, the second resist pattern 27 is removed.

  FIG. 26B is a plan view after removing the second resist pattern 27, and FIG. 5A corresponds to a cross-sectional view taken along line A4-A4 of FIG. FIG. 17A corresponds to a cross-sectional view taken along line B3-B3 of FIG.

  As shown in FIG. 26B, the capacitor dielectric film 20a has a striped planar shape common to the plurality of island-shaped upper electrodes 21a.

  Here, when the ferroelectric film 20 is patterned to form the ferroelectric film 20a, the ferroelectric film 20a may be damaged and its ferroelectric characteristics may be deteriorated. The damage is recovered by annealing in an oxygen atmosphere. Such annealing is also called recovery annealing, and is performed, for example, under a substrate temperature of 650 ° C.

  Subsequently, as shown in FIGS. 5B and 17B, the first hydrogen barrier insulating film 28 is sputtered on the first conductive film 19, the capacitor dielectric film 20a, and the upper electrode 21a. An alumina film is formed to a thickness of about 50 nm by the method.

  The first hydrogen barrier insulating film 28 is formed to protect the capacitor dielectric film 20a, which is easily reduced, from a reducing substance such as hydrogen, and includes any of a PZT film, a PLZT film, and a titanium oxide film in addition to an alumina film. It may be.

  Next, as shown in FIGS. 6A and 18A, a photoresist is applied on the first hydrogen barrier insulating film 28, and is exposed and developed to form the third resist pattern 30. To do.

  FIG. 27A is a plan view after this process is completed. 6A corresponds to a cross-sectional view taken along the line A5-A5 in FIG. 27A, and FIG. 18A corresponds to a cross-sectional view taken along the line B4-B4 in FIG. To do.

  As shown in FIG. 27A, the planar shape of the third resist pattern 30 is a stripe shape covering the capacitor dielectric film 20a.

  Next, steps required until a sectional structure shown in FIGS. 6B and 18B is obtained will be described.

  FIG. 29 is a configuration diagram of the ICP etching apparatus 100 used in this process.

In this ICP etching apparatus 100, the side wall 102 of the chamber 106 is made of quartz (SiO ₂ ), and an antenna coil 103 for generating plasma in the chamber 106 is wound around the side wall 102. The antenna coil 103 is connected to a first high frequency power source 104 having a frequency of 13.56 MHz, for example.

  On the other hand, a substrate mounting table 101 for mounting the silicon substrate 1 is provided below the chamber 106, and a second high-frequency power source 105 for bias that attracts ion species in the chamber 106 to the silicon substrate 1 side is provided on the substrate. It is connected to the mounting table 101 at a high frequency. The frequency of the second high-frequency power source 105 is not particularly limited, but is 460 kHz in this embodiment.

  Further, the chamber 106 is provided with a gas inlet 106a for introducing an etching gas and a gas outlet 106b for exhausting the gas to reduce the pressure inside the chamber 106 to a predetermined pressure.

  In the steps of FIGS. 6B and 18B, using such an ICP etching apparatus 100, a two-step dry etching is performed as follows while using a mixed gas of chlorine and argon as an etching gas. .

  In the first first step, the third resist pattern 30 is used as a mask, and dry etching is performed to a depth in the middle of the first conductive film 19. In the initial stage of this step, the portion of the first hydrogen barrier insulating film 28 that is not covered with the third resist pattern 30 is also etched.

The flow ratio of chlorine and argon in this step is set to 45:55 (= Cl ₂ : Ar), the power of the first high-frequency power source 104 is 1800 W, and the power of the second high-frequency power source 105 is 1000 W. The substrate temperature is 25 ° C. and the pressure in the chamber 106 is 0.9 Pa.

  Under such etching conditions, the etching proceeds in the lateral direction of the substrate, so that the conductive etching product derived from the first conductive film 19 is difficult to adhere to the side surface of the capacitor dielectric film 21a. The side surfaces of the third resist pattern 30 are set back.

  In the next second step, the etching conditions are changed so that the etching selectivity between the third resist pattern 30 and the first conductive film 19 is lower than that in the first step. 19 etching is completed.

  The etching selectivity can be controlled by a process parameter such as a flow rate ratio between chlorine gas and argon gas, the power of the first high-frequency power source 104, the power of the second high-frequency power source 105, the pressure in the chamber 106, and the substrate temperature. .

For example, by increasing the chlorine flow rate in the etching gas as compared with the first step, the etching selectivity between the third resist pattern 30 and the first conductive film 19 is lower than that in the first step. In this embodiment, the flow ratio of chlorine and argon is 60:40 (= Cl ₂ : Ar).

  By adopting such conditions, the receding of the side surface of the third resist pattern 30 is further accelerated than in the first step, so that the adhesion of etching products to the side surface of the capacitor dielectric film 20a is further suppressed. The

  Etching is performed while preventing the size of the lower electrode 19a from becoming smaller than the design value due to excessive inclination of the side surface of the lower electrode 19a by performing etching in a plurality of steps while changing the selection ratio in this way. Can be suppressed.

  If priority is given to the dimensional accuracy of the lower electrode 19a, the first conductive film 19 may be etched only in the first step. If priority is given to the suppression of etching products, the first conductive film 19 may be etched only in the second step.

  Regardless of whether or not the etching is performed in a plurality of times, the side surface of the third resist pattern 30 recedes as described above. Therefore, in the middle of etching, the upper electrode 21a on the side of the third resist pattern 30 and the first hydrogen barrier insulating film 28 are exposed and etched.

  Thereby, as shown in the dotted circle in FIG. 6B, the upper surface of the upper electrode 21a has a stepped surface 21x that is higher than the other regions reflecting the recession of the third resist pattern 30. A stepped portion 21y is formed.

  Through the steps so far, a ferroelectric capacitor Q formed by sequentially laminating the lower electrode 19a, the capacitor dielectric film 20a, and the upper electrode 21a is formed.

  Thereafter, the third resist pattern 30 is removed.

  FIG. 27B is a plan view after the third resist pattern 30 is removed in this manner. 6B corresponds to a cross-sectional view taken along line A6-A6 in FIG. 27B, and FIG. 18B corresponds to a cross-sectional view taken along line B5-B5 in FIG. To do.

  As shown in FIG. 27B, the stepped portion 21y is formed along a virtual straight line L common to the plurality of upper electrodes 21a, reflecting the side surface of the receding third resist 30. .

  Next, as shown in FIGS. 7 and 19, an alumina film having a thickness of about 20 nm is used as the silicon substrate 1 as a second hydrogen barrier insulating film 32 that protects the capacitor dielectric film 20 a from a reducing substance such as hydrogen. Is formed on the entire upper surface of the substrate by sputtering. Note that any of a PZT film, a PLZT film, and a titanium oxide film may be formed instead of the alumina film.

  Since the side surface of the capacitor Q is tapered, the second hydrogen barrier insulating film 32 is formed on the side surface with good coverage. Therefore, it is difficult to form a locally thin portion in the second hydrogen barrier insulating film 32 on the side surface of the capacitor Q, and the hydrogen blocking property on the side surface can be maintained.

  Then, a silicon oxide film is formed as a second interlayer insulating film 33 on the second hydrogen barrier insulating film 32 by the CVD method, and then the surface is polished and planarized by the CMP method.

After the CMP is completed, annealing for dehydrating the second interlayer insulating film 33 may be performed. Such dehydration annealing is performed, for example, in an N ₂ O plasma atmosphere.

  Further, an alumina film having a thickness of about 50 nm is formed on the second interlayer insulating film 33 by sputtering, and the alumina film is used as the third hydrogen barrier insulating film 34. Similar to the first and second hydrogen barrier insulating films 28 and 32, the third hydrogen barrier insulating film 34 serves to protect the capacitor dielectric film 20a from reducing substances such as hydrogen. Examples of the film having such a function include an alumina film, a PZT film, a PLZT film, and a titanium oxide film.

  Then, a silicon oxide film is formed on the third hydrogen barrier insulating film 34 to a thickness of about 300 nm by the CVD method, and the silicon oxide film is used as a cap insulating film 35.

  Next, as shown in FIGS. 8 and 20, a photoresist is applied on the cap insulating film 35, and is exposed and developed to form a fourth resist pattern 36.

Then, by performing dry etching through the window 36a of the fourth resist pattern 36, the first holes 33a are formed in the insulating films 28 and 32-35 on the upper electrode 21a. This dry etching is performed by, for example, a parallel plate plasma etching apparatus using a mixed gas of C ₄ F ₈ , Ar, O ₂ , and CO as an etching gas.

  Further, as shown in FIG. 20, the second holes 33b are formed in the insulating films 28 and 32-35 on the contact region CR of the lower electrode 19a by this etching.

  Thereafter, the fourth resist pattern 36 is removed.

  Next, as shown in FIGS. 9 and 21, recovery annealing is performed in an oxygen-containing atmosphere in order to recover the damage received by the capacitor dielectric film 20a in the steps so far.

  At this time, the first conductive plugs 13 a and 13 b are prevented from being oxidized by the oxidation preventing insulating film 16.

  Next, as shown in FIGS. 10 and 22, a photoresist is applied to the entire upper surface of the silicon substrate 1, and is exposed and developed to form a fifth resist pattern 39.

  Then, dry etching is performed through a window 39a provided in the fifth resist pattern 39, and third holes 33c are formed in the insulating films 17, 32 to 35 above the first conductive plug 13a.

This dry etching is performed by a parallel plate plasma etching apparatus using a mixed gas of C ₄ F ₈ , Ar, O ₂ , and CO as an etching gas, and the oxidation-preventing insulating film 16 made of silicon oxynitride serves as a stopper in this etching. Become.

  Thereafter, the fifth resist pattern 39 is removed.

Subsequently, as shown in FIGS. 11 and 23, the anti-oxidation insulating film 16 under the third hole 33c is formed in a parallel plate etching apparatus using a mixed gas of CHF ₃ , Ar, and O ₂ as an etching gas. Etch.

  As a result, the first conductive plugs 13a and 13b are exposed in the third hole 33c, and the foreign matters in the first and second holes 33a and 33b are removed, and exposed from the holes 33a and 33b. The upper surfaces of the upper electrode 21a and the lower electrode 19a to be cleaned are cleaned.

  Next, steps required until a sectional structure shown in FIGS.

  First, a titanium nitride film as a glue film is formed on the inner surfaces of the first to third holes 33a to 33c and the upper surface of the cap insulating film 35 by a sputtering method to a thickness of about 100 nm. Then, a tungsten film is formed on the glue film by a CVD method, and each of the holes 33a to 33c is completely filled with this tungsten film. Thereafter, excess glue film and tungsten film on the cap insulating film 35 are removed by polishing by the CMP method, and these films are left as the second conductive plugs 37 only in the holes 33a to 33c.

  FIG. 28 is a plan view after this process is completed. 12 corresponds to a cross-sectional view taken along line A7-A7 in FIG. 28, and FIG. 24 corresponds to a cross-sectional view taken along line B6-B6 in FIG.

  Next, as shown in FIG. 13, a metal laminated film is formed on the upper surfaces of the cap insulating film 35 and the second conductive plug 37 by sputtering, and is patterned to form a first-layer metal wiring 40.

  In this patterning, overetching is performed so that no etching residue of the metal laminated film remains on the cap insulating film 35. Even if over-etching is performed in this way, the third hydrogen barrier insulating film 34 is protected by the cap insulating film 35. Therefore, the third hydrogen barrier insulating film 34 is not etched, and the third hydrogen barrier insulating film 34 is not etched. The film thickness and hydrogen barrier property of the film 34 can be maintained.

  Examples of the metal laminated film include a titanium film having a thickness of about 60 nm, a titanium nitride film having a thickness of about 30 nm, a copper-containing aluminum film having a thickness of about 360 nm, a titanium film having a thickness of about 5 nm, and a thickness of about 70 nm. These titanium nitride films are formed in this order.

  In addition, a silicon oxynitride film may be formed as an antireflection film on the metal laminated film before patterning.

  Thereafter, as shown in FIG. 14, a plurality of metal wirings and interlayer insulating films are laminated to obtain a multilayer wiring structure.

  In this example, a plurality of second to fifth metal wirings 41 to 44 and third to sixth interlayer insulating films 45 to 48 are alternately stacked. Among these, the metal wirings 41 to 44 are obtained by patterning a metal laminated film including an aluminum film, similarly to the first-layer metal wiring 40. Further, as the third to sixth interlayer insulating films 45 to 48, silicon oxide films can be formed by, for example, a CVD method.

  A first passivation film 49 made of silicon oxide and a second passivation film 50 made of silicon nitride having an excellent water blocking property are formed on the uppermost fifth-layer metal wiring 44 by a CVD method. Laminated sequentially.

  Thus, the basic structure of the semiconductor device according to this embodiment is completed.

  In this method of manufacturing a semiconductor device, as described with reference to FIG. 6B, the first conductive film 19 is etched using etching conditions such that the side surfaces of the third resist pattern 30 are retreated, A lower electrode 19a was formed.

  As described above, it is possible to suppress the conductive etching product derived from the first conductive film 19 from adhering to the side surface of the capacitor dielectric film 20a by employing the condition that the resist recedes as described above. . Thereby, it is difficult to electrically short-circuit the upper electrode 21a and the lower electrode 19a by the etching product on the side surface of the capacitor dielectric film 20a, and it is possible to prevent the ferroelectric capacitor Q from being defective.

FIGS. 30A to 30C are diagrams drawn on the basis of SEM (Scanning Electron Microscope) images of the ferroelectric capacitor Q samples. In each sample, when etching the first conductive film 19 in two steps as described above, the flow rate ratio of chlorine in the etching gas in the first step (= 100 × Cl ₂ flow rate / (Cl ₂ flow rate + Ar flow)) is changed.

  As shown in FIG. 30A, when the chlorine flow rate in the etching gas is 35%, the etching product 90 adheres to the side surface of the capacitor dielectric film 20a in a fence shape. This is because the etching selectivity between the third resist pattern 30 (see FIG. 6B) and the first conductive film 19 is larger than in the other two cases, and the retreat amount of the third resist pattern 30 is insufficient. It is assumed that the etching is not sufficiently performed on the side surface of the capacitor dielectric film 20a.

  On the other hand, as shown in FIGS. 30B and 30C, when the chlorine flow rate in the etching gas is 45% and 55%, the etching product 90 as described above is not generated.

  According to the investigation of the present inventor, the etching product 90 starts to appear when the chlorine flow rate falls below about 37%. Therefore, in order to suppress the generation of the etching product 90, it is effective to control the chlorine flow rate to 37% or more.

  However, another investigation conducted by the inventor of the present application revealed that ferroelectric characteristics such as the switching charge amount Qsw of the capacitor dielectric film 20a deteriorate if the chlorine flow rate in the etching gas is too large. . This is because if the chlorine flow rate is too large, the third resist pattern 30 recedes excessively, increasing the amount of etching of the side surface of the capacitor dielectric film 20a, and reducing the planar size of the capacitor dielectric film 20a. Presumed to be the cause.

  Such deterioration of the ferroelectric characteristics becomes remarkable when the chlorine flow rate in the etching gas exceeds 52%.

  Therefore, by controlling the chlorine flow rate ratio in the range of 37% to 52%, it is possible to suppress the generation of etching products while maintaining the ferroelectric characteristics of the capacitor dielectric film 20a.

  However, if the accuracy of the chlorine mass flow meter provided in the ICP etching apparatus 100 (see FIG. 29) is insufficient, even if the chlorine gas is controlled within the above range, the range is actually within that range. May fall off. For example, when the flow rate is to be controlled near the upper limit of the operation guarantee range of the analog mass flow meter, the flow rate error is about ± 5%. Accordingly, when the errors of the chlorine mass flow meter and the argon mass flow meter are combined, it becomes about ± 10%, and it is difficult to accurately control the chlorine flow rate ratio.

  Whether or not the chlorine flow ratio can be controlled is difficult to grasp during the manufacturing of the semiconductor device, and may be clarified only by discovering the etching product by visual observation after the completion of the semiconductor device. However, this makes it impossible to find defects in the semiconductor device until completion, which is extremely inefficient.

Therefore, in the present embodiment, as a guide for determining whether or not the chlorine flow rate is controlled within the above range, the width c _{1 of} the step surface 21x (see FIG. 6B) formed on the upper surface of the upper electrode 21a. Is used as follows.

FIG. 31 shows the chlorine flow rate ratio (= 100 × Cl ₂ flow rate / (Cl ₂ flow rate + Ar flow rate)) when etching the first conductive film 19 with a mixed gas of chlorine and argon, and the ferroelectric capacitor Q. each width g of, b, is a graph obtained by investigating the relationship between c _1.

  The horizontal axis of this graph represents the chlorine flow rate ratio in the first step when the first conductive film 19 is etched in two steps. The chlorine flow ratio in the second step is fixed in this study.

The expression on the right side of each graph represents an approximate expression of each graph. The coefficient R ² below the approximate expression is called a determination coefficient of the approximate expression, and the closer this value is to 1, the higher the accuracy of the approximation.

Furthermore, as shown in the lower cross-sectional view and the plan view of the same drawing, g of each width indicates the width of the lower surface of the lower electrode 19a. Further, b is the width of the lower surface of the upper electrode 21a, c ₁ denotes the width of the step surface 21x formed on the upper electrode 21a.

  As described above, in order to suppress the generation of etching products while maintaining the ferroelectric characteristics of the capacitor dielectric film 20a, it is preferable to control the chlorine flow rate ratio in the range of 37% to 52%. In FIG. 31, such a range is shown as an allowable range ΔG for the chlorine flow rate ratio.

Further, as shown in FIG. 31, the widths g, b, and c ₁ are reduced as the chlorine flow rate ratio is increased.

  This is because when the chlorine flow rate ratio increases, the etching selection ratio between the third resist pattern 30 and the first conductive film 19 decreases, the amount of receding of the side surface of the third resist pattern 30 increases, and the capacitor Q This is presumably because the etching amount on the side surface increases.

Further, the widths g, b, and c ₁ depend almost linearly on the chlorine flow rate ratio, and the widths g, b, and c ₁ and the chlorine flow rate ratio generally correspond one to one. Therefore, by the width g, b, a c ₁ to measure, so that it is possible to estimate the value of the approximate chlorine flow rate.

For example, an allowable width ΔZ of the width c ₁ corresponding to the allowable range ΔG of the chlorine flow ratio is obtained, and if the measured value of the width c ₁ is within the allowable width ΔZ, the chlorine flow ratio is also within the allowable range ΔG. Can be estimated.

However, that's gentle slope of the graph, the width g, b, caused large error in the estimated value of the chlorine flow rate by the measurement error of c _1, the estimation accuracy is deteriorated.

Therefore, the width g, b, the absolute value of the slope of the graph of c ₁ measures the width c ₁ of the largest stepped surface 21x, based on the measurement values, other widths g, than when using the b It is preferable to estimate the chlorine flow ratio with high accuracy.

  As described above, the horizontal axis of FIG. 31 shows the chlorine flow rate ratio in the first step when the first conductive film 19 is etched in two steps. Therefore, the chlorine flow rate ratio estimated as described above is a value in the first step.

  In the etching in the second step, as described above, the etching selectivity between the third resist pattern 30 and the first conductive film 19 is made lower than that in the first step, and the recession of the third resist pattern 30 is accelerated. Therefore, etching products are hardly generated in the first place. Therefore, it is the first step rather than the second step that requires high-precision control of the chlorine flow rate ratio in order to suppress the generation of etching products.

  However, if it is required to control the chlorine flow rate ratio with high accuracy even in the second step, the same investigation as in FIG. 31 is performed for the chlorine flow rate ratio in the second step, and the chlorine flow rate ratio is estimated in the same manner as described above. May be. The same applies to the case where the first conductive film 19 is etched by only a single step.

By the way, the chlorine flow rate ratio may be estimated from only the width c ₁ as described above, or may be estimated by combining the width c ₁ and other widths.

For example, the width c ₀ of the upper surface of the upper electrode 21a (see FIG. 4A) and the width c ₁ of the step surface 21x are combined, and the chlorine flow ratio is estimated using the difference (c ₀ −c ₁ ). May be performed.

FIG. 32 is a graph schematically showing the relationship between the chlorine flow rate ratio and the difference (c ₀ −c ₁ ).

Also in this case, as in FIG. 31, an allowable width ΔZ of the difference (c ₀ −c ₁ ) corresponding to the allowable range ΔG of the chlorine flow rate ratio is obtained, and the measured value of the difference (c ₀ −c ₁ ) If it falls within the width ΔZ, it can be estimated that the chlorine flow rate ratio is also within the allowable range ΔG.

In particular, the difference (c ₀ −c ₁ ) is an amount corresponding to the retraction amount of the third resist pattern 30 on the upper electrode 21a, and is an amount that does not depend on the design dimension of the upper electrode 21a. Therefore, the graph of FIG. 32 shows almost the same tendency even in the types having different design dimensions of the upper electrode 21a. Therefore, the chlorine flow rate ratio can be estimated for all types by using FIG.

  The estimation method will be described in detail below.

  33 to 35 are flowcharts showing the method of manufacturing the semiconductor device according to this embodiment.

  As shown in FIG. 33, in the first step S1, the first resist pattern 23 described in FIG. 3A is formed.

  Next, the process proceeds to step S2, and the width a (see FIG. 3A) of the lower surface of the first resist pattern 23 is automatically measured using a line width measuring device such as a CD-SEM device.

  If the width a is outside the allowable range in design, the width of the upper electrode 21a formed by etching using the first resist pattern 23 as a mask deviates from the design value.

  Therefore, in the next step S3, it is determined whether or not the width a is within the allowable range in design.

  If it is determined that the value is not within the allowable range (NO), the process proceeds to step S9, where the first resist pattern 23 is peeled off, and then the first resist pattern 23 is re-formed. Try again.

  On the other hand, if it is determined in step S3 that it is within the allowable range (YES), the process proceeds to step S4, where the second conductive film 21 described in FIG. 4A is dry-etched to form the upper electrode 21a. To do.

Subsequently, the procedure proceeds to step S5, measuring the width b of the lower surface of the upper electrode 21a as shown in FIG. Of FIG. 4 (a), and a width c ₀ of the upper surface of the upper electrode 21a. This measurement is automatically performed using a line width measuring device such as a CD-SEM device after removing the hard mask 21a.

Thus, by actually measuring the widths b and c ₀ , it is possible to grasp whether or not the upper electrode 21a is processed with a designed width.

  Next, the process proceeds to step S6, and the second resist pattern 27 described with reference to FIG.

  Then, the process proceeds to step S7, and the width d (see FIG. 4B) of the lower surface of the second resist pattern 27 is measured using a CD-SEM apparatus or the like.

  The second resist pattern 27 serves as an etching mask for the ferroelectric film 20. When the width of the second resist pattern 27 deviates from the allowable range in design, the capacitor dielectric obtained by etching the ferroelectric film 20 is used. The width of the film 20a deviates from the design value.

  Therefore, in the next step S7, it is determined whether or not the width d is within an allowable range that is permitted in design.

  If it is determined that the value is not within the allowable range (NO), the process proceeds to step S10, the second resist pattern 27 is peeled off, the second resist pattern 27 is formed again, and the process is repeated from step S7.

  On the other hand, if it is determined in step S7 that it is within the allowable range (YES), the process proceeds to step S11 in FIG.

  In step S11, as described with reference to FIG. 5A, the ferroelectric film 20 is dry-etched using the second resist pattern 27 as a mask to form a capacitor dielectric film 20a.

  Next, the process proceeds to step S12, and the width e (see FIG. 5A) of the lower surface of the capacitor dielectric film 20a is measured. The measurement is performed using, for example, a CD-SEM apparatus. Thus, by actually measuring the width e, it is possible to grasp whether or not the capacitor dielectric film 20a can be processed according to the design dimensions.

  Subsequently, the process proceeds to step S13, and the first hydrogen barrier insulating film 28 described with reference to FIG.

  Thereafter, the process proceeds to step S14, and the third resist pattern 30 as described with reference to FIG.

  In step S15, the width f of the lower surface of the third resist pattern 30 is automatically measured using a CD-SEM apparatus or the like.

  The third resist pattern 30 is used as a mask for etching the first conductive film 19. Therefore, if the width of the third resist pattern 30 is deviated from the allowable range in design, the width of the lower electrode 19a obtained by etching the first conductive film 19 is deviated from the design value.

  In order to avoid such an inconvenience, in the next step S16, it is determined whether or not the width f of the lower surface of the third resist pattern 30 measured above is within a design allowable range.

  And when it is judged that it is not in an allowable range (NO), it moves to step S20 and the 3rd resist pattern 30 is peeled. Then, after forming the third resist pattern 30 again, the process is repeated from step S15.

  On the other hand, if it is determined in step S16 that it is within the allowable range (YES), the process proceeds to step S17.

  In step S17, as described with reference to FIG. 6B, the first conductive film 19 is dry-etched using the third resist pattern 30 as a mask to form the lower electrode 19a.

  In this dry etching, since the side surface of the third resist pattern 30 has receded, the step surface 21x (see FIG. 6B) as described above is formed on the upper surface of the upper electrode 21a.

As described with reference to FIGS. 31 and 32, the width c ₁ of the stepped surface 21x can be used to estimate the chlorine flow ratio in the etching gas used in this dry etching.

In the next step S18, the width g (FIG. 6 (b) refer) width c ₁ and the lower electrode 19a of the stepped surface 21x and automatically measured by the length measuring device such as a CD-SEM.

Next, the process proceeds to step S19, and the difference (c ₀ −c ₁ ) between the width c ₀ of the upper surface of the upper electrode 21a measured in step S5 and the width c ₁ of the step surface 21x measured in step S18 is calculated.

Then, the process proceeds to the next step S21 in FIG. 35, and it is determined whether or not the difference (c ₀ −c ₁ ) is within the allowable range ΔZ in FIG.

  Here, when it is determined that it is within the allowable range ΔZ (YES), it is estimated that the chlorine flow rate ratio is within the allowable range ΔG (see FIG. 32). In this case, it is presumed that the etching product does not adhere to the side surface of the capacitor Q, and the capacitor dielectric film 20a is not deteriorated. Exit.

  On the other hand, if it is determined that it is not within the allowable range ΔZ (NO), it is estimated that the chlorine flow ratio is out of the allowable range ΔG (see FIG. 32). There is a possibility that an object is attached to the fence.

  Therefore, in this case, the process proceeds to step S22, and the presence or absence of the fence is confirmed by actually observing the capacitor Q with an SEM or the like.

  If it is determined that there is no etching product (NO), the capacitor Q is not likely to be defective, and the formation of the capacitor Q is terminated.

  On the other hand, if it is determined that there is an etching product (YES), the etching product once attached cannot be removed. Therefore, the process proceeds to step S23, and one lot (25 sheets) of silicon to which the capacitor Q belongs. The substrate 1 is discarded.

  Then, after moving to step S24, the operation of the ICP etching apparatus 100 (see FIG. 29) is stopped, and then the state of the etching apparatus 100 is confirmed in step S25. In this step, for example, confirmation work such as whether the mass flow meter for measuring the chlorine flow rate is correctly calibrated is performed.

  As described above, the basic steps in the present embodiment are completed.

As described above, in the present embodiment, the fact that the width c ₁ of the stepped surface 21x of the upper electrode 21a depends on the chlorine flow ratio during the etching of the first conductive film 19 is used, so the capacitor Q is actually observed. Even if it is not, it can be judged whether there exists an etching product in the side surface. Therefore, only when it is determined that there is an etching product, the capacitor Q may be observed for confirmation, and the manufacturing process can be simplified. Further, when it is determined that there is an etching product, it is possible to prevent the etching product from occurring in the subsequent product lot by stopping the operation of the etching apparatus.

In particular, as shown in FIG. 31, the width c ₁ of the step surface 21x is more sensitive to fluctuations in the chlorine flow rate than the other widths g and b. Therefore, the difference (c ₀ −c ₁ ) also reacts sensitively to fluctuations in the chlorine flow rate, so it is possible to accurately estimate whether the chlorine flow rate is within the allowable range by using the difference (c ₀ −c ₁ ). it can.

  On the other hand, in Patent Document 1, an amount corresponding to (b−g) / 2 is defined as “spread ΔW”, and the relationship between this “spread ΔW” and the chlorine flow rate ratio is disclosed. However, as described above, the widths g and b have a slow response to fluctuations in the chlorine flow rate ratio, so it is difficult to estimate the chlorine flow rate ratio with high accuracy as in this embodiment by using “spread ΔW”. It is.

  By the way, in the above description, attention is paid to the chlorine flow rate ratio among the etching conditions when the first conductive film 19 is etched. However, the receding amount of the third resist pattern 30 is not only the chlorine flow rate ratio but also the first and first flow rates. It also depends on process parameters such as the power of the two high frequency power supplies 104 and 105 (see FIG. 29), the pressure in the chamber 106, and the substrate temperature.

  Therefore, the presence or absence of an etching product can be determined in the same manner as described above by creating a similar graph of FIG. 31 for each of these process parameters.

  FIG. 36 is a diagram schematically showing such a graph.

The horizontal axis of FIG. 36 shows the power of the first and second high-frequency power supply 104 and 105, the pressure in the chamber 106, and any one of the process parameters P _E of the substrate temperature. On the other hand, the vertical axis indicates the width c ₁ of the step surface 21x as in FIG.

In this case, by performing an experiment in advance by changing the process parameter P _E in various ways, the process parameter P _E is allowed so that no etching product is generated and the switching charge amount of the capacitor dielectric film 20a is not reduced. The range ΔG is obtained in advance.

When the measured value of the width c ₁ falls within the range ΔZ corresponding to the allowable range ΔG according to the flowcharts of FIGS. 33 to 35 described above, no etching product is generated and the capacitor It can be determined that the switching charge amount of the dielectric film 20a has not decreased.

  As mentioned above, although embodiment of this invention was described in detail, this invention is not limited to the said embodiment. For example, in the above, the upper electrode 21a and the first-layer metal wiring 40 are electrically connected via the second conductive plug 37 in the step of FIG. 13, but the second conductive plug 37 is omitted. The first-layer metal wiring 40 may be directly buried in the first hole 33a.

  Further, instead of the wirings 40 to 44 including the aluminum film, copper wirings may be formed.

  The aspects of the present invention are summarized in the following supplementary notes.

(Additional remark 1) The process of forming a 1st insulating film above a semiconductor substrate,
Forming a first conductive film, a ferroelectric film, and a second conductive film on the first insulating film in order;
Patterning the second conductive film to form an upper electrode;
Patterning the ferroelectric film into a capacitor dielectric film;
Forming a resist pattern on the upper electrode;
Etching the first conductive film while retreating the side of the resist pattern using the resist pattern as a mask, and forming a lower electrode;
Of the upper surface of the upper electrode, the step of measuring the width of the step surface that is higher than the other region reflecting the recession of the resist pattern,
Determining the presence or absence of an etching product attached to the side surface of the capacitor dielectric film during the etching based on the width of the step surface;
A step of covering the upper electrode, the capacitor dielectric film, and the lower electrode with a second insulating film when it is determined that the etching product is absent;
A method for manufacturing a semiconductor device, comprising:

(Appendix 2) Measuring the width of the upper electrode;
A step of obtaining a difference between the width of the upper electrode and the width of the step surface,
The method of manufacturing a semiconductor device according to appendix 1, wherein the presence or absence of the etching product is determined based on the difference.

  (Supplementary Note 3) In the determination of the presence or absence of the etching product, an allowable range of the difference for preventing the generation of the etching product is obtained in advance, and the etching generation is performed when the difference is out of the allowable range. The method for manufacturing a semiconductor device according to appendix 2, wherein it is determined that an object is generated.

  (Additional remark 4) As the said tolerance | permissible_range of the said difference, the range which does not generate | occur | produce the said etching product and does not degrade the ferroelectric characteristic of the said capacitor dielectric film is employ | adopted, The additional description 3 characterized by the above-mentioned. A method for manufacturing a semiconductor device.

  (Additional remark 5) The said width | variety of the said upper electrode is a width | variety of the upper surface of this upper electrode, The manufacturing method of the semiconductor device in any one of Additional remark 1-Additional remark 4 characterized by the above-mentioned.

  (Supplementary Note 6) The etching of the first conductive film is performed in a plurality of steps by changing an etching selection ratio between the resist pattern and the first conductive film. 6. A method for manufacturing a semiconductor device according to claim 5.

(Appendix 7) The etching of the first conductive film is performed in a plasma atmosphere containing chlorine and argon gas,
The etching selection ratio is changed by changing any one of a flow rate ratio of chlorine and argon gas, a pressure of the plasma atmosphere, a power of high-frequency power for generating the plasma, and a substrate temperature. The manufacturing method of the semiconductor device according to appendix 6.

  (Supplementary note 8) The semiconductor according to any one of supplementary notes 1 to 7, wherein a noble metal film or a noble metal oxide film is formed as at least one of the first conductive film and the second conductive film. Device manufacturing method.

(Appendix 9) a semiconductor substrate;
An insulating film formed above the semiconductor substrate;
A lower electrode, a capacitor dielectric film made of a ferroelectric material, and a ferroelectric capacitor provided with an upper electrode;
A semiconductor device, wherein a step portion is formed on an upper surface of the upper electrode.

(Supplementary Note 10) The lower electrode is formed in a stripe shape,
A plurality of the upper electrodes are formed above the lower electrode,
The semiconductor device according to appendix 9, wherein the stepped portion is formed along a virtual straight line common to the plurality of upper electrodes.

1A and 1B are cross-sectional views (part 1) in a direction orthogonal to the word line direction in the course of manufacturing the semiconductor device according to the present embodiment. 2A and 2B are cross-sectional views (No. 2) in a direction orthogonal to the word line direction in the course of manufacturing the semiconductor device according to the present embodiment. 3A and 3B are cross-sectional views (part 3) in the direction orthogonal to the word line direction during the manufacturing of the semiconductor device according to the present embodiment. 4A and 4B are cross-sectional views (part 4) in a direction orthogonal to the word line direction during the manufacture of the semiconductor device according to the present embodiment. 5A and 5B are cross-sectional views (No. 5) in a direction orthogonal to the word line direction in the course of manufacturing the semiconductor device according to the present embodiment. 6A and 6B are cross-sectional views (No. 6) in a direction orthogonal to the word line direction in the course of manufacturing the semiconductor device according to this embodiment. FIG. 7 is a cross-sectional view (No. 7) in the direction orthogonal to the word line direction during the manufacturing of the semiconductor device according to the present embodiment. FIG. 8 is a sectional view (No. 8) in the direction orthogonal to the word line direction in the course of manufacturing the semiconductor device according to the present embodiment. FIG. 9 is a sectional view (No. 9) in the direction orthogonal to the word line direction in the course of manufacturing the semiconductor device according to the present embodiment. FIG. 10 is a cross-sectional view (No. 10) in the direction orthogonal to the word line direction in the course of manufacturing the semiconductor device according to the present embodiment. FIG. 11 is a cross-sectional view (No. 11) in a direction orthogonal to the word line direction in the course of manufacturing the semiconductor device according to the present embodiment. FIG. 12 is a sectional view (No. 12) in a direction orthogonal to the word line direction in the course of manufacturing the semiconductor device according to the present embodiment. FIG. 13 is a cross-sectional view (No. 13) in the direction orthogonal to the word line direction in the course of manufacturing the semiconductor device according to this embodiment. FIG. 14 is a cross-sectional view (No. 14) in the direction orthogonal to the word line direction in the course of manufacturing the semiconductor device according to the present embodiment. 15A and 15B are cross-sectional views (part 1) in the word line direction during the manufacturing of the semiconductor device according to the embodiment. 16A and 16B are cross-sectional views (part 2) in the word line direction during the manufacturing of the semiconductor device according to this embodiment. 17A and 17B are cross-sectional views (part 3) in the word line direction during the manufacturing of the semiconductor device according to this embodiment. 18A and 18B are cross-sectional views (part 4) in the word line direction during the manufacturing of the semiconductor device according to this embodiment. FIG. 19 is a cross-sectional view (part 5) in the word line direction during the manufacturing of the semiconductor device according to the present embodiment. FIG. 20 is a cross-sectional view (No. 6) in the word line direction during the manufacturing of the semiconductor device according to the present embodiment. FIG. 21 is a sectional view (No. 7) in the word line direction during the manufacturing of the semiconductor device according to the embodiment. FIG. 22 is a cross-sectional view (No. 8) in the word line direction during the manufacturing of the semiconductor device according to the present embodiment. FIG. 23 is a sectional view (No. 9) in the word line direction during the manufacturing of the semiconductor device according to the embodiment. FIG. 24 is a cross-sectional view (No. 10) in the word line direction during the manufacturing of the semiconductor device according to the present embodiment. FIGS. 25A and 25B are plan views (part 1) in the course of manufacturing the semiconductor device according to the present embodiment. 26A and 26B are plan views (part 2) in the middle of manufacturing the semiconductor device according to the present embodiment. 27A and 27B are plan views (part 3) of the semiconductor device according to the present embodiment in the middle of manufacture. FIG. 28 is a plan view (part 4) of the semiconductor device according to the present embodiment during manufacturing. FIG. 29 is a configuration diagram of an ICP etching apparatus used in the embodiment of the present invention. 30A to 30C are diagrams drawn on the basis of SEM images of samples of the ferroelectric capacitor Q. FIG. FIG. 31 was obtained by investigating the relationship between the chlorine flow rate ratio when etching the first conductive film with a mixed gas of chlorine and argon and the respective widths g, b, and c ₁ of the ferroelectric capacitor. It is a graph. FIG. 32 is a graph schematically showing the relationship between the chlorine flow rate ratio and the difference (c ₀ −c ₁ ). FIG. 33 is a flowchart (No. 1) showing the method for manufacturing the semiconductor device according to the embodiment of the invention. FIG. 34 is a flowchart (No. 2) showing the method for manufacturing the semiconductor device according to the embodiment of the invention. FIG. 35 is a flowchart (No. 3) showing the method for manufacturing a semiconductor device according to the embodiment of the present invention. FIG. 36 is a graph showing the relationship between the process parameter when etching the first conductive film and the width of the step surface of the upper electrode.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Silicon substrate, 2 ... Element isolation insulating film, 3 ... p well, 4 ... gate insulating film, 5 ... gate electrode, 6a, 6b ... n-type source / drain extension, 7 ... insulating side wall, 8a, 8b ... n-type source / drain region, 9 ... refractory metal silicide layer, 12a, 12b ... contact hole, 13a, 13b ... first conductive plug, 14 ... cover insulating film, 15 ... first interlayer insulating film, 16 ... Antioxidation insulating film, 17 ... insulating adhesive film, 18 ... base insulating film, 19 ... first conductive film, 19a ... lower electrode, 20 ... ferroelectric film, 20a ... capacitor dielectric film, 21 ... second Conductive film, 21a ... upper electrode, 22 ... mask material film, 22a ... hard mask, 23 ... first resist pattern, 27 ... second resist pattern, 28 ... first hydrogen barrier insulating film, 30 ... third Les 32 ... second hydrogen barrier insulating film, 33 ... second interlayer insulating film, 33a-33c ... first to third holes, 34 ... third hydrogen barrier insulating film, 35 ... cap insulating film, 36 ... 4th resist pattern, 36a ... Window, 37 ... 2nd conductive plug, 39 ... 5th resist pattern, 39a ... Window, 40 ... 1st layer metal wiring, 41-44 ... 2nd layer-5th layer Eye metal wirings, 45 to 48, third to sixth interlayer insulating films, 49, first passivation film, and 50, second passivation film.

Claims (6)

Forming a first insulating film over the semiconductor substrate;
Forming a first conductive film, a ferroelectric film, and a second conductive film on the first insulating film in order;
Patterning the second conductive film to form an upper electrode;
Patterning the ferroelectric film into a capacitor dielectric film;
Forming a resist pattern on the upper electrode;
Etching the first conductive film while retreating the side of the resist pattern using the resist pattern as a mask, and forming a lower electrode;
Of the upper surface of the upper electrode, the step of measuring the width of the step surface that is higher than the other region reflecting the recession of the resist pattern,
Determining the presence or absence of an etching product attached to the side surface of the capacitor dielectric film during the etching based on the width of the step surface;
A step of covering the upper electrode, the capacitor dielectric film, and the lower electrode with a second insulating film when it is determined that the etching product is absent;
A method for manufacturing a semiconductor device, comprising: Measuring the width of the upper electrode;
A step of obtaining a difference between the width of the upper electrode and the width of the step surface,
The method of manufacturing a semiconductor device according to claim 1, wherein the presence or absence of the etching product is determined based on the difference.   In the determination of the presence or absence of the etching product, an allowable range of the difference for preventing the generation of the etching product is obtained in advance, and the etching product is generated when the difference is out of the allowable range. The method of manufacturing a semiconductor device according to claim 2, wherein the method is determined to be.   4. The semiconductor device according to claim 3, wherein the allowable range of the difference is a range that does not generate the etching product and does not deteriorate the ferroelectric characteristics of the capacitor dielectric film. Production method.   The etching of the first conductive film is performed in a plurality of steps by changing an etching selection ratio between the resist pattern and the first conductive film. A method for manufacturing a semiconductor device according to claim 1. A semiconductor substrate;
An insulating film formed above the semiconductor substrate;
A lower electrode, a capacitor dielectric film made of a ferroelectric material, and a ferroelectric capacitor provided with an upper electrode;
A semiconductor device, wherein a step portion is formed on an upper surface of the upper electrode.

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