JP2009282689A - Data processor and data processing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a data processor and a data processing method for more efficiently executing an algorithm by using a plurality of CPU. <P>SOLUTION: This data processor 1 includes first and second CPUs, and configured to preliminarily store the algorithm having a plurality of series of processing steps including a step of outputting at least an intermediate result, and to execute the processing step of the algorithm from the head by the first or second CPU on the basis of data to be continuously input, and to supply the intermediate result to the other CPU when the step of outputting the intermediate result is executed, and to execute a processing step after the step of outputting the intermediate result of the algorithm by the other CPU on the basis of the intermediate result when the intermediate result is supplied. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to, for example, a data processing apparatus and a data processing method for sequentially processing data input continuously.

  Conventionally, a data processing apparatus such as a paper sheet processing apparatus has been put into practical use, for example, information including feature amounts is acquired from an object by a sensor, and various processes are performed on the information acquired by the sensor to perform inspections. Has been.

  In the paper sheet processing apparatus, images of paper sheets that are continuously conveyed are sequentially captured to obtain an image of the paper sheets. The paper sheet processing apparatus performs a plurality of processes on an image acquired from a paper sheet based on a program stored in advance. The paper sheet processing apparatus determines the type of paper sheet or authenticity based on the processed image.

  A processing program used for processing an image as described above has a large amount of data as a whole. Therefore, the plurality of processing programs are stored in a memory provided outside the CPU that executes the processing. As a result, the CPU needs to read the processing program from the external memory to the internal RAM memory for each process and execute the process, which may take time.

Therefore, a sheet processing apparatus including a CPU that reads a plurality of processing programs stored in an external memory into the internal memory in units of processing programs, and a CPU that executes the processing programs stored in the internal memory of the CPU. Is provided (for example, refer to Patent Document 1).
JP 2006-29392 A

  As described above, when sequentially input data is sequentially processed, one CPU sequentially reads a plurality of processing programs stored in an external memory into the internal memory in units of processing programs, and the other CPU Execute the processing program. For this reason, an algorithm that is a set of processing programs is divided and stored in units of processing programs. Thus, dividing the algorithm results in a significant change in the program itself. As a result, there is a problem that an operation error occurs or time is spent on the operation check operation.

  Further, even when a plurality of processing programs stored in the shared memory are directly accessed from a plurality of CPUs, there is a problem that the processing becomes complicated due to arbitration control.

  Therefore, an object of the present invention is to provide a data processing apparatus and a data processing method that can execute an algorithm more efficiently using a plurality of CPUs.

  A data processing apparatus according to an embodiment of the present invention is a data processing apparatus having first and second CPUs, and stores in advance an algorithm having a plurality of processing steps including at least a step of outputting an intermediate result. Storage means, input means for continuously inputting data, and processing steps of the algorithm by any one of the first and second CPUs based on the data input by the input means. First processing means executed from the beginning, intermediate result supply means for supplying the intermediate result to the other CPU when the step of outputting the intermediate result is executed by the first processing means, and the intermediate result Is supplied, the processing step after the step of outputting the intermediate result of the algorithm by the other CPU based on the intermediate result is provided. Comprising a second processing means for performing up and.

  A data processing method according to an embodiment of the present invention is a data processing apparatus having first and second CPUs, and includes an algorithm having a plurality of processing steps including at least a step of outputting an intermediate result. A step of executing the processing step of the algorithm from the top by any one of the first and second CPUs based on the data stored in advance and continuously input, and outputting the intermediate result When executed, the intermediate result is supplied to the other CPU, and when the intermediate result is supplied, the processing step after the step of outputting the intermediate result of the algorithm by the other CPU based on the intermediate result is executed. To do.

  According to one aspect of the present invention, it is possible to provide a data processing apparatus and a data processing method that can execute an algorithm more efficiently using a plurality of CPUs.

Hereinafter, a data processing apparatus and a data processing method according to embodiments of the present invention will be described in detail with reference to the drawings.
FIG. 1 is a diagram schematically showing a configuration example of an image processing apparatus 1 according to the present embodiment.

  The image processing apparatus 1 is a data processing apparatus that captures an object, acquires an image, and performs various processes on the acquired image in a face authentication system used in a traffic control system, for example.

  The image processing apparatus 1 includes a camera 11 and an image processing board 12. The camera 11 includes an optical system such as a lens (not shown) for receiving light, and an imaging device that can convert the light received by the optical system into an electrical signal and acquire an image (signal). The camera 11 sequentially acquires images in time series and sequentially supplies the acquired images to the image processing board 12. That is, the camera 11 functions as an input means for continuously inputting data.

  The image processing board 12 is a unit that performs various processes on the image acquired by the camera 11. The image processing board 12 includes an image distributor 13, a CPU 14A, and a CPU 14B. The image distributor 13 sequentially outputs the images supplied from the camera 11 to the subsequent CPU.

The CPU 14 </ b> A and the CPU 14 </ b> B perform various processes on the image supplied from the camera 11. The CPU 14A and the CPU 14B respectively include a RAM 141A and a RAM 141B that function as a storage unit. The RAM 141A and RAM 141B function as working memory, and temporarily store data being processed by the CPU. The CPU 14A and the CPU 14B each include a ROM (not shown) that stores a control program, control data, and the like in advance. The processing results by the CPU 14A and CPU 14B are output to the host computer 20 connected to the image processing board 12.
Further, common management software and algorithms are stored in a nonvolatile memory (not shown) connected to the inside or outside of the image processing board 12.

The common management software has an image collection function by the camera 11, an information transmission / reception function to the algorithm, and the like. That is, the common management software includes a program that is controlled by the input / output device and a program that manages tasks executed by the CPU 14A and CPU 14B.
An algorithm is a set of processing programs. The algorithm includes a plurality of processing programs to be performed on input data input by the camera 11.
The CPU 14A and CPU 14B read the common management software and algorithm from the nonvolatile memory and store them in the internal RAM 141A and RAM 141B, respectively.

  FIG. 2 is an explanatory diagram for schematically explaining the processing of the CPU 14A and the CPU 14B when the common management software and the algorithm are stored in the RAM 141A and the RAM 141B. Here, it is assumed that the CPU 14A operates as a host and the CPU 14B operates as a slave.

  As shown in FIG. 2, the RAM 141A of the CPU 14A stores host common management software 16A and an algorithm 17. The RAM 141B of the CPU 14B stores slave common management software 16B and an algorithm 17.

  The CPU 14A executes various processes by executing the common management software 16A. For example, when the input data input by the camera 11 shown in FIG. 1 is received, the CPU 14A transmits a message including an instruction of the processing program to be executed to the task executing the algorithm 17. When an intermediate result is received from a task executing the algorithm 17, the CPU 14A transmits the received intermediate result to the CPU 14B. That is, the CPU 14A functions as an intermediate result supply unit that supplies an intermediate result to the CPU 14B.

  Further, the CPU 14A executes various processing programs by executing the algorithm 17. For example, when a message is received from a task executing the common management software 16A, the processing program is executed based on the content of the received message. In addition, a message including a processing result or an intermediate result is transmitted to the task executing the common management software 16A. That is, the CPU 14A functions as a processing unit that executes the processing steps of the algorithm from the top based on the input data.

  The CPU 14B executes various processes by executing the common management software 16B. For example, when the intermediate result is received from the CPU 14A, the CPU 14B transmits a message including an instruction of the processing program to be executed to the task executing the algorithm 17. When the processing result is received from the task executing the algorithm 17, the CPU 14B outputs the received processing result to the host computer 20 shown in FIG. 1 as output data.

  Further, the CPU 14B executes various processing programs by executing the algorithm 17. For example, when a message is received from a task executing the common management software 16B, the processing program is executed based on the content of the received message. In addition, a message including a processing result or an intermediate result is transmitted to the task executing the common management software 16B. That is, the CPU 14B functions as a processing unit that executes a processing step after the step of outputting the intermediate result based on the supplied intermediate result.

  The host computer 20 stores comparison data, and performs a verification process by matching the processing result output from the image processing board 12 with the stored comparison data. That is, the host computer 20 stores a face image as comparison data, and calculates the similarity between the image obtained by performing various processes on the face image acquired from the person to be authenticated and the stored image. To perform the authentication process.

  FIG. 3 is a flowchart for explaining a series of processing steps of the algorithm stored in the RAM 141A and the RAM 141B. Assume that each processing program (each processing step) of the algorithm used in the present embodiment performs processing in series. That is, each processing step performs processing using the processing result of the previous processing step.

  As shown in FIG. 2, the algorithm 17 is stored in each RAM of the CPU 14A and the CPU 14B, and is individually executed by the CPU 14A and the CPU 14B to start a task.

  As shown in FIG. 3, the algorithm 17 includes a processing step A, a processing step B, and a processing step C. Further, the algorithm 17 has a step of receiving a message before each of the processing step A and the processing step C. Further, the algorithm 17 has a step of transmitting a message after each of the processing step B and the processing step C.

  Here, in the processing step A, for example, a filtering process for deleting unnecessary information from the image acquired by the camera 11 is performed. Further, in the processing step B, for example, a binarization process for binarizing image pixel data based on a predetermined threshold is performed. Further, the processing step C performs, for example, a feature extraction process for converting an image into a feature amount for personal recognition.

  When the task executing the algorithm 17 is activated, it is placed in a standby state until a message is received from the task executing the common management software 16A (step S11).

  When a message is received from a task executing the common management software 16A (step S11, YES), the task executing the algorithm 17 executes a processing step based on the received message. Here, processing step A is executed (step S12). Further, the task executing the algorithm 17 executes the processing step B using the processing result of the processing step A (step S13).

  When processing step B is executed, the task executing algorithm 17 stores the processing result of processing step B as an intermediate result in the transmission buffer, and transmits a message to the task executing common management software 16A. (Step S14). That is, here, the intermediate result is transmitted to the task executing the common management software 16A.

  When the message is transmitted, the task executing the algorithm 17 is put on standby until the message is received again (step S15).

  When a message is received from a task executing the common management software 16B (step S15, YES), the task executing the algorithm 17 executes a processing step based on the received message. Here, processing step C is executed (step S16).

  When processing step C is executed, the task executing algorithm 17 stores the processing result of processing step C in the transmission buffer, and transmits a message to the task executing common management software 16B (step S17). ). That is, here, the processing result of the processing performed by the algorithm 17 on the input data is transmitted to the task executing the common management software 16B.

  All processes performed in each task are performed based on the control of the CPU 14A and the CPU 14B.

  Further, when a message is received from a task executing the common management software 16, the task executing the algorithm 17 has been described to execute the processing step A, the processing step B, and the processing step C. The processing steps to be executed are not limited to those described above. A message from a task executing the common management software 16 indicates the start position of a series of processing steps. The task executing the algorithm 17 executes processing from the processing step indicated by the message.

  FIG. 4 is a flowchart for explaining the processing of the common management software 16A stored in the RAM 141A.

  When the task executing the common management software 16A is activated, it is placed in a standby state until it receives input data from the camera 11 (step S21).

  When the input data from the camera 11 is received (step S21, YES), the task executing the common management software 16A includes the received input data and information indicating the start position in a series of processing steps. A message is transmitted to the task executing the algorithm 17 (step S22). Here, the task executing the common management software 16A instructs to start processing from the first processing step in the series of processing steps, that is, processing step A.

  When the message is transmitted, the task executing the common management software 16A is placed in a standby state until a message is received from the task executing the algorithm 17 (step S23).

  When a message is received from a task executing the algorithm 17 (step S23, YES), the task executing the common management software 16A uses the intermediate result included in the received message as the common management software 16B of the CPU 14B. Is transmitted to the task that is executing (step S24).

  When the task executing the common management software 16A transmits the intermediate result to the task executing the common management software 16B of the CPU 14B, the task returns to step S21 and proceeds to processing for the next input data.

  FIG. 5 is a flowchart for explaining the processing of the common management software 16B stored in the RAM 141B.

  When the task executing the common management software 16B is activated, it is placed in a standby state until it receives an intermediate result from the CPU 14A (step S31).

  When the intermediate result is received from the CPU 14A (step S31, YES), the task executing the common management software 16B receives a message including the received intermediate result and information indicating the start position of the series of processing steps. It transmits with respect to the task which is executing the algorithm 17 (step S32). Here, the task executing the common management software 16B instructs to start the processing from the processing step after the step of transmitting the intermediate result in the series of processing steps, that is, the processing step C.

  When the message is transmitted, the task executing the common management software 16B is placed in a standby state until a message is received from the task executing the algorithm 17 (step S33).

  When a message is received from a task executing the algorithm 17 (step S33, YES), the task executing the common management software 16B displays the processing result included in the received message as shown in FIG. 20 (step S34).

  When the task executing the common management software 16B outputs the processing result to the host computer 20, the task returns to step S31 and shifts to the processing for the intermediate result received next.

  As described above, since the camera 11 continuously acquires images, input data is continuously input to the CPU 14A. The CPU 14A and the CPU 14B perform processing in parallel as shown in FIG.

FIG. 6 is a time chart for explaining processing performed in CPU 14A and CPU 14B.
As illustrated in FIG. 6, the CPU 14A acquires the first input data A in the first phase, performs the processing step A and the processing step B on the acquired input data A, and performs the processing of the processing step B. The intermediate result A as a result is transmitted to the CPU 14B. The CPU 14B does not perform processing in the first phase.

  In the second phase, the CPU 14A acquires the second input data B, performs the processing step A and the processing step B on the acquired input data B, and obtains the intermediate result B that is the processing result of the processing step B. It transmits to CPU14B. In the second phase, the CPU 14B acquires the intermediate result A from the CPU 14A, and performs the processing step C on the acquired intermediate result A.

  In the third phase, the CPU 14A acquires the third input data C, performs processing step A and processing step B on the acquired input data C, and obtains an intermediate result C that is the processing result of processing step B. It transmits to CPU14B. In the third phase, the CPU 14B acquires the intermediate result B from the CPU 14A, and performs processing step C on the acquired intermediate result B.

  In the above-described embodiment, the CPU 14B performs the processing step C on the data that has been subjected to the processing step A and the processing step B in the CPU 14A. For this reason, for example, when the time required for the processing step A and the processing step B is longer than the time required for the processing step C, the CPU 14B waits for data to be supplied from the CPU 14A.

  Further, for example, when the time required for the processing step A and the processing step B is shorter than the time required for the processing step C, the processing of the processing step C by the CPU 14B cannot catch up with the supplied data. For this reason, the time for completing the processing for all the data is largely shifted between the CPU 14B and the CPU 14A, and the overall processing efficiency is lowered.

  That is, the processing efficiency improves as the difference between the processing time by the CPU 14A and the processing time by the CPU 14B in one phase decreases.

  According to the configuration described above, a processing step for outputting an intermediate result is included in a series of processing steps of the algorithm. When a plurality of series of processes are performed on data continuously acquired from the object, the image processing apparatus 1 first executes the data acquired by the CPU 14A in order from the first process in the series of processes. When the intermediate result is output, the output result is supplied to the CPU 14B.

  Subsequently, in the image processing apparatus 1, the CPU 14A performs processing for the next data, and the CPU 14B executes processing subsequent to the processing for outputting the intermediate result for the intermediate result. For this reason, in the processes after the second phase, the CPU 14A and the CPU 14B can perform the processes in parallel.

  As a result, it is possible to provide a data processing apparatus and a data processing method capable of executing an algorithm using a plurality of CPUs more efficiently.

  In addition, this invention is not limited to the said embodiment as it is, It can implement by changing a component in the range which does not deviate from the summary in an implementation stage. In addition, various inventions can be formed by appropriately combining a plurality of components disclosed in the embodiment. For example, some components may be deleted from all the components shown in the embodiment. Furthermore, you may combine the component covering different embodiment suitably.

  In the above-described embodiment, an example using two CPUs has been described. However, the present invention is not limited to this configuration. The present invention can be implemented if there are at least two CPUs. In this case, the processing steps may be shared by providing processing steps for outputting intermediate results in a series of processing steps of the algorithm in accordance with the number of CPUs.

  Further, the CPU 14A and the CPU 14B read the common management software and the algorithm from the nonvolatile memory and store them in the internal RAM 141A and the RAM 141B, respectively. However, the present invention is not limited to this configuration. For example, common management software and algorithms may be stored in the ROM of the CPU 14A and the CPU 14B in advance.

  Furthermore, although the algorithm in the above-described embodiment includes processing step A, processing step B, and processing step C, it is not limited to this. Further, a step of outputting the intermediate result may be placed at any position in the series of processing steps of the algorithm.

FIG. 1 is a diagram schematically illustrating a configuration example of an image processing apparatus according to the present embodiment. FIG. 2 is an explanatory diagram for schematically explaining the processing of the CPU when the common management software and the algorithm are stored in the RAM. FIG. 3 is a flowchart for explaining a series of processing steps of the algorithm stored in the RAM. FIG. 4 is a flowchart for explaining the processing of the common management software stored in the RAM. FIG. 5 is a flowchart for explaining the processing of the common management software stored in the RAM. FIG. 6 is a time chart for explaining processing performed in the CPU.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Image processing apparatus, 11 ... Camera, 12 ... Image processing board, 13 ... Image distributor, 14B ... CPU, 14A ... CPU, 16A ... Common management software, 16B ... Common management software, 16 ... Common management software, 17 ... Algorithm, 20 ... host computer, 141A ... RAM, 141B ... RAM.

Claims (6)

A data processing apparatus having first and second CPUs,
Storage means for storing in advance an algorithm having a plurality of series of processing steps including a step of outputting at least an intermediate result;
An input means for continuously inputting data;
First processing means for executing a processing step of the algorithm from the top by any one of the first and second CPUs based on data input by the input means;
Intermediate result supply means for supplying the intermediate result to the other CPU when the step of outputting the intermediate result is executed by the first processing means;
Second processing means for executing a processing step after the step of outputting the intermediate result of the algorithm by the other CPU based on the intermediate result when the intermediate result is supplied;
A data processing apparatus comprising:   The data processing apparatus according to claim 1, wherein the input unit includes an image capturing unit that continuously captures image data by sequentially capturing images of an object.   The data processing apparatus according to claim 1, wherein the first processing unit and the second processing unit execute processing in parallel. A data processing apparatus having first and second CPUs,
Pre-stored an algorithm having a plurality of processing steps including at least a step of outputting an intermediate result;
Based on the continuously input data, the processing step of the algorithm is executed from the top by any one of the first and second CPUs,
When the step of outputting the intermediate result is executed, the intermediate result is supplied to the other CPU,
Performing a processing step after the step of outputting the intermediate result of the algorithm by the other CPU based on the intermediate result when the intermediate result is supplied;
A data processing method.   The data processing method according to claim 4, wherein the image data is continuously acquired by continuously imaging the object in time series.   The data processing method according to claim 4, wherein the first CPU and the second CPU execute processing in parallel.

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