JPH02224468A - Picture coding system - Google Patents

Abstract

PURPOSE:To relieve the excess load of a processing to a post-stage multi- processor by adjusting a threshold level for coding implemented by a pre-stage multi-processor depending on the data storage quantity of a buffer placed between the pre-stage multi-processor and the post-stage multi-processor and controlling an effective block number to the constant. CONSTITUTION:As for input data inputted from an input terminal 1 and stored in an input frame memory 4, the pre-stage processing such as movement compensation, conditional picture element supplement, etc., are executed by a processing unit in the pre-stage multi-processor 5 and its result of processing is outputted to a buffer 7. The block data stored in the buffer 7 is subjected to a post-stage processing such as vector quantization, discrete COS transformation and decoding by a post-stage multi-processor 6. An output control section 8 sends a feedback data to the pre-stage multi-processor 5 to control a threshold level, thereby limiting the quantity of production of a coded data to the constant. Thus, the load of the post-stage multi-processor 6 is relieved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an image encoding system that processes a large amount of image signals at high speed.

[Conventional technology]

FIG. 4 shows, for example, a real time video signal processor module (Real time video signal processor module).
de.

Signal Processor Module)
[IC8SP
'87) Proceedings (Dallas, USA, April 1987) P19
61-1964) is a block diagram showing a conventional image encoding system. In the figure, 1 is an input terminal into which input data is input, 2 is a plurality of (M) processors that are connected to this input terminal 1 via a human power bus and performs signal processing operations on the input data, and 3 is each of these processors. processor 2
This is an output terminal to which the processing results from are output via the output bus. In addition, 20 is 1 input from the input terminal 1.
Screen data 21 for one frame is small screen data obtained by dividing the screen data 20 for one frame into regions.

FIG. 3 is a block diagram showing a typical example of a high-efficiency encoding algorithm for a moving image screen to be processed. In the figure, 1 is an input terminal, 10 is a motion compensator that performs motion compensation for input data from input terminal 1, and 11 is this motion compensator 1.
12 is a block discriminator that divides the data from the interframe subtractor 11 into valid block data and invalid block data; 13 is a block discriminator 12 an encoder/decoder that encodes and decodes effective block data from the encoder/decoder 13; an interframe adder 14 that adds the decoded data from the encoder/decoder 13 and the data from the motion compensator 10; 15 is a coded frame memory that stores data from the interframe adder 14 and invalid block data from the block identifier 12; 16 is a pre-processing unit including a motion compensator 10 and an interframe difference unit 11; 17 is a coder; It is a post-processing section including an encoder/decoder 13 and an interframe adder 14, and 18 is an output terminal to which processed output data is output.

Next, the operation will be explained. This image encoding system targets signal processing of moving images, and uses 20
is divided into M small screen data 21 and allocated to each processor 2. Each processor 2 takes one frame time to capture the small screen data 21 of the area in its charge. Next, each processor 2 spends one frame time to perform predetermined processing, and outputs the processing results to the output bus in synchronization with the other processors 2. At this time, the individually processed small screen data 21 is assembled again in units of one frame.

In the above processing method, only one frame is divided into M pieces and sent to the encoder/decoder 13, and encoding/decoding is performed for each frame when code division is performed. The interlayer T in the small screen at this time is
The relationship between the effective block rate α and the processing time T of a small screen is given by: Tf: processing time per frame in one processing unit Tfn: processing time per small screen in the n-th processing unit. From this, by increasing the number of divisions, high-speed image processing is possible even if a relatively slow processor 2 is used, but on the other hand, the overall processing speed is determined by the processing speed of the slowest processor 2.

In the algorithm of the high-efficiency encoder for the moving image screen to be processed as shown in FIG. After the difference processing with the input data is performed in the subtractor 11, the effective program α T = aBH+ bBN□ is extracted by the block discriminator 12.
(2) a, t): Constant BN: Indicated by the number of blocks within the small screen.

FIG. 5 shows this equation (2). In the conventional image encoding system, since each processor 2 performs input/output in synchronization, it is necessary to uniformly allocate the maximum processing time to each processor 2, resulting in idle time corresponding to the area indicated by diagonal lines in the figure.

[Problems to be Solved by the Invention] Since the conventional image encoding system is configured as described above, in processing where the processing time differs depending on the processing block, the processing time is uniformly set for each processor 2. It was necessary to set the allocation to the worst-case value, which caused problems such as the number of processors increasing unnecessarily even though there was sufficient processing power.

This invention was made to solve the above-mentioned problems, and aims to provide an image encoding system that can perform efficient processing with a smaller number of processors.

[Means to solve the problem]

The image encoding system according to the present invention divides encoding processing into processing in which all pixels of input data are to be encoded and processing in which only valid blocks are to be encoded, and a pre-stage multiprocessor is in charge of the former. , a post-stage multiprocessor that is in charge of the latter, a buffer that buffers the difference in processing time between the pre-processor and post-processor, and threshold control to limit the amount of encoded data generated from the pre-processor to a certain level. It is equipped with an output control unit that maintains the processing amount of the subsequent multiprocessor at a constant level based on the amount of data stored in the buffer, and has the function of adding data information to the first multiprocessor, and allows the subsequent multiprocessor to decode the data information. It has the function of

[For production]

In the image encoding system according to the present invention, the output control unit is controlled by the upstream multiprocessor depending on the amount of data stored in the buffer placed between the upstream multiprocessor that encodes all pixels and the downstream multiprocessor that encodes only valid blocks. By adjusting the threshold of encoding to be performed and controlling the number of effective blocks to a constant value, excessive processing burden on the subsequent multiprocessor is alleviated, and the number of processors required in the entire system is reduced.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. 1st
In the figure, 1 and 3 are the aforementioned input terminals and output terminals, and 4 is an input frame memory in which input data input from the input terminal 1 is stored. 5 is a pre-stage multiprocessor connected to this input frame memory 4 and consisting of a plurality of processors 2 that can be expanded in parallel in accordance with the processing amount, and targets all pixels of input data input from input terminal 1. It is in charge of encoding processing and has the function of adding valid/invalid block information and position information within a frame to block data.

6 is a rear multiprocessor consisting of a plurality of processors 2 that can be expanded in parallel according to the processing amount;
It is in charge of processing to encode only valid blocks of input data input from input terminal 1, and identifies and identifies valid blocks from valid/invalid block information and position information added to block data by pre-stage multiprocessor 5. It has the ability to reconstruct frames.

These buffers 7 are arranged between the front-stage multiprocessor 5 and the rear-stage multiprocessor 60, and store the encoded data output from the front-stage multiprocessor 5, and also buffer the processing time of the front-stage multiprocessor 5 and the rear-stage multiprocessor 6. It is. 8 is the rear multiprocessor 6
is connected to receive encoded data, and sends feedback data to the pre-stage multiprocessor 5 to adjust the threshold value for controlling the amount of encoded data generated, thereby keeping the amount of encoded data generated by the pre-stage multiprocessor 5 constant. This is an output control unit that limits the number of blocks to 1, changes the number of effective blocks according to the amount of data stored in the buffer 7, holds the processing amount of the subsequent multiprocessor constant, and sends output data from the output terminal 3. Reference numeral 9 denotes a coded frame memory which is similarly connected to the subsequent multiprocessor 6, stores incoming decoded data, and sends it to the preceding multiprocessor 5 when processing the next frame.

71 is block data processed by the pre-stage multiprocessor 5 and stored in the buffer 7, and 72 is a parameter added to each block data 71 to indicate the attribute of the data.

Next, the operation will be explained. When the encoding process that is the subject of this invention is divided into a pre-processing before conditional pixel replenishment and a post-processing after that, the relationship between the effective block rate α and the processing time T of the pre-processing and post-processing is It is shown by the following formula.

In the case of pre-processing, T=C・・・・・・・・・・・・・・・・・・・・・
・・・・・・(3) C: For constant post-processing T=Aα ・・・・・・・・・・・・・・・・・・・・・
(4) A: Constant The above formulas (3) and (4) are shown in FIG. From the figure,
Based on the characteristics of processing time, encoding processing is roughly divided into front-stage processing in which the processing time is constant regardless of the effective block rate α, and latter-stage processing in which the processing time is proportional to the effective block rate α. In the present invention, the first-stage processing and the second-stage processing are performed separately by a first-stage multiprocessor 5 and a second-stage multiprocessor 6, each of which can be expanded in parallel in accordance with the amount of processing.

That is, it is input from the input terminal 1 and sent to the input frame memory 4.
The input data stored in is subjected to pre-processing such as motion compensation and conditional pixel supplementation by the processing unit in the pre-stage multiprocessor 5, and the processing results are output to the buffer 7. Each processor 2 constituting the pre-stage multiprocessor 5 inputs block data from the input frame memory 4 to the machine that has completed processing. Since the processing time of each processor 2 at this time varies depending on the block data,
The order of output to the buffer 7 does not match the order of scanning of the input frame memory 4. Therefore, the front stage multiprocessor 5
The data output from each processor 2 to the buffer 7 has a data structure in which position information indicating the position within the frame is added, as well as valid/invalid information and data type information.

The block data stored in the buff tear is subjected to post-processing such as vector quantization, discrete COS conversion, and decoding by the post-stage multiprocessor 6. The encoded data is sent to the output control unit 8, and the decoded data is sent to the encoder. Each is output to the frame memory 9.

At this time, processing is performed only on valid blocks with reference to data additional information. The decoded data stored in the encoded frame memory 9 is sent to the previous stage multiprocessor 5 and used for encoding the next frame. The output control section 8 sends feedback data to the pre-stage multiprocessor 5 to control the threshold value for the pre-processing, thereby limiting the amount of generated encoded data to a constant value. Furthermore, the output control unit 8 monitors the amount of data in the buffer 7 and changes the number of effective blocks according to the amount of accumulated data, thereby reducing the burden on the subsequent multiprocessor 6 by limiting the processing amount of subsequent processing to a constant value. do.

Furthermore, the processing time difference 'r2-'rl between the first-stage processing time T1 and the second-stage processing time T2 shown in FIG. and front stage multiprocessor 5
In addition, processing performance close to the maximum processing capacity of the rear-stage multiprocessor 6 is realized.

As a result, it is possible to eliminate the loss caused by idle time in the area indicated by diagonal lines in FIG. 5 during the entire encoding process.

〔Effect of the invention〕

As described above, according to the present invention, the front-stage multiprocessor and the rear-stage multiprocessor individually process the encoding of all pixels and the encoding of only effective blocks, and the threshold value control is used to process the encoding of the front-stage multiprocessor. By limiting the amount of generated data to a certain level and changing the number of effective blocks depending on the amount of data accumulated in the buffer that buffers both, the processing amount of the subsequent multiprocessor is kept constant, so the processing time is Since there is no need to set it to the value,
The processing power of each processor can always be maximized, which has the effect of reducing the number of processors required for processing.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an image encoding system according to an embodiment of the present invention, FIG. 2 is an explanatory diagram showing the relationship between processing time and effective block rate, and FIG. 3 is a typical high-efficiency encoding system. FIG. 4 is a block diagram showing an example of the configuration of an algorithm, FIG. 4 is a block diagram showing a conventional image encoding system, and FIG. 5 is an explanatory diagram showing the relationship between processing time and effective block rate. 2 is a processor, 5 is a front stage multiprocessor, 6 is a rear stage multiprocessor, T is a buffer, and 8 is an output control unit. In addition, the same symbols in the figures indicate the same or equivalent parts. Nini Diagram Diagram Diagram Procedure Amendment (Spontaneous) Patent Application No. 1-45632 2, Name of Invention Image Coding System 3, Relationship with the case of the person making the amendment Patent Applicant Address Marunouchi, Chiyoda-ku, Tokyo 2-2-3 Name (601) Mitsubishi Electric Corporation Representative Moriya Shiki 4, Agent Postal code 105 6. Contents of amendment (1) The scope of the claims will be amended as shown in the attached sheet. (2) Delete the text "and said block...invalid block data" from line 3 to line 4 of page 4 of the specification. (3) In the third line of page 7 of the specification, the phrase "less than a number" should be amended to read "less than a number." (4) "Processing time" on page 9, line 15 of the specification is corrected to "processing time difference." 7. A document stating the scope of claims after the amendment to the list of attached documents: 1 version Responsible for the encoding process targeting all pixels of the claims input data after the above amendment;
A plurality of processors that can be expanded in parallel in accordance with the amount of processing are provided, and a pre-stage multiprocessor has a function of adding valid/invalid block information and position information within a frame to block data, and encodes only valid blocks of the input data. A function of providing a plurality of processors that are in charge of processing to be processed and expandable in a parallel direction according to the amount of processing, and identifying a valid block based on the valid/invalid block information added to the block data, and the block A post-stage multiprocessor having a function of reconstructing a frame based on the position information added to data; and a post-processor located between the pre-stage multiprocessor and the post-stage multiprocessor, which stores encoded data output from the pre-stage multiprocessor. At the same time, a buffer for buffering the processing time difference between the preceding multiprocessor and the subsequent multiprocessor, and a threshold value controlling the amount of encoded data generated by the preceding multiprocessor are adjusted, and the encoding of the preceding multiprocessor is performed. Image encoding comprising: an output control unit that limits the amount of data generation to a constant level and maintains the processing amount of the subsequent multiprocessor constant by changing the number of effective blocks by approximately 2 according to the amount of data accumulated in the buffer. system.

Claims (1)

[Claims] Responsible for encoding processing for all pixels of input data,
A plurality of processors that can be expanded in parallel in accordance with the amount of processing are provided, and a pre-stage multiprocessor has a function of adding valid/invalid block information and position information within a frame to block data, and a pre-stage multiprocessor that adds only valid blocks of the input data. A function of providing a plurality of processors that are in charge of processing to be encoded and expandable in a parallel direction according to the amount of processing, and identifying valid blocks based on the valid/invalid block information added to the block data; a subsequent multiprocessor having a function of reconstructing a frame based on the position information added to block data;
a buffer located between the preceding multiprocessor and the subsequent multiprocessor, which stores encoded data output from the preceding multiprocessor and buffers the processing time of the preceding multiprocessor and the subsequent multiprocessor; The threshold value for controlling the amount of encoded data generated by the multiprocessor is adjusted to limit the amount of encoded data generated by the preceding multiprocessor to a constant value, and the number of effective blocks is adjusted according to the amount of data accumulated in the buffer. an output control unit that maintains the processing amount of the subsequent multiprocessor constant by changing the amount of processing of the subsequent multiprocessor.