JP2009278552A - False sine-wave generation circuit and false sine-wave multiplication circuit using the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem wherein a cost is raised and an area for forming other circuits is restricted when the circuit is provided by using a chip such as ASIC, since a conventional sine-wave generation circuit includes a capacitance or an inductance in a circuit configuration. <P>SOLUTION: In this sine-wave generation circuit, first and second input switches 11, 21 are connected to input terminals 10a<SB>0</SB>-10a<SB>n-1</SB>, 20a<SB>0</SB>-20a<SB>n-1</SB>of first and second ladder resistance networks and first and second output switches 14, 24 are connected to output terminals 10b, 20b. An open/close control means 50 performs open/close control on switches 11, 14, 21, 24 and inputs to an operational amplifier 40 sine-wave like first and second input signals 15, 25 having polarities which are inverse to each other. The operational amplifier 40 outputs an output signal 41, which is changed in a sine-wave shape, by differentially amplifying the first and second input signals 15, 25. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a pseudo sine wave generation circuit, and in particular, it is configured to obtain an output signal that changes in a sine wave shape by opening / closing control of an input switch and an output switch connected to a ladder resistor network, thereby reducing capacitance and inductance. The present invention relates to a new improvement that can be made unnecessary and can be more easily realized by a chip such as an ASIC.

  As this type of sine wave generation circuit that has been conventionally used, for example, a sine wave generation circuit shown in the following Non-Patent Document 1 or the like is used. That is, conventionally, an LC oscillation circuit, a CR oscillation circuit, a crystal oscillation circuit, or the like is used as the sine wave generation circuit.

Tsunemoto Tsuji 314-337 pages of transistor circuit design (written by Masaomi Suzuki, CG Publishing Co., Ltd.) (14th edition, issued July 1, 2004)

In the conventional sine wave generating circuit as described above, since the circuit configuration includes capacitance and inductance, when a circuit is realized using a chip such as an ASIC, a large area is required to create the capacitance and inductance. This is necessary and increases the cost, and limits the area for forming other circuits.
Further, when a capacitance or inductance is used, the output frequency is fixed by a constant such as a capacitance value of the capacitance, for example, and it becomes difficult to change the output frequency.

  The present invention has been made to solve the above-described problems, and an object thereof is to provide a pseudo sine wave generation circuit that can eliminate the need for capacitance and inductance and can be more easily realized by a chip such as an ASIC. That is.

  A pseudo sine wave generation circuit according to the present invention is connected to a first ladder resistor network having a plurality of first input terminals and the first input terminal, and the first input terminals are respectively connected to a first reference voltage or a ground. A first input switch to be connected; a first output switch connected to a first output terminal of the first ladder resistor network; and connecting the first output terminal to a positive input terminal or a negative input terminal of an operational amplifier; A second ladder resistor network having two input terminals and a second reference terminal connected to the second input terminal and connected to the second reference voltage or the ground having a polarity opposite to the first reference voltage. A two-input switch; a second output switch connected to the second output terminal of the second ladder resistor network; and connecting the second output terminal to the positive input terminal or the negative input terminal; and the first input switch; in front A first output switch; a second input switch; and an open / close control means connected to the second output switch, wherein the open / close control means is based on a digital angle position signal from the outside. By performing open / close control of the first output switch, the second input switch, and the second output switch, sinusoidal first and second input signals having opposite polarities can be obtained. The operational amplifier is input to the operational amplifier from an output terminal, and the operational amplifier differentially amplifies the first and second input signals and outputs an output signal that changes in a sine wave shape.

The opening / closing control means performs opening / closing control of the first and second input switches based on a predetermined first quadrant opening / closing pattern every time the angular position of the digital angle position signal changes by a predetermined unit angle. The order of the first quadrant opening / closing pattern is reversed every time the angular position changes 90 degrees, and the first and second output terminals for the positive input terminal and the negative input terminal every time the angular position changes 180 degrees. Is switched to reverse the polarity of the output signal.
The opening / closing control means outputs the sine wave signal or the cosine wave signal corresponding to the angular position of the digital angular position signal by the opening / closing control based on the first quadrant opening / closing pattern and the polarity inversion of the output signal. Output as a signal.
The operational amplifier outputs first and second differential outputs having opposite polarities as the output signal.

  Further, the pseudo sine wave multiplication circuit according to the present invention uses the pseudo sine wave generation circuit and uses arbitrary analog signals having opposite polarities as the first and second reference voltages.

  According to the pseudo sine wave generation circuit of the present invention, an output signal that changes in a sine wave shape is obtained by opening / closing control of an input switch and an output switch connected to a ladder resistor network, so that no capacitance or inductance is required, and an ASIC, etc. This can be realized more easily with this chip.

The opening / closing control means performs opening / closing control of the first and second input switches based on a predetermined first quadrant opening / closing pattern every time the angular position of the digital angle position signal changes by a predetermined unit angle. The order of the first quadrant opening / closing pattern is reversed every time the angular position changes 90 degrees, and the first and second output terminals for the positive input terminal and the negative input terminal every time the angular position changes 180 degrees. Since the polarity of the output signal is inverted by switching the connection, the output signals of the first to fourth quadrants can be obtained using the first quadrant opening / closing pattern, and the configuration of the logic circuit can be simplified.
The open / close control means outputs a sine wave signal or a cosine wave signal corresponding to the angular position of the digital angular position signal by the open / close control based on the first quadrant open / close pattern and the polarity inversion of the output signal. Therefore, the application range can be expanded.
Further, since the operational amplifier outputs first and second differential outputs having opposite polarities as the output signal, it is possible to suppress the influence of noise when the output signal is used in a subsequent circuit.

  According to the pseudo sine wave multiplication circuit of the present invention, since the sine wave analog signals having opposite polarities are used as the first and second reference voltages, the output signal is converted into an arbitrary analog signal. A multiplied waveform can be obtained.

The best mode for carrying out the present invention will be described below with reference to the drawings.
Embodiment 1 FIG.
FIG. 1 is a circuit diagram showing a pseudo sine wave generating circuit according to Embodiment 1 of the present invention. The pseudo sine wave generation circuit of this embodiment uses a ladder-type multiplying D / A conversion circuit to obtain a staircase output that changes like a sine wave. In FIG. 1, the first and second ladder resistor networks 10 and 20 have the same configuration, and as is well known, two types of resistance elements having resistance values R and 2R are connected in a ladder shape. Is. The first ladder resistor network 10 includes a plurality of first input terminals 10a _{0 to} 10a _n−1 and a first output terminal 10b, and the second ladder resistor network 20 includes a plurality of second input terminals 10a _{0 to} 10a _n−1 . Input terminals 20a _{0 to} 20a _n−1 and one second output terminal 20b are provided (where n is a natural number).

A first input switch 11 is connected to each of the first input terminals 10a _{0 to} 10a _n−1. The first input switch 11 includes a plurality of first signal input switch units 11a _{0 to} 11a _n−1 . A plurality of first ground switch units -11a ₀ to -11a _n-1 are provided. Note that the sign-used here means inversion, and in the figure, it is expressed as a bar with inversion meaning. The first signal input switch units 11a _{0 to} 11a _n-1 connect the first input terminals 10a _{0 to} 10a _n-1 to the first reference voltage 12, respectively, and each first ground switch unit 11a. _{0 ~-11a n-1} is used to connect each of the respective first input terminal _10a 0 10 a _n-1 to the ground 30. In this embodiment, the first reference voltage 12 is a DC voltage having a predetermined voltage value Vref.

  A first output switch 14 is connected to the first output terminal 10b, and the first output switch 14 is provided with a first positive connection switch section 14a and a first negative connection switch section -14a. Yes. The first positive connection switch unit 14a connects the first output terminal 10b to the positive input terminal 40a of the operational amplifier 40, and the first negative connection switch unit -14a connects the first output terminal 10b to the positive output terminal 40a. The operational amplifier 40 is connected to the negative input terminal 40b. An input resistor Rin is connected to each of the positive input terminal 40a and the negative input terminal 40b, and the first output terminal 10b is connected to the positive input terminal 40a and the negative input terminal 40b via the input resistor Rin. Connected to.

A second input switch 21 is connected to each of the second input terminals 20a _{0 to} 20a _n−1 , and the second input switch 21 includes a plurality of second signal input switch units 21a _{0 to} 21a _n−1 . A plurality of second ground switch units -21a ₀ to -21a _n-1 are provided. The second signal input switch units 21a _{0 to} 21a _n-1 connect the second input terminals 20a _{0 to} 20a _n-1 to the second reference voltage 22, respectively, and each second ground switch unit -21a. _{0 ~-21a n-1} is used to connect each of the respective second input terminals _20a 0 _{~20a n-1} to the ground 30. The second reference voltage 22 is a DC voltage having a voltage value −Vref having a polarity opposite to that of the first reference voltage 12.

  A second output switch 24 is connected to the second output terminal 20b. The second output switch 24 is provided with a second positive connection switch section -24a and a second negative connection switch section 24a. Yes. The second positive connection switch section -24a connects the second output terminal 20b to the positive input terminal 40a, and the second negative connection switch section 24a connects the second output terminal 20b to the negative input terminal 40b. To connect to. The second output terminal 20b is connected to the positive input terminal 40a and the negative input terminal 40b through the input resistor Rin.

Although not specifically shown, the first input switch 11, the first output switch 14, the second input switch 21, and the second output switch 24 are connected to an open / close control means 50. The switches 11, 14, 21, 24 are controlled to open / close by control signals D (D _{0 to} D _n−1 , D _m , −D ₀ to −D _n−1 , −D _m ) from the opening / closing control means 50. . The control signal D (D _{0 to} D _n−1 , D _m , −D ₀ to −D _n−1 , −D _m ) is a signal having binary levels of H and L.

Said first and second signal input switch unit _{11a 0 ~11a n-1, 21a} 0 ~21a n-1 is the control signal _D 0 _{to D n-1} is H level of the corresponding positions (0 to n-1) It is closed at the time of, and it is opened at the L level. That is, in the first signal input switch units 11a _{0 to} 11a _n-1 and the second signal input switch units 21a _{0 to} 21a _n-1 , the switch units at the same position ( _{0 to n} -1) are simultaneously closed. Is done. Control signal _-D 0 _{to D n-1} is the control signal _D 0 _{to D n-1} of the inverted signal, the first and second ground switch section _{-11a 0 ~-11a n-1} , -21a _{0 ~-21a n-1,} the control signal _-D 0 _{~-D n-1} of the corresponding position is closed when the H level, is open at the L level. That is, the control signal _{D 0 ~D n-1, -D} 0 by _{to D n-1,} selectively the first and to the input terminals _{10a 0 ~10a n-1, 20a} 0 ~20a n-1 Second reference voltages 12 and 22 are applied.

The first positive connection switch unit 14a and the second negative connection switch unit 24a are closed when the control signal _Dm is at the H level, and are opened when the control signal _Dm is at the L level. Control signal -D _m is an inverted signal of the control signal _{D m,} the first negative connection switch unit -14a and the second positive connection switch unit -24a, the control signal -D _m is at the H level Closed and opened when at L level. That is, the control signal _D m, by -D _m, the first and second output terminals 10b, one of 20b are connected to the positive input terminal 40a, the other is connected to the negative input terminal 40b.

When the opening / closing control by the opening / closing control means 50 is performed, the output signal 41 of the operational amplifier 40 is expressed by the following equation (1). Note that D _{0 to} D _n−1 , D _m , −D ₀ to −D _n−1 , −D _m in the expression (1) are control signals D _{0 to} D _n−1 , D _m , −D ₀ to It is ₁ when −D _n−1 and −D _m are at H level, and 0 when it is at L level. Rin is the resistance value of the input resistor Rin, and Rf is the resistance value of the feedback resistor Rf.

  Here, if Rf = 2R and Rin = R, the equation (1) becomes the following equation (2). That is, the resistance value of the resistor used in the pseudo sine wave generation circuit can be two types.

That is, first and second sinusoidal input signals 15 and 25 having opposite polarities are input to the operational amplifier 40 from the first and second output terminals 10b and 20b, and the operational amplifier 40 performs the first and second input signals. The two input signals 15 and 25 are differentially amplified to obtain an output signal 41. The output signal 41, corresponding to the first and second signal input switch unit _{11a 0 ~11a n-1, 21a} 0 ~21a n-1 , which is closed, the voltage value of the second n-th power.

  The operational amplifier 40 outputs first and second differential outputs 41 a and 41 b having opposite polarities as the output signal 41. The first and second differential outputs 41a and 41b are used as differential signals in the subsequent circuit.

Next, FIG. 2 is an explanatory diagram showing the output signal 41 of FIG. As described above, the output signal 41 is generated from the 2 n power values by closing the first and second signal input switch units 11a _{0 to} 11a _n−1 and 21a _{0 to} 21a _n−1. Become. Further, the polarity of the output signal 41 is inverted by the opening / closing control of the first and second output switches 14, 24. As will be described in detail later, the open / close control means 50 performs open / close control of the switch units 11, 14, 21, and 24 using these characteristics, whereby the output signal 41 is output in a staircase that changes in a sine wave shape. (Pseudo sine wave signal).

  Returning to FIG. 1, the open / close control means 50 performs open / close control of the switch units 11, 14, 21, 24 based on an external digital angular position signal ωt. Thus, the output signal 41 is a sine wave signal corresponding to the angular position of the digital angular position signal ωt. In addition, the waveform of FIG. 2 is a case where n = 4, and the amplitude is 31 values. The digital angular position signal ωt is 8 bits, and the angle axis (horizontal axis) is 256 sampling.

  Next, FIG. 3 is an explanatory diagram showing the ideal sine wave of FIG. As is well known, the sine wave (sin ωt) has a point-symmetric relationship with respect to the point of ωt = π in the range of 0 ≦ ωt <π and the range of π ≦ ωt <2π. In addition, the range of 0 ≦ ωt <π / 2 and the range of π / 2 ≦ ωt <π have a line-symmetric relationship about the axis of ωt = π / 2.

  That is, if a first quadrant opening / closing pattern for generating a pseudo sine wave signal in the first quadrant (0 ≦ ωt <π / 2) is configured, the first quadrant opening / closing pattern is used to generate the second quadrant quadrant opening / closing pattern. A pseudo sine wave signal can be generated. Specifically, a pseudo sine wave signal in the second quadrant can be generated by reversing the order of the first quadrant opening / closing pattern. Further, if the first quadrant opening / closing pattern is executed in the forward direction and the reverse direction with the polarity reversed, the pseudo sine wave signals in the third and fourth quadrants can be generated.

  Next, FIG. 4 is a circuit diagram showing the opening / closing control means 50 of FIG. 1 in more detail. In the figure, the opening / closing control means 50 includes first to third bit cutout units 51 to 53, a first quadrant generation logic unit 54, an input side control signal generation unit 55, an order inversion unit 56, and an output side. A control signal generation unit 57 is provided.

  The digital angle position signal ωt is input to the first to third bit cutout units 51 to 53, and the output side control signal generation unit 57 is connected to the first bit cutout unit 51, and the order The reversing part 56 is connected to the second and third cutout parts 52 and 53. The first quadrant generation logic unit 54 is connected to the third bit cutout unit 53 via the order inversion unit 56, and the input side control signal generation unit 55 is connected to the first quadrant generation logic unit 54. ing.

  Here, the digital angle position signal ωt is a bit group of the upper third bit or less that is sequentially incremented every time the angle position changes by a predetermined unit angle, and an upper order that is incremented every time the angle position changes by 90 degrees. The second bit of the second bit and the first bit which is the most significant bit incremented every time the angular position changes by 180 degrees.

  The third bit cutout unit 53 cuts out the bit group from the digital angular position signal ωt, and inputs the bit group to the first quadrant generation logic unit 54 through the order inversion unit 56.

  The first quadrant generation logic unit 54 is composed of a digital logic circuit that realizes the first quadrant opening / closing pattern described above, and generates a first quadrant logic signal 54a corresponding to the value of the bit group. Input to section 55. The first quadrant generation logic unit 54 may be composed of a ROM instead of a digital logic circuit.

The input control signal generating unit 55, the first quadrant logic signal 54a control signal _D 0 _{to D n-1} based, -D 0 _{to D n-1} of said first and second input switches 11 and 21 inputs (each switch section _{11a 0 ~11a n-1, 21a} 0 ~21a n-1, -11a 0 ~11a n-1, -21a 0 ~21a n-1) to. That is, the control signal _D 0 _{to D n-1} is the first quadrant logic signal 54a, the control signal _-D 0 _{to D n-1} are those which the first quadrant logic signal 54a is inverted. Thus, every time the angular position of the digital angular position signal ωt changes by a predetermined unit angle, the opening / closing control based on the first quadrant opening / closing pattern is performed, and a pseudo sine wave signal in the first quadrant is generated.

  The second bit cutout unit 52 cuts out the second bit from the digital angular position signal ωt and inputs the second bit to the order inversion unit 56. The order inversion unit 56 is provided with a non-inversion side switch 56a and an inversion side switch 56b, and inverts the bit group input to the first quadrant generation logic unit 54 based on the second bit. . Thus, every time the angular position changes by 90 degrees, the order of the first quadrant opening / closing pattern is reversed, and a second quadrant pseudo sine wave signal is generated.

The first bit cutout unit 51 cuts out the first bit from the digital angular position signal ωt, and inputs the first bit to the output side control signal generation unit 57. The output control signal generation section 57, the control signal _D m based on the first bit, said -D _m first and second output switches 14, 24 (first positive connection switch portion 14a, the first negative connection switch -14a, second positive connection switch unit -24a, and second negative connection switch unit 24a). That is, the control signal D _m is the first bit, the control signal -D _m are those wherein the first bit is inverted. Thus, every time the angular position changes by 180 degrees, the connection of the first and second output terminals 10b and 20b to the positive input terminal 40a and the negative input terminal 40b is switched, and the polarity of the output signal 41 is inverted. Thus, pseudo sine wave signals in the third and fourth quadrants are generated. That is, in this embodiment, the first bit cutout unit 51 constitutes a polarity switching unit 58.

In such a pseudo sine wave generation circuit, an output signal that changes in a sine wave shape is obtained by opening / closing control of an input switch and an output switch connected to a ladder resistor network, so that capacitance and inductance are unnecessary, and a chip such as an ASIC Can be realized more easily.
In addition, the frequency of the output signal can be changed by changing the period of the digital angular position signal, and the application range can be expanded compared to a circuit using capacitance or inductance.
Further, since the differential input and the differential output are used, the influence of noise, the offset of the output voltage due to the input bias current of the operational amplifier, and the like can be reduced. Specifically, in the case of a single input / output configuration, common mode noise, that is, changes in the reference signal due to power fluctuations and noise from the surrounding environment appear in the output, but by making the input and output differential, Such common mode noise can be removed. Further, by making the input / output differential, it is possible to handle twice the amplitude as in the case of single input / output, and by increasing the S / N ratio, the influence of noise can be reduced. On the other hand, the offset of the output voltage due to the influence of the input bias current of the operational amplifier 40 is mainly caused by the unbalance of the resistance values of the resistors connected to the positive input terminal 40a and the negative input terminal 40b of the operational amplifier. For this reason, generally, as shown in FIG. 5, a contrivance is made to eliminate the influence by inserting a resistor having the same value as that when the input resistor and the feedback resistor are arranged in parallel. The same applies to the case of multiplication type D / A. In the case of a single input / output configuration using an inverting amplifier circuit or the like, the overall resistance value of the operational amplifier input group varies depending on the open / close state of each analog switch. Therefore, every time the open / close state changes, the output offset may change unless the same adjustment as in FIG. 5 is made. In the configuration of the embodiment, since the open / close state of the switch is changed simultaneously at both the positive input terminal 40a and the negative input terminal 40b of the operational amplifier 40, the resistance value is always the same value as positive and negative. The influence of current can be suppressed. Also, regarding the output offset, as in the case of noise, since it has a differential input / output configuration, the input / output signal amplitude can be double that of a single input / output in terms of differential amplitude, By increasing the signal amplitude, it is possible to reduce the influence of the offset.

  The open / close control means 50 opens and closes the first and second input switches 11 and 21 based on a predetermined first quadrant open / close pattern every time the angular position of the digital angular position signal ωt changes by a predetermined unit angle. When the angle position changes by 90 degrees, the order of the first quadrant opening / closing pattern is reversed, and every time the angle position changes by 180 degrees, the first input to the positive input terminal 40a and the negative input terminal 40b Since the polarity of the output signal 41 is reversed by switching the connection between the first and second output terminals 10b and 20b, the output signal 41 in the first to fourth quadrants can be obtained using the first quadrant opening / closing pattern, and the circuit The configuration can be simplified. That is, the open / close pattern can be reduced to 1/4 compared to the case where the open / close pattern is used individually for all quadrants.

Embodiment 2. FIG.
FIG. 6 is a circuit diagram showing the switching control means of the pseudo sine wave generating circuit according to the second embodiment of the present invention. Note that portions that are the same as or equivalent to those in Embodiment 1 are described using the same reference numerals. In the first embodiment, the first bit cutout unit 51 configures the polarity switching unit 58, and a sine wave signal corresponding to the angular position of the digital angular position signal ωt is output as the output signal 41. By changing the configuration of the switching unit 58, a cosine wave signal corresponding to the angular position of the digital angular position signal ωt can be output as the output signal 41.

In FIG. 6, the polarity switching unit 58 includes the first and second bit cutout units 51 and 52 and an inverted EXOR unit 59. The inverted EXOR unit 59 is a logic circuit that outputs an inverted EXOR signal 59a of the first and second bits of the digital angular position signal ωt, and inputs the inverted EXOR signal 59a to the output-side control signal generation unit 57. . That is, in this embodiment, the control signal _{D m} is the inverted EXOR signal 59a, the control signal -D _m are those wherein the inverted EXOR signal 59a is inverted. As a result, the starting point of the angular position of polarity inversion of the output signal 41 can be shifted by 90 degrees compared to the circuit of the first embodiment, and a cosine wave signal can be output as the output signal 41. Other configurations are the same as those in the first embodiment.

  As described above, since the cosine wave signal can be output as the output signal 41 by the configuration of the polarity switching unit 58, the applicable range of the circuit can be expanded.

Embodiment 3 FIG.
Since the configuration of the pseudo sine wave multiplication circuit according to the third embodiment of the present invention is the same as the configuration of the pseudo sine wave generation circuit according to the first embodiment as a whole, FIG. 1 is used to describe the configuration. In the first and second embodiments, the first and second reference voltages 12 and 22 have been described as using DC voltages having a predetermined voltage value ± Vref. However, as the first and second reference voltages 12 and 22, Arbitrary analog signals having opposite polarities can also be used. Thus, by using arbitrary analog signals as the first and second reference voltages 12 and 22, the output signal 41 can have a waveform obtained by multiplying an arbitrary analog signal by a sine wave.

1 is a circuit diagram illustrating a pseudo sine wave generation circuit according to a first embodiment of the present invention. FIG. It is explanatory drawing which shows the output signal of FIG. It is explanatory drawing which shows the ideal sine wave of FIG. It is a circuit diagram which shows the opening / closing control means of FIG. 1 in detail. General operational amplifier circuit configuration It is a circuit diagram which shows the opening / closing control means of the pseudo sine wave generation circuit by Embodiment 2 of this invention.

Explanation of symbols

10 first ladder resistor network 10a ₀ 10 A _n-1 first input terminal 10b first output terminal 11 first input switch 12 first reference voltage 14 the first output switch 15 first input signal 20 and the second ladder resistance network 20a ₀ -20a _n-1 second input terminal 20b second output terminal 21 second input switch 22 second reference voltage 24 second output switch 25 second input signal 30 ground 40 operational amplifier 40a positive input terminal 40b negative input terminal 41 output signal 41a , 41b Differential output 50 Opening / closing control means ωt Digital angular position signal

Claims (5)

A first ladder resistor network (10) having a plurality of first input terminals (10a _{0 to} 10a _n-1 );
Connected to said first input terminal _{(10a 0 ~10a n-1)} , respectively connected to the each first input terminal _(10a 0 10 A _n-1) a first reference voltage (12) or ground (30) A first input switch (11);
The first ladder resistor network (10) is connected to the first output terminal (10b), and the first output terminal (10b) is connected to the positive input terminal (40a) or the negative input terminal (40b) of the operational amplifier (40). A first output switch (14) to
A second ladder resistor network (20) having a plurality of second input terminals (20a _{0 to} 20a _n-1 );
The second input to the second reference voltage (22) or the ground (30) connected to the second input terminals (20a _{0 to} 20a _n-1 ) and having a polarity opposite to that of the first reference voltage (12). A second input switch (21) for connecting the terminals (20a _{0 to} 20a _n-1 ) respectively;
A second output terminal (20b) of the second ladder resistor network (20) is connected, and the second output terminal (20b) is connected to the positive input terminal (40a) or the negative input terminal (40b). An output switch (24);
Open / close control means (50) connected to the first input switch (11), the first output switch (14), the second input switch (21), and the second output switch (24),
Based on a digital angle position signal (ωt) from the outside, the opening / closing control means (50) is configured to provide the first input switch (11), the first output switch (14), the second input switch (21), By performing open / close control of the second output switch (24), sinusoidal first and second input signals (15, 25) having polarities opposite to each other are converted into the first and second output terminals (10b, 10b, 20b) to the operational amplifier (40),
The pseudo-sine wave generating circuit, wherein the operational amplifier (40) differentially amplifies the first and second input signals (15, 25) and outputs an output signal (41) that changes in a sine wave shape. The opening / closing control means (50)
Each time the angular position of the digital angular position signal (ωt) changes by a predetermined unit angle, the first and second input switches (11, 21) are controlled to open / close based on a predetermined first quadrant opening / closing pattern,
Every time the angular position changes by 90 degrees, the order of the first quadrant opening / closing pattern is reversed,
Each time the angular position changes by 180 degrees, the connection of the first and second output terminals (10b, 20b) to the positive input terminal (40a) and the negative input terminal (40b) is switched to change the output signal (41). 2. The pseudo sine wave generating circuit according to claim 1, wherein the polarity of the sine wave is inverted.   The opening / closing control means (50) uses the digital angle position signal (ωt) as the output signal (41) by the opening / closing control based on the first quadrant opening / closing pattern and the polarity inversion of the output signal (41). 3. The pseudo sine wave generation circuit according to claim 2, wherein a sine wave signal or a cosine wave signal corresponding to the angular position is output.   The said operational amplifier outputs the 1st and 2nd differential output (41a, 41b) which has a mutually reverse polarity as said output signal (41), The any one of Claim 1 to 3 characterized by the above-mentioned. 2. The pseudo sine wave generation circuit according to item 1. Using the pseudo sine wave generating circuit according to any one of claims 1 to 4,
A pseudo sine wave multiplication circuit using arbitrary analog signals having opposite polarities as the first and second reference voltages (12, 22).

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