JP2009278125A - Copper interconnect wiring and method and apparatus for forming therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To cap a layer on a surface of a copper interconnect wiring layer for use in interconnect structures for integrated circuits and to provide a method and apparatus for forming improved integration interconnection structures for integrated circuits by the application of gas-cluster ion-beam processing. <P>SOLUTION: Reduced copper diffusion and improved electromigration lifetime result, and the use of selective metal capping techniques and their attendant yield problems are avoided. Various cluster tool configurations including gas-cluster ion-beam processing modules for copper capping, cleaning, etching, and film formation steps are disclosed. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention generally relates to an improved method and apparatus for forming an interconnect structure for a semiconductor integrated circuit by applying a capping layer on the surface of a copper interconnect wiring layer and a gas cluster ion beam (GCIB) process. About.

  Densification and the continued scaling of semiconductors by Moore's Law for further properties has resulted in significant productivity gains for industry and our society. However, the problem due to this scaling is that more current must flow through the smaller interconnect lines. When the current density and temperature in such fine wiring becomes extremely high, the interconnect wiring may be deteriorated by a phenomenon called electrophoresis. Due to the so-called “electronic window” effect that occurs in high current density interconnects, metal atoms are pushed out of their original lattice positions, and as a result, in the region where these diffused metal atoms gather, the wiring becomes open circuit or An extrusion short circuit occurs. By introducing copper as a wiring material instead of aluminum, a great improvement in the lifetime of electrophoresis can be obtained. However, the continued scaling of interconnect wiring suggests that additional improvements in copper electrophoretic lifetime will be required in the future.

  Unlike aluminum interconnects where problems arise due to diffusion of aluminum atoms along grain boundaries, the failure mode of copper interconnect electrophoresis is controlled by diffusion along the surface and interface. In particular, in the conventional interconnection structure of copper wiring, the upper surface of the copper wiring is usually covered with a dielectric cap layer. This dielectric cap layer has good diffusion barrier properties and needs to suppress migration of copper to the surrounding dielectric. The two most commonly used dielectric cap materials are silicon nitride and silicon carbonitride, which are typically deposited by plasma enhanced chemical vapor deposition (PECVD) techniques. Unfortunately, these PECVD cap materials form a defective interface with copper, which accelerates the migration of copper along the top surface of the copper interconnects, which The probability of failure increases. Typically, the other surface of the copper interconnect structure constitutes an interface with a barrier layer or bilayer layer (usually a metal such as TaN / Ta, Tan / Ru or Ru), which is between the copper and A strong interface is formed such that copper diffusion is suppressed, thereby suppressing the influence of electrophoresis. We refer to such a barrier or bilayer layer as a “barrier layer”. We refer to the layers of wiring interconnects as interconnect layers, wiring layers, or interlayer connection layers, each of the wiring interconnect layers having at least a layer of metal conductors, and also a low level substrate or lower interconnect. It has a layer of interlayer dielectric that insulates the metal conductor layer from the connection layer and from other metal conductors in the same layer of wiring interconnect.

  By capping the upper surface of the copper wiring, measures for improving the electrophoresis of the copper wiring with a selectively formed metal cap are being studied. In fact, it has been reported that when the top copper interface is capped by a selective tungsten or selective cobalt tungsten phosphorous (CoWP) metal layer, a significant improvement in the electrophoretic lifetime of copper is observed. Unfortunately, all methods that use selective metal caps have several possibilities for depositing some metal on adjacent insulator surfaces, which makes it possible to In addition, an unintended leak or short circuit may occur. The present invention uses a gas cluster ion beam processing process to solve many of these problems.

  FIG. 1 schematically illustrates a conventional silicon nitride interconnect structure 300 that caps copper interconnects, widely used in copper dual damascene integration processes. This includes a first copper wiring layer 302, a second copper wiring layer 304, and a copper via structure 306 connecting the two copper layers. The sidewalls and bottom portions of both wiring layers 302 and 304 and the via structure 306 are surrounded by a barrier layer 312. Barrier layer 312 provides excellent diffusion barrier properties, which suppresses the diffusion of copper into adjacent insulator structures and provides a significantly lower diffusion interface for copper. Electrophoresis along is suppressed. The first interlayer dielectric layer 308 and the second interlayer dielectric layer 310 provide insulation between the copper interconnects. The upper surface of the first copper wiring layer 302 and the upper surface of the second copper wiring layer 304 are respectively covered with insulating barrier films 314 and 316, which are usually made of silicon nitride or silicon carbonitride. The Conventionally, these insulating barrier films 314 and 316 are deposited by PECVD, and the interface they form with the exposed copper surface is defective and provides a fast diffusion path for the migration of copper atoms. In this conventional interconnect structure, almost all undesirable material movement occurs along these interfaces during copper electrophoresis. In such conventional dual damascene copper interconnects, at each interconnect level, after the formation of trenches and vias in the interlayer dielectric layer and subsequent formation of interconnect lines and vias by copper deposition Typically, the planarization step is performed using chemical mechanical polishing (CMP) techniques. In the planarization step, the barrier layer material is removed from the upper surface of the interlayer connection dielectric layer to form the upper surface of the copper wiring layer and the upper surface of the interlayer connection dielectric layer that is coplanar therewith. Both CMP and post-CMP brush cleaning processes use corrosion inhibitors, and these corrosion inhibitors and other contaminants are removed from the copper surface by in-situ cleaning prior to cap layer deposition. Need to be done. An ex-situ cleaning process may be used to leave the copper surface sensitive to corrosion and oxidation. PECVD reactants are typically not configured to perform an effective in-situ cleaning process on the copper surface prior to depositing the insulator cap layer. Although not shown in FIG. 1, wiring structure 300 is typically formed on a semiconductor structure having active and / or passive elements that require electrical interconnection to complete an integrated circuit.

  FIG. 2 shows a conventional selective metal-capped copper interconnect wiring structure 400. It has a first copper wiring layer 402, a second copper wiring layer 404, and a copper via structure 406 connecting the two copper layers. The side walls and bottom of both wiring layers 402 and 404 and the via structure 406 are all surrounded by the barrier layer 412. Barrier layer 412 provides excellent diffusion barrier properties, which suppress the diffusion of copper into the adjacent insulator structure and provides an excellent low diffusion interface between the copper and these interfaces. Along the electrophoresis is suppressed. The first interlayer dielectric layer 408 and the second interlayer dielectric layer 410 provide insulation between the copper interconnects. The upper surface of the first copper wiring layer 402 and the upper surface of the second copper wiring layer 404 are capped with selectively formed metal layers 414 and 416, respectively. It consists of either selective tungsten or selective CoWP deposited by chemical vapor deposition (CVD) or electroless technology. In this conventional dual damask copper interconnect, at each interconnect level, after formation of the interlevel dielectric layer trenches and vias and subsequent copper deposition, interconnect lines and vias are formed, and typically A planarization step is performed using chemical mechanical polishing (CMP) techniques. In the planarization step, the barrier layer material is removed from the upper surface of the interlayer dielectric layer to form the upper surface of the copper interconnect and the upper surface of the interlayer connection dielectric layer in the same plane. In both CMP and post-CMP brush cleaning processes, corrosion inhibitors are used, and these and other contaminants need to be removed from the copper surface before the cap layer is deposited. It has been reported that when either the tungsten or CoWP material layer caps the upper copper interface of the copper layer, a significant improvement in the electrophoretic lifetime of copper is obtained. Unfortunately, all solutions that provide selective material capping, for example, can deposit undesirable metal 418 on the adjacent insulator surface, resulting in a gap between adjacent metal lines. In addition, electrical leaks or short circuits can occur. Selective metal deposition techniques provide tremendous electrophoretic improvements, but these are not well implemented in manufacturing. This is because unfavorable film formation of contamination metal on the surface of the insulator adjacent to the interlayer dielectric layer is likely to reduce the yield of the semiconductor die. Although not shown in FIG. 2, the wiring structure 400 is typically configured on a semiconductor substrate having active and / or passive elements that require electrical interconnection to complete an integrated circuit.

  Gas cluster ion beams for treating surfaces are known (see, for example, US Pat. No. 5,814,194 to Deguchi et al.). As used herein, the term gas cluster refers to an aggregate of nano-sized material that is a gas at standard temperature and pressure conditions. Such gas clusters usually consist of weakly bound aggregates of several to thousands of molecules, forming gas clusters. The gas clusters are ionized by electron impact or other means, which form a guided beam of controllable energy. Each such ion typically carries a positive charge of q · e, where e is the charge of the electron and q is a number from 1 to several values representing the charge state of the gas cluster ion. Is an integer up to). Non-ionized gas clusters may be present in the gas cluster ion beam. Large size gas cluster ions are often most beneficial because they can carry a significant amount of energy per unit gas cluster ion, but may have only moderate energy per unit molecule. The gas clusters are separated by collision, and each individual molecule carries only a small portion of the total gas cluster ion energy. As a result, the impact effect of large gas cluster ions is substantial, but this is limited to a very narrow surface area. For this reason, gas cluster ions are effective in many surface modification treatment processes, and do not cause deep damage below the surface as in the conventional monomolecular ion beam treatment process. Means for forming and accelerating such a GCIB is shown in the aforementioned document (US 5,814,194). Currently available gas cluster ion sources form gas cluster ions having a wide size distribution N (where N is the number of molecules of each gas cluster ion, and in this application is a monomolecular gas such as argon) The atoms of a monoatomic gas are referred to as molecules, and the ionized atoms of such monomolecular gases are referred to as molecular ions, or simply referred to as monomolecular ions). Many beneficial surface treatment process effects can be obtained by surface impact by the GCIB method. These processing process effects include, but are not necessarily limited to, cleaning, smoothing, etching, doping, and film formation or growth. U.S. Pat. No. 6,537,606 to Allen et al. Shows that GCIB is used to improve the spatial uniformity of the initial non-uniform thin film modified etch process. The contents of US Pat. No. 6,537,606 are incorporated herein by reference.

During the collision of energetic gas clusters with the solid target surface, the entry of cluster atoms into the target surface is usually very slight. This is because the penetration depth is limited by the low energy of each individual constituent atom, and in principle depends on the effect of transitional (transient) heat that occurs during gas cluster ion collisions. The gas clusters are separated upon impact, and individual gas atoms can then be freely reflected and escape from the target surface. Except for the energy dissipated by the dissipation of individual gas atoms, the total energy of the active cluster prior to collision is imparted to the collision area of the target surface. The size of the target collision area depends on the energy of the clusters, but depends on the order of the cross-sectional dimensions of the colliding clusters, which is, for example, about 30 angstroms in diameter for a cluster of 1000 atoms. Since most of the total energy carried by the cluster is applied to the micro-collision region of the target, large heat is transiently generated at the target material collision site. Transient heat is quickly dissipated and energy is dissipated from the collision area by transmission deep inside the target. The time of transient heat is determined by the conductivity of the target material, but is usually less than ^10-6 seconds.

  In the vicinity of the gas cluster collision site, a portion of the target surface instantaneously reaches a temperature of several hundred to several thousand K. For example, in the collision of a gas cluster carrying a total energy of 10 keV, it is expected that the temperature will increase instantaneously by about 2000 K in a nearly hemispherical region over about 100 angstroms under the surface due to intense stigma. . This high transient heat accelerates the intermixing and / or reaction of the sample and the gas cluster ion beam structure, resulting in improved electrophoretic lifetime.

  After the generation of hot transient heat within the target portion below the active gas cluster collision site, the affected area is rapidly cooled. Some gas cluster constructs dissipate during this treatment process, while others remain behind and are incorporated into the surface. Further, the original surface material portion is removed by the influence of sputtering or the like. In general, highly volatile and inert components of gas clusters tend to dissipate more, and less volatile and more chemically reactive components tend to be incorporated on the surface. Although the actual processing process is more complex, it is preferred to refer to the impact sites and surrounding areas of the gas cluster as the “melt zone” where the gas cluster atoms can easily interact with the substrate surface. Acting and mixing, the gas cluster material escapes from the surface or is introduced in the depth direction of the affected area from the surface. The terms “introducing” or “introducing” are used by the inventors of the present invention to describe this processing process, which is distinct from ion “implantation” or “implantation processing”. The result is very different from ion “implantation”. The noble gases in the active gas cluster ions, such as argon and xenon, are volatile, non-reactive, and dissipate with high probability from the affected area, whereas for example carbon, boron, fluorine, sulfur Materials such as nitrogen, oxygen, germanium and silicon tend to be less volatile and / or prone to form chemical bonds, stay in the affected area and tend to be incorporated into the substrate surface .

  For example, but not limited to, inert noble gases such as argon and xenon can be mixed with gases containing less volatile and / or more reactive elements, in which case mixing A cluster is formed. Such a gas cluster is obtained by using an existing gas cluster ion beam processing apparatus shown below, by using an appropriate source mixed gas as a source gas for generating the gas cluster ion beam, or by 2 or 3 or more It can be formed by supplying a gas (or mixed gas) to a gas cluster generation source and mixing them in the source source. In a recent publication by Borland et al. ("USJ and strained Si formation using introduced dopants and deposition processes", Solid State Technology, p53, March 2004) This layer has been shown to transition smoothly from the substrate material to the surface deposition layer.

  Accordingly, it is an object of the present invention to provide a method for capping copper interconnects in an interconnect structure that does not require the use of a selective metal deposition cap to suppress sensitivity to undesirable electrophoretic effects. It is.

  Another object of the present invention is to provide a method for effectively capping copper interconnects in an interconnect structure without affecting the insulation or leakage characteristics of adjacent dielectric materials.

  Another object of the present invention is to provide a method of forming a multi-level copper interconnect for a circuit having a high process process yield and reduced sensitivity to failure due to electrophoresis effects.

  Yet another object of the present invention is to provide an improved capped copper interconnect layer for integrated circuits with high process process yield and reduced sensitivity to electrophoretic failures.

  It is yet another object of the present invention to provide an improved apparatus for implementing improved capping on copper interconnect structures for integrated circuits. According to the method of the present invention, undesirable contamination can be suppressed by an integration processing step in a cluster tool configured to perform at least one step of the method by a gas cluster ion beam processing process.

In one embodiment of the invention,
A method of forming a capped structure on a structure having one or more copper interconnect surfaces and one or more surfaces of a barrier layer material covering a dielectric material comprising:
Installing the structure in a vacuum chamber;
Forming an accelerated capping GCIB in the vacuum chamber;
The accelerated capping GCIB on at least one of the one or more copper interconnect surfaces and on at least one of the one or more surfaces of the barrier layer material covering the dielectric material. , Wherein the accelerated capping GCIB is induced on the one or more copper interconnect surfaces and at least one on the one or more copper interconnect surfaces. A step of forming a capped structure;
Is provided.

The barrier layer material has a first thickness;
The inducing step further comprises introducing an introduction layer on at least one of the one or more surfaces of the barrier layer material covering the dielectric material;
The introduction layer may have a second thickness that is less than the first thickness. The method may further comprise the step of etching away the introduction layer and the barrier layer material covering the dielectric material. The etching and removing step further includes:
Forming an accelerated etching process GCIB in the vacuum chamber;
Inducing the accelerated etching process GCIB on at least one surface of the barrier layer material covering the dielectric material;
You may have.

The method further includes the steps of forming and guiding the capping GCIB,
Forming an accelerated cleaning process GCIB in the vacuum chamber;
The accelerated cleaning treatment GCIB is applied to at least one of the one or more copper interconnect surfaces and at least one of the one or more surfaces of the barrier layer material covering the dielectric material. A guiding step;
Have
The accelerated cleaning treatment GCIB may be guided to the one or more surfaces, and the one or more surfaces may be cleaned. The step of forming the accelerated cleaning treatment GCIB further generates gas cluster ions from at least one gas molecule selected from the group consisting of Ar, N ₂ , NH ₃ , and H ₂ You may have the step to do. The step of forming the accelerated cleaning process GCIB may further comprise accelerating the cleaning process GCIB gas cluster ions with an acceleration potential in the range of about 3 kV to about 50 kV. Deriving at least one of the one or more copper interconnect surfaces and at least one or more surfaces of the barrier layer material covering the dielectric material by inducing the accelerated capping GCIB. For example, an irradiation dose in the range of about 1 × 10 ¹⁴ to about 1 × 10 ¹⁷ gas cluster ions / cm ² may be provided.

The method may further comprise forming at least one insulating layer covering the formed at least one capped structure. The step of forming at least one insulating layer may utilize a PECVD film forming process. The at least one insulating layer to be formed may have one material selected from the group consisting of silicon carbide, silicon nitride, and silicon carbonitride. Forming at least one insulating layer covering the at least one capped structure further comprises:
Forming an accelerated deposition GCIB in the vacuum chamber;
Inducing the accelerated deposition GCIB on the one or more copper interconnect surfaces, wherein the at least one insulating layer is formed;
You may have. The at least one insulating layer covering the at least one capping structure may be a dielectric diffusion barrier film.

In another embodiment of the invention, a cluster tool is provided for processing at least one wafer in a reduced pressure environment, the cluster tool comprising:
At least one lock for moving the at least one wafer into and / or out of the cluster tool;
At least one transfer chamber;
At least one GCIB processing chamber;
At least one cleaning process chamber;
At least one wafer transfer device adapted to transfer said at least one wafer from chamber to chamber;
You may have.

  The GCIB processing chamber is adapted to perform a copper capping process on at least a portion of the at least one wafer, and the cleaning process chamber performs a cleaning process prior to the copper capping process. It may be adapted to perform. The GCIB processing chamber may be adapted to form a dielectric diffusion barrier film on at least a portion of the at least one wafer.

In yet another embodiment of the present invention, a cluster tool for processing at least one wafer in a reduced pressure environment, comprising:
At least one lock for moving the at least one wafer into and / or out of the cluster tool;
At least one transfer chamber;
At least one GCIB processing chamber;
At least one deposition chamber;
At least one wafer transfer device adapted to transfer said at least one wafer from chamber to chamber;
A cluster tool is provided.

  The GCIB processing chamber is adapted to perform a copper capping process on at least a portion of the at least one wafer, and the deposition chamber is on a capped copper of at least a portion of the at least one wafer. In addition, it may be adapted to form a dielectric diffusion barrier film. The film forming chamber may be a PECVD film forming chamber. The GCIB processing chamber may be adapted to perform a cleaning process prior to the copper capping process.

In yet another embodiment of the present invention, a cluster tool for processing at least one wafer in a reduced pressure environment, comprising:
At least one lock for moving the at least one wafer into and / or out of the cluster tool;
At least one transfer chamber;
At least one GCIB processing chamber;
At least one deposition chamber;
At least one cleaning process chamber;
At least one wafer transfer device adapted to transfer said at least one wafer from chamber to chamber;
A cluster tool is provided.

  The GCIB processing chamber is adapted to perform a copper capping process on at least a portion of the at least one wafer, and the cleaning process chamber performs a cleaning process prior to the copper capping process. It may be adapted to perform. The GCIB processing chamber is adapted to perform a copper capping process on at least a portion of the at least one wafer, and the deposition chamber forms a dielectric diffusion barrier film on the capped copper. May be adapted as such. The film forming chamber may be a PECVD film forming chamber. The cleaning process chamber may be a plasma cleaning process chamber. The GCIB processing chamber may be adapted for forming a dielectric diffusion barrier film. The GCIB processing chamber may be adapted to clean at least a portion of the at least one wafer.

In yet another embodiment of the present invention, a cluster tool for processing at least one wafer in a reduced pressure atmosphere comprising:
At least one lock for moving the at least one wafer into and / or out of the cluster tool;
Multiple GCIB processing chambers;
At least one wafer transfer device adapted to transfer said at least one wafer from chamber to chamber;
A cluster tool is provided.

  The GCIB processing chamber is adapted to perform a copper capping process on at least a portion of the at least one wafer, and the GCIB processing chamber forms a dielectric diffusion barrier film on the capped copper. May be adapted to do. The GCIB processing chamber is adapted to perform a copper capping process on at least a portion of the at least one wafer, and the GCIB processing chamber performs a cleaning process prior to the copper capping process. May be adapted to do. The GCIB processing chamber is adapted to perform a copper capping process on at least a portion of the at least one wafer, and the GCIB processing chamber performs a cleaning process prior to the copper capping process. And the GCIB processing chamber may be adapted to form a dielectric diffusion barrier film over the capped copper.

In yet another embodiment of the present invention, a method for forming a capped structure on a structure having one or more copper interconnect surfaces and one or more dielectric surfaces comprising:
Installing the structure in a vacuum chamber;
Forming an accelerated capping GCIB in the vacuum chamber;
Inducing the accelerated capping GCIB on at least one of the one or more copper interconnect surfaces and the one or more dielectric surfaces, comprising: Inducing the accelerated capping GCIB on a surface to form at least one capped structure on the one or more surfaces;
Is provided.

  The step of forming the accelerated capping GCIB further comprises an electrically insulating material when introduced to the copper surface and from an element that forms the electrically insulating material when introduced to the dielectric surface, There may be the step of generating gas cluster ions, and the formed at least one capped structure is an electrically insulating capped structure.

Forming the accelerated capping GCIB further comprises:
Comprising a conductive material when introduced on the copper surface, and generating gas cluster ions from elements constituting the electrically insulating material when introduced on the dielectric surface;
The at least one capped structure formed is at least one of a conductive capping structure on the irradiated region of the copper interconnect portion and an electrically insulating capped structure on the irradiated region of the dielectric portion. You may have. The step of forming the accelerated capping GCIB further comprises the step of generating gas cluster ions from a noble gas or mixed noble gas, wherein the at least one capped structure formed is the copper interconnect. The irradiation region of the portion may have at least a conductive capping structure.

  The step of forming the accelerated capping GCIB further includes the step of generating gas cluster ions from Ar, Xe, or a mixed gas of Ar and Xe, wherein the at least one capped structure formed is The irradiated region of the copper interconnect portion may have at least a conductive capping structure.

In yet another embodiment of the invention,
A method of forming a copper capping structure on an integrated circuit interconnect layer having one or more copper interconnect surfaces and one or more dielectric layer regions coated with a barrier layer material. There,
Forming at least one capped structure on the one or more copper interconnect surfaces;
After the step of forming at least one capped structure on the one or more copper interconnect surfaces, the barrier layer material covering at least one of the one or more dielectric layer regions is removed. Steps,
Is provided. The forming step further comprises: forming an accelerated capping GCIB; inducing the accelerated capping GCIB on at least one of the one or more copper interconnect surfaces; You may have. The removing step may include forming an accelerated etching process GCIB and inducing the accelerated etching process GCIB in the barrier layer material.

In yet another embodiment of the invention,
A method of forming a copper capping structure on an integrated circuit interconnect layer having one or more copper interconnect surfaces and one or more dielectric layer regions coated with a barrier layer material. There,
Forming an accelerated capping GCIB using a first beam acceleration potential;
Directing the accelerated capping GCIB to at least one of the one or more copper interconnect surfaces, wherein at least one capping is applied to the one or more copper interconnect surfaces. A step in which a structure is formed;
Forming an accelerated etching process GCIB using a second beam acceleration potential lower than the first beam acceleration potential;
Inducing the accelerated etching process GCIB on the at least one capped structure and on the barrier layer material, the barrier layer material being removed; and
Is provided.

In yet another embodiment of the invention,
A method of forming a copper capping structure on an integrated circuit interconnect layer having one or more copper interconnect surfaces and one or more dielectric layer regions coated with a barrier layer material. There,
Forming an accelerated capping GCIB;
Directing the accelerated capping GCIB to at least one of the one or more copper interconnect surfaces, wherein at least one capping is applied to the one or more copper interconnect surfaces. A step in which a structure is formed;
Forming an accelerated etching process GCIB;
Directing the accelerated etching process GCIB on the at least one capped structure and on the barrier layer material, wherein all of the at least one capped structure is not removed and the 1 or Removing the barrier layer material covering at least one of the two or more dielectric layer regions;
Is provided.

In yet another embodiment of the invention,
An integrated circuit interconnect layer having one or more capped copper interconnect surfaces and one or more dielectric layer regions comprising:
An integrated circuit interconnect layer is provided that is fabricated by one or more steps of the foregoing method.

In yet another embodiment of the invention,
An integrated circuit interconnect layer having one or more capped copper interconnect surfaces and one or more dielectric layer regions comprising:
An integrated circuit interconnect layer is provided that is fabricated by one or more steps of the foregoing method.

In yet another embodiment of the invention,
A method of processing a semiconductor wafer in a cluster tool system while maintaining the cluster tool system in a reduced pressure environment,
In a first GCIB processing chamber of the cluster tool, using a GCIB process, forming a capping layer on the copper interconnect surface on the semiconductor wafer and the barrier layer material surface covering the dielectric material;
Transferring the semiconductor wafer from the first GCIB processing chamber to the second GCIB processing chamber of the cluster tool in the reduced pressure environment of the cluster tool;
Removing the barrier layer from the dielectric layer using a GCIB etching process in the second GCIB processing chamber;
Is provided.

The method further includes, prior to the forming step,
Cleaning the copper interconnect surface and the barrier layer material surface using a cleaning process in a third processing chamber of the cluster tool;
Transferring the semiconductor wafer from a third processing chamber of the cluster tool to a first GCIB processing chamber of the cluster tool in the reduced pressure environment of the cluster tool;
You may have. The third processing chamber of the cluster tool may be a GCIB processing chamber, and the cleaning process may include a GCIB cleaning process.

In yet another embodiment of the invention,
A method of processing a semiconductor wafer in a cluster tool system while maintaining the cluster tool system in a reduced pressure environment,
Forming a capping layer on a copper interconnect surface on a semiconductor wafer and on a dielectric material using a GCIB process in a first GCIB processing chamber of the cluster tool;
Transferring the semiconductor wafer from the first GCIB processing chamber to the second processing chamber of the cluster tool in the reduced pressure environment of the cluster tool;
Forming a dielectric diffusion barrier film on the capping layer using a dielectric film formation process in the second processing chamber of the cluster tool;
Is provided.

The method further includes prior to the forming step,
Cleaning the copper interconnect surface and the barrier layer material surface using a cleaning process in a third processing chamber of the cluster tool;
Transferring the semiconductor wafer from a third processing chamber of the cluster tool to a first GCIB processing chamber of the cluster tool in the reduced pressure environment of the cluster tool;
You may have. The third processing chamber of the cluster tool may be a GCIB processing chamber, and the cleaning process may include a GCIB cleaning process. The second processing chamber of the cluster tool may be a GCIB processing chamber, and the dielectric film formation processing process may include a GCIB introduction processing process.

It is the figure which showed schematically the conventional silicon nitride capped copper interconnection wiring structure. FIG. 6 schematically illustrates a conventional selective metal-capped copper interconnect wiring structure. It is the figure which showed schematically the basic element of the conventional GCIB processing apparatus. FIG. 3 is a diagram schematically showing a copper interconnection capping process by the GCIB introduction method according to the first embodiment of the present invention. FIG. 3 is a diagram schematically showing a copper interconnection capping process by the GCIB introduction method according to the first embodiment of the present invention. FIG. 3 is a diagram schematically showing a copper interconnection capping process by the GCIB introduction method according to the first embodiment of the present invention. FIG. 3 is a diagram schematically showing a copper interconnection capping process by the GCIB introduction method according to the first embodiment of the present invention. FIG. 3 is a diagram schematically showing a copper interconnection capping process by the GCIB introduction method according to the first embodiment of the present invention. FIG. 6 is a diagram schematically showing a copper interconnection capping process using a GCIB introduction process and a film forming process according to a second embodiment of the present invention. FIG. 6 is a diagram schematically showing a copper interconnection capping process using a GCIB introduction process and a film forming process according to a second embodiment of the present invention. FIG. 6 is a diagram schematically showing a copper interconnection capping process using a GCIB introduction process and a film forming process according to a second embodiment of the present invention. FIG. 6 is a diagram schematically showing a copper interconnection capping process using a GCIB introduction process and a film forming process according to a second embodiment of the present invention. FIG. 6 is a diagram schematically showing a copper interconnection capping process using a GCIB introduction process and a film forming process according to a second embodiment of the present invention. FIG. 6 is a diagram schematically showing a copper interconnection capping process using a GCIB introduction process and a film forming process according to a second embodiment of the present invention. FIG. 6 is a diagram schematically showing a copper interconnection capping process using a GCIB introduction process and a film forming process according to a second embodiment of the present invention. FIG. 6 is a diagram schematically showing a copper interconnection capping process using a GCIB introduction process and a film forming process according to a second embodiment of the present invention. FIG. 6 is a diagram schematically showing a copper interconnection capping process using a GCIB introduction process and a film forming process according to a second embodiment of the present invention. FIG. 6 is a diagram schematically showing a copper interconnection capping process using a GCIB introduction process and a film forming process according to a second embodiment of the present invention. FIG. 6 is a diagram schematically showing a copper interconnection capping process using a GCIB introduction process and a film forming process according to a second embodiment of the present invention. FIG. 6 is a diagram schematically showing a copper interconnection capping process using a GCIB introduction process and a film forming process according to a second embodiment of the present invention. FIG. 6 is a diagram schematically showing a copper interconnection capping process using a GCIB introducing process and a film forming process according to a third embodiment of the present invention. FIG. 6 is a diagram schematically showing a copper interconnection capping process using a GCIB introducing process and a film forming process according to a third embodiment of the present invention. FIG. 6 is a diagram schematically showing a copper interconnection capping process using a GCIB introducing process and a film forming process according to a third embodiment of the present invention. FIG. 6 is a diagram schematically showing a copper interconnection capping process using a GCIB introducing process and a film forming process according to a third embodiment of the present invention. FIG. 6 is a diagram schematically showing a copper interconnection capping process using a GCIB introducing process and a film forming process according to a third embodiment of the present invention. FIG. 6 is a diagram schematically showing a copper interconnection capping process using a GCIB introducing process and a film forming process according to a third embodiment of the present invention. FIG. 6 is a diagram schematically showing a copper interconnection capping process using a GCIB introducing process and a film forming process according to a third embodiment of the present invention. FIG. 10 is a diagram schematically showing a copper interconnection capping process using a GCIB introduction process and a film forming process according to a fourth embodiment of the present invention. FIG. 10 is a diagram schematically showing a copper interconnection capping process using a GCIB introduction process and a film forming process according to a fourth embodiment of the present invention. FIG. 10 is a diagram schematically showing a copper interconnection capping process using a GCIB introduction process and a film forming process according to a fourth embodiment of the present invention. FIG. 10 is a diagram schematically showing a copper interconnection capping process using a GCIB introduction process and a film forming process according to a fourth embodiment of the present invention. FIG. 10 is a diagram schematically showing a copper interconnection capping process using a GCIB introduction process and a film forming process according to a fourth embodiment of the present invention. FIG. 10 is a diagram schematically showing a copper interconnection capping process using a GCIB introduction process and a film forming process according to a fourth embodiment of the present invention. FIG. 10 is a diagram schematically showing a copper interconnection capping process using a GCIB introduction process and a film forming process according to a fourth embodiment of the present invention. FIG. 2 schematically illustrates an example cluster tool that may be used in some example embodiments of the present invention. FIG. 2 schematically illustrates an example cluster tool that may be used in some example embodiments of the present invention. It is the figure which showed the table | surface which shows the example from which the Example of this application differs.

  For a better understanding of the present invention, together with other objects, the present invention will now be described in detail with reference to the accompanying drawings.

  FIG. 3 schematically shows basic elements of a typical configuration of a conventional GCIB processing apparatus. This shows the following: The vacuum vessel 102 is divided into three communicating chambers: a source chamber 104, an ionization / acceleration chamber 106, and a processing chamber 108. Each of the three chambers is depressurized to an appropriate operating pressure using vacuum pump systems 146a, 146b, and 146c. The first gas storage cylinder 111 stores a first condensable source gas 112 (for example, argon, nitrogen, or a premixed mixed gas), and the first gas storage cylinder 111 includes the first gas storage cylinder 111. The gas shut-off valve 115, the first gas measurement valve 113, and the gas supply pipe 114 are connected to the stagnation chamber 116 under a pressure environment. The second gas storage cylinder 230 stores an optional second condensable source gas 232 (eg, carbon dioxide, oxygen, or a premixed gas mixture), and the second gas storage cylinder 230 The second gas shut-off valve 236 and the second gas measurement valve 234 are connected in a pressure environment. If both source gases are used, they are mixed in the gas supply line 114 and stagnant chamber 116. The gas or gas mixture in the stagnation chamber 116 is released at a substantially low pressure through a properly shaped nozzle 110. An ultrasonic gas jet 118 is produced. Due to the cooling phenomenon resulting from jet expansion, a portion of the gas jet 118 aggregates into gas clusters, each of which is composed of weak bonds of several to thousands of atoms or molecules. The gas skimmer aperture 120 partially separates gas molecules from the gas cluster jet that have not been condensed into the gas cluster jet, such that downstream regions where such high pressure is undesirable (e.g., ionizer 122, high voltage electrode 126, and The pressure in the processing chamber 108) is minimized. Suitable condensable source gases 112 may include, but are not necessarily limited to, argon, nitrogen, carbon dioxide, oxygen, and other gases and / or mixed gases.

After the ultrasonic gas jet 118 containing the gas cluster is formed, the gas cluster is ionized in the ionizer 122. The ionizer 122 is typically an electron impact ionizer that forms thermal electrons from one or more incandescent filaments 124 that accelerate the electrons so that they collide with gas clusters within the gas jet 118. Induce. Thereafter, the jet is discharged from the ionizer 122. Electron collision causes electrons to be emitted from the gas cluster, whereby a part of the gas cluster is positively ionized. Some gas clusters emit more than one electron and may be multivalently ionized. A set of appropriately biased high voltage electrodes 126 extract gas cluster ions from the ionizer and beams are formed, after which these beams are accelerated (typically from hundreds of volts to tens of kV). GCIB128 is formed by accelerating and focusing to the desired energy. The filament power supply 136 provides a filament voltage V ₁ and the ionizer filament 124 is heated. The anode power supply 134 provides an anode voltage V _A , thereby accelerating the thermoelectrons emitted from the filament 124 and irradiating the gas head 118 including the gas clusters to form ions. Extraction power 128 provides extracted voltage V _E to bias the high voltage electrode, by which the ions are extracted from the ionization region of ionizer 122, GCIB 128 is formed. The accelerator power supply 140 provides the ionizer 122 with an acceleration voltage V _ACC that biases the high voltage electrode, thereby making the total GCIB acceleration potential equal to V _ACC . One or more lens power supplies (eg 142, 144) may be provided, and the high voltage electrode may be biased by a focusing voltage (eg V _L1 and V _L2 ), thereby focusing the GCIB 128.

  The sample 152 may be a semiconductor wafer or other sample processed by a GCIB processing process, and this sample is held by a sample holder 150 disposed in the path of the GCIB 128. For most applications, it is assumed that large samples that are spatially uniform will be processed, so the scanning system preferably scans GCIB128 uniformly over a large area, resulting in spatially uniform results. It is done.

  The GCIB 128 is stationary and has a GCIB axis 129, and the sample 152 is mechanically scanned through the GCIB 128 to distribute the effects of the GCIB 128 across the surface of the sample 152.

  The X-scan actuator 202 provides the sample holder 150 with a linear motion in the X-scan movement direction 208 (direction entering and exiting the page). The Y-scan actuator 204 provides the sample holder 150 with a linear movement in the Y-direction scan movement direction 210, which is orthogonal to the X-scan movement direction 208. Due to the combination of X scan and Y scan, the sample 152 held by the sample holder 150 moves during the raster scan movement through the GCIB 128, and the sample 152 is processed onto the surface of the sample 152 by the GCIB 128 for processing the sample 152. Uniform (or programmed) irradiation is possible. The sample holder 150 causes the sample 152 to be inclined with respect to the axis of the GCIB 128, so that the GCIB 128 has a beam incident angle 206 with respect to the surface of the sample 152. The beam incident angle 206 may be 90 ° or another angle, but is usually 90 ° or an angle close to 90 °. During the Y scan, the sample 152 and sample holder 150 move from the position indicated by the alternative position “A” indicated by 152A and 150A, respectively. Note that during movement between the two positions, the sample 152 is scanned through the GCIB 128, and at both final positions, the sample 152 moves completely out of the path of the GCIB 128 (overscan). There is a need. Although not explicitly shown in FIG. 3, a similar scanning scheme and overscan is performed in the (usually) orthogonal X-scan movement direction 208 (direction entering and exiting the page).

  A beam current sensor 218 is installed above the sample holder 150 in the GCIB 128 path, and this sensor blocks the GCIB 128 sample when the sample holder 150 is scanned out of the GCIB 128 path. The beam current sensor 218 is usually a Faraday cap or the like, and is closed except for a beam incident opening. In a normal case, the beam current sensor 218 is installed on the wall of the vacuum vessel 102 using an electrically insulating mount 212.

  A controller 220, which may be a control system microcomputer, is connected to the X-scan actuator 202 and the Y-scan actuator 204 via an electric cable 216, controls the X-scan actuator 202 and the Y-scan actuator 204, and controls the sample 152. Is placed inside or outside the GCIB 128, so that the sample 152 is uniformly scanned with respect to the GCIB 128, and the sample 152 is subjected to a desired processing process by the GCIB 128. Controller 220 receives sampled beam current collected by beam current sensor 218 via lead 214, thereby removing sample 152 from GCIB 128 when a predetermined desired dose is being delivered. Thus, the GCIB is monitored, and the GCIB dose received by the sample 152 is controlled.

  FIG. 4A schematically shows a wiring structure 500 for copper interconnection capping using the GCIB introduction process according to the first embodiment of the present invention (for example, but not limited to 2 Two copper wiring layer interconnect levels are shown). This scheme shows a substrate 501 that supports a first copper wiring layer 502, a second copper wiring layer 504, and a copper via structure 506 that connects the two copper layers, each layer being conventional It may be formed using this technique. The substrate 501 is typically a semiconductor substrate and has active and / or passive elements that require electrical interconnection (including the lower interconnect level where possible). The sidewalls and bottom of both copper wiring layers 502 and 504, as well as via structure 506, are surrounded by TaN / Ta or other conventional barrier layer 512, which is constructed using conventional techniques. Also good. The first interlayer dielectric layer 508 and the second interlayer dielectric layer 510 provide electrical insulation between the copper wiring layer and other members, these layers using conventional techniques It may be formed. The upper surface of the first copper wiring layer 502, the upper surface of the first intermediate dielectric layer 508, the upper surface of the second copper wiring layer 504, and the upper surface of the second interlayer dielectric layer 510 are all GCIB. Cap films 514, 516, and 518 are formed by the capping process. A separate GCIB capping process is preferably performed on the upper surface of each interconnect level. In conventional dual-mask mask interconnections, typically the exposed copper and interlayer dielectric layer material after formation of the trenches and vias in the interlayer dielectric layer and subsequent deposition of copper to form the interconnect wiring and vias. A planarization step is performed on the surface using chemical mechanical polishing (CMP) techniques. During both the CMP technique and the post-CMP brush cleaning process, a corrosion inhibitor is used on the surface to be polished, which is achieved by an in-situ cleaning process just prior to the formation of the cap layer, resulting in copper and dielectric Is preferably removed from the surface (along with other contaminants) (as used herein, “in-situ”) means that the cap or cap is not returned to atmospheric pressure during the cleaning and capping steps. This means that cleaning is performed in the same reduced-pressure atmosphere as when film formation is performed, and the opportunity for re-contamination on the cleaned surface is suppressed between the cleaning step and the capping step).

  PECVD reactors are typically not configured to perform an effective in-situ cleaning of the copper surface prior to the formation of the insulating capping layer. Unlike PECVD systems, for example, GCIB processing systems, such as processing equipment 100, are simple and are typically configured to perform subsequent cleaning and capping processes in-situ. After any conventional dry cleaning process, or preferably a process such as the GCIB process described above, is performed and the exposed copper and interlayer dielectric layer surfaces are cleaned, preferably in-situ GCIB An introduction process is performed and the planarized surface is capped (at the same time as the copper and exposed interlayer dielectric layer).

FIG. 4B shows a preliminary stage 500B of the wiring structure 500. At the stage shown, an interconnect level is formed on the substrate 501. The interconnect level has a first interlayer dielectric 508, which is deposited on the substrate using conventional techniques. Conventional trenches and vias are formed in the first interlayer dielectric 508 and are surrounded by a conventional barrier layer 512. Copper is deposited in the trenches and vias using conventional techniques. The top surface of this structure is planarized and cleaned using conventional processing processes. The upper surfaces of the first copper wiring layer 502 and the first interlayer dielectric layer 508 have a residual contamination material 503. This stage, and the corresponding stage of each subsequent interconnect level (assuming more than one interconnect level) is preferably in-situ, eg, a conventional dry cleaning process, a plasma cleaning process, Alternatively, a GCIB cleaning process may be performed. The GCIB cleaning process involves irradiating the surface to be cleaned with GCIB cluster ions composed of gas molecules such as Ar, N ₂ , NH ₃ , H ₂ , or a mixture of these, and approximately 5 × 10 ^Using a beam acceleration potential V _ACC preferably in the range of about 3 kV to about 50 kV, with a total gas cluster ion dose in the range of ¹³ to about 5 × 10 ¹⁶ ions / cm ² . The present invention is not limited to these gas examples, and may be practiced with other gases or mixed gases that remove post-CMP residues, copper oxide, and other contaminants from the copper surface. It will be apparent to those skilled in the art. Although not the essence of the present invention, the GCIB cleaning process is preferably an in-situ cleaning process.

FIG. 4C shows stage 500 of wiring structure 500 following the GCIB cleaning process. Contaminants are removed from the upper surfaces of the first copper wiring layer 502 and the first interlayer dielectric layer 508, and the capping step is prepared. At this stage, and at the corresponding stage of each subsequent interconnect level (assuming more than one interconnect level), a GCIB capping process is performed. When the GCIB capping process is introduced into the original exposed dielectric and / or copper surface, the first copper wiring layer 502 and / or the first copper is formed using GCIB composed of an element that forms an insulating material. Illuminating the top surface of the interlevel dielectric layer 508. For example, GCIB having a gas cluster ion element composed of C, N, O, Si, B, Ge, or a mixture thereof is preferred, which can be formed on copper, for example, Si ₃ N ₄ , SiCN, CuCO. _3. Form an inclined capping film such as BN. Other elements and combinations that form suitable dielectric materials may be utilized upon introduction into copper and / or adjacent insulators. For example, source gases such as CH ₄ , SiH ₄ , NH ₃ , N ₂ , CO ₂ , B ₂ H ₆ , GeH ₄ , and mixtures thereof may be used. By using such gases or by mixing them with an inert gas such as Ar or Xe, their pure form of cluster ions is formed. Referring to the GCIB processor 100 of FIG. 3, a beam acceleration potential V _ACC that is in the range of about 3 kV to about 50 kV is used, and the total gas cluster ion dose that occurs is about 1 × 10 ¹⁴ to 1 × 10 ¹⁷ ions. / Cm ² range.

FIG. 4D shows a stage 500D of the wiring structure 500 following the GCIB capping process. On the copper surface and / or the adjacent interlayer dielectric layer surface, collision energy and transient heat characteristic of GCIB treatment are introduced into the upper surface of the copper wiring and / or the adjacent interlayer dielectric layer structure exposed to the GCIB. And capping layers 514 and 516 are formed, respectively. The capping layers 514 and 516 may each optionally have an upper layer portion that functions as a dielectric barrier film, if desired. During the initial portion of the formation process, a gradient layer 514A of mixed copper / GCIB species composition is introduced on the copper surface. This mixed layer provides a tilted interface between any subsequent deposited dielectric barrier film 514B and the underlying copper, thereby suppressing copper diffusion at the interface and improving electrophoretic lifetime. The dielectric barrier layer 514B to be formed thereafter may be a film separately formed by conventional PECVD, but this may be formed by GCIB as a continuation of the GCIB capping introduction step. It is preferred that a mere capped GCIB irradiation process, which initially forms a mixed graded layer, continues until the process proceeds from the introduction process to a pure deposition process (at a high dose), and the copper introduction surface A dielectric material is deposited on the mixed layer. The mixed gradient layer 514A introduced initially functions as a capping layer, and additional film formation of a dielectric material is performed by continuous GCIB irradiation to form a film formation dielectric film 514B. This forms a dielectric film integrated into the copper interconnect by the mixed graded layer, resulting in improved interfacial properties including excellent electrophoretic lifetime. The capping layer 516 is preferably formed on the interlayer dielectric layer 508 by the same (or different) capping GCIB that forms the capping layer 514. Like the capping layer 514, the capping layer 516 may be bilayer. The capping layer 516 initially forms a mixed graded layer of mixed dielectric / GCIB species composition on the surface, and is a dielectric barrier film by continuous GCIB processing or by additional separate (eg, PECVD) deposition. May be formed. For example, if the dielectric barrier film 514B is not configured by an extended GCIB process, or if a particularly thick dielectric barrier film 514B is required, the introduction capping layer 514 or the capping layer 516 may be formed by Si film by PECVD, if necessary. _It may be coated with a conventional insulating layer such as ₃ N ₄ , SiCN, SiC, thereby providing a dielectric barrier film for additional copper diffusion barriers or having via etch stop properties. Following the capping process and formation of the dielectric barrier film, an additional level of interconnect is added, if necessary, using conventional techniques.

  FIG. 4E shows a stage 500E of the wiring structure 500 following installation of the second interconnect level on the first GCIB capped interconnect level (including the dielectric barrier). At this stage, a second interconnect level is formed on the capping layers 514 and 516. The second interconnect level consists of a second interlayer dielectric layer 510, which is deposited on the capping layers 514 and 516 using conventional techniques. Grooves and vias are formed in second interlayer dielectric layer 510, which surrounds barrier layer 512, and copper is deposited in the grooves and vias using conventional techniques. The top surface of this structure is planarized and cleaned by conventional processing such as CMP. The top surfaces of the second copper interconnect layer 504 and the second interlayer dielectric layer 510 are shown to have residual contamination material 505. At the second interconnect level (if present) and the subsequent higher interconnect level (if present), the above-described GCIB cleaning and GCIB introduction steps are applied for the wiring structure 500 and (for example) FIG. 4A A capped film 518 as shown in FIG. This forms the desired two or more levels of interconnect structure.

  Thus, the technique shown suppresses electrophoresis and avoids unwanted side effects associated with selective metal capping processes. On the dielectric surface, the introductory layer and the dielectric remain insulative, and with a very thin introductory layer, the influence on the overall dielectric constant of the layer and the influence on the interlayer capacitance can be neglected.

FIG. 5A schematically illustrates a wiring structure 600 for copper interconnect capping using GCIB introduction and deposition according to a second embodiment of the present invention (eg, but not limited to this). There are two copper interconnect layer interconnect levels shown). This figure shows a substrate 601 that supports a first copper interconnect layer 602, a second copper interconnect layer 604, and a copper via structure 606 connecting the two copper layers, and these layers and via structures. Each of these is constructed using conventional techniques. Substrate 601 is typically a semiconductor substrate, which has active and / or passive elements (including lower interconnect levels where possible) that require electrical interconnection. The sidewalls and bottom of both copper interconnect layers 602 and 604 and the via structure 606 are surrounded by TaN / Ta or other barrier layer 612 formed by conventional techniques. The first interlayer dielectric layer 608 and the second interlayer dielectric layer 610 provide electrical insulation between the copper wiring layers, which may be formed by conventional techniques. Often, the interlayer dielectric layers 608 and 610 are preferably porous, which improves the dielectric properties. In such a case, the interlayer dielectric layer may be deposited on a hard mask layer, such as the first hard mask layer 609 and the second hard mask layer 611, respectively, as necessary. Each is composed of a material such as SiO ₂ , SiC or Si ₃ N ₄ , each of which may be deposited using conventional techniques. A first copper interconnect layer 602, a first interlayer dielectric layer 608 (or an upper surface of the first hard mask layer 609, if present), a second copper interconnect layer 604, and a second The top surface of the interlayer dielectric layer 610 (or the top surface of the second hard mask layer 611, if present) is all capped by GCIB treatment, and the capped layers 614, 616, 618, 620 are formed. In the second embodiment, the elements contained in the GCIB gas cluster ions are selected so that the introduced chemical species retain conductivity on the copper surface (copper cap films 614 and 618). It is different from the example. However, when the introduced element is introduced into the surface of the interlayer dielectric layer and / or dielectric hard mask material in the dielectric region (interlayer dielectric or hard mask cap film 610, 620) at each interconnect level, It may be selected so that an insulating film is formed by the same element. The improved dielectric diffusion barriers (barrier film 622 for the first interconnect level and barrier film 624 for the second interconnect level) are preferably formed by the GCIB deposition method. May be configured by conventional techniques. In such a barrier film, the diffusion barrier characteristics and the via etching stop characteristics in the GCIB introduction step are further improved.

  The GCIB introduction process is preferably applied to the upper surface of each interconnect level to form copper and interlayer dielectric caps. As previously described, the GCIB in-situ cleaning process is used to perform subsequent CMP planarization of the interconnect and interlayer dielectric. FIG. 5G shows a wiring structure 600G, but the interlayer dielectric layers 608 and 610 do not have the hard mask layers 609 and 611 on the upper surface. Hereinafter, the process which comprises the wiring structure 600G is demonstrated.

FIG. 5B shows a preliminary stage 600B of the wiring structure 600G. The interconnect level formed on the substrate 601 consists of a first interlayer dielectric layer 608 deposited in a conventional manner, in which grooves and vias are formed, which are barrier layers 612. Surrounded by Copper is deposited in the trenches and vias by conventional techniques. The upper surface of this structure is planarized and cleaned. The top surfaces of the first copper interconnect layer 602 and the first interlayer dielectric layer 608 are shown as having residual contamination material 603. At this stage, and at the upper surface of each subsequent stage of each subsequent interconnect level (assuming more than one interconnect level), it is preferable to be in-situ, eg, a conventional process such as a plasma cleaning process The dry cleaning process or the GCIB cleaning process may be performed. The GCIB cleaning process includes irradiating the surface to be cleaned with GCIB cluster ions composed of gas molecules of Ar, N ₂ , NH ₃ , H ₂ , or mixtures thereof, from about 3 kV to about 50 kV. A beam acceleration voltage V _ACC is preferably used, and the total gas cluster ion dose ranges from about 5 × 10 ¹³ to about 5 × 10 ¹⁶ ions / cm ² . The present invention is not limited to this gas example and is implemented using other gases or mixed gases that remove post-CMP residue, copper oxide, and other contaminants from the copper surface. It will be apparent to those skilled in the art. Although not the essence of the present invention, this GCIB cleaning process is preferably an in-situ cleaning process.

FIG. 5C shows an intermediate stage 600C constituting the wiring structure 600G following the GCIB cleaning step. Contamination materials are removed from the upper surfaces of the first copper wiring layer 602 and the first interlayer dielectric layer 608 to prepare for the capping step. At this stage, and at each subsequent interconnect level stage (assuming more than one interconnect level), a GCIB capping process may be applied to the cleaned top surface. Using a GCIB introduction process (preferably in-situ), the planar surface (copper and / or exposed interlayer dielectric layer) is capped simultaneously (or alternately with separate capping GCIBs). In the GCIB capping process, the top surface of the first copper wiring layer 602 and the first interlayer dielectric layer 608 is irradiated using the GCIB of the element constituting the conductive material during the introduction process to the copper surface. This element may constitute an electrically insulating material when introduced into the interlayer dielectric surface. Also, these conductive elements are selected from those that do not have a high solid solubility in copper, thereby avoiding the adverse effects of their conductivity. Although not limited to this, GCIB with gas cluster ions containing B or Ti is suitable, but not limited to, suitable dielectric hard masks such as SiO ₂ , SiC, SiCN, SiCOH, etc. In combination with the material, an insulating oxide, carbide or nitride may be formed. Some suitable source gases including B and Ti may include, but are not limited to, B ₂ H ₆ , TiCl ₄ , tetradiethylaminotitanium (TDEAT), and tetradimethylaminotitanium (TDMAT). . These gases may be used in pure form or mixed with an inert gas such as Ar or Xe. On the dielectric surface, for example, it is in the form of a graded film of TiO ₂ and borosilicate glass, whereas on the copper surface, these are, for example, in the form of a graded film of boron and titanium. good. Alternatively, but not limited to, by physical changes on the copper surface using GCIB containing only inert gas-cluster ions such as Ar, Xe, other noble gases, or mixed gases thereof, An inclined cap film may be formed. In this case, the copper capping structure is a physically modified copper layer, which is tilted from the beginning, has conductivity, and is physically formed in the interlayer dielectric layer. The modified layer is insulating. These alternative GCIBs, which contain only inert gas cluster ions, such as Ar, Xe and other rare gases, or a mixture of these, do not form an introductory layer, but instead have an effective capping structure for copper. The resulting surface is physically altered to maintain the dielectric insulation. Therefore, this effect is that the GCIB capping process is an element that constitutes the conductive material, and when introduced, the GCIB having an element that forms the conductive material on the copper surface allows the copper and interlayer dielectric layers to be formed. This is similar to the case of having an irradiation step on the upper surface of the substrate. Alternatively, even when no new chemical species is introduced to the surface, an electrically insulating material is formed upon introduction to the interlayer dielectric surface. Referring to the GCIB instrument 100 of FIG. 3, a beam acceleration potential V _ACC, preferably in the range of about 3 kV to about 50 kV, is used, and the total gas cluster ion dose ranges from about 1 × 10 ¹⁴ to about 1 × 10 ¹⁷ ions. / Cm ² range. On the copper and dielectric surfaces, the collision energy of the GCIB introduction process creates a high temperature transient region that promotes intermixing and / or reaction of the introduced species with the dielectric or dielectric hard mask layer ( Alternatively, a new insulating material (on the interlayer dielectric layer or hard mask) is formed, and an introduced conductive film is formed on the surface of the copper wiring, thereby suppressing the interfacial diffusion of copper and improving the electrophoretic lifetime. Therefore, in the single GCIB capping introduction step, as shown in FIG.5D, a conductive cap film 614 is formed on the first copper wiring layer 602, and on the first interlayer dielectric layer 608, An electrically insulating cap film 616 is formed.

FIG. 5E shows a step 600E of configuring the wiring structure 600G following the GCIB capping step. The GCIB process is performed on the top surface at this stage and each subsequent level of interconnect to form a dielectric diffusion barrier film. The dielectric diffusion barrier film 622 is preferably made of silicon carbonitride, but it may be silicon nitride, silicon carbide, or other dielectric film. This may be formed by a conventional PECVD method, but is preferably formed by irradiating the surface of the cap film (614 and 616), and on this, an insulating material is introduced. A barrier film 622 is formed by GCIB formed of the elements constituting the above. For example, GCIB with gas cluster ion elements such as C, N, Si, and combinations thereof is suitable, which allows diffusion barrier films such as Si ₃ N ₄ , SiCN, and SiC to be formed on copper. Is done. Source gases containing C, N, and Si include, but are not limited to, CH ₄ , SiH ₄ , NH ₃ , and N ₂ . Using such a gas, gas cluster ions are formed, and film formation is performed using either a pure gas or a mixed gas of these and an inert gas such as Ar or Xe. It is preferred to use a beam acceleration potential V _ACC that ranges from about 3 kV to about 50 kV, and the total gas cluster ion dose ranges from about 1 × 10 ¹⁴ to about 1 × 10 ¹⁷ ions / cm ² . FIG. 5F shows a stage 600F in constructing the interconnect structure 600G, where the first GCIB capped interconnect level (including the dielectric barrier film) and the barrier film 622 are over the second An interconnect level is added. The second interconnect level consists of a second interlayer dielectric layer 610 placed on the barrier film 622, in which trenches and vias are formed, which are surrounded by the barrier layer 612. . Copper is deposited in the trenches and vias by conventional techniques. The top surface of this structure is planarized and cleaned using conventional processing processes. The top surfaces of the second copper interconnect layer 604 and the second interlayer dielectric layer 610 are shown to have residual contamination material. The upper surface of the second interconnect level and the subsequent higher interconnect level (if necessary) are subjected to the GCIB cleaning step, GCIB introduction step and GCIB deposition step as described above, and the wiring structure 600G is It is formed. As a result of these processing steps, cap films 618, 620 and barrier film 624 are formed. This forms the desired two level interconnect structure or multiple level interconnect structure of FIG. 5G.

  FIG. 5H shows a preliminary stage 600H in constructing a wiring structure 600 (with hard mask layers 609 and 611), as fully shown in FIG. 5A. The first interconnect level formed on the substrate 601 has a first interlayer dielectric layer 608 that is deposited on the substrate using conventional techniques. A hard mask layer 609 formed by conventional techniques covers the upper surface of the first interlayer dielectric layer 608. Grooves and vias are formed in the first interlayer dielectric layer 608, which are surrounded by the barrier layer 612, and copper is deposited in the grooves and vias. The top surface of this structure is planarized and cleaned using a conventional cleaning process. The top surfaces of first copper interconnect layer 602 and hard mask layer 609 are shown to have residual contamination material 605. At this stage, and at the corresponding stage of each subsequent interconnect level, the top surface is preferably subjected to a GCIB cleaning process as described above. This is not the essence of the present invention, but the GCIB cleaning process is preferably an in-situ cleaning process.

  FIG. 5I shows a stage 600I in the process of configuring the wiring structure 600 following the GCIB cleaning process. Contaminants are removed from the upper surfaces of the first copper wiring layer 602 and the hard mask layer 609 to prepare for the capping step. At this stage and each corresponding stage at each subsequent interconnect level, the top surface may be subjected to a GCIB cleaning process as described above, thereby forming capping layers 614 and 616. (Figure 5J). In this embodiment, the capping layer 616 is formed on the hard mask layer 609 rather than directly on the first interlayer dielectric layer 608.

  FIG. 5J shows a stage 600J in the process of constructing wiring structure 600 following the step of forming capping layers 614 and 616. As described above, a GCIB treatment process is applied to the upper surface of this stage and each corresponding stage of each subsequent interconnect level to form a dielectric diffusion barrier film 622 on the capping layers 614, 616. Also good.

  FIG. 5K shows a stage 600K in the process of forming the wiring structure 600 following the formation of the barrier film 622.

  FIG. 5L shows a stage 600L in the process of configuring the wiring structure 600 after the second interconnect level has been added over the first GCIB capped interconnect level (including the dielectric barrier film). At this stage, a second interconnect level is formed on the barrier film 622. The second interconnect level is comprised of a second interlayer dielectric layer 610, which is deposited on the barrier film 622 using conventional techniques. A hard mask layer 611 formed by conventional techniques covers the upper surface of the first interlayer dielectric layer 610. In the second interlayer dielectric layer 610, conventional grooves and vias are formed, which are surrounded by a conventional barrier layer 612, and copper is placed in the grooves and vias by conventional techniques. Is done. The top surface of this structure is planarized and cleaned using conventional processing processes. The top surfaces of the second copper interconnect layer 640 and the hard mask layer 611 are shown to have residual contamination material 613. The second interconnect level (if necessary) and the subsequent higher interconnect level (if necessary) are implemented with a GCIB introduction step and a GCIB deposition step for wiring structure 600 as described above, ( For example, cap films 618, 620 are formed, and a barrier film 624 is formed (FIG. 5A). In this way, the desired two interconnect level structure of FIG. 5A or a multi-level interconnect structure may be formed.

  Thus, the technique shown suppresses electrophoresis and avoids unwanted side effects associated with selective metal capping. On the dielectric surface, the dielectric maintains insulation even after the capping process, and the influence on the dielectric constant is ignored by the extremely thin insulating layer.

  FIG. 6A schematically shows a wiring structure 700 for copper interconnection capping using a GCIB introduction process according to a third embodiment of the present invention (for example, but not limited to, Two copper wiring layer interconnect levels are shown). A substrate 701 is schematically shown that supports a first copper interconnect layer 702, a second copper interconnect layer 704, and a copper via structure 706 connecting the two copper layers, each of which is conventional. It may be formed using this technique. Substrate 701 is typically a semiconductor substrate that has active and / or passive elements that require electrical interconnection (including lower interconnection levels where possible). The sidewalls and bottom of both copper interconnect layers 702 and 704 and the via structure 706 are surrounded by a barrier layer 712, which may be constructed with conventional techniques. The first interlayer dielectric layer 708 and the second interlayer dielectric layer 710 provide electrical insulation between the copper interconnects and these may be formed using conventional techniques. The first interlayer dielectric layer 708 has an upper surface 709 and the second interlayer dielectric layer 710 has an upper surface 711. As shown in more detail below, at each copper interconnect interconnect level deposited by conventional deposition methods, the barrier layer 712 initially covers the upper surfaces 709, 711 of the interlayer dielectric layers 708, 710 (FIG. 6B). ). In this embodiment of the invention, the GCIB treatment process described below removes the material of the barrier layer 712 from the top surfaces 709, 711, so that in the complete structure shown in FIG. Not visible. The upper surface of the first copper wiring layer 702 and the upper surface of the second copper wiring layer 704 are capped by the GCIB treatment process to form introduction cap films 713 and 715. Introduced copper cap films 713, 715, and respective adjacent interlayer dielectric layers 708, 710 may be capped with dielectric barrier films 714 and 716, respectively, if desired, to improve the copper diffusion barrier and Etching stop characteristics are obtained. The dielectric barrier films 714 and 716 are preferably silicon carbonitride, but may be silicon nitride, silicon carbide, or a suitable dielectric, which is deposited by conventional techniques such as PECVD. Alternatively, it is preferably formed by a GCIB film forming method.

FIG. 6B shows a preliminary stage 700B in the process of configuring the wiring structure 700. In the stage shown in the figure, an interconnect level is formed on the substrate 701. The interconnect level is comprised of a first interlayer dielectric layer 708 deposited on the substrate. Grooves and vias are formed in the first interlayer dielectric 708 and are surrounded by a barrier layer 712. Copper is deposited in the trenches and vias. Initially barrier layer 712 covers top surface 709 of interlayer dielectric layer 708. The conventional CMP method removes the copper overburden, which is stopped on the barrier layer 712 material. Also, using conventional CMP processing conditions selected to selectively remove copper at a significantly higher rate compared to barrier layer materials, for example, high removal of copper compared to barrier materials. By using the selective slurry, the copper becomes slightly recessed below the surface of the barrier layer 712 as shown in the figure. The surface is cleaned using conventional processing processes. The top surfaces of the first copper interconnect layer 702 and barrier layer 712 are shown to have residual contamination material 703. The upper surface of this stage and each corresponding stage of each subsequent interconnect level (assuming two or more interconnect levels) is preferably in-situ, such as a plasma cleaning process A conventional dry cleaning process or a GCIB cleaning process may be performed. The GCIB cleaning process has the step of irradiating the surface to be cleaned with GCIB cluster ions consisting of gaseous molecules of Ar, N ₂ , NH ₃ , H ₂ or mixed gas, and a beam in the range of about 3 kV to about 50 kV. An accelerating potential V _ACC is used, and the total gas cluster ion dose ranges from about 5 × 10 ¹³ to about 5 × 10 ¹⁶ ions / cm ² . The present invention is not limited to this gas example, and can be practiced with other gases or mixed gases that remove post-CMP residue, copper oxide, and other contaminants from the copper surface. Will be apparent to those skilled in the art. Although not the essence of the present invention, this GCIB cleaning process is preferably an in-situ cleaning process.

FIG. 6C shows a stage 700C in the process of configuring the wiring structure 700 following the GCIB cleaning step. Contaminants are removed from the upper surfaces of the first copper interconnect layer 702 and the barrier layer 712 and are ready for the capping step. A GCIB capping process may be applied. Using the GCIB etching process (preferably in-situ) and the introduction capping process, even if the surface of the first copper wiring layer 702 is capped, the barrier layer 712 covering the upper surface 709 is removed. good. When the GCIB etching process and the capping process are introduced to the copper surface, the upper surface of the copper wiring layer 702 and the first interlayer dielectric 708 is irradiated using GCIB made of an element constituting the capping material. Having steps. This element may be the material of the etching barrier layer 712. The GCIB irradiation removes the material of the exposed barrier layer 712 on the upper surface 709 and introduces a capping chemical species into the first copper wiring layer 702 to form a cap film 713. Source gases include elements such as, but not limited to, fluorine and / or sulfur, but SF ₆ , CF ₄ , C ₄ F ₈ , or NF ₃ are used in forming the GCIB. The These gases are used to form gas cluster ions for introduction using pure gas or using a gas mixed with N ₂ or an inert gas such as Ar or Xe. By such an introduction process, a copper cap film such as CuF ₂ is formed. The beam acceleration potential V _ACC is preferably in the range of about 10 kV to about 50 kV, and the nozzle gas flow rate may be in the range of about 200 sccm to about 3000 sccm. For example, in a preferred process for etching the barrier layer material and forming a copper cap film, a mixed source gas of N ₂ and 10% NF ₃ is used at a flow rate of 700 sccm. The GCIB etch and introduction process continues until all the barrier layer material is removed, resulting in a top surface 709 with relatively little change in the first interlayer dielectric layer 708 and a cap film 713 An introduced copper surface is obtained. Since the top surface 709 is protected from the GCIB by the material of the barrier layer 712 during most of the process, the top surface 709 has only a minor effect.

  FIG. 6D shows a stage 700D during the process of configuring the wiring structure 700 following the GCIB etching and introduction step. The upper surface of the first copper wiring layer 702 is capped with a capping layer 713, the barrier layer 712 is etched away, and the upper surface 709 of the first interlayer dielectric layer 708 remains. This structure is prepared for the formation of a dielectric barrier film. A dielectric diffusion barrier film 714 is formed on the capping layer 713 and on the upper surface 709 of the first interlayer dielectric layer 708 by performing the GCIB process to form the barrier film 622 described above. May be formed.

  FIG. 6E shows a stage 700E in the process of forming the wiring structure 700 following the formation of the dielectric diffusion barrier film 714.

  FIG. 6F shows a stage 700F during the process of constructing the second interconnect level interconnect structure 700 on the first GCIB capped interconnect level (including the dielectric barrier film). At this stage, a second interconnect level is formed on the barrier film 714. The second interconnect level is comprised of a second interlayer dielectric layer 710 that is deposited on the barrier film 714. Grooves and vias are formed in the second interlayer dielectric layer 710 and are surrounded by a barrier layer 712. Copper is deposited in the trenches and vias using conventional techniques. Initially barrier layer 712 covers the top surface of interlayer dielectric layer 710. Conventional CMP processing removes the copper topload, which is stopped on the barrier layer 712 material. Also, using conventional CMP processing conditions selected to preferentially remove copper at a faster rate than the barrier layer material, for example, with high selectivity to selectively remove copper compared to barrier materials. By using the slurry, the copper becomes slightly recessed below the surface of the barrier layer 712 as shown in the figure. This surface is cleaned using conventional processing processes. The top surfaces of the second copper interconnect layer 704 and the barrier layer 712 are shown to have residual contamination material 717. At the second interconnect level (if necessary) and the subsequent high interconnect level (if necessary), the GCIB cleaning step, GCIB (etching) as described above, due to the first interconnect level of the wiring structure 700 And an introduction capping step) and a GCIB film forming step are applied to form a cap film 715 and a barrier film 716 (for example). Also, the desired two interconnect level structures of FIG. 6A or a multi-level interconnect structure may be formed.

  Following the removal of the CMP copper top load shown in wiring structure 700 above, if the exposed barrier layer material has an undesirable spatially non-uniform thickness, the GCIB can be compensated, if necessary, by a compensatory method. Etching is performed to reduce spatial non-uniformity. Sample wafer surface using a conventional metal film mapping device (eg, Rudolf Technology, METAPULSE®-II metal film measurement system, commercially available from Rudolf Technology, 07836 Flanders, Sulfur, New Jersey, USA) The first mapping process of the barrier layer thickness over time allows subsequent etching of the barrier layer that is compensated for etching as described above, resulting in greater etching when the barrier layer material is thicker. When the barrier layer material is thinner, a less lossy etch process is possible, and the initial thickness of the barrier layer material removes the lower interlayer dielectric in areas that may be over-etched Can be minimized. This spatially compensated etching process is performed by using a measured barrier layer thickness map in combination with the technique shown in Allen et al. US Pat. No. 6,537,606 (the '606 patent). The literature is incorporated herein by reference. Gas cluster ion beam processing equipment, such as the Epion Corporation nFusuion® GCIB processing system (Epion Corporation, Billerica, Mass.), Can be obtained from measurement maps using the techniques described in the aforementioned '606 patent. It has a function of automatic compensation etching, which is commercially available.

In this embodiment of the invention, both the barrier layer etch and the copper capping process are preferably performed in a single step using a GCIB process, so that both are processed simultaneously as described above. The Also, in some environments, it is possible to perform barrier layer etching and copper capping with separate GCIB processing process steps, using different characteristics of GCIB at each step. In such a case, when the stage shown in FIG. 6C is reached, first, the GCIB etch process removes the barrier layer material covering the top surface 709 of the interlayer dielectric layer 708 prior to the GCIB cap step. . Next, a GCIB etching step is performed to reveal the structure shown in FIG. 6G, which is prepared for capping the copper interconnect layer and the interlayer dielectric layer, and is shown in the various embodiments of the present invention described above. These cappings are performed using the GCIB capping process. At each interconnect level, a preferred etching process step is a source gas that includes fluorine, such as, but not limited to, a source gas that includes SF ₆ , CF ₄ , C ₄ F ₈ , or NF _3. The surface to be cleaned is irradiated with GCIB cluster ions composed of Using these gases, gas cluster ions are formed, and an etching process is performed using either pure gas or a mixed gas of N ₂ or an inert gas such as Ar or Xe. . The beam acceleration potential V _ACC is preferably in the range of about 10 kV to about 50 kV, and the nozzle gas flow rate in the range of about 200 sccm to about 3000 sccm may be used. For example, in a process that is a process for etching the barrier layer material, a mixed source gas of N ₂ and 10% NF ₃ is used, and the flow rate is 700 sccm. If necessary, the GCIB etch step is a compensation etch step as described above, which compensates for initial spatial non-uniformities within the thickness of the barrier layer material.

  FIG. 7A schematically illustrates a copper interconnect capped wiring structure 800 using a GCIB introduction process according to a fourth embodiment of the present invention (eg, but not limited to 2 Two copper wiring layer interconnect levels are shown). The figure schematically shows a substrate 801 that supports a first copper wiring layer 802, a second copper wiring layer 804, and a copper via structure 806 that connects the two copper layers. Each may be formed by conventional techniques. The substrate 801 is typically a semiconductor substrate with active and / or passive elements (including lower interconnect levels where possible), which need to be electrically interconnected. The sidewalls and bottom of both copper wiring layers 802, 804 and via structure 806 are surrounded by a barrier layer 812, which may be constructed with conventional techniques. The first interlayer dielectric layer 808 and the second interlayer dielectric layer 810 provide electrical insulation between the copper wiring layers, which may be constructed with conventional techniques. The first interlayer dielectric layer 808 has an upper surface 809 and the second interlayer dielectric layer 810 has an upper surface 811. As described in detail below, at each copper interconnect level deposited by conventional techniques, barrier layer 812 initially covers upper surfaces 809 and 811 of interlayer dielectric layers 808, 810. In this embodiment of the invention, the material of the barrier layer 812 is removed from the top surfaces 809, 811 and is therefore not visible on these surfaces in the complete structure shown in FIG. 7A. Removal of the material of the barrier layer 812 from the top surfaces 809, 811 is preferably performed by the GCIB treatment process described herein or by conventional methods. The upper surface of the first copper wiring layer 802 and the upper surface of the second copper wiring layer 804 are capped by the GCIB treatment process, and introduction cap films 813 and 815 are formed. Introduced capping films 813, 815 and adjacent interlayer dielectric layers 808, 810 may be capped with dielectric barrier films 814 and 816, respectively, if desired, thereby improving copper diffusion. Barrier and via etch stop properties are obtained. Dielectric barrier films 814 and 816 are preferably silicon carbonitride, but may be silicon nitride, silicon carbide, or other suitable dielectric, including conventional deposition such as PECVD. Technology, or preferably, a GCIB deposition method is applied.

FIG. 7B shows a preliminary stage 800B in the process of configuring the wiring structure 800. At the stage shown, an interconnect level is formed on the substrate 801. The interconnect level is comprised of a first interlayer dielectric layer 808 deposited on the substrate. Grooves and vias are formed in the first interlayer dielectric layer 808 and are surrounded by the barrier layer 812. Copper is deposited in the trenches and vias. The barrier layer 812 initially covers the top surface 809 of the interlayer dielectric layer 808. The conventional CMP method removes the copper overload, which is stopped on the barrier layer 812 material. Also, using conventional CMP processing conditions selected to preferentially remove copper at a greater rate than barrier layer materials, for example, high removal of copper compared to barrier materials. By using the selective slurry, copper becomes slightly recessed below the surface of the barrier layer 812 as shown in the figure. This surface is cleaned by conventional processing processes. The top surfaces of the first copper interconnect layer 802 and barrier layer 812 are shown to have residual contamination material 803. At this stage, and at the upper surface of each corresponding stage of each interconnect level (assuming two or more interconnect levels), preferably in-situ, a conventional dry cleaning such as a plasma cleaning process Processing or GCIB cleaning processing is performed. The GCIB cleaning process includes irradiating the surface to be cleaned with GCIB cluster ions composed of Ar, N ₂ , NH ₃ , H ₂ , or mixed gas molecules thereof, preferably from about 3 kV A beam acceleration potential V _{ACC in} the range of about 50 kV is used, and the total gas cluster ion dose ranges from about 5 × 10 ¹³ to about 5 × 10 ¹⁶ ions / cm ² . The present invention is not limited to this gas example, it can be practiced from the copper surface with other gases or gas mixtures that provide post-CMP residue, copper oxide, and other contaminants. Will be apparent to those skilled in the art. Although not the essence of the present invention, this GCIB cleaning process is preferably an in-situ cleaning process.

FIG. 7C shows a process stage 800C of configuring the wiring structure 800 following the GCIB cleaning step. Contamination materials are removed from the upper surfaces of the first copper wiring layer 802 and the barrier layer 812, and the capping step is prepared. Here, GCIB capping processing may be performed. The GCIB introduction capping process is used to cap the surface of the first copper wiring layer 802 and the barrier layer 812 installed on the upper surface 809 simultaneously. The GCIB etching and capping process is a step of irradiating the upper surfaces of the first copper wiring layer 802 and the exposed barrier layer 812 with GCIB composed of elements constituting the capping material when introduced to the copper surface. Have By GCIB irradiation, capping chemical species are introduced into the first copper wiring layer 802 to form a cap film 813 (FIG. 7D). At the same time, the introduction layer is introduced into the exposed barrier layer material 812 by GCIB irradiation. In this embodiment, the introduction condition is selected such that the introduction depth into the exposed barrier layer is shorter than the thickness of the exposed barrier layer 812 covering the upper surface 809 when the capping introduction step is completed. Accordingly, the capped species do not enter the interlayer dielectric layer 808 upon introduction of the capped species into the exposed barrier layer 812. The barrier layer 812 protects the interlayer dielectric layer 808 from the introduction process of copper capping, so that the barrier layer 812 is introduced to the capped chemical species that may lead to deterioration of the characteristics of the interlayer dielectric layer 808 when introduced. The available range of capped species can be expanded. The depth of introduction depends on the beam acceleration potential that accelerates the GCIB. The beam accelerating potential V _ACC is preferably used in the range of about 3 kV to about 50 kV, and the actual value is such that the introduction layer is surely formed in the exposed barrier layer and does not enter the interlayer dielectric layer 808. Selected. During the copper capping introduction process, a GCIB dose in the range of about 1 × 10 ¹⁴ to about 1 × 10 ¹⁷ ions / cm ² is used. Any source gas that forms the copper cap film (many of those previously mentioned with respect to other embodiments of the invention) may be used, but in this embodiment the interlayer dielectric layer is derived from the introduced species. To be protected, a gas or mixed gas is selected regardless of whether a conductive layer is formed and whether a film detrimental to the interlayer dielectric material is formed. Some example source gases are WF ₆ , other metal fluoride gases, carbon-containing gases, and organometallic gases.

  FIG. 7D shows a stage 800D in the process of configuring the wiring structure 800 following the GCIB capping step. The upper surface of the first copper wiring layer 802 is capped by the capping layer 813, and the barrier layer 812 has the introduction layer 818 obtained by the capping introduction step. In the enlarged view 820, an enlarged view of the introduction layer 818 in the capping layer 813 and the exposed barrier layer 812 is shown. This structure is prepared for the removal of the barrier layer 812 and the introduction layer 818 covering the top surface 809 of the interlayer dielectric layer 808. Here, an etching process (preferably using the GCIB process described below) may be performed, thereby removing the upper portion of the barrier layer 812 and the interlayer dielectric layer 808 without removing the introduced copper capping layer. The introductory layer 818 covering the surface 809 is removed (although if an effective capping layer remains, some portion or copper capping layer is removed).

  FIG. 7E shows a stage 800E in the process of configuring the wiring structure 800 following the GCIB etching step. The upper surface of the first copper wiring layer 802 is capped with a capping layer 813, the barrier layer 812 is etched away, and the upper surface 809 of the interlayer dielectric layer 808 is exposed. This structure is prepared for the formation of a dielectric barrier film. If necessary, the dielectric diffusion barrier film 814 is formed on the capping layer 813 and the upper surface 809 of the first interlayer dielectric layer 808 by using a film formation method as described for the formation of the barrier film 622. (FIG. 7F) may be formed.

  FIG. 7F shows a stage 800F in the process of forming the wiring structure 800 following the formation of the optional dielectric diffusion barrier film 814.

  FIG. 7G shows a stage 800G in the process of constructing a wiring structure 800 having a second interconnect level on a first GCIB capped interconnect level (including a dielectric film). At this stage, a second interconnect level is formed on the barrier film 814. The second interconnect level is composed of a second interlayer dielectric layer 810 deposited on the barrier film 814. The second interlayer dielectric layer configuration 810 is formed with grooves and vias that surround the barrier layer 812. Copper is deposited in the trenches and vias using conventional techniques. The barrier layer 812 initially covers the top surface of the configuration 810 with an interlayer dielectric layer. The conventional CMP method removes the copper topload, which is stopped on the barrier layer 812 material. Also, using conventional CMP processing conditions selected to preferentially remove copper at a greater rate compared to barrier layer materials, for example, high removal of copper selectively compared to barrier materials. By using a selective slurry, the copper becomes slightly recessed below the surface of the barrier layer 812, as shown. This surface may be cleaned using conventional processing processes. The top surfaces of the second copper interconnect layer 804 and barrier layer 812 are shown to have residual contamination material 817. GCIB cleaning, GCIB as described above, as shown for the first interconnect level in wiring structure 800, at the second interconnect level (if necessary) and the subsequent higher interconnect level (if necessary) Introducing capping, GCIB etching, and GCIB deposition steps may be applied, thereby forming (for example) a cap film 815 and an optional barrier film 816. Also, the desired two interconnect level structures of FIG. 7A or multiple levels of interconnect structures may be formed.

At each interconnect level, the preferred etching step is not limited to this, but with GCIB cluster ions formed from a source gas containing fluorine such as SF ₆ , CF ₄ , C ₄ F ₈ , or NF _3. Irradiating the surface to be cleaned. By using these gases, gas cluster ions are formed, and an etching process is performed using either a pure gas or a mixed gas of this with an inert gas such as N _2, Ar, or Xe. The beam acceleration potential V _ACC may be in the range of about 10 kV to about 50 kV, and the nozzle gas flow rate may be in the range of about 200 to about 3000 sccm. For example, a suitable processing process that etches the barrier layer material and barely etches copper uses a mixed source gas of N ₂ and 10% NF ₃ at a flow rate of 800 sccm. In this fourth embodiment of the present invention, the effect of the GCIB etching step preferably does not enter through the capping layer previously formed on the copper surface by the GCIB copper capping introduction step. Therefore, the beam acceleration potential V _ACC used for accelerating the GCIB for etching the barrier material is preferably selected to be smaller than the value used when accelerating the copper capping introduction GCIB.

  Each of the aforementioned fourth embodiments of the present invention has the necessary steps for the use of a GCIB treatment process, or a GCIB treatment process is optionally used. The GCIB processing steps of embodiments of the present invention may be performed in combination with conventional (non-GCIB) processing steps, if necessary, and in some cases, by a series of applications of each required step, the present invention Is implemented. Of course, in combination with other standard stand-alone tools that provide other processing steps (eg, but not limited to PECVD tools for deposition and plasma processing tools for cleaning) It is practical (and preferred in some circumstances) to implement the present invention using a GCIB processing system such as that shown in FIG. However, other processing tools are preferred depending on the capacity required for manufacturing. For several reasons, it may be preferable to perform multiple series of steps simultaneously with a single tool. One such reason is processing power. Semiconductor wafers are processed to move more quickly through the manufacturing process and there is little time for the wafer to move from tool to tool. High throughput leads to low costs. Another advantage of performing multiple steps with a single tool is that good circuit characteristics are obtained with high processing quality. For example, when copper wiring is oxidized, the resistance of the wiring increases and the reliability of the wiring decreases. Accordingly, it is preferred that all steps of cleaning, capping, and forming the dielectric diffusion barrier film be performed in-situ and in a single vacuum system, and the wafer is not exposed to the atmosphere between steps. Also, by performing multiple steps within a single tool, there is no exposure to the atmosphere during the step (when operated in a reduced pressure atmosphere or vacuum), contamination is avoided and in the processing process The need for extra cleaning steps is reduced.

A particular advantage of the method of the fourth embodiment is the order in which a copper capping step and a diffusion barrier removal step from the top surface of the interlayer dielectric are performed. In the above-described conventional processing procedure, and in the first two embodiments of the present invention, for each interconnect layer, the top surface of the interlayer dielectric layer prior to performing the copper capping process in the interconnect layer The barrier layer material is removed. In a third embodiment of the invention, for each interconnect layer, the barrier layer material is removed from the top surface of the interlayer dielectric layer simultaneously with the copper capping process in the interconnect layer. In the entire series of conventional processes, and in the first two embodiments of the present invention, the capping process is performed so that the copper capping process does not interact in an unfavorable manner with the top surface of the interlayer dielectric layer. This is subject to the effects of a copper capping process because the upper surface of the interlayer dielectric layer is protected without being subjected to undesirable and additional masking steps. In the third embodiment of the present invention, the copper capping process is limited to the use of an etchable GCIB for the barrier layer material, at the same time a copper capping layer is formed, and the barrier layer material is completely When etched into
There are several potential contaminations or undesirable effects on the top surface of the interlayer dielectric layer that can occur during irradiation of the interlayer dielectric layer upon completion of the etch / capping process. In a fourth embodiment of the present invention, the barrier layer material on the top surface of the interlayer dielectric layer completely masks the top surface of the interlayer dielectric during the copper capping process and is used for the GCIB copper capping process. When selecting the GCIB component to be used, complete freedom is obtained and the copper capping characteristics are optimized without any unfavorable effect on the interlayer dielectric.

  Therefore, when the present invention is introduced into high capacity manufacturing, it is preferable to use the cluster tool shown in FIG. 8A. FIG. 8A shows a schematic diagram of the cluster tool 900A. The transfer chamber 902 includes a sample transfer device 904, which is preferably a wafer transfer robot that transfers a sample from one position to another. A load / unload lock 906 provides atmospheric and vacuum locks and samples are transported into and out of the cluster tool. The load / unload lock 906 has shutters or valves 908, 910 that operate to allow sample transport into and out of the cluster tool. The load / unload lock 906 can switch between vacuum (reduced pressure atmosphere) and atmospheric pressure, and facilitates transport of a sample (not shown) from the atmosphere of the cluster tool to the vacuum atmosphere. Samples are individually conveyed through a load / unload lock 906, or in a cassette or container that contains a plurality of samples. Although a single load / unload lock is shown for both sample placement and removal from the cluster tool, separate loading and uncorresponding to various standard configurations of the cluster tool are shown. One skilled in the art will readily appreciate that an unload lock may be used.

  Cluster tool 900A has a plurality of processing chambers (eg, but not limited to, 912, 916, 920, 924 and 928 are shown). Each processing chamber is in communication with a transfer chamber 902 via a shutter or valve (914, 918, 922, 926 and 930, respectively). Each processing chamber may be configured as a tool to process a different (or the same) type of sample, and the cluster tool has five (shown in the figure) or more or fewer processing chambers Also good. Typically, all of the transfer chamber 902 and the processing chamber operate under vacuum conditions, which eliminates exposure of the sample to the atmosphere during the processing steps, making it easier to perform multiple processes on the sample. The processing function of the GCIB processing system as shown in FIG. 3 may be configured in the cluster tool processing chamber, which introduces a GCIB processing step into the cluster tool. GCIB processing system adapted to function as a cluster tool processing module. Produced and marketed by Epion, Billerica, Massachusetts, USA.

  FIG. 8B shows processing module A, processing module B, processing module C (corresponding to each of the processing chambers (912, 916, 920, 924, and 928) of FIG. 8A. A cluster tool 900B comprising five processing chambers, processing module C), processing module D, and processing module E is shown. One or more of these processing modules (processing chambers) are configured as a GCIB processing system. The other of these processing modules is configured as another processing system, such as, but not limited to, a plasma cleaning system, a PECVD film forming system, and the like. The sample transfer device 904 moves the wafer along various processing chambers (912, 916, 920, 924, and 928), the transfer chamber 902, and the load / unload lock 906. Once the cluster tool is configured with one or two plasma cleaning system modules, the plasma cleaning system module can be sampled using conventional techniques before performing the GCIB copper capping process on the same cluster tool ( Adapted to perform cleaning of the wafer). When configured with one or more PECVD deposition system modules, the PECVD deposition system modules can be used on top of already capped copper using GCIB copper capping operations performed in the same cluster tool. Adapted to perform the deposition of the dielectric film. The cluster tool may be composed of multiple GCIB processing chambers. Such a GCIB processing chamber is adapted to perform all of the GCIB copper capping process, the GCIB surface cleaning process, and / or the GCIB deposition process (eg, capped by GCIB process in the same cluster tool). Deposition of a dielectric film including a dielectric diffusion barrier film on the formed copper).

  The above-described fourth embodiment of the present invention incorporates the steps and optional steps described in the various examples shown in the table of FIG. For the fourth embodiment of the present invention, the table in FIG. 9 shows the effective execution of several possible positional combinations and combinations of various steps of the processing steps using conventional processing and GCIB processing. Cluster tool configurations (including preferred configurations) are shown.

  The cluster tool configuration shown in the table of FIG. 9 shows up to four processing modules, but in some cases, the use of additional processing modules can result in more than what is needed in the table of FIG. It will be apparent to those skilled in the art that a cluster tool that can support a processing module will be beneficial, with slower processing being reproduced, sharing work between replication modules, and / or not forming part of the present invention. By adding additional processing steps, the throughput is optimized. However, such additional processing steps are necessarily performed before and after the series of steps of the various embodiments of the present invention and are required as an additional part of the overall integrated circuit manufacturing process.

Although the present invention has been described in terms of various embodiments, it should be noted that the present invention can be widely used in further and other embodiments without departing from the spirit of the invention. For example, it will be apparent to those skilled in the art that the present invention is not limited to the dual damascene integration scheme and can be equally applied to other copper interconnect schemes. The present invention also provides an introduction film and an installation film, or various components (for example, Si ₃ N ₄ , SiC, SiCN, BN, CuF ₂ , TiO ₂ , CuCO ₃ , B, Ti, silicon nitride, silicon carbide, silicon carbonitride). , Boron nitride, copper fluoride, titanium dioxide, copper carbonate, boron, titanium, and borosilicate glass), but many films and layers formed by the present invention are graded. Or in pure form, which do not have the exact stoichiometry represented by the chemical formula or name, or are approximately equal to the stoichiometry, and in normal cases when using such membranes One skilled in the art will appreciate that additional hydrogen and / or other impurities may be included.

Claims (15)

A cluster tool for processing at least one wafer in a reduced pressure atmosphere,
At least one lock when moving the at least one wafer into and / or out of the cluster tool;
At least one transfer chamber;
At least one GCIB processing chamber;
At least one additional chamber selected from the group consisting of a cleaning process chamber and a deposition chamber;
At least one wafer transfer device adapted to transfer said at least one wafer from chamber to chamber;
Cluster tool with The at least one GCIB processing chamber is adapted to perform a copper capping process on at least a portion of the at least one wafer;
The cluster tool of claim 1, wherein the at least one additional chamber includes a cleaning process chamber adapted to perform a cleaning process prior to the copper capping process. The at least one GCIB processing chamber is adapted to perform a copper capping process on at least a portion of the at least one wafer;
The cluster tool of claim 1, wherein the at least one GCIB processing chamber is adapted to perform a GCIB etching process. The at least one GCIB processing chamber is adapted to perform a copper capping process on at least a portion of the at least one wafer;
The at least one additional chamber includes a deposition chamber adapted to form a dielectric diffusion barrier film over at least a portion of the capped copper of the at least one wafer. Item 1. The cluster tool according to item 1. (A) the at least one additional chamber is a GCIB cleaning process chamber adapted to perform a cleaning process prior to the copper capping process; or (b) the at least one additional chamber is 4. The cluster tool according to claim 1, wherein the cluster tool is a GCIB deposition chamber adapted to form a dielectric diffusion barrier film on the capped copper.   The cluster tool according to claim 1, wherein the at least one additional chamber is selected from the group consisting of a PECVD deposition chamber and a plasma cleaning process chamber. The at least one GCIB processing chamber is adapted to perform a copper capping process on at least a portion of the at least one wafer;
The at least one additional chamber includes at least one GCIB cleaning process chamber adapted to perform a cleaning process prior to the copper capping process, and a dielectric diffusion barrier on the capped copper. 5. The cluster tool according to any one of claims 1 to 4, comprising at least one GCIB deposition chamber adapted to form a film. A method of processing a semiconductor wafer in a cluster tool system while maintaining the cluster tool system in a reduced pressure environment,
(A) forming a capping layer on a copper interconnect surface on a semiconductor wafer using a GCIB capping process in a first GCIB processing chamber of the cluster tool;
(B) transferring the semiconductor wafer from the first GCIB processing chamber to the second processing chamber of the cluster tool in the reduced pressure environment of the cluster tool;
(C) performing additional processing in the second processing chamber;
Having a method. Forming the capping layer further comprises:
(A) forming a capping layer on the surface of the barrier layer material covering the dielectric material on the semiconductor wafer; or (b) forming a capping layer on the dielectric material on the semiconductor wafer;
9. The method of claim 8, comprising: The additional processing is:
(A) removing the barrier layer from the dielectric layer using GCIB etching, or (b) forming a dielectric diffusion barrier film on the capping layer;
The method of claim 9, comprising:   11. The method of claim 10, wherein the step of forming the dielectric diffusion barrier film is a GCIB treatment process. Furthermore, before the step of forming the capping layer,
Cleaning the copper interconnect surface in a third processing chamber of the cluster tool using a cleaning process;
Transferring the semiconductor wafer from a third processing chamber of the cluster tool to a first GCIB processing chamber of the cluster tool in the reduced pressure environment of the cluster tool;
12. The method according to any one of claims 8 to 11, characterized by comprising: The third processing chamber of the cluster tool is a GCIB processing chamber;
13. The method of claim 12, further wherein the cleaning process includes a GCIB cleaning process. The third processing chamber of the cluster tool is a plasma processing chamber;
The method according to claim 12, wherein the cleaning process includes a plasma cleaning process. The second processing chamber is a PECVD processing chamber;
The method of claim 10, wherein the step of forming the dielectric diffusion barrier film is a PECVD process.

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