KR20080098514A - Copper interconnect wiring and method and apparatus for forming thereof - Google Patents

Abstract

Capping layer or layers on a surface of a copper interconnect wiring layer for use in interconnect structures for integrated circuits and methods and apparatus for forming improved integration interconnection, structures for integrated circuits by the application of gas-cluster ion-beam processing. Reduced copper diffusion and improved electromigration lifetime result and the use of selective metal capping techniques and their attendant yield problems are avoided. Various cluster tool configurations including gas-cluster ion-bearn processing modules for copper capping, cleaning, etching, and film formation steps are disclosed.

Description

Copper interconnect wiring and method and apparatus for forming the same

BACKGROUND OF THE INVENTION Field of the Invention The present invention is generally an improvement for forming interconnect structures in semiconductor integrated circuits by applying a capping layer and gas-cluster ion beam (GCIB) processing of copper interconnect wiring layer surfaces. To a method and apparatus.

Semiconductor's continuing “Moore's Law” scaling for high density and high performance has resulted in significant productivity gains for industry and our society. However, a problem resulting from this size reduction is the need to carry higher currents in smaller interconnect interconnects. If the current density and the temperature in such a small wiring become too high, the interconnect wiring can be broken by a phenomenon called electromigration. The so-called "electron wind" effect, which occurs in high current density interconnect wiring, causes metal atoms to deviate from their original lattice position, leading to open circuits or areas in which these diffused atoms are crowded. Causes an extrusion short at The introduction of copper as a wiring material to replace aluminum has significantly improved the electromigration lifetime, but the continued reduction in interconnect wiring suggests that further improvements in copper electromigration lifetime will be needed in the future.

Unlike aluminum interconnects, which are broken by diffusion of aluminum atoms along grain boundaries, copper interconnect electron transport failure behavior is controlled by diffusion along the surface and interface. In particular, for conventional copper interconnect interconnect designs, the top surface of the copper interconnect typically must have good diffusion barrier properties to prevent copper migration to the surrounding dielectric. It has a layer of pings. The two most commonly used dielectric capping materials are silicon nitride and silicon nitride, which have been deposited by conventional plasma-enhanced chemical vapor deposition (PECVD) techniques. Unfortunately, these PECVD deposited capping materials, together with copper, form a defective interface that increases copper migration along the top surface of the copper interconnect, thus increasing the electron transport breakage rate. Other surfaces of copper interconnect structures typically form barriers or bi-layers (typically metallic) that form a strong interface with copper to limit copper diffusion to inhibit electron transfer effects. , For example, TaN / Ta, TaN / Ru, or Ru). Hereinafter, such a blocking layer or a double layer is referred to as "blocking layer". The layers of wiring interconnection are referred to as interconnect layers, wiring layers or interconnect layers, each layer of wiring interconnection being from one or more metal conductor layers, and from a lower-level substrate or lower interconnect layer and from the same layer of wiring interconnection. And a layer of inter-level dielectric that insulates the metal conductor layer from other metal conductors in.

Attempts have been made to improve electromigration of copper interconnects by capping the top surface of the copper interconnects using selectively deposited metal caps. Indeed, when capping the upper copper interface with a selective tungsten or selective cobalt tungsten phosphide (CoWP) metal layer, it has been reported that there is a significant improvement in copper electromigration lifetime. Unfortunately, all methods using selective metal capping solutions are also capable of depositing some metal on adjacent insulator surfaces, resulting in unintended leakage or shorts between adjacent metal lines. . The present invention uses gas-cluster ion beam processing to solve many of these problems.

1 shows a schematic diagram illustrating a wiring design 300 of a silicon nitride capped copper interconnect of the prior art commonly used in a copper dual damascene integration process. This includes a first copper wiring layer 302, a second copper wiring layer 304, and a copper via structure 306 connecting these two copper layers. Sidewalls and bottoms of both wiring layers 302 and 304 and via structure 306 are both lined with a blocking layer 312. The blocking layer 312 provides excellent diffusion blocking properties, which prevents the diffusion of copper into adjacent insulator structures and also provides an excellent low diffusion interface to copper to inhibit electron migration along their interface. The first inter-level dielectric layer 308 and the second inter-level dielectric layer 310 provide insulation between the copper interconnects. The top surface of the first copper wiring layer 302 and the top surface of the second copper wiring layer 304 are respectively covered with insulating blocking films 314 and 316 made of silicon nitride or silicon nitride carbon. These insulating barrier films 314 and 316 are typically deposited by PECVD, and the interfaces they form with the exposed copper surface are significant defects and provide a fast diffusion path for moving copper atoms. In this prior art wiring design, along these interfaces, almost all undesirable material transfer occurs during copper electromigration. As such, in conventional dual damascene copper interconnects, at each interconnect level, trenches and vias are formed in the inter-level dielectric layer and then copper is deposited to form interconnect wiring and vias, followed by chemical mechanical This is followed by a planarization step that is typically performed using chemical mechanical polishing (CMP) techniques. The planarization step removes the barrier layer material from the top surface of the inter-level dielectric layer, and simultaneously makes the top surface of the copper interconnect layer and the top surface of the inter-level dielectric layer flat. Corrosion inhibitors are used in both the CMP and post-CMP brush cleaning processes, and these corrosion inhibitors and other contaminants must be removed from the copper surface by in-situ cleaning prior to depositing the capping layer. Using an ex-situ cleaning process is likely to make the copper surface susceptible to corrosion and oxidation. PECVD reactors are typically not configured to effectively perform in-situ cleaning of the copper surface prior to depositing the insulator capping layer. Although not shown in FIG. 1, wiring design 300 typically contains semiconductors containing active and / or passive elements that require electrical interconnection to complete an integrated circuit. It is formed on a substrate.

2 shows a wiring design 400 of prior art selective metal-capped copper interconnects. This includes a first copper wiring layer 402, a second copper wiring layer 404, and a copper via structure 406 connecting these two copper layers. Sidewalls and bottoms of both wiring layers 402 and 404 and via structure 406 are both lined with a blocking layer 412. The blocking layer 412 provides excellent diffusion blocking properties, which prevents the diffusion of copper into adjacent insulator structures and also provides an excellent low diffusion interface to copper to inhibit electron migration along the interface. The first inter-level dielectric layer 408 and the second inter-level dielectric layer 410 provide insulation between the copper interconnects. The top surface of the first copper wiring layer 402 and the top surface of the second copper wiring layer 404 are each selectively made of selective tungsten or selective CoWP which is typically deposited by chemical vapor deposition (CVD) or electroless technique. Capped with the deposited metal layers 414 and 416. In this conventional dual damascene copper interconnect, at each interconnect level, trenches and vias are formed in the inter-level dielectric layer and then copper is deposited to form interconnect wiring and vias, followed by chemical mechanical polishing (CMP) techniques. This is followed by a planarization step that is typically performed. The planarization step removes the barrier material from the top surface of the inter-level dielectric layer, and simultaneously makes the top surface of the copper interconnect layer and the top surface of the inter-level dielectric layer flat. Corrosion inhibitors are used in both the CMP and post-CMP brush cleaning processes, and these and other contaminants must be removed from the copper side before depositing the capping layer. When the upper copper interface of the copper layer is capped with a tungsten or CoWP metal layer, it has been reported that there has been a significant improvement in copper electromigration lifetime. Unfortunately, all methods using selective metal capping solutions are likely to deposit unwanted metal 418, for example, as shown, on adjacent insulator surfaces, thus causing electrical shorts or short circuits between adjacent metal lines. Can be. Selective metal deposition techniques offer the potential to greatly improve electron transport, but are fabricated because of the high potential for yield loss in semiconductor die due to the deposition of unwanted contaminating metals on adjacent insulator surfaces of inter-level dielectric layers. It is not widely adopted at the stage. Although not shown in FIG. 2, wiring design 400 is typically formed on a semiconductor substrate containing reactive and / or non-reactive elements that require electrical interconnection to complete the integrated circuit.

The use of gas-cluster ion beams for surface processing is known in the art (see US Pat. No. 5,814,194 to Deguchi et al.). As used herein, the term gas-cluster is a nanosize aggregate of materials that is gaseous under standard temperature and pressure conditions. Such gas-clusters typically consist of aggregates in which several to thousands of molecules are loosely bound to form a gas-cluster. The gas-clusters can be ionized by electron bombardment or other means, forming them as directed beams of controllable energy. Each of these ions typically has a positive charge of q · e, where e is electronic charge and q is one (1) to several integers representing the charge state of the gas-cluster ion. Unionized gas-clusters may also be present in the gas-cluster ion beam. Larger sized gas-cluster ions are often the most useful because of their ability to carry significant energy per gas-cluster ion while having only moderate energy per molecule. In a collision, the gas-cluster decomposes with each individual molecule having only a very small fraction of the total gas-cluster ion energy. As a result, the collision effect of large gas-cluster ions is significant, but the effect is limited to a very shallow surface area. This allows gas-cluster ions to be effective in various surface modification processes, without the possibility of causing damage under deep surfaces that is characteristic of conventional monomer ion beam processing. Means for the generation and acceleration of such GCIBs are described in the references cited above (US Pat. No. 5,814,194). Currently available gas-cluster ion sources represent a wide range of sizes, N (where N represents the number of molecules in each gas-cluster ion, and throughout the discussion, for gaseous units such as argon, The atom of the monoatomic gas is referred to as a molecule, and the ionized atom of this monoatomic gas produces a gas-cluster ion having molecular ions, or simply monomer ions). . Many useful surface-processing effects can be achieved by bombarding the surface with GCIB. These processing effects include, but are not necessarily limited to, cleaning, smoothing, etching, doping and film formation or growth. Allen et al., US Pat. No. 6,537,606, teach the use of GCIB for correct etching of initial non-uniform thin films to improve spatial uniformity. The entirety of US Pat. No. 6,537,606 is incorporated herein by reference.

When impinging an energetic gas-cluster on the surface of a solid target, the penetration of cluster atoms into the target surface is typically very shallow because the penetration depth is limited by the low energy of each individual constituent atom and the gas This is mainly due to the transient thermal effect that occurs during cluster ion collisions. The gas-cluster splits on impact, after which individual gas atoms are free to recoil, possibly leaving the surface of the target. In addition to the energy dissipated by the departure of individual gas atoms, the total energy of the cluster with the energy before the collision will accumulate in the impact zone of the target surface. The size of the target impact zone depends on the energy of the cluster, but is about the size of the cross section of the colliding cluster, for example, as small as approximately 30 Angstroms in diameter for a cluster of 1000 atoms. Since most of the total energy carried by the clusters accumulates in a small impact area on the target, very severe thermal transients occur within the target material at the point of impact. This thermal transient is quickly dissipated as energy is lost from the impact zone by conduction going deep into the target. The duration of thermal transients is determined by the conductivity of the target material, but is typically less than 10 ⁻⁶ seconds.

Near the point of impact of the gas-cluster, most of the target surface instantaneously reaches hundreds of Kelvin temperatures to several thousand Kelvin temperatures. As an example, it is estimated that the collision of a gas-cluster with a total energy of 10 keV can produce a temporary temperature increase of about 2000 Kelvin temperature over a highly excited approximately hemispherical region extending under the surface to about 100 angstroms. . This high temperature transient promotes mixing and / or reaction of the workpiece and gas-cluster ion beam components, thus improving the electromigration lifetime.

After the onset of elevated temperature transients in the target volume below the gas-cluster impact point with energy, the affected area cools rapidly. During this process, some of the gas-cluster components leave, but others remain behind and incorporate into the surface. In addition, part of the original surface material can be removed by effects such as sputtering. In general, more volatile and inert components of the gas-cluster are more likely to escape, but less volatile and more chemically reactive components are more likely to be incorporated into the surface. The actual process may be much more complicated, but the gas-cluster collision point and the affected area surrounding it, the gas-cluster atoms simply interact and mix with the substrate surface, and the gas-cluster material is released from the surface or It is convenient to consider it as a "melt zone" which is injected into the surface up to the depth of the affected area. The term "infusion" or "infusing" is used by the inventors to refer to ions "implantation" or "implanting" which are very different processes that produce very different results. To distinguish, it is used to represent the process. For example, noble gases in gas-cluster ions with energies such as argon and xenon are volatile and non-reactive, so they are more likely to deviate from the affected areas, for example carbon, boron, Materials such as fluorine, sulfur, nitrogen, oxygen, germanium and silicon are less volatile and / or can form chemical bonds better and are therefore more likely to remain in the affected area and incorporated into the surface of the substrate.

For example, but not limited to, inert rare gases such as argon and xenon can be mixed with gases containing less volatile and / or more reactive elements to form mixed clusters. Such gas-clusters can be supplied by using a suitable source gas mixture as a source gas for gas-cluster ion beam generation, or by supplying two or more gases (or gas mixtures) to the gas-cluster ion generating source and they By mixing in, it can be formed using conventional gas-cluster ion beam processing equipment as described below. In a recent publication, Borland et al. ("USJ and strained-Si formation using infusion doping and deposition", Solid State Technology, May 2004, p. 53) reported that GCIB implantation from the substrate material into the deposited layer of the surface. It is shown that a smoothly changing graded surface layer can be created.

Accordingly, one object of the present invention is to provide a method of capping copper interconnects in an interconnect structure to reduce susceptibility to undesirable electromigration effects without the need for using a selective metal deposition cap.

It is a further object of the present invention to provide a method for effectively capping copper interconnects in interconnect structures without affecting the insulating or short-circuit characteristics of adjacent dielectric materials.

It is a further object of the present invention to provide a method of forming a multi-level copper interconnect for a circuit, in which the process yield is high and the sensitivity of breakage due to the electron transfer effect is reduced.

It is a further object of the present invention to provide an improved capped copper interconnect layer for integrated circuits, with high process yield and reduced susceptibility to electromigration breakdown.

It is another object of the present invention to avoid undesirable contamination by incorporating process steps in a cluster tool configured to perform one or more steps of the method by gas-cluster ion beam processing. Accordingly, there is provided an improved apparatus for performing improved capping of copper interconnect structures for integrated circuits.

One aspect of the present invention provides a method of forming a capping structure on a structure comprising at least one copper interconnect surface, and at least one surface of a barrier layer material covering the dielectric material, which is a pressure reducing chamber ( placing the structure in a reduced pressure chamber, forming an accelerated capping GCIB in a reduced pressure chamber, and at least one of the one or more copper interconnect surfaces and at least one surface of the barrier layer material covering the dielectric material. Directing the GCIB to form one or more capping structures on one or more copper interconnect surfaces to which the accelerated capping GCIB is directed.

The barrier layer material may have a first thickness, and the directing step may inject the layer to one or more of the one or more surfaces of the barrier layer material covering the dielectric material, the injected layer having a second thickness less than the first thickness. Has The method may further comprise etching the implanted layer and the barrier layer material covering the dielectric material. The etching step may further comprise forming an accelerated etch GCIB in the pressure reducing chamber and directing the accelerated etch GCIB to one or more surfaces of the barrier layer material covering the dielectric material.

The method includes the steps of forming an accelerated cleaning GCIB in a reduced pressure chamber and at least one of the at least one copper interconnect surface and at least one of the at least one surface of the barrier layer material covering the dielectric material prior to capping GCIB forming and directing steps. Directing the cleaning GCIB to clean one or more surfaces to which the accelerated cleaning GCIB is directed. Forming the accelerated clean GCIB may further comprise generating gas-cluster ions from molecules of one or more gases selected from the group consisting of Ar, N ₂ , NH ₃ and H ₂ . Forming the accelerated clean GCIB may further include accelerating the clean GCIB gas cluster ions to an acceleration potential of about 3 to about 50 kV. Directing the accelerated cleaning GCIB may include a dosage ranging from about 1 × 10 ¹⁴ to about 1 × 10 ¹⁷ gas-cluster ions / cm 2, at least one of the at least one copper interconnect surface and at least one surface of the barrier layer material covering the dielectric material. Can be delivered to one or more of the following.

The method may further comprise forming one or more insulating layers overlying the formed one or more capping structures. Forming one or more insulating layers may use PECVD deposition. The at least one insulating layer formed may be made of one material selected from the group consisting of silicon carbide, silicon nitride and silicon nitride carbon. Forming at least one insulating layer overlying at least one capping structure includes forming an accelerated deposition GCIB in a reduced pressure chamber and directing the accelerated deposition GCIB to at least one copper interconnect surface, thereby depositing at least one insulating layer. It may further comprise. One or more insulating layers overlying one or more capping structures may be a dielectric diffusion barrier.

Another aspect of the invention provides a cluster device for processing one or more wafers in a reduced pressure atmosphere, the cluster device comprising one or more fixtures for moving one or more wafers into and / or out of the cluster device. lock), one or more conveying chambers, one or more GCIB processing chambers, one or more cleaning chambers, and one or more wafer conveying devices suitable for transferring one or more wafers from the chamber to the chamber.

The GCIB processing chamber may be suitable for performing a copper capping process on at least a portion of one or more wafers, and the cleaning chamber may be suitable for performing cleaning prior to the copper capping process. The cleaning chamber may be a plasma cleaning chamber. The GCIB processing chamber may be suitable for forming a dielectric diffusion barrier in at least a portion of one or more wafers.

Another aspect of the invention provides a cluster device for processing one or more wafers in a reduced pressure atmosphere, the cluster device comprising one or more fixtures for moving one or more wafers into and / or out of the cluster device; One or more conveying chambers, one or more GCIB processing chambers, one or more deposition chambers, and one or more wafer conveying devices suitable for transferring one or more wafers from the chamber to the chamber.

The GCIB processing chamber may be suitable for performing a copper capping process on at least a portion of one or more wafers, and the deposition chamber may be suitable for forming a dielectric diffusion barrier over capped copper on at least a portion of the one or more wafers. The deposition chamber may be a PECVD deposition chamber. GCIB processing chambers may be suitable for performing cleaning prior to the copper capping process.

Another aspect of the invention provides a cluster device for processing one or more wafers in a reduced pressure atmosphere, the cluster device comprising one or more fixtures for moving one or more wafers into and / or out of the cluster device; One or more conveying chambers, one or more GCIB processing chambers, one or more deposition chambers, one or more cleaning chambers, and one or more wafer conveying devices suitable for transferring one or more wafers from the chamber to the chamber.

The GCIB processing chamber may be suitable for performing a copper capping process on at least a portion of one or more wafers, and the cleaning chamber may be suitable for performing cleaning prior to the copper capping process. The GCIB processing chamber may be suitable for performing a copper capping process on at least a portion of one or more wafers, and the deposition chamber may be suitable for forming a dielectric diffusion barrier over the capped copper. The deposition chamber may be a PECVD deposition chamber. The cleaning chamber may be a plasma cleaning chamber. GCIB processed chambers may be suitable for forming dielectric diffusion barriers. The GCIB processing chamber may be suitable for cleaning at least a portion of one or more wafers prior to the copper capping process.

Another aspect of the invention provides a cluster device for processing one or more wafers in a reduced pressure atmosphere, the cluster device comprising one or more fixtures for moving one or more wafers into and / or out of the cluster device; A plurality of GCIB processing chambers and one or more wafer conveying devices suitable for transferring one or more wafers from the chamber to the chamber may be included.

The GCIB processed chamber may be suitable for performing a copper capping process on at least a portion of one or more wafers, and the GCIB processed chamber may be suitable for forming a dielectric diffusion barrier over the capped copper. The GCIB processing chamber may be suitable for performing a copper capping process on at least a portion of one or more wafers, and the GCIB processing chamber may be suitable for performing a cleaning process prior to the copper capping process. The GCIB processing chamber may be suitable for performing a copper capping process on at least a portion of one or more wafers, the GCIB processing chamber may be suitable for performing cleaning prior to the copper capping process, and the GCIB processing chamber may be placed on the capped copper It may be suitable for forming a dielectric diffusion barrier.

Another aspect of the invention provides a method of forming a capping structure over a structure comprising at least one copper interconnect surface and at least one dielectric surface, the method comprising disposing a structure in a reduced pressure chamber, accelerated capping GCIB in the reduced pressure chamber. And directing the accelerated capping GCIB to one or more of the one or more copper interconnect surfaces and the one or more dielectric surfaces to form one or more capping structures on the one or more surfaces to which the accelerated capping GCIB is directed. .

Forming the accelerated capping GCIB may further include generating an electrically insulating material when injected into the copper surface and generating gas-cluster ions from the element that forms the electrically insulating material when injected into the dielectric surface, At least one capping structure is an electrically insulating capping structure. Forming the accelerated capping GCIB may further include generating gas-cluster ions from the element that forms an electrically conductive material when injected into the copper surface and that forms an electrically insulating material when injected into the dielectric surface, the formed The one or more capping structures can include one or more of an electrically conductive capping structure over the irradiated area of the copper interconnect portion and an electrically insulating capping structure over the irradiated area of the dielectric portion. Forming the accelerated capping GCIB may further include generating gas cluster ions from the rare gas or mixture of rare gases, wherein the one or more capping structures formed comprise at least an electrically conductive capping structure over the irradiated area of the copper interconnect portion. Can be. Forming the accelerated capping GCIB may further comprise generating gas cluster ions from Ar or Xe or a mixture of Ar and Xe, wherein the one or more capping structures formed are at least electrically conductive capping over the irradiated area of the copper interconnect portion. It may include a structure.

Another aspect of the invention provides a method of forming a copper capping structure over an integrated circuit interconnection layer comprising at least one copper interconnect surface and at least one dielectric layer region coated with a barrier layer material, the method comprising at least one copper interconnect structure. Forming one or more capping structures on the interconnect surface, and after forming one or more capping structures on the one or more copper interconnect surfaces, removing the barrier layer material covering one or more of the one or more dielectric layer regions. . The forming step may further include forming the accelerated capping GCIB and directing the accelerated capping GCIB to one or more of the one or more copper interconnect surfaces. The removing may include forming an accelerated etch GCIB and directing the accelerated etch GCIB to the barrier layer material.

Another aspect of the invention provides a method of forming a copper capping structure over an integrated circuit interconnection layer comprising at least one copper interconnect surface and at least one dielectric layer region coated with a barrier layer material, the method comprising: a first beam Forming an acceleration capping GCIB using an acceleration potential, directing the acceleration capping GCIB to one or more of the one or more copper interconnect surfaces to form one or more capping structures on the one or more copper interconnect surfaces, the lower than the first beam acceleration potential Forming an accelerated etch GCIB using the second beam acceleration potential, and directing the accelerated etch GCIB to the one or more capping structures and the barrier layer material to remove the barrier layer material.

Another aspect of the invention provides a method of forming a copper capping structure on an integrated circuit interconnection layer comprising at least one copper interconnect surface and at least one dielectric layer region coated with a barrier layer material, the method comprising an accelerated capping GCIB Forming at least one capping structure on at least one copper interconnect surface, directing the accelerated capping GCIB to at least one of the at least one copper interconnect surface, forming at least one capping structure, and blocking at least one capping structure and blocking. Directing the accelerated etching GCIB to the layer material to remove the barrier layer material covering one or more of the one or more dielectric layer regions without removing all of the one or more capping structures.

Another aspect of the invention provides an integrated circuit interconnection layer made by one or more of the above described method steps, comprising one or more capped copper interconnect surfaces and one or more dielectric layer regions.

Another aspect of the invention provides an integrated circuit interconnection layer made by one or more of the above described method steps, comprising one or more capped copper interconnect surfaces and one or more dielectric layer regions.

A further aspect of the present invention provides a method of processing a semiconductor wafer in a cluster device system while maintaining a reduced pressure atmosphere in the cluster device system, the method using a GCIB process in a first GCIB processing chamber of the cluster device on a semiconductor wafer. Forming a capping layer on the copper interconnect surface and the barrier layer material surface over the dielectric material, transferring the semiconductor wafer from the first GCIB processing chamber of the cluster device to the second GCIB processing chamber in a reduced pressure atmosphere of the cluster device; And removing the barrier layer material from the dielectric layer using a GCIB etching process in the 2 GCIB processing chamber.

The method comprises, prior to the forming step, cleaning the copper interconnect surface and the barrier layer material surface in a third processing chamber of the cluster device using a cleaning process and in the third processing chamber of the cluster device in a reduced pressure atmosphere of the cluster device. The method may further include transferring the semiconductor wafer to the first GCIB processing chamber of the cluster device. The third processing chamber of the cluster device may be a GCIB processing chamber, and the cleaning process includes a GCIB cleaning process.

A further aspect of the present invention provides a method of processing a semiconductor wafer in a cluster device system while maintaining a reduced pressure atmosphere in the cluster device system, the method using a GCIB process in a first GCIB processing chamber of the cluster device on a semiconductor wafer. Forming a capping layer over the copper interconnect surface and the dielectric material, transferring the semiconductor wafer from the first GCIB processing chamber of the cluster device to the second processing chamber in a reduced pressure atmosphere of the cluster device, and using a dielectric film-forming process And forming a dielectric diffusion barrier on the capping layer in the second processing chamber of the cluster device.

The method comprises, prior to the forming step, cleaning the copper interconnect surface and the barrier layer material surface in a third processing chamber of the cluster device using a cleaning process and in the third processing chamber of the cluster device in a reduced pressure atmosphere of the cluster device. The method may further include transferring the semiconductor wafer to the first GCIB processing chamber of the cluster device. The third processing chamber of the cluster device may be a GCIB processing chamber, and the cleaning process includes a GCIB cleaning process. The second processing chamber of the cluster device may be a GCIB processing chamber, and the dielectric film-forming process may include a GCIB injection process.

In order to better understand the present invention, together with other and further objects of the present invention, reference is made to the accompanying drawings and the detailed description of the invention.

1 is a schematic diagram showing a prior art silicon nitride capped copper interconnect wiring design.

2 is a schematic diagram illustrating a prior art selective metal capped copper interconnect wiring design.

3 is a schematic view showing the basic elements of a GCIB processing apparatus of the prior art.

4A, 4B, 4C, 4D and 4E are schematic diagrams illustrating a copper interconnect capping process by GCIB injection in accordance with a first aspect of the present invention.

5A, 5B, 5C, 5D, 5E, 5F, 5G, 5H, 5I, 5J, 5K, and 5L show copper using GCIB implantation and deposition according to a second aspect of the present invention. A schematic diagram illustrating the interconnect capping process.

6A, 6B, 6C, 6D, 6E, 6F and 6G are schematic diagrams illustrating a copper interconnect capping process using GCIB implantation and deposition in accordance with a third aspect of the present invention.

7A, 7B, 7C, 7D, 7E, 7F and 7G are schematic diagrams illustrating a copper interconnect capping process using GCIB implantation and deposition in accordance with a fourth aspect of the present invention.

8A and 8B show diagrams of example cluster devices that may be used in some exemplary aspects of the invention.

9 is a table showing another example of an embodiment described in the present specification.

Detailed Description of Certain Aspects of the Invention

FIG. 3 is a schematic illustration of the basic elements of a typical configuration for a GCIB processing apparatus 100 of the type known in the prior art, which may be described as follows: The vacuum vessel 102 is a source chamber 104, It is divided into three communicating chambers, an ionization / acceleration chamber 106 and a processing chamber 108. These three chambers are each evacuated to a suitable operating pressure by vacuum pumping systems 146a, 146b and 146c. The first condensable source gas 112 (eg, argon or nitrogen or a premixed gas mixture) stored in the first gas storage cylinder 111 is passed through the first gas shutoff valve 115 and the first gas metering. It is introduced into the atmospheric chamber 116 under pressure through the valve 113 and the gas supply tube 114. Any second condensable source gas 232 (eg, carbon dioxide, oxygen, or premixed gas mixture) stored in any second gas storage cylinder 203 is passed through the second gas shutoff valve 236 and It is optionally introduced under pressure through the second gas metering valve 234. In the case of using both source gases, they are mixed in the gas supply tube 114 and the atmospheric chamber 116. The gas or gas mixture in the atmospheric chamber 116 is evacuated to a substantially lower pressure vacuum through the nozzle 110 having a suitable shape. Supersonic gas jet 118 is generated. Cooling resulting from expansion in the jet condenses a portion of the gas jet 118 into a gas-cluster, which consists of several or thousands of weakly bonded atoms or molecules each. The gas skimmer aperture 120 partially separates gas molecules that have not condensed from the gas-cluster jet into the gas-cluster jet, so that this higher pressure is disadvantageous in downstream regions (eg, ionizers). 122), the high voltage electrode 126 and the processing chamber 108 are minimized. Suitable condensable source gases 112 include, but are not limited to, argon, nitrogen, carbon dioxide, oxygen and other gases and / or gas mixtures.

After the supersonic gas jet 118 containing the gas-cluster is formed, the gas-cluster is ionized in the ionizer 122. Ionizer 122 typically produces hot electrons from one or more incandescent filaments 124 in the region where gas jet 118 passes through ionizer 122 to produce gas-clusters within gas jet 118. It is an electron collision type ionization device that accelerates and directs these electrons so as to collide with them. Electron impingement releases electrons from the gas-cluster so that a portion of the gas-cluster is ionized reliably. Some gas-clusters may have one or more electrons emitted and may be multiple ionized. A suitably biased high voltage electrode set 126 extracts gas-cluster ions from the ionizer, forming a beam, and then accelerating them with a predetermined energy (typically an acceleration potential of several hundred V to several tens of kV), These are concentrated to form GCIB 128. The filament power supply 136 provides a filament voltage V _f for heating the ionizer filament 124. The anode power supply 134 provides an anode voltage V _A for accelerating hot electrons emitted from the filament 124 to irradiate the gas-cluster containing gas jet 118 to produce ions. The extraction power supply 138 provides an extraction voltage V _E for biasing the high voltage electrode to extract ions from the ionization region of the ionizer 122 to form the GCIB 128. The accelerator power supply 140 provides an acceleration voltage V _Acc for biasing the high voltage electrode to the ionizer 122 so that the overall GCIB acceleration potential is equal to V _Acc . One or more lens power supplies (eg, 142 and 144 shown) may be provided to bias the concentrated voltage (eg, V _L1 and V _L2 ) to the high voltage electrode to concentrate the GCIB 128. .

The workpiece 152, which may be a semiconductor wafer or other workpiece that may be processed by GCIB processing, is held in the workpiece holder 150, which may be placed in the path of the GCIB 128. In most applications, large workpieces are considered to be processed to have a spatially uniform result, so in order to produce a spatially homogeneous result, the scanning system needs to scan the GCIB 128 uniformly over a large area. desirable.

GCIB 128 is fixed, has a GCIB axis 129, and workpiece 152 is mechanically scanned through GCIB 128 to distribute the effect of GCIB 128 over the surface of workpiece 152. do.

The X-scan actuator 202 provides a linear motion of the workpiece holder 150 in the direction of the X-scan motion 208 (left and right relative to the paper surface). Y-scan actuator 204 provides linear movement of workpiece holder 150 in the direction of Y-scan motion 210, which is typically perpendicular to X-scan motion 208. The combination of X-scanning and Y-scanning motion moves the workpiece 152 held by the workpiece holder 150 in a raster-type scanning motion through the GCIB 128 to process the workpiece 152. To the surface of the workpiece 152 uniformly (or alternatively by program) by the GCIB 128. Since the workpiece holder 150 places the workpiece 152 at an angle with respect to the axis of the GCIB 128, the GCIB 128 has a beam incidence angle with respect to the workpiece 152 surface. The angle of incidence 206 of the beam may be 90 °, or may be another angle, but is typically 90 ° or nearly 90 °. During Y-scanning, the workpiece 152 and the workpiece hold 150 move from the position shown to other positions “A”, denoted by 152A and 150A, respectively. Note that in the movement between the two positions, the workpiece 152 is scanned through the GCIB 128 and, at both extreme positions, moves completely off the path of the GCIB 128 (over-scanned). do. Although not clearly shown in FIG. 3, similar scanning and over-scanning is performed (normally) in a direction perpendicular to the X-scan motion 208 direction (left and right relative to the longitudinal plane).

The beam current sensor 218 is disposed in the path of the GCIB 218 past the workpiece holder 150 to scan a sample of the GCIB 128 when the workpiece holder 150 is scanning off the path of the GCIB 128. Block it. Beam current sensor 218 is typically a Faraday cup or the like, closed except for the beam-entry opening, and is typically fastened to the wall of vacuum vessel 102 using electrically insulating mount 212. It is.

The controller 220, which may be a microcomputer based controller, connects with the X-scan actuator 202 and the Y-scan actuator 204 via an electrical cable 216, and the X-scan actuator 202 and the Y-scan The actuator 204 is controlled to allow the workpiece 152 to enter or exit the GCIB 128 and to scan the workpiece 152 uniformly with respect to the GCIB 128 so that the purpose of the workpiece 152 by the GCIB 128 is achieved. To achieve processing. The controller 220 receives the sample beam current collected by the beam current sensor 218 by the lead wire 214 and thereby monitors the GCIB so that the workpiece (from the GCIB 128 when the desired desired dose is delivered) By removing 152, the amount of GCIB radiation received by the workpiece 152 is controlled.

4A is a schematic diagram illustrating a wiring design 500 of a capped copper interconnect using GCIB implantation in accordance with a first aspect of the present invention (eg, showing, but not limited to, two copper interconnect layer interconnect levels). to be. The schematic diagram shows a substrate 501 for supporting a first copper wiring layer 502, a second copper wiring layer 504 and a copper via structure 506 connecting two copper layers, each of which employs conventional techniques. Can be formed using. Substrate 501 is typically a semiconductor substrate (possibly including a lower interconnect level) containing reactive and / or non-reactive elements that require electrical interconnection. Sidewalls and bottoms of both copper interconnect layers 502 and 504 and via structure 506 are lined with TaN / Ta or other conventional blocking layers 512 that can be formed using conventional techniques. The first inter-level dielectric layer 508 and the second inter-level dielectric layer 510 provide electrical insulation between the copper wiring layer and other members, and can be formed using conventional techniques. The top surface of the first copper wiring layer 502 and the top surface of the first inter-level dielectric layer 508 and the top surface of the second copper wiring layer 504 and the top surface of the second inter-level dielectric layer 510 are both capped by GCIB processing. To form capping films 514, 516, and 518. It is desirable to perform a separate GCIB capping process on top of each interconnection level. In conventional dual damascene copper interconnects, trenches and vias are formed in the inter-level dielectric layer and then copper is deposited to form interconnect wiring and vias, followed by exposure to copper and interconnects using chemical mechanical polishing (CMP) techniques. A planarization step is typically performed at the level dielectric layer material surface. Corrosion inhibitors are used on surfaces to be polished in both CMP techniques and post-CMP brush cleaning processes, and in situ cleaning ("in-situ" as used herein) is performed at the same reduced pressure atmosphere just prior to forming the capping layer. Means that cleaning occurs at the copper and copper capping depositions, wherein the capping deposition does not return to atmospheric pressure between the cleaning and capping steps and is performed to reduce the chance of recontamination of the cleaned surface between the cleaning and capping steps). It is desirable to remove (along with other contaminants) from the dielectric surface. PECVD reactors are typically not configured to perform effective in situ cleaning of the copper surface prior to insulator capping layer deposition. Unlike PECVD systems, for example, GCIB processing systems such as processing apparatus 100 are configured to achieve easy and typically continuous in-situ cleaning and capping. As described below, the exposed copper and inter-levels, which may preferably be performed in place, for example by a plasma cleaning process or, preferably, conventional dry cleaning processes such as GCIB processing. After cleaning the dielectric surface, the GCIB implantation process is used to cap the planarized surface (copper and exposed inter-level dielectric simultaneously).

4B shows a preliminary step 500B of the wiring design 500. In the step shown, the interconnect level is formed on the substrate 501. The interconnect level includes a first inter-level dielectric 508 deposited on a substrate using conventional techniques. Conventional trenches and vias are formed in the first inter-level dielectric 508 and lined with conventional blocking layers 512. Copper is deposited in trenches and vias using conventional techniques. The top surface of the structure is planarized and cleaned using conventional processes. There is residual contaminant 503 on top of the first copper interconnect layer 502 and the first inter-level dielectric layer 508. At this stage and in the corresponding stage of each subsequent interconnect level (assuming one or more interconnect levels), for example, a conventional dry cleaning process, preferably in place, such as a plasma cleaning process or a GCIB cleaning process Can be performed. GCIB cleaning uses a beam acceleration potential (V _Acc ) of the surface (s) to be cleaned, preferably in the range of about 3 kV to about 50 kV, and a total gas in the range of about 5 × 10 ¹³ to about 5 × 10 ¹⁶ ions / cm 2. Irradiating with GCIB cluster ions consisting of molecules of Ar, N ₂ , NH ₃ or H ₂ gas or mixtures thereof in a cluster ion dosage. Those skilled in the art recognize that the present invention is not limited to these exemplary gases, but may be practiced with other gases or gas mixtures that remove post-CMP residues, copper oxides and other contaminants from the copper surface. something to do. Although not essential to the present invention, it is preferred that this GCIB cleaning process is an in-situ cleaning process.

4C shows step 500C of wiring design 500 after the GCIB cleaning step. The contaminants are cleaned on the top surfaces of the first copper interconnect layer 502 and the first inter-level dielectric layer 508 and prepared for the capping step. At this stage and at the corresponding stage of each subsequent interconnect level (assuming one or more interconnect levels), a GCIB capping process is performed. The GCIB capping process irradiates the top surface of the first copper interconnect layer 502 and / or the first inter-level dielectric layer 508 with GCIB made of original exposed dielectric and / or elements that form an insulating material upon injection into the copper surface. It includes. For example, GCIB having a gas-clustered ionic element consisting of C, N, O, Si, B or Ge, or mixtures thereof is suitable, and on copper, for example, Si ₃ N ₄ , SiCN, CuCO _A conversion capping film such as ₃ and BN can be formed. Other elements and combinations that form suitable dielectric materials when injected into copper and / or adjacent insulators may also be used. For example, source gases such as CH ₄ , SiH ₄ , NH ₃ , N ₂ , CO ₂ , B ₂ H ₆ , GeH ₄ and mixtures thereof can be used. Such gases can be used in their pure form or mixed with an inert gas such as, for example, Ar or Xe to form cluster ions. Referring to the GCIB processing apparatus 100 of FIG. 3, in order to achieve implantation, the beam acceleration potential (V _Acc ) in the range of about 3 kV to about 50 kV and in the range of about 1 × 10 ¹⁴ to about 1 × 10 ¹⁷ ions / cm 2 The total gas-cluster ion dosage can be used.

4D shows step 500D of wiring design 500 after the GCIB capping step. At the copper surface and / or adjacent inter-level dielectric surfaces, the collision energy and thermal transients characteristic of the GCIB process are injected into the top surface of the copper wiring and / or adjacent inter-level dielectric structures exposed to the GCIB, respectively, so that the capping layer ( 514, 516. The capping layers 514 and 516 may each optionally further include an upper portion that acts as a dielectric barrier. During the initial part of the formation process, the conversion layer 514A of mixed copper / GCIB species composition is injected into the copper surface. This mixed layer provides a conversion interface between all subsequent dielectric barrier films 514B and underlying copper, thereby limiting copper diffusion at the interface and improving electromigration lifetime. The dielectric barrier 514B layer deposited thereafter may be a separate additional film deposited by conventional PECVD, but in short, the mixed conversion layer is passed until the process proceeds from the implantation process (at increased dosage) to the pure deposition process. It is desirable to deposit by GCIB as an extension of the GCIB capping implantation step, which continues the initial capping GCIB irradiation process and deposits a dielectric material over the mixed layer at the implantation surface of copper. The initially injected mixed conversion layer 514A acts as a capping layer, and as GCIB irradiation continues, subsequent deposition of additional dielectric material forms a deposited dielectric barrier film 514B. This results in a dielectric film that is integrated with the copper interconnect due to the mixed conversion layer, thus resulting in improved interfacial properties, including good electrophoretic lifetime. The same (or other) capping GCIB forming capping layer 514 preferably forms capping layer 516 on inter-level dielectric 508. Like capping layer 514, capping layer 516 may be a bilayer. The capping layer 516 initially forms a mixed conversion layer of dielectric / GCIB species composition mixed on the surface, and may also deposit the dielectric barrier film deposited by a subsequent GCIB process or additional separate (eg, PECVD) deposition. It may include. For example, when the dielectric barrier 514B is not formed using an extended GCIB process, or particularly when a thick dielectric barrier 514B is required, the injected capping layer 514A or capping layer 516 may optionally Over-capping with conventional insulating layers such as PECVD Si ₃ N ₄ , SiCN or SiC can provide dielectric barriers for additional copper diffusion barriers or dielectric barriers for via etch-stop properties. have. After the capping step and the dielectric barrier film forming step, additional levels of interconnect can be added, if desired, using conventional techniques.

4E shows step 500E of wiring design 500 after adding a second interconnect level on the GCIB capped first interconnect level (including dielectric isolation). In this step, a second interconnect level is formed on the capping layers 514, 516. The second interconnect level consists of the second inter-level dielectric 510 deposited on the capping layers 514, 516 using conventional techniques. Trench and vias are formed in second inter-level dielectric 510, trenches and vias lined with blocking layer 512, and copper is deposited in trenches and vias using conventional techniques. The top surface of this structure is planarized and cleaned using conventional processes such as, for example, CMP. The top surface of the second copper interconnect layer 504 and the second inter-level dielectric layer 510 is shown with residual contaminants 505. At the second interlevel level (if any) and subsequent higher interconnect levels (if any), the GCIB cleaning and GCIB implantation steps are applied as described above for wiring design 500, capping film 518 as shown in FIG. 4A. ). Thus, in some cases, two-level or multi-level interconnect structures may be formed.

Thus, the above technique reduces electron transfer and avoids undesirable side effects associated with selective metal capping processes. At the dielectric surface, the injection layer and the dielectric remain insulating, and the extremely thin injection layer has a negligible effect on the overall dielectric constant and the lnter-layer capacitance of the layer.

5A illustrates a wiring design 600 of a capped copper interconnect using GCIB implantation and deposition in accordance with a second aspect of the present invention (eg, showing, but not limited to, two copper interconnect layer interconnect levels). It is a schematic diagram showing. The schematic diagram shows a substrate 601 supporting a first copper wiring layer 602, a second copper wiring layer 604, and a copper via structure 606 connecting two copper wiring layers, each of which employs conventional techniques. Can be used. Substrate 601 is typically a semiconductor substrate (possibly including a low interconnect level) that includes reactive and / or non-reactive elements that require electrical interconnection. Sidewalls and bottoms of both copper wiring layers 602 and 604 and via structure 606 are lined with TaN / Ta or other blocking layers 612 that can be formed using conventional techniques. The first inter-level dielectric layer 608 and the second inter-level dielectric layer 610 provide electrical insulation between the copper interconnect layers and may be formed using conventional techniques. Often, it is desirable for the inter-level dielectric layers 608, 610 to be porous to improve dielectric properties. In this case, the inter-level dielectric layer is a first hardmask layer composed of a material such as, for example, SiO ₂ , SiC or Si ₃ N ₄ , respectively, which can be deposited using conventional techniques, respectively. Hard mask layers such as 609 and second hard mask layer 611 may be optionally deposited. First copper interconnect layer 602, first inter-level dielectric layer 608 (or, optionally, the top surface of first hardmask layer 609, if present), second copper interconnect layer 604, and second inter-level The top surface of the dielectric layer 610 (or, optionally, the top surface of the second hard mask layer 611, if present) is all capped by GCIB processing to form the capping films 614, 616, 618, 620. The second aspect differs from the first aspect in that the element (s) containing GCIB gas-cluster ions are selected to retain conductor properties on the implanted paper copper surface (copper capping films 614, 618). Can be distinguished. However, the implanted element (s) may also have the same element (s) inter-level dielectric and / or dielectric hardmask within the dielectric region of each interconnect level (inter-level dielectric or hardmask capping films 616 and 620). It is selected to form an insulating film when injected into the surface of the material. The enhanced dielectric diffusion barrier (the barrier 622 for the first interconnect level and the barrier 624 for the second interconnect level) is preferably formed by GCIB deposition, but may be formed by conventional techniques. This barrier further enhances the diffusion barrier performance and via etch-stop properties of the GCIB injection cap.

It is desirable to apply a GCIB implantation process on top of each interconnection level to form copper and inter-level dielectric caps. As noted above, it is desirable to use GCIB in-situ cleaning after CMP planarization of copper interconnects and inter-level dielectrics. 5G shows a wiring design 600G in which the inter-level dielectric layers 608, 610 have no hard mask layers 609, 610 on top. Hereinafter, a process for configuring the wiring design 600G will be described.

5B shows a preliminary step 600B of the wiring design 600G. The interconnect level formed on the substrate 601 typically consists of a first inter-level dielectric 608 deposited therein, with trenches and vias formed and lined with a blocking layer 612. Trench and vias are deposited with copper using conventional techniques. The top surface of the structure is flattened and cleaned. An upper surface of the first copper interconnect layer 602 and the first inter-level dielectric layer 608 is shown having residual contaminants 603. At this stage and on top of the corresponding respective stage of each subsequent interconnect level (assuming at least one interconnect level), for example, in-situ, such as a plasma cleaning process or a GCIB cleaning process, Conventional dry cleaning processes may be performed. GCIB cleaning uses a beam acceleration potential (V _Acc ) of the surface (s) to be cleaned, preferably in the range of about 3 kV to about 50 kV, and a total gas in the range of about 5 × 10 ¹³ to about 5 × 10 ¹⁶ ions / cm 2. Irradiating with GCIB cluster ions consisting of molecules of Ar, N ₂ , NH ₃ or H ₂ gas or mixtures thereof in a cluster ion dosage. Those skilled in the art recognize that the present invention is not limited to these exemplary gases, but may be practiced with other gases or gas mixtures that remove post-CMP residues, copper oxides and other contaminants from the copper surface. something to do. Although not essential to the present invention, such a GCIB cleaning process is preferably an in situ cleaning process.

5C shows an intermediate step 600C in the configuration of the wiring design 600G after the GCIB cleaning step. The contaminants are cleaned on the top surfaces of the first copper interconnect layer 602 and the first inter-level dielectric layer 608 and prepared for the capping step. The GCIB capping process can now be applied to the cleaned top surface (s) of this step and each step of each subsequent interconnect level (assuming one or more interconnect levels). Using a (preferably in place) GCIB implantation process, the planarized surface (copper and / or exposed inter-level dielectric) is capped simultaneously (or by a separate capping GCIB). The GCIB capping process uses the first copper interconnect layer 602 and the first copper interconnect layer 602 and GCIB to form an electrically conductive material upon injection into the copper surface but an electrically insulating material upon injection into the inter-level dielectric surface. Irradiating the top surface of one inter-level dielectric layer 608. In addition, such conductive elements are selected so that the solid solubility in copper is not high so as not to adversely affect the electrical conductivity. Although not limited, GCIBs having gas-cluster ions comprising element B or Ti are suitable, which include, but are not limited to, SiO ₂ , SiC, SiCN, SiCOH, etc. to form insulating oxides, carbides or nitrides. In combination with a suitable dielectric hardmask material. Some suitable source gases containing B and Ti include, but are not limited to, B ₂ H ₆ , TiCl ₄ , tetra diethylamino titanium (TDEAT), tetradimethylamino titanium (TDMAT), and the like. These gases can be used in pure form or mixed with an inert gas such as, for example, Ar or Xe. A conversion film of, for example, TiO ₂ and borosilicate glass is formed on the dielectric surface by injection, and a conversion film of, for example, boron and titanium is formed on the copper surface. Alternatively, GCIB containing only inert gas-cluster ions, including but not limited to Ar or Xe or other rare gases or mixtures thereof, can form a conversion capping film by physically changing the surface of copper. In this case, the copper capping structure is a physically deformed layer of copper that is naturally converted and electrically conductive, and the physically deformed layer formed in the inter-level dielectric layer is electrically insulating. For example, these other GCIBs containing only inert gas-cluster ions such as Ar or Xe or other rare gases or mixtures thereof do not form an implanted layer but instead result in an effective capping structure for copper and insulation conditions. Physically alter the surface in such a way that the dielectric remains. Thus, the effect is that the GCIB capping process forms an electrically conductive material when implanted into a copper surface and an electrically insulating material when implanted into an inter-level dielectric surface, but no new species injection into the surface occurs by itself. The same applies to the case of irradiating the GCIB made of the element to the upper copper surface and the inter-level dielectric layer. Referring to the GCIB apparatus 100 of FIG. 3, preferably using a beam acceleration potential (V _Acc ) in the range of about 3 kV to about 50 kV, the overall range of about 1 × 10 ¹⁴ to about 1 × 10 ¹⁷ ions / cm 2. A gas-cluster ion dosage can be used. On copper and dielectric surfaces, the impact energy of the GCIB implantation process may be used to create transient high temperature regions or novel insulating (or inter-level dielectric or hard mask) materials that promote the intermixing and / or reaction of existing dielectrics and implant species. It creates a dielectric hard mask layer to form, and also forms a conductive film implanted on the copper wiring surface, thereby limiting copper interfacial diffusion and improving electron transfer life. Thus, the single GCIB capping implantation step forms an electrically conductive capping film 614 on the first copper interconnect layer 602 and an electrically insulating capping film on the first inter-level dielectric layer 608, as shown in FIG. 5D. 616 is formed.

5E shows step 600E in the configuration of wiring design 600G following the GCIB capping step. The GCIB process may be performed at the top (s) of this step and each step of each subsequent interconnect level to form a dielectric diffusion barrier. The dielectric diffusion barrier 622 is preferably made of silicon nitride, but may be silicon nitride, silicon carbide, or another dielectric film. This may typically be deposited by PECVD, but is preferably deposited by irradiating the surface of the capping films 614 and 616 on which the blocking film 622 is to be deposited with GCIB formed of an element that forms an insulating material upon injection. For example, GCIB having gas-clustered ionic elements such as C, N and Si or mixtures thereof is suitable, which deposits diffusion barriers such as, for example, Si ₃ N ₄ , SiCN and SiC on copper. can do. Source gases such as C, N and Si include, but are not limited to, CH ₄ , SiH ₄ , NH ₃ and N ₂ . Such gases can be used to form gas-cluster ions by evaporation by using pure gas or by mixing with an inert gas such as, for example, Ar or Xe. Preferably a beam acceleration potential (V _Acc ) in the range of about 3 kV to about 50 kV is used as the total gas-cluster ion dosage in the range of about 1 × 10 ¹⁴ to about 1 × 10 ¹⁷ ions / cm 2.

5F shows step 600F in the configuration of the wiring design 600G, reflecting the addition of the second interconnect level to the GCIB capped first interconnect level (including dielectric barrier) and the barrier 622. Drawing. The second interconnect level consists of a second inter-level dielectric 610 deposited on the blocking film 622, where trenches and vias are formed and lined with the blocking layer 612. Copper is deposited in trenches and vias using conventional techniques. The top surface of the structure is planarized and cleaned using conventional processes. The top surface of the second copper interconnect layer 604 and the second inter-level dielectric layer 610 is shown with residual contaminants 626. To construct the wiring design 600G, at the top surface (s) of the second interconnect level and (if any) the next higher interconnect level, the GCIB cleaning and GCIB implantation and GCIB deposition steps may be applied as described above. By these processing steps, the capping films 618 and 620 and the blocking film 624 are formed. Thus, in some cases, two interconnect level structures or multi-level interconnect structures of FIG. 5G may be formed.

FIG. 5H shows a preliminary step 600H in the process of constructing the wiring design 600 (with the hard mask layers 609, 611) as completed in FIG. 5A. The first interconnect level formed on the substrate 601 consists of a first inter-level dielectric 608 deposited on the substrate using conventional techniques. The hard mask layer 609 formed by conventional techniques covers the top surface of the first inter-level dielectric 608. Trenchs and vias are formed in the first inter-level dielectric 608, lined with a blocking layer 612, and copper is deposited in the trenches and vias. The upper surface of the structure is planarized and cleaned using a conventional cleaning process. An upper surface of the first copper wiring layer 602 and the hard mask layer 609 is illustrated as having residual contaminants 605. At the top (s) of this step and the corresponding step of each subsequent interconnect level, as described above, a GCIB cleaning process is preferably performed. Although not essential to the invention, it is preferred that the present GCIB cleaning process is an in-situ cleaning process. Although not essential to the invention, it is preferred that this GCIB cleaning process is an in-situ cleaning process.

FIG. 5I shows step 600I in the process of constructing the wiring design 600 (of FIG. 5A) after the GCIB cleaning step. The contaminants are cleaned on the upper surfaces of the first copper wiring layer 602 and the hard mask layer 609 and prepared for the capping step. The top surface (s) of this step and the corresponding respective step of each subsequent interconnect level may be subjected to a GCIB capping process to form capping layers 614, 616, as described above (FIG. 5J). . In this aspect, the capping layer 616 is not formed directly on the first inter-level dielectric layer 608, but is formed on the hard mask layer 609.

5J shows step 600J in the process of constructing wiring design 600 after forming capping layers 614, 616. To form the dielectric diffusion barrier film 622 on the capping layers 614, 616, the GCIB process, as described above, on the top (s) of this step and the corresponding respective step of each subsequent interconnect level. Can be applied.

5K shows step 600K in the process of constructing wiring design 600 after depositing barrier film 622.

5L shows step 600L in the process of configuring wiring design 600 after adding the second interconnect level on the GCIB capped first interconnect level (including the dielectric barrier). In this step, a second interconnect level is formed on the blocking film 622. The second interconnect level consists of a second inter-level dielectric 610 deposited on the blocking film 622 using conventional techniques. The hard mask layer 611 formed by conventional techniques covers the top surface of the first inter-level dielectric 610. Conventional trenches and vias are formed in the second inter-level dielectric 610, which are lined with conventional blocking layers 612, and copper is formed in the trenches and vias using conventional techniques. Deposited. The upper surface of the structure is planarized and cleaned using conventional processes. The upper surfaces of the second copper wiring layer 604 and the hard mask layer 611 are shown to have residual contaminants 613. At the second interconnect level (if present) and the subsequent higher interconnect level (if present), the GCIB cleaning and GCIB implantation and GCIB deposition steps are applied as described above for the wiring design 600 to provide a capping film (e.g., 618 and 620 are formed, and the blocking film 624 is formed (FIG. 5A). Thus, in some cases, two interconnect level structures or multi-level interconnect structures of FIG. 5A may be formed.

Thus, the disclosed technique reduces electromigration and moreover avoids undesirable side effects associated with selective metal capping processes. At the dielectric surface, the dielectric remains insulative even after capping, and the extremely thin injection layer has a negligible effect on the dielectric constant.

6A is a schematic diagram illustrating a wiring design 700 of a capped copper interconnect using GCIB implantation in accordance with a third aspect of the present invention (eg, showing, but not limited to, two copper interconnect layer interconnect levels). . The schematic diagram shows a substrate 701 supporting a first copper wiring layer 702, a second copper wiring layer 704, and a copper via structure 706 connecting two copper layers, each of which may be formed using conventional techniques. ). Substrate 701 is typically a semiconductor substrate that contains reactive and / or nonreactive elements (possibly including lower interconnect levels) that require electrical interconnection. Sidewalls and bottoms of both copper wiring layers 702 and 704 and via structure 706 are lined with a blocking layer 712 that can be formed using conventional techniques. The first inter-level dielectric layer 708 and the second inter-level dielectric layer 710 provide electrical insulation between copper interconnects and can be formed using conventional techniques. The first inter-level dielectric layer 708 has a top surface 709, and the second inter-level dielectric layer 710 has a top surface 711. As described in more detail below, at each copper interconnect interconnect level, as is typically deposited, the blocking layer 712 initially covers the top surfaces 709 and 711 of the inter-level dielectric layers 708 and 710. Sheathed (FIG. 6B). In this aspect of the invention, the GCIB processing described below removes the barrier layer 712 material from the top surfaces 709 and 711, so that in the finished structure shown in FIG. 6A they do not appear on the surface described above. . The top surface of the first copper wiring layer 702 and the top surface of the second copper wiring layer 704 are capped by GCIB processing to form the injection capping films 713 and 715. The implanted copper capping films 713 and 715 and adjacent inter-level dielectric layers 708 and 710 may be further capped with dielectric barrier films 714 and 716, respectively, to provide improved copper diffusion blocking and via etch-stop properties. . The dielectric barrier films 714 and 716 are preferably silicon nitride, but may also be silicon nitride or silicon carbide or other suitable dielectric, typically deposited using PECVD, but preferably applied by GCIB deposition.

6B shows a preliminary step 700B in the process of constructing the wiring design 700. In the step shown, interconnect levels are formed on the substrate 701. The interconnect level consists of a first inter-level dielectric 708 deposited on a substrate. Trenchs and vias are formed in the first inter-level dielectric 708 and lined with a blocking layer 712. Copper is deposited in the trenches and vias. The blocking layer 712 initially covers the top surface 709 of the inter-level dielectric layer 708. Excess copper is removed by conventional CMP that stops on the material of barrier layer 712. In addition, by using conventional CMP process conditions selected to preferentially remove copper at significantly higher rates than the barrier layer material, for example, a highly selective slurry that selectively removes copper over the barrier material can be removed. By using, copper slightly enters below the upper surface of the blocking layer 712, as shown. The surface is cleaned using conventional processes. Upper surfaces of the first copper interconnect layer 702 and the blocking layer 712 are illustrated as having residual contaminants 703. At the top (s) of this step and the corresponding step of each subsequent interconnect level (assuming one or more interconnect levels), preferably in situ, such as, for example, a plasma cleaning process or a GCIB cleaning process Dry cleaning process may be performed. GCIB cleaning uses a beam acceleration potential (V _Acc ) of the surface (s) to be cleaned, preferably in the range of about 3 kV to about 50 kV, and a total gas in the range of about 5 × 10 ¹³ to about 5 × 10 ¹⁶ ions / cm 2. Irradiating with GCIB cluster ions consisting of molecules of Ar, N ₂ , NH ₃ or H ₂ gas or mixtures thereof in a cluster ion dosage. Those skilled in the art recognize that the present invention is not limited to these exemplary gases, but may be practiced with other gases or gas mixtures that remove post-CMP residues, copper oxides and other contaminants from the copper surface. something to do. Although not essential to the present invention, it is preferred that this GCIB cleaning process is an in-situ cleaning process.

6C shows step 700C of the process of constructing the wiring design 700 after the GCIB cleaning step. The contaminants are cleaned on the upper surfaces of the first copper wiring layer 702 and the blocking layer 712 and prepared for the capping step. You can now apply the GCIB capping process. The GCIB etch and implant capping process (preferably in place) is used to simultaneously cap the surface of the first copper interconnect layer 702 and etch the blocking layer 712 overlying the top surface 709. The GCIB etch and capping process is a GCIB consisting of an element that forms a capping material upon injection into the copper surface but the blocking layer 712 material is an etch of the first copper interconnect layer 702 and the first inter-level dielectric layer 708. Investigate the top surface. GCIB irradiation, which etches the blocking layer 712 material exposed on the top surface 709 while simultaneously injecting capping species into the first copper interconnect layer 702, forms the capping film 713. Source gases containing fluorine and / or elemental sulfur, including but not limited to SF ₆ , CF ₄ , C ₄ F ₈ or NF ₃ , are used to form GCIB. These gases can be used to form gas-cluster ions for injection by using pure gas or by mixing with N ₂ or by mixing with an inert gas such as, for example, Ar or Xe. This implantation forms, for example, a copper capping film such as CuF ₂ . It is preferred to use a beam acceleration potential (V _Acc ) in the range of about 10 kV to about 50 kV, and nozzle gas flowing in the range of about 200 sccm to about 3000 sccm may be used. For example, a preferred process for etching a barrier layer material while simultaneously forming a copper capping film uses a source gas mixture of 10% NF ₃ in N ₂ at a flow rate of 700 sccm. The GCIB etch and implant process proceeds until all barrier layer material is removed, thereby revealing a relatively unchanged top surface 709 of the first inter-level dielectric layer 708 and also implanting with the capping film 713. Exposed copper surface. During most of the process there is little effect on top 709 because it is shielded from GCIB by the barrier layer 712 material.

6D shows step 700D in the process of configuring wiring design 700 after the GCIB etch and capping step. The top surface of the first copper wiring layer 702 is capped with a capping layer 713, and the blocking layer 712 is etched to expose the top surface 709 of the first inter-level dielectric layer 708. The structure is prepared to form a dielectric barrier film. Now, on the capping layer 713 and on the top surface 709 of the first inter-level dielectric layer 708 by performing a GCIB process, using the same method as described above to deposit the blocking film 622. The diffusion barrier layer 714 may be formed.

6E shows step 700E in the process of constructing the wiring design 700 after formation of the dielectric diffusion barrier 714.

FIG. 6F shows step 700F in the process of configuring the wiring design 700 of the second interconnect level on the GCIB capped first interconnect level (including the dielectric barrier). In this step, a second interconnect level is formed on the blocking film 714. The second interconnect level consists of a second inter-level dielectric 710 deposited on the blocking film 714. Trench and vias are formed in the second inter-level dielectric 710 and lined with a blocking layer 612. Copper is deposited in trenches and vias using conventional techniques. The blocking layer 712 initially covers the top surface of the inter-level dielectric layer 712. Excess copper is removed by conventional CMP that stops on the material of barrier layer 712. In addition, by using conventional CMP process conditions selected to preferentially remove copper at significantly higher rates than the barrier layer material, for example, by using a highly selective slurry that selectively removes copper over the barrier material. , Copper is slightly below the upper surface of the blocking layer 712 as shown. The surface is cleaned using conventional processes. The top surfaces of the second copper interconnect layer 704 and the blocking layer 712 are shown having residual contaminants 717. At the second interconnect level (if any) and at the subsequent higher interconnect level (if any), the GCIB clean and GCIB (etch and injection capping) and GCIB deposition steps are performed as described above for the first interconnect level in the wiring design 700. In addition, the capping film 715 and the blocking film 716 are formed. Thus, in some cases, two interconnect level structures or multi-level interconnect structures of FIG. 6A may be formed.

After the excess copper CMP removal described in wiring design 700, if the exposed barrier layer material has an undesirable spatial non-uniform thickness, the GCIB etch is spatially non-uniform in a selective but corrective manner. It is desirable to make it. First, Rudolf Technologies, Inc., available from Rudolph Technologies, Inc. of 07836 Flanders One Rudolph Road, NJ, USA. By using a metal film measuring system) to create a map of the thickness of the blocking layer over the entire surface of the workpiece wafer, the blocking layer is etched to be corrected etching as described above, where the blocking layer material is thicker. By allowing a lot of etch and less of the barrier layer material to be etched thinner, it is possible to minimize the removal of the underlying inter-level dielectric in areas that are excessively etched due to the initial thickness of the barrier layer material. This spatially corrected etch method is a barrier layer thickness measured with the technique taught in Allen et al. US Pat. No. 6,537,606, the contents of which are incorporated herein by reference (hereinafter referred to as the '606 patent). Is achieved using a map. Gas-clusters such as Epiion Corporation's nFusion ™ GCIB processing system (Epion Corporation, Willerca, Mass.) With automatic etch correction, operating from measurement maps according to the technique disclosed in the '606 patent. Ion beam processing equipment is commercially available.

In this aspect of the present invention, as described above, it is preferable to perform both the barrier layer etching and the copper capping in a single step using GCIB processing to perform both simultaneously. It is also possible to perform the barrier layer etch and copper capping process as separate GCIB process steps, with GCIB having different characteristics for each step, and may be useful in some cases. In this case, once the step shown in FIG. 6C is reached, the barrier layer material that is initially overlying the top surface 709 of the inter-level dielectric layer 708 is removed by the GCIB etching process prior to the GCIB capping step. . After the GCIB etching step, a structure as shown in FIG. 6G is revealed and prepared for copper interconnect layer and inter-level dielectric layer capping, which is performed using the GCIB capping process described above in various aspects of the invention. At each interconnect level, the preferred etching step comprises forming the surface to be cleaned from source gas (s) containing elemental fluorine, including but not limited to a gas such as SF ₆ , CF ₄ , C ₄ F ₈ or NF _3. Irradiation with GCIB cluster ions. These gases can be used to form gas-cluster ions for etching by using pure gas or by mixing with N ₂ or by mixing with an inert gas such as, for example, Ar or Xe. Preferably, a beam acceleration potential (VAcc) in the range of about 10 kV to about 50 kV is used, and a nozzle gas flowing in the range of about 200 sccm to about 3000 sccm may be used. For example, a preferred process for etching the barrier layer material uses a source gas mixture of 10% NF ₃ in N ₂ at a flow rate of 700 sccm. If desired, the GCIB etch step may be a correction etch step as described above to correct for initial spatial non-uniformity in the thickness of the barrier layer material.

FIG. 7A is a schematic diagram illustrating a wiring design 800 of a capped copper interconnect using GCIB implantation (eg, showing, but not limited to, two wiring layer interconnect levels) in accordance with a fourth aspect of the present invention. . The schematic diagram shows a substrate 801 supporting a first copper wiring layer 802, a second copper wiring layer 804, and a copper via structure 806 connecting these two copper layers, each of which is a conventional technique. It can be formed using. Substrate 801 is typically a semiconductor substrate (possibly including a lower interconnect level) containing reactive and / or non-reactive elements requiring electrical interconnection. Sidewalls and bottoms of both copper wiring layers 802 and 804 and via structure 806 are lined with a blocking layer 812 that can be formed using conventional techniques. The first inter-level dielectric layer 808 and the second inter-level dielectric layer 810 provide electrical insulation between copper wires and can be formed using conventional techniques. The first inter-level dielectric layer 808 has a top surface 809, and the second inter-level dielectric layer 810 has a top surface 811. As described in more detail below, at each copper interconnect interconnect level, as is typically deposited, the blocking layer 812 initially covers the top surfaces 809, 811 of the inter-level dielectric layers 808, 810. Cover. In this embodiment of the present invention, the barrier layer 812 material is removed from the top surfaces 809 and 811, so it does not appear on these surfaces in the finished structure shown in FIG. 7A. The removal of the barrier layer 812 material from the top surfaces 809 and 811 may preferably be performed by GCIB processing or conventional methods described herein. The top surface of the first copper wiring layer 802 and the top surface of the second copper wiring layer 804 are capped by a GCIB process to form the injected capping films 813 and 815. The implanted copper capping films 813, 815 and the adjacent inter-level dielectric layers 808, 810 may optionally be capped with dielectric barrier films 814, 816, respectively, to provide improved copper diffusion blocking and via etch-stop properties. . The dielectric barrier films 814 and 816 are preferably silicon nitride, but may also be silicon nitride or silicon carbide or other suitable dielectrics, which can typically be deposited using PECVD, but are preferably applied by GCIB deposition.

7B shows a preliminary step 800B in the process of constructing the wiring design 800. In the step shown, the interconnect level is formed on the substrate 801. The interconnect level consists of a first inter-level dielectric 808 deposited on a substrate. Trench and vias are formed in first inter-level dielectric 808 and lined with blocking layer 812. Copper is deposited in the trenches and vias. The blocking layer 812 initially covers the top surface 809 of the inter-level dielectric layer 808. Excess copper is removed by conventional CMP that stops on the material of barrier layer 812. Additionally, by using conventional CMP process conditions selected to preferentially remove copper at significantly higher rates than the barrier layer material, for example by using a highly selective slurry that selectively removes copper relative to the barrier material, As shown in the figure, copper is slightly below the upper surface of the blocking layer 812. The surface is cleaned using conventional processes. Upper surfaces of the first copper interconnection layer 802 and the blocking layer 812 are illustrated as having residual contaminants 803. On the top (s) of this step and the corresponding step of each subsequent interconnect level (assuming one or more interconnect levels), preferably in situ, such as, for example, a plasma cleaning process or a GCIB cleaning process, Conventional dry cleaning processes may be performed. GCIB cleaning uses a beam acceleration potential (V _Acc ) of the surface (s) to be cleaned, preferably in the range of about 3 kV to about 50 kV, and a total gas in the range of about 5 × 10 ¹³ to about 5 × 10 ¹⁶ ions / cm 2. Irradiating with GCIB cluster ions consisting of molecules of Ar, N ₂ , NH ₃ or H ₂ gas or mixtures thereof in a cluster ion dosage. Those skilled in the art recognize that the present invention is not limited to these exemplary gases, but may be practiced with other gases or gas mixtures that remove post-CMP residues, copper oxides and other contaminants from the copper surface. something to do. Although not essential to the present invention, it is preferred that this GCIB cleaning process is an in-situ cleaning process.

7C shows step 800C in the process of constructing the wiring design 800 after the GCIB cleaning step. The contaminants are cleaned on the upper surfaces of the first copper wiring layer 802 and the blocking layer 812 and prepared for the capping step. You can now apply the GCIB capping process. The GCIB injection capping process is used to simultaneously cap the surfaces of the first copper interconnect layer 802 and the blocking layer 812, which overlays the top surface 809. GCIB etching and capping processes include irradiating the top surface of the first copper interconnect layer 802 and the exposed blocking layer 812 with GCIB, which is an element that forms a capping material upon injection into the copper surface. GCIB irradiation injects the capping species into the first copper wiring layer 802 to form a capping film 813 (FIG. 7D). GCIB irradiation simultaneously injects the implanted layer into exposed bare layer material 812. In this aspect, the implant conditions are selected such that when the capping implant step is complete, the implant depth of the exposed barrier layer is less than the thickness of the exposed barrier layer 812 overlaying the top surface 809. Thus, implantation of the capping species into the exposed blocking layer 812 does not penetrate into the inter-level dielectric 808. Since the blocking layer 812 shields the inter-level dielectric 808 from copper camping implantation, the range of implant capping species available includes capping species that degrade the characteristics of the inter-level dielectric 808 when implanted. To enlarge. Injection depth depends on the beam acceleration potential that accelerates the GCIB. Preferably a beam acceleration potential (V _Acc ) in the range of about 3 kV to about 50 kV is used, and the actual value is selected so that the implanted layer formed in the exposed blocking layer does not penetrate into the inter-level dielectric 808. GCIB dosages ranging from about 1 × 10 ¹⁴ to about 1 × 10 ¹⁷ ions / cm 2 are used for copper capping implantation. Any source gas suitable for forming a copper capping film (many of which are listed above for another aspect of the present invention) can be used, but since the inter-level dielectric is shielded from the injected species, the gas or gas mixture may be Can be selected regardless of whether they produce a conductor layer in an inter-level dielectric material or otherwise create a disadvantageous film. Some exemplary source gases are WF ₆ , other metal fluoride gases, carbon-containing gases, and organometallic gases.

7D shows step 800D in the process of constructing the wiring design 800 after the GCIB capping step. The top surface of the first copper wiring layer 802 is capped with a capping layer 813, and the blocking layer 812 has an implanted layer 818 produced from the capping implantation step. The enlarged insert 820 shows the capping layer 813 and the injected layer 818 in the exposed blocking layer 812 in more detail. The structure is prepared to remove the barrier layer 812 and the implanted layer 818 overlying the top surface 809 of the inter-level dielectric layer 808. A blocking layer 812 is now performed to perform an etching process (preferably using a GCIB process as described below) to overlay the top surface 809 of the inter-level dielectric layer 808 without removing the implanted copper capping layer. ) And the implanted layer 818 may be removed (a partial or copper capping layer may be removed if an effective capping layer remains).

7E shows step 800E in the process of constructing the wiring design 800 after the GCIB etching step. The top surface of the first copper wiring layer 802 is capped by a capping layer 813, and the blocking layer 812 is etched to expose the top surface 809 of the first inter-level dielectric layer 808. The structure is prepared to form a dielectric barrier film. Now, on the capping layer 813 and on the top surface 809 of the first inter-level dielectric layer 808, using a deposition process (preferably GCIB) as described above for the deposition of the barrier film 622. The diffusion barrier 814 (FIG. 7F) can be formed arbitrarily.

7F shows step 800E in the process of constructing the wiring design 800 after any formation of the dielectric diffusion barrier 814.

FIG. 7G shows step 800G in the process of configuring the wiring design 800 of the second interconnect level on the GCIB capped first interconnect level (including the dielectric barrier). In this step, a second interconnect level is formed on the blocking film 814. The second interconnect level consists of a second inter-level dielectric 810 deposited on the blocking film 814. Trenchs and vias are formed in the second inter-level dielectric 810 and lined with a blocking layer 812. Copper is deposited in trenches and vias using conventional techniques. The blocking layer 812 initially covers the top surface of the inter-level dielectric layer 810. Excess copper is removed by conventional CMP that stops on the material of barrier layer 812. In addition, by using conventional CMP process conditions selected to preferentially remove copper at significantly higher rates than the barrier layer material, for example, by using a highly selective slurry that selectively removes copper over the barrier material, As shown in the figure, copper is slightly below the upper surface of the blocking layer 812. The surface is cleaned using conventional processes. The top surfaces of the second copper interconnect layer 804 and the blocking layer 812 are shown as having residual contaminants 817. At the second interconnect level (if any) and at the subsequent higher interconnect level (if any), apply GCIB cleaning, GCIB injection capping, GCIB etching, and GCIB deposition steps as described above for the first interconnect level in wiring design 800. Thus, the capping film 815 and the optional blocking film 816 can be formed (for example). Thus, in some cases, the two interconnect level structures or the multi-level interconnect structure of FIG. 7A may be configured.

At each interconnect level, a preferred etch step involves GCIB cluster ions formed from source gas (s) containing elemental fluorine including but not limited to SF ₆ , CF ₄ , C ₄ F ₈ or NF ₃ to be cleaned. To investigate. These gases can be used to form gas-cluster ions for etching by using pure gas or mixing with N ₂ , or by mixing with an inert gas such as, for example, Ar or Xe. Preferably, a beam acceleration potential (V _Acc ) in the range of about 10 kV to about 50 kV, and a nozzle gas flowing in the range of about 200 sccm to about 3000 sccm may be used. For example, a preferred process for etching the barrier layer material with little or no etching of copper uses a source gas mixture of 10% NF ₃ in N ₂ at a flow rate of 800 sccm. In a fourth aspect of the invention, it is preferred that the effect of the GCIB etching step does not penetrate through the capping layer previously formed on the copper surface by the GCIB copper capping implantation step. Therefore, it is also desirable to select a lower beam acceleration potential (V _Acc ) used to accelerate the barrier material etch GCIB than that used to accelerate the copper capping implanted GCIB.

Each of the four aspects of the present invention described above includes steps requiring the use of GCIB processing or steps in which the use of GCIB processing is optional. The GCIB processing steps of embodiments of the present invention may optionally be performed in some cases in combination with conventional (non-GCIB) processing steps to realize the present invention by successive application of each required step. Of course, the GCIB processing system as shown in FIG. 3 in combination with other standard stand-alone devices (including but not limited to PECVD equipment for deposition and plasma processing equipment for cleaning) to provide other process steps. It is practical to practice the present invention using (preferably in some situations). However, depending on the volume of manufacture required, other processing equipment may be desirable. For several reasons, it may be desirable to operate multiple successive steps simultaneously with one device. One reason for this is throughput-the semiconductor wafer to be processed moves through the manufacturing process several times faster than the wafer must be transferred from the device to the device. Another advantage of performing multiple steps with one device is higher quality processing resulting in better integrated circuit performance. For example, when copper wiring is oxidized, the resistance of the wiring increases and the reliability of the wiring decreases. Thus, cleaning, capping and forming all of the dielectric diffusion barrier is preferably performed in place in a single vacuum system without exposing the wafer to the atmosphere between steps. In addition, by performing multiple steps in one instrument, contamination can be avoided without exposing to the atmosphere between the steps (operating with reduced pressure or vacuum), thus reducing the need for additional cleaning steps in the process. You can.

A unique advantage of this fourth aspect method results from the order of performing the copper capping step and removing the diffusion barrier from the top surface of the inter-level dielectric. In the prior art processing sequence as described above and in the two first aspects of the present invention, for each interconnection layer, the barrier layer material is interconnected prior to performing the capping process for copper in the interconnection layer. It is removed from the top surface of the level dielectric. In a third aspect of the invention, for each interconnection layer, a barrier layer material is removed from the top surface of the inter-level dielectric while performing a capping process for copper in the interconnection layer. In both prior art processing sequences and in the two first aspects of the present invention, the copper capping process is constrained to the use of a capping process that does not interact with the inter-level dielectric top surface in an undesirable manner, because Without the undesirable additional masking step of shielding the level dielectric top surface, this is exposed to the effect of the copper capping process. In the case of the third aspect of the present invention, the copper capping process is constrained to the use of GCIB capable of etching the barrier layer material simultaneously with forming the copper capping layer, and further, if the barrier layer material is completely etched, the etching / At the end of the capping process there is a possibility of undesirable effects or slight contamination on the top surface of the inter-level dielectric layer resulting from short-term irradiation of the inter-level dielectric layer. In the case of the fourth aspect of the present invention, the masking layer material on the top surface of the inter-level dielectric and the top surface of the inter-level dielectric throughout the copper capping process are completely masked and possible undesirable effects on the inter-level dielectric and Regardless, the GCIB component used for GCIB copper capping is completely free to optimize copper capping performance.

Therefore, in high volume manufacturing using the present invention, it is preferable to use a cluster device as shown in Fig. 8A. 8A shows a diagram of a cluster device 900A. The conveying chamber 902 contains a workpiece conveying device 904, preferably a wafer transfer robot, or the like, for conveying a workpiece from one position to another. A load / unload lock 906 provides a standby-to-vacuum lock for transferring the workpiece into and out of the cluster device. The load / unload fixture 906 has shuttles or valves 908, 910 that can be operable to deliver the workpiece into and out of the cluster device. The load / unload fixture 906 may circulate between vacuum (decompressed atmosphere) and atmospheric pressure to facilitate transfer of the workpiece (not shown) from the atmosphere to the vacuum atmosphere of the cluster device. The workpieces can be delivered through the load / unload fixture 906 individually or in a cassette or pod containing multiple workpieces. Although a single load / unload fixture 906 is shown for both placing the workpiece in the cluster instrument and removing the workpiece from the cluster instrument, those skilled in the art will appreciate that the artisan will have a separate It will be appreciated that load and unload fixtures may also be used.

The cluster device 900A has a number of processing chambers (e.g., but not limited to 912, 916, 920, 924, 928). Each processing chamber communicates with the transport chamber 902 via a shuttle or valve (914, 918, 922, 926, 930, respectively). Each processing chamber can be configured as a tool for processing different (or same) types of workpieces, and the cluster machine can have five (as shown) or more attached processing chambers. Typically, both the delivery chamber 902 and the processing chamber operate under vacuum conditions to facilitate performing multiple processes on the workpiece without exposing the workpiece to the atmosphere between process steps. The functional machining performance of the GCIB machining system shown in FIG. 3 may be configured such that the cluster machine machining chamber can insert the GCIB machining step into the cluster machine. A GCIB processing system suitable for acting as a cluster instrument processing module has been manufactured and is commercially available from Epiion Corporation of Billerica, Massachusetts.

8B shows five processing chambers called Processing Module A, Processing Module B, Processing Module C, Processing Module D, and Processing Module E (corresponding to processing chambers 912, 196, 920, 924, 928, respectively, in FIG. 8A). Shows a cluster device 900B mounted. One or more of these processing modules (process chambers) may be configured as a GCIB processing system. The remainder of these processing modules may be configured as other processing systems such as, but not limited to, plasma cleaning systems, PECVD deposition systems, and the like. The workpiece transport device 904 moves the wafer between the various process chambers 912, 196, 920, 924, 928 and the transport chamber 902 and the load / unload fixture 906. If the cluster device consists of one or more plasma cleaning system modules, the plasma cleaning system module may be adapted to perform cleaning of the workpiece (wafer) using conventional techniques prior to GCIB copper capping operations performed in the same cluster device. . When composed of one or more PECVD deposition system modules, the PECVD deposition system modules can be adapted to deposit dielectric films on pre-capped capped copper using GCIB copper capping operations performed in the same cluster device. The cluster device may be composed of multiple GCIB processing chambers. Such a GCIB processing chamber may comprise a GCIB copper capping process, a GCIB surface cleaning process, and / or a GCIB deposition process (e.g., deposition of a dielectric film including deposition of a dielectric diffusion barrier on copper capped by the GCIB process in the same cluster device). Can be adapted to perform.

The four aspects of the present invention described above include the steps and any steps listed in the various embodiments shown in the table of FIG. For the four aspects of the invention, the table of FIG. 9 shows cluster instrument configurations (including preferred configurations) for efficiently performing several possible exemplary combinations of processing steps and combinations of various steps using conventional processing and GCIB processing. Shows.

Although the cluster device configuration shown in the table of FIG. 9 shows up to four processing modules, there are, in some cases, additional cluster devices capable of supporting more processing modules than required according to the table of FIG. 9. The processing module is used to perform slower processes in duplicate to distribute the workload between the dual modules to optimize throughput and / or to occur naturally before or after the sequence of steps of the various aspects of the present invention, although not part of the present invention. It will be apparent to those skilled in the art that the benefit of adding the additional process steps required as an additional part of the integrated circuit fabrication process can be benefited.

While the invention has been described in terms of various aspects, it should be appreciated that the invention is capable of a wide variety of additional and further aspects within the spirit of the invention. For example, it will be apparent to those skilled in the art that the present invention is not limited to dual damascene integrated designs, but is equally applicable to other copper interconnect designs. In addition, the present invention (for example, Si ₃ N ₄ , SiC, SiCN, BN, CuF ₂ , TiO ₂ , CuCO ₃ , B, Ti, silicon nitride, silicon carbide, silicon nitride, boron nitride, copper fluoride, titanium dioxide Although described in terms of implanted and deposited films or layers comprising various compounds (such as copper carbonate, boron, titanium and borosilicate glass), those skilled in the art will appreciate that many films and layers formed in the practice of the present invention It does not have a precise stoichiometry that is converted and also implied by a chemical formula or chemical name, even in its simplest form, but rather approximates to a stoichiometric value and, as is common in such membranes used in similar applications, hydrogen and / or other It will be appreciated that additional impurities may be included.

Claims (55)

A method of forming a capping structure on a structure comprising at least one copper interconnect surface and at least one surface of a barrier layer material covering the dielectric material, the method comprising: Placing the structure in a reduced pressure chamber, Forming an accelerated capping GCIB in the reduced pressure chamber; and Directing the accelerated capping GCIB to at least one of the at least one copper interconnect surface and at least one of the at least one surface of the barrier layer material covering the dielectric material, thereby forming at least one capping structure on the at least one copper interconnect surface to which the accelerated capping GCIB is directed. Method comprising the steps of: The method of claim 1, wherein the barrier layer material has a first thickness, and wherein the directing step further injects the injection layer into at least one of the one or more surfaces of the barrier layer material covering the dielectric material, wherein the injected layer is of the first thickness. Rather than having a second thickness. The method of claim 2, further comprising etching the implanted layer and the barrier layer material covering the dielectric material. The method of claim 3, wherein the etching further comprises forming an accelerated etch GCIB in the reduced pressure chamber and directing the accelerated etch GCIB to one or more surfaces of the barrier layer material covering the dielectric material. The method of claim 1, prior to the capping GCIB formation and directing step, Forming an accelerated cleaning GCIB in a reduced pressure chamber, and Directing the accelerated cleaning GCIB to at least one of the at least one copper interconnect surface and at least one of the at least one surface of the barrier layer material covering the dielectric material, thereby cleaning the at least one surface to which the accelerated clean GCIB is directed. Way. The method of claim 5, wherein forming the accelerated clean GCIB further comprises generating gas-cluster ions from molecules of one or more gases selected from the group consisting of Ar, N ₂ , NH _3, and H ₂ . . The method of claim 5, wherein forming an accelerated clean GCIB further comprises accelerating the clean GCIB gas cluster ions to an acceleration potential of about 3 to about 50 kV. The method of claim 5, wherein directing the accelerated clean GCIB delivers a dosage in the range of about 5 × 10 ¹³ to about 5 × 10 ¹⁶ gas-cluster ions / cm 2 to one or more of the one or more copper interconnect surfaces. The method of claim 1 wherein the dielectric material comprises a portion of an inter-level dielectric layer. The method of claim 1, wherein the step of forming the accelerated capping GCIB comprises Ar, Xe, CH ₄ , SiH ₄ , NH ₃ , N ₂ , CO ₂ , GeH ₄ , B ₂ H ₂ , B ₂ H ₆ , TiCl ₄ and And generating gas cluster ions comprising one or more molecules of the group consisting of TDEAT. The method of claim 1, wherein forming an accelerated capping GCIB further comprises accelerating the generated gas cluster ions to an acceleration potential of about 3 to about 50 kV. The method of claim 1, wherein directing the accelerated capping GCIB comprises applying a dosage in the range of about 1 × 10 ¹⁴ to about 1 × 10 ¹⁷ gas-cluster ions / cm 2 to cover at least one of the one or more copper interconnect surfaces and the dielectric material. Transferring to one or more of the one or more surfaces of the barrier layer material. The method of claim 1, further comprising forming at least one insulating layer overlying the formed at least one capping structure. The method of claim 13, wherein forming at least one insulating layer uses PECVD deposition. The method of claim 13, wherein the at least one insulating layer formed is of one material selected from the group consisting of silicon carbide, silicon nitride, and silicon nitride carbon. The method of claim 13, wherein forming at least one insulating layer overlying at least one capping structure Forming an accelerated deposition GCIB in a reduced pressure chamber; and Directing the accelerated deposition GCIB to one or more copper interconnect surfaces to deposit one or more insulating layers. The method of claim 13, wherein the at least one insulating layer overlying the at least one capping structure is a dielectric diffusion barrier. One or more locks for moving one or more wafers into and / or out of the cluster device, One or more carrying chambers, One or more GCIB processing chambers, One or more cleaning chambers and A cluster device for processing one or more wafers in a reduced pressure atmosphere, the apparatus comprising at least one wafer transport device suitable for transferring one or more wafers from the chamber to the chamber. The cluster device of claim 18, wherein the one or more GCIB processing chambers are suitable for performing a copper capping process on at least a portion of the one or more wafers, and further wherein the one or more cleaning chambers are suitable for performing cleaning prior to the copper capping process. 20. The cluster device of claim 19, wherein the at least one cleaning chamber is a plasma cleaning chamber. 20. The cluster device of claim 19, wherein the one or more GCIB processing chambers are suitable for forming a dielectric diffusion barrier in at least a portion of the one or more wafers. One or more fixtures for moving one or more wafers into and / or out of the cluster device, One or more carrying chambers, One or more GCIB processing chambers, One or more deposition chambers and A cluster device for processing one or more wafers in a reduced pressure atmosphere, the apparatus comprising at least one wafer transport device suitable for transferring one or more wafers from the chamber to the chamber. The method of claim 22, wherein the one or more GCIB processing chambers are suitable for performing a copper capping process on at least a portion of the one or more wafers, and further wherein the one or more deposition chambers are dielectric diffused over the capped copper over at least a portion of the one or more wafers. Cluster device suitable for forming the barrier. The cluster device of claim 22, wherein the at least one deposition chamber is a PECVD deposition chamber. The cluster device of claim 22, wherein the one or more GCIB processing chambers are suitable for performing cleaning prior to the copper capping process. One or more fixtures for moving one or more wafers into and / or out of the cluster device, One or more carrying chambers, One or more GCIB processing chambers, One or more deposition chambers, One or more cleaning chambers and A cluster device for processing one or more wafers in a reduced pressure atmosphere, the apparatus comprising at least one wafer transport device suitable for transferring one or more wafers from the chamber to the chamber. 27. The cluster apparatus of claim 26, wherein the one or more GCIB processing chambers are suitable for performing a copper capping process on at least a portion of the one or more wafers, and further wherein the one or more cleaning chambers are suitable for performing cleaning prior to the copper capping process. 27. The cluster apparatus of claim 26, wherein the one or more GCIB processing chambers are suitable for performing a copper capping process on at least a portion of the one or more wafers, and further wherein the one or more deposition chambers are suitable for forming a dielectric diffusion barrier over the capped copper. . 27. The cluster device of claim 26, wherein the at least one deposition chamber is a PECVD deposition chamber. 27. The cluster device of claim 26, wherein the at least one cleaning chamber is a plasma cleaning chamber. 27. The cluster device of claim 26, wherein the one or more GCIB processed chambers are suitable for forming a dielectric diffusion barrier. 27. The cluster device of claim 26, wherein the one or more GCIB processing chambers are suitable for cleaning at least a portion of the one or more wafers prior to the copper capping process. One or more fixtures for moving one or more wafers into and / or out of the cluster device, Many GCIB processing chambers and A cluster device for processing one or more wafers in a reduced pressure atmosphere, the apparatus comprising at least one wafer transport device suitable for transferring one or more wafers from the chamber to the chamber. 34. The cluster of claim 33, wherein the one or more GCIB processing chambers are suitable for performing a copper capping process on at least a portion of the one or more wafers, and further wherein the one or more GCIB processing chambers are suitable for forming a dielectric diffusion barrier over the capped copper. device. 34. The cluster of claim 33, wherein the one or more GCIB processing chambers are suitable for performing a copper capping process on at least a portion of the one or more wafers, and further wherein the one or more GCIB processing chambers are suitable for performing a cleaning process prior to the copper capping process. device. The method of claim 33, wherein the one or more GCIB processing chambers are suitable for performing a copper capping process on at least a portion of the one or more wafers, and further wherein the one or more GCIB processing chambers are suitable for performing cleaning prior to the copper capping process, Additionally, cluster devices in which at least one GCIB processed chamber is suitable for forming a dielectric diffusion barrier over the capped copper. A method of forming a capping structure over a structure comprising at least one copper interconnect surface and at least one dielectric surface, the method comprising: Placing the structure in a reduced pressure chamber, Forming an accelerated capping GCIB in the reduced pressure chamber; and Directing the accelerated capping GCIB to at least one of the at least one copper interconnect surface and the at least one dielectric surface to form at least one capping structure at at least one surface to which the accelerated capping GCIB is directed. 38. The method of claim 37, wherein forming the accelerated capping GCIB further comprises generating gas-cluster ions from the element forming the electrically insulating material when injected into the copper surface and forming the electrically insulating material when injected into the dielectric surface. Wherein the at least one capping structure formed is an electrically insulating capping structure. 38. The method of claim 37, wherein forming an accelerated capping GCIB further comprises generating gas-cluster ions from an element that forms an electrically conductive material when injected into the copper surface and forms an electrically insulating material when injected into the dielectric surface. Wherein the at least one capping structure formed comprises at least one of an electrically conductive capping structure over the irradiated area of the copper interconnect portion and an electrically insulating capping structure over the irradiated area of the dielectric portion. 38. The method of claim 37, wherein forming the accelerated capping GCIB further comprises generating gas cluster ions from the rare gas or the mixture of rare gases, wherein the formed one or more capping structures are at least electrically conductive capping over the irradiated area of the copper interconnect portion. How to include a structure. 38. The method of claim 37, wherein forming an accelerated capping GCIB further comprises generating gas cluster ions from Ar or Xe or a mixture of Ar and Xe, wherein the formed one or more capping structures are formed over the irradiated region of the copper interconnect portion. At least an electrically conductive capping structure. A method of forming a copper capping structure over an integrated circuit interconnection layer comprising at least one copper interconnect surface and at least one dielectric layer region coated with a barrier layer material. Forming at least one capping structure on at least one copper interconnect surface, and Forming one or more capping structures on the one or more copper interconnect surfaces, and then removing the barrier layer material covering one or more of the one or more dielectric layer regions. 43. The method of claim 42, wherein forming further comprises forming an accelerated capping GCIB and directing the accelerated capping GCIB to one or more of the one or more copper interconnect surfaces. 43. The method of claim 42, wherein removing comprises forming an accelerated etch GCIB and directing the accelerated etch GCIB to the barrier layer material. A method of forming a copper capping structure over an integrated circuit interconnection layer comprising at least one copper interconnect surface and at least one dielectric layer region coated with a barrier layer material. Forming an acceleration capping GCIB using the first beam acceleration potential, Directing the accelerated capping GCIB to one or more of the one or more copper interconnect surfaces to form one or more capping structures on the one or more copper interconnect surfaces, Forming an accelerated etching GCIB using a second beam acceleration potential that is lower than the first beam acceleration potential, and Directing the accelerated etching GCIB to the at least one capping structure and the barrier layer material to remove the barrier layer material. A method of forming a copper capping structure over an integrated circuit interconnection layer comprising at least one copper interconnect surface and at least one dielectric layer region coated with a barrier layer material. Forming an accelerated capping GCIB, Directing the accelerated capping GCIB to one or more of the one or more copper interconnect surfaces to form one or more capping structures on the one or more copper interconnect surfaces, Forming an accelerated etch GCIB, and Directing the accelerated etching GCIB to the one or more capping structures and the barrier layer material to remove the barrier layer material covering one or more of the one or more dielectric layer regions without removing all of the one or more capping structures. 43. An integrated circuit interconnection layer made by the method of claim 42, comprising at least one capped copper interconnect surface and at least one dielectric layer region. An integrated circuit interconnection layer made by the method of claim 45 comprising at least one capped copper interconnect surface and at least one dielectric layer region. A method of processing a semiconductor wafer in a cluster device system while maintaining a reduced pressure atmosphere in the cluster device system, Forming a capping layer on the copper interconnect surface and the barrier layer material surface over the dielectric material on the semiconductor wafer using a GCIB process in the first GCIB processing chamber of the cluster device, Conveying the semiconductor wafer from the first GCIB processing chamber of the cluster device to the second GCIB processing chamber in a reduced pressure atmosphere of the cluster device; and Removing the barrier layer material from the dielectric layer using a GCIB etching process in a second GCIB processing chamber. The method of claim 49, wherein prior to the forming step, Cleaning the copper interconnect surface and the barrier layer material surface in a third processing chamber of the cluster machine using a cleaning process; and And transferring the semiconductor wafer from the third processing chamber of the cluster device to the first GCIB processing chamber of the cluster device in the decompressed atmosphere of the cluster device. 51. The method of claim 50, wherein the third processing chamber of the cluster device is a GCIB processing chamber and the cleaning process comprises a GCIB cleaning process. A method of processing a semiconductor wafer in a cluster device system while maintaining a reduced pressure atmosphere in the cluster device system, Forming a capping layer over the copper interconnect surface and the dielectric material on the semiconductor wafer using a GCIB process in a first GCIB processing chamber of the cluster device, Transferring the semiconductor wafer from the first GCIB processing chamber of the cluster device to the second processing chamber in the decompression atmosphere of the cluster device; and Forming a dielectric diffusion barrier on the capping layer in the second processing chamber of the cluster device using the dielectric film-forming process. The method of claim 52, wherein prior to the forming step, Cleaning the copper interconnect surface and the barrier layer material surface in a third processing chamber of the cluster machine using a cleaning process; and And transferring the semiconductor wafer from the third processing chamber of the cluster device to the first GCIB processing chamber of the cluster device in the decompressed atmosphere of the cluster device. 54. The method of claim 53, wherein the third processing chamber of the cluster device is a GCIB processing chamber and the cleaning process comprises a GCIB cleaning process. 53. The method of claim 52, wherein the second processing chamber of the cluster device is a GCIB processing chamber and the dielectric film-forming process comprises a GCIB implantation process.

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