JP2009272426A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device including a DMOS transistor with small ON resistance. <P>SOLUTION: A sidewall 26 formed on a sidewall of a gate electrode 27 is different in thickness in a horizontal direction (along an upper surface of a semiconductor layer 2) between a drain side and a source side differently from a side wall 8 of a CMOS transistor 1, and a sidewall 26B on the drain side is thicker than a sidewall 26A on the source side. The sidewall 26A on the source side is nearly as thick as the sidewall 8 of the CMOS transistor 1. A drift region 23, an LDD region 25, a drain region 21, and a source region 24 are formed on those sidewalls 26A and 26B in a self-matching manner. Consequently, the LDD region 25 is made smaller in length in the horizontal direction by the difference in thickness between the sidewalls 26A and 26B than the drift region 23. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a structure of a DMOS transistor and a manufacturing method thereof.

  In recent years, a switching power supply circuit using a synchronous rectification method has been widely used as a power supply used for a CPU such as a computer is lowered in voltage. In this power supply circuit, a DMOS transistor having a withstand voltage of several V to several tens V according to the input voltage is used. A high-speed and low-resistance element is suitable as a DMOS transistor for a power supply circuit.

  In such a DMOS transistor, an offset layer (electric field relaxation portion) is provided in the drain region in order to increase the breakdown voltage (see, for example, Patent Document 1). The offset layer is laid out so as to surround the drain contact region (low resistance region).

Since the length of this offset is normally determined by mask alignment, it is necessary to set a margin in consideration of mask displacement, and there is a problem that the on-resistance increases accordingly.
JP 2004-349377 A

  The present invention provides a semiconductor device including a DMOS transistor having a low on-resistance and capable of determining an offset layer in a self-aligned manner, and a manufacturing method thereof.

  In a semiconductor device according to one aspect of the present invention, a CMOS transistor and a DMOS transistor are formed in the same first conductivity type semiconductor layer, and the CMOS transistor includes a first insulating film on the semiconductor layer. The first gate electrode formed through the first gate electrode, the first source region of the second conductivity type provided adjacent to the first gate electrode on the surface of the semiconductor layer, and the surface of the semiconductor layer, A first drain region of a second conductivity type provided so as to sandwich the first gate electrode together with the first source region, and the DMOS transistor is formed on the semiconductor layer via a second insulating film The second gate electrode, a second source region of a second conductivity type provided adjacent to the second gate electrode on the surface of the semiconductor layer, and the second source region on the surface of the semiconductor layer Above A drift region of a second conductivity type provided so as to sandwich the two gate electrodes; and provided on the surface of the semiconductor layer so as to be adjacent to the drift region and sandwich the second gate electrode together with the second source region. A second drain region of the second conductivity type, a first sidewall is provided on a side surface of the first gate electrode, a second sidewall is provided on a side surface of the second gate electrode, The first sidewall and the second sidewall are formed by laminating a plurality of types of insulating layers, and the second sidewall on the second drain region side is more than the second sidewall on the second source region side. The thickness in the direction along the second gate insulating film is large.

  A method for manufacturing a semiconductor device according to an aspect of the present invention is a method for manufacturing a semiconductor device in which a CMOS transistor and a DMOS transistor are formed in the same first conductivity type semiconductor layer, the semiconductor device being formed on the semiconductor layer. Forming a first gate electrode for the CMOS transistor and a second gate electrode for the DMOS transistor via an insulating film on the semiconductor layer including the first and second gate electrodes; A step of laminating a plurality of types of insulating layers; a step of covering the drain region side of the DMOS transistor of the second gate electrode with a mask, and then etching a part of the insulating layer using the mask; Then, anisotropic etching is performed on the plurality of types of insulating layers to leave the insulating layers on the side walls of the first gate electrode and the second gate electrode. Characterized by comprising a step of forming a Lumpur.

    A method for manufacturing a semiconductor device according to an aspect of the present invention is a method for manufacturing a semiconductor device including a DMOS transistor, wherein a plurality of gate electrodes are formed on the semiconductor layer with an insulating film interposed therebetween, and the plurality of gates are formed. Forming a dummy electrode at a first gap between the gate electrode and a position sandwiched between the electrodes; and implanting ions into the semiconductor layer using the gate electrode and the dummy electrode as a mask to form the DMOS A step of forming a drift region of the transistor, and an insulating film on the semiconductor layer including the gate electrode and the dummy electrode, the insulating film being smaller than the first interval and less than ½ of the first interval. Depositing a large second thickness; performing anisotropic etching on the insulating film to form a sidewall on the sidewall of the gate electrode; After removal of Me electrodes, characterized by comprising a step of forming a drain region, and a source region of the DMOS transistor by ion implantation into the semiconductor layer.

  According to the present invention, the offset layer can be determined in a self-aligning manner, and a semiconductor device including a DMOS transistor having a low on-resistance and a manufacturing method thereof can be provided.

  Hereinafter, embodiments of a semiconductor device according to the present invention will be described in detail with reference to the drawings.

[First Embodiment]
FIG. 1 is a schematic cross-sectional view of a semiconductor device according to the present embodiment, in which a CMOS transistor and a low breakdown voltage DMOS transistor are mixedly mounted on the same substrate.

  FIG. 1A shows a structural cross-sectional view of the CMOS transistor portion, and FIG. 1B shows a structural cross-sectional view of the DMOS transistor portion. In this embodiment, the case of an N-type MOS transistor will be described as an example. That is, in the present embodiment, the first conductivity type is described as P type, and the second conductivity type is described as N type. However, it is not limited to this and may be reversed. Hereinafter, unless otherwise specified, the DMOS transistor is described as meaning a low breakdown voltage DMOS transistor having a static breakdown voltage of about 5 to 10 V, for example.

  First, the structure of the CMOS transistor will be described with reference to FIG. The CMOS transistor 1 is formed in the P − type high resistance semiconductor layer 2 (first area). The P − type semiconductor layer 2 may be a P − type substrate or a P type well region formed on a silicon substrate.

  The CMOS transistor 1 has a gate electrode 9 selectively formed on the P − type semiconductor layer 2 via an insulating film 5. A channel region 7 which is a P-type semiconductor region is formed in the P − -type semiconductor layer below the gate electrode 9. The channel region 7 forms an inversion layer when a drive voltage equal to or higher than the threshold voltage is applied to the gate electrode 9. N-type LDD regions 6 and 6 ′ that are N-type semiconductor regions are formed on both sides of the channel region 7. An LDD (Lightly Doped Drain) region is formed by impurity doping at a lower concentration than a source region 3 and a drain region 4 described later. A source region 3, which is an N + type semiconductor region doped with impurity ions at a higher concentration than the LDD region 6, is formed on the side farther from the gate electrode 9 in the lateral direction of the LDD region 6. At a position sandwiching the gate electrode 9 together with the source region 3, a drain region 4 which is an N + type semiconductor region doped with impurities at a higher concentration than the LDD regions 6 and 6 'is formed.

  The insulating film 5 is formed of, for example, a silicon oxide film. A portion of the insulating film 5 formed below the gate electrode 9 forms a gate oxide film 12 of the MOS transistor. The gate oxide film 12 is formed to a desired thickness according to the gate drive voltage. A gate electrode 9 is formed on the gate oxide film 12. The gate electrode 9 is made of, for example, selectively formed conductive polysilicon. Sidewalls 8 are formed on the side walls of the gate electrode 9. As will be described in detail below, the sidewall 8 is formed by sequentially depositing, for example, a silicon oxide film and a silicon nitride film. The sidewalls have the same thickness on the drain side and the source side. A contact hole is selectively opened in the insulating film 5, and a source electrode 10 and a drain electrode 11 are formed in the opening.

  In the case of the CMOS transistor 1, for example, in the case of a 5V-type CMOS transistor, the device breakdown voltage and the gate drive voltage are both 5V, and therefore when the reverse bias of about 5V is applied between the gate and the drain, the gate oxide film 12 has 5V The above voltage is not applied. In the CMOS transistor 1, the impurity concentration and lateral dimensions of the LDD regions 6 and 6 ′ are symmetrical with respect to the channel region 7, and the lateral dimensions of the source region 3 and the drain region 4 also sandwich the channel region 7. Is symmetrical.

  Next, the structure of the DMOS transistor will be described with reference to FIG. The DMOS transistor 20 is formed in another region (second area) in the same P − type semiconductor layer 2 as the above-described CMOS transistor 1 is formed. Here, the P − type semiconductor layer 2 may be a P − type substrate or a P type well region formed on a silicon substrate.

  The DMOS transistor 20 has a gate electrode 27 selectively formed on the P − type semiconductor layer 2 via an insulating film 30. A channel region 7 ′ that is a P-type semiconductor region is formed in the P − -type semiconductor layer below the gate electrode 27. The channel region 7 ′ forms an inversion layer when a drive voltage equal to or higher than the threshold voltage is applied to the gate electrode 27. On the left side (source side) of the channel region 7 ′, an LDD region 25 which is an N-type diffusion region doped with impurities at a lower concentration than the source region 24 described later is formed. A drift region 23 is formed on the right side (drain side) of the channel region 7 ′, that is, at a position sandwiching the gate electrode 27 together with the LDD region 25. The drift region 23 is often doped with impurities at a lower concentration than the LDD region 25. Therefore, the impurity doping concentration of the LDD region 25 and the impurity doping concentration of the drift region 23 are formed so as to be asymmetric with respect to the channel region 7.

  On the side farther from the gate electrode 27 in the lateral direction of the LDD region 25, a source region 24 which is a high concentration N + type diffusion region doped with impurities at a higher concentration than the LDD region 25 is formed. A contact region 22, which is a high concentration P + diffusion region doped with an impurity at a higher concentration than the semiconductor layer 2, is formed on the side far from the gate electrode 27 in the lateral direction of the source region 24. On the side far from the gate electrode 27 in the lateral direction of the drift region 23, a drain region 21, which is a high concentration N + diffusion region doped with an impurity at a higher concentration than the drift region 23, is formed.

  The insulating film 30 is formed by, for example, a silicon oxide film. A portion of the insulating film 30 formed below the gate electrode 27 constitutes the gate oxide film 12 of the MOS transistor. A gate oxide film 31 is formed on the surface of the P − type semiconductor layer 2. The gate oxide film 31 can be formed to a desired thickness according to the gate drive voltage. In the case of the low breakdown voltage DMOS transistor 20, normally, the gate drive voltage is designed lower than that of the same breakdown voltage type CMOS transistor, and the gate oxide film 31 is designed thinner. A gate electrode 27 is formed on the gate oxide film 31. The gate electrode 27 is made of, for example, selectively formed conductive polysilicon.

  Sidewalls 26 are formed on the side walls of the gate electrode 27. As will be described in detail below, the sidewall 26 is formed by sequentially depositing, for example, a silicon oxide film, a silicon nitride film, and a silicon oxide film. Unlike the sidewall 8 of the CMOS transistor 1, the sidewall 26 differs in thickness in the horizontal direction (direction along the surface of the semiconductor layer 2) on the drain side and the source side. The wall 26B is thicker than the side wall 26A on the source side. The source side wall 26 </ b> A has substantially the same thickness as the side wall 8 of the CMOS transistor 1. The drift region 23, the LDD region 25, the drain region 21, and the source region 24 are formed on these sidewalls 26A and 26B in a self-aligned manner. For this reason, the LDD region 25 has a smaller horizontal length than the drift region 23 by the difference in thickness between the sidewalls 26A and 26B. A contact hole is selectively opened in the insulating film 30, and a source electrode 28 and a drain electrode 29 are selectively formed in the opening. A source electrode 28 is commonly connected to the source region 24 and the contact region 22.

  As will be described in detail below, in the present embodiment, the source region 3 and the drain region 4, and the source region 24 and the drain region 21 are formed by using the respective side walls 8 and 26 (26A and 26B) as masks. The LDD regions 6 and 6 ′ of the CMOS transistor 1 and the LDD regions 25 and the drift region 23 of the DMOS transistor 20 can be formed at a desired distance without being affected by the mask misalignment. In this way, two types of devices with different withstand voltage systems can be mixedly mounted on the same substrate while maintaining a degree of freedom in design. Further, in the side wall 26, the source side wall 26A and the drain side side wall 26B have different thicknesses, and the on-resistance of the DMOS transistor is compared with the case where both have the same thickness. Can be reduced. Further, the element area of the DMOS transistor 20 can be reduced. As an example, the thickness (horizontal direction) of the sidewall 26A is about 100 nm, and the thickness of the sidewall 26B is about twice that of the sidewall 12.

  Next, a first manufacturing method of a semiconductor device according to the present embodiment, in which the CMOS transistor 1 and the DMOS transistor 20 are formed on the same substrate, will be described. 2A to 2I show a part of this manufacturing method. For convenience of explanation, the annealing process is omitted.

  First, as shown in FIG. 2A, a predetermined impurity ion implantation process is performed on the P − type semiconductor layer 2 to form channel regions 7 and 7 ′. Next, insulating films (for example, silicon oxide films) 5 and 30 to be gate oxide films are formed. At this time, the thickness of the insulating films 5 and 30 may be the same or different between the CMOS transistor region and the DMOS transistor region depending on the gate drive voltage. For example, polysilicon is selectively formed on the insulating films 5 and 30 by photolithography and an etching process, and these become the gate electrodes 9 and 27.

Next, as shown in FIG. 2B, desired ion implantation is performed in a self-aligned manner in order to form an impurity diffusion region having a concentration lower than that of the source region 3 in the gate electrode 9 of the CMOS transistor 1. Specifically, for example, phosphorus (P) or the like is ion-implanted into the substrate at an implantation energy of 50 to 70 keV and an implantation amount of about 10 ¹⁴ cm ⁻² , for example. Thus, the LDD regions 6 and 6 ′ of the CMOS transistor 1 are formed.

At the same time, desired ion implantation is performed in a self-aligned manner on the gate electrode 27 of the DMOS transistor 20 in order to form an impurity diffusion region having a lower concentration than the source region 24 only on the source side. Specifically, for example, phosphorus (P) or the like is implanted into the substrate with an implantation energy of 50 to 70 keV, for example, using a photoresist having an opening in the left side (source side) of the gate electrode 27 and the CMOS transistor region as a mask. Ion implantation is performed in an amount of about 10 ¹⁴ cm ⁻² . In this way, the LDD region 25 of the DMOS transistor 20 and the LDD regions 6 and 6 ′ of the CMOS transistor 1 which are lower concentration impurity diffusion regions than the source region 24 are formed simultaneously.

Next, using a photoresist having an opening on the right side (drain side) of the gate electrode 27 as a mask, for example, phosphorus (P) or the like is implanted into the substrate at an implantation energy of 50 to 70 keV, an implantation amount of 10 ¹³ cm ⁻² , for example. Ion implantation is performed at a degree. In this way, the drift region 23 that becomes an impurity diffusion region having a lower concentration than the LDD region 25 is formed.

  Next, as shown in FIG. 2C, a silicon oxide film 40 having a predetermined thickness, a silicon nitride film 41 having a predetermined thickness, and a silicon oxide film 42 having a predetermined thickness are sequentially deposited on the entire substrate. These insulating films can be deposited by, for example, a thermal CVD method or a plasma CVD method. Here, the thickness of the film can be set to a desired thickness of several nm to several hundred nm.

  Next, as shown in FIG. 2D, a photoresist is applied, and a mask 43 that covers only the drain region of the DMOS transistor region is formed by photolithography.

Subsequently, as shown in FIG. 2E, the insulating film 42 is wet-etched (isotropically etched) using a mask 43 using, for example, dilute hydrofluoric acid (HF) or ammonium fluoride (NH ₄ F). Remove. Here, the silicon nitride film 41 functions as a stopper film for the wet etchant (in this case, hydrofluoric acid). Next, the mask 43 is removed.

  Next, as shown in FIG. 2F, a mask 44 having an opening in the region of the DMOS transistor 20 is formed by using a photolithography technique. Next, using this mask 44, the silicon oxide film 42 in the region of the DMOS transistor 20 is etched back by dry etching (anisotropic etching) such as RIE (Reactive Ion Etching). At this time, the silicon oxide film 42 is left on the side surface of the gate electrode 27 due to the characteristics of anisotropic etching. Next, the mask 44 is removed.

  Subsequently, as shown in FIG. 2G, the silicon nitride film 41 and the silicon oxide film 40 in the region of the CMOS transistor 1 are removed by dry etching (anisotropic etching) such as RIE, and the source of the region in the DMOS transistor 20 is also removed. The region side silicon nitride film 41 and silicon oxide film 40 are removed. Further, in addition to the silicon nitride film 41 and the silicon oxide film 40, the silicon oxide film 42 is also etched on the drain region side of the region of the DMOS transistor 20. By using anisotropic etching, the etching rate in the direction perpendicular to the substrate surface is greatly increased, but the etching rate in the direction parallel to the substrate surface is very slow and the etching hardly proceeds. As a result, the gate electrode 9, The side walls 8 and 26 are formed by leaving the silicon oxide film and the silicon nitride film only on the side surfaces 27. The thickness of the sidewalls 8 and 26 substantially corresponds to the thickness of the silicon oxide film and silicon nitride film that are anisotropically etched. As a result, the sidewalls 8 and 26 have the same thickness on both sides of the CMOS transistor 1 and on the source side of the DMOS transistor 20, but on the drain side of the DMOS transistor 20, the thickness in the horizontal direction is equivalent to the silicon oxide film 42. Becomes bigger.

Next, as shown in FIG. 2H, for both the CMOS transistor 1 and the DMOS transistor 20, the sidewalls 8 and 26 are used as a mask to form an impurity diffusion region having a concentration higher than that of the LDD regions 6 and 6 ′. Therefore, the ion implantation process is performed in a self-aligned manner. By using the sidewalls 26A and 26B having different thicknesses as masks, misalignment due to mask alignment can be prevented, and the drift region 23 having the minimum dimension can be formed. As the n + dopant used for the ion implantation process, for example, arsenic (As) can be used. In that case, the ion implantation is performed under the conditions of, for example, 30 keV to 60 keV and an ion implantation amount of 2.0 × 10 ¹⁵ cm ^{−2 to} 5.0 × 10 ¹⁵ cm ⁻² . Thus, the N + type source region 3 and the N + type drain region 4 of the CMOS transistor 1 and the N + type source region 24 and the N + type drain region 21 of the DMOS transistor 20 are simultaneously formed.

Further, a P + -type contact region 22 is selectively formed by ion implantation processing. As the p + dopant used for the ion implantation process, for example, boron (B) or the like can be used. In that case, ion implantation is performed under the conditions of, for example, 5 keV to 40 keV and an ion implantation amount of 2.0 × 10 ¹⁴ cm ^{−2 to} 5.0 × 10 ¹⁵ cm ⁻² .

  Finally, as shown in FIG. 2I, contact holes are opened in the insulating films 5 and 30, for example, a tungsten (W) film is embedded. Next, aluminum (Al) sputtering or copper (Cu) plating is performed to form a metal layer. Thereafter, the source electrode 10 and the drain electrode 11 of the CMOS transistor 1 and the source electrode 28 and the drain electrode 29 of the DMOS transistor 20 are simultaneously formed by photolithography and etching processes.

  According to this embodiment, a CMOS transistor and a DMOS transistor can be formed on the same substrate, and drift can be achieved by using a sidewall as a mask for forming a source region and a drain region. Deviation due to mask alignment during region formation can be reduced. Further, in the DMOS transistor, sidewalls having different thicknesses can be formed on the source side and the drain side, so that the on-resistance of the DMOS transistor can be reduced and the element area can be reduced. As a result, the chip area of the semiconductor device in which the CMOS transistor and the DMOS transistor are mounted together can be reduced.

  Next, a second method for manufacturing a semiconductor device according to the present embodiment, in which a CMOS transistor and a DMOS transistor are formed on the same substrate, will be described. 2J to 2N show a part of this manufacturing method. This method differs from the above-described method in that the anisotropic etching for forming the sidewall 26B is performed before the isotropic etching for removing a part of the film 42.

  After the steps of FIGS. 2A to 2C are performed, as shown in FIG. 2J, a photoresist is applied, and a mask 43 ′ in which the drain region of the DMOS transistor region is exposed is formed by photolithography.

  Subsequently, as shown in FIG. 2K, the film 42 on the drain region side of the DMOS transistor 20 is removed by dry etching (anisotropic etching) such as RIE using a mask 43 '. As a result, the film 42 is left only on the side surface of the DMOS transistor 20 on the drain region side.

Next, as shown in FIG. 2L, after forming a mask 44 ′ that covers only the drain region side of the DMOS transistor 20, in a region exposed without being covered by the mask 44 ′, as shown in FIG. The silicon oxide film 42 is removed by wet etching using hydrofluoric acid (HF) or ammonium fluoride (NH ₄ F). Here, the silicon nitride film 41 functions as a stopper film for the wet etchant (in this case, hydrofluoric acid). Next, the mask 44 'is removed. Thereafter, as shown in FIG. 2N, by performing dry etching (anisotropic etching) such as RIE, sidewalls 8 and 26 (26A and 26B) similar to the first method (FIG. 2G) are formed. . Thereafter, the same steps as those in FIGS. 2H and 2I are performed to complete the semiconductor device having the structure shown in FIG.

  Next, a third manufacturing method of a semiconductor device according to the present embodiment formed by mixing CMOS transistors and DMOS transistors on the same substrate will be described. 2P to 2S show a part of this manufacturing method. This method differs from the above method in that anisotropic etching for forming the sidewalls 26A and 26B is performed before isotropic etching for removing a part of the film 42. Yes.

  After performing the steps of FIGS. 2A to 2C, as shown in FIG. 2P, a photoresist is applied, and a mask 43 ″ with the DMOS transistor region exposed is formed by photolithography, and this mask 43 ″ is used. Then, the films 40 to 42 on the source region side and the drain region side of the DMOS transistor 20 are removed by dry etching (anisotropic etching) such as RIE. As a result, the films 40 to 42 are left on both side surfaces of the DMOS transistor 20.

Next, as shown in FIG. 2R, after forming a mask 44 ″ that covers only the drain region side of the DMOS transistor 20, in a region exposed without being covered by the mask 44 ″, as shown in FIG. Then, the silicon oxide film 42 is removed by wet etching using dilute hydrofluoric acid (HF) or ammonium fluoride (NH ₄ F). Here, the silicon nitride film 41 functions as a stopper film for the wet etchant (in this case, hydrofluoric acid). Next, the mask 44 'is removed. Thereafter, as shown in FIG. 2S, by performing dry etching (anisotropic etching) such as RIE, sidewalls 8 and 26 (26A and 26B) similar to the first method (FIG. 2G) are formed. . Thereafter, the same steps as those in FIGS. 2H and 2I are performed to complete the semiconductor device having the structure shown in FIG.

  Next, a fourth manufacturing method of a semiconductor device according to the present embodiment formed by mixing CMOS transistors and DMOS transistors on the same substrate will be described. 2T to 2Y show a part of this manufacturing method. In this method, the sidewalls 26A and 26B are formed by depositing another film after forming a sidewall only on the drain region side of the DMOS transistor 20, and anisotropically etching the film. Is different.

  2A to 2B, a silicon oxide film 40 having a predetermined thickness and a silicon nitride film 41 having a predetermined thickness are sequentially deposited on the entire substrate as shown in FIG. 2T. These insulating films can be deposited by, for example, a thermal CVD method or a plasma CVD method. Here, the thickness of the film can be set to a desired thickness of several nm to several hundred nm.

  Further, as shown in FIG. 2U, a silicon oxide film 42 having a predetermined thickness is deposited on the entire substrate. The side wall 26B on the drain side of the DMOS transistor 20 will be formed later than the side wall 8 of the CMOS transistor 1 by the thickness of the silicon oxide film 42.

  Next, as shown in FIG. 2V, a photoresist is applied, and a mask 45 in which the DMOS transistor region is exposed is formed by a photolithography technique. Using this mask 45, the film 42 in the DMOS transistor region is dry etched such as RIE. It is removed by (anisotropic etching). As a result, the films 42A and 42B are left on both side surfaces of the gate electrode 27 of the DMOS transistor 20.

Next, as shown in FIG. 2W, after forming a mask 46 that covers only the drain region side of the DMOS transistor 20, in a region exposed without being covered by the mask 46, for example, dilute hydrofluoric acid (HF) or ammonium fluoride. The silicon oxide film 42 is removed by wet etching using (NH ₄ F). As a result, the film 42B is left only on the drain region side of the gate electrode 27 of the DMOS transistor 20. Here, the silicon nitride film 41 functions as a stopper film for the wet etchant (in this case, hydrofluoric acid).

  Next, the mask 46 is removed. Thereafter, as shown in FIG. 2X, a silicon oxide film 47 having a predetermined thickness is deposited on the entire substrate.

  Thereafter, as shown in FIG. 2Y, dry etching (anisotropic etching) such as RIE is performed. Since the film is thickened only on the drain region side of the gate electrode 27 of the DMOS transistor by the amount of the film 42B, the side wall left on the side surface of the gate electrode as a result of anisotropic etching is thick only on the drain region side of the gate electrode 27. . In this way, sidewalls 8 and 26 (26A and 26B) similar to the first method (FIG. 2G) are formed. Thereafter, the same steps as those in FIGS. 2H and 2I are performed to complete the semiconductor device having the structure shown in FIG.

  In this embodiment, the three types of films 40 to 42 are formed to form the sidewalls 8 and 26, but it goes without saying that the present invention is not limited to this. It is within the scope of the present invention as long as two or more different films are sequentially deposited and at least one of the films is peeled off at a portion where the sidewall thickness is desired to be reduced.

[Second Embodiment]
FIG. 3 schematically shows a cross-sectional view of the structure of a semiconductor device according to the second embodiment. Since the CMOS transistor region is the same as that in the first embodiment, the description thereof is omitted. The DMOS transistor 60 of the semiconductor device according to the present embodiment differs from the DMOS transistor 20 of the first embodiment described above in that it has a P-type body region 61 in the P − -type semiconductor layer 2. The P-type body region 61 is formed so as to surround the source-side contact region 22, the source region 24, and the LDD region 25 and to partially extend below the gate oxide film 31. Therefore, the impurity concentration below the gate oxide film 31 is higher on the source side than on the drain side. The peak of the impurity concentration of the P-type body region 61 is at a deeper position than the surface of the semiconductor layer where the source region 24 is formed.

  The P-type body region 61 is mainly for adjusting the threshold voltage of the DMOS transistor 60. In order to obtain a high source-drain breakdown voltage, the impurity concentration of the drift region 23 of the DMOS transistor 60 is set lower than that of the LDD region 6 of the CMOS transistor 1. If the P-type well region formed in the entire region of the CMOS transistor 1 is also formed in the entire region of the DMOS transistor 60 in order to adjust the threshold value of the CMOS transistor 1 region, the effective impurity concentration in the drift region 23 is lowered. It is not preferable. Therefore, a P-type body region 61 is provided only on the source side of the DMOS transistor 60 instead of the P-well region, and the threshold value is adjusted by this. However, it is not preferable that the P-type body region 61 overlaps with the drift region 23 because the effective impurity concentration in the drift region decreases and the on-resistance increases. Therefore, the P-type body region 61 is formed only on the source side below the gate oxide film 31. In addition, the P-type body region 61 has an effect of suppressing punch-through.

  Next, a method for manufacturing a semiconductor device according to the present embodiment will be described with reference to the drawings. FIG. 6 shows a process of forming the P-type diffusion body region 61 of the power MOS transistor 60 according to the present embodiment.

  First, as described with reference to FIG. 2A of the first embodiment, a predetermined impurity ion implantation process is performed on the P − type semiconductor layer 2 to form channel regions 7 and 7 ′. Thereafter, gate oxide films 5 and 30 are formed, and then gate electrodes 9 and 27 are formed.

Next, as shown in FIG. 4, a resist is applied to the entire surface, and a mask 62 having an opening only in a portion where the P-type body region 61 is to be formed is formed by photolithography. Next, using this mask 62, ion implantation of, for example, boron (B) or BF ₂ is performed obliquely from above, for example, at an incident angle of 30 ° or more. In that case, ion implantation is performed under conditions of, for example, 5 keV to 40 keV and an ion implantation amount of 1.0 × 10 ¹³ cm ^{−2 to} 5.0 × 10 ¹³ cm ⁻² . By oblique ion implantation, ions are implanted to a position immediately below the gate electrode 27, and a P-type body region 61 is formed. Next, the mask 62 is removed.

  As another method for forming the P-type body region 61, as shown in FIG. 5, ion implantation is performed using a mask 63 having an opening only in the P-type body region 61 of the power MOS transistor 60 to form the P-type body region 61. Then, after removing the mask 63, the gate electrodes 9 and 27 may be formed.

  Since the subsequent steps are the same as those in the first embodiment described above, description thereof will be omitted.

[Third Embodiment]
FIG. 6 schematically shows a sectional view of the structure of a semiconductor device according to the third embodiment. Since the CMOS transistor region is the same as that in the first embodiment, the description thereof is omitted. In the DMOS transistor of the semiconductor device according to the present embodiment, the horizontal thickness of the sidewall 26B is made thicker than the sidewall 26A, and the P-type semiconductor layer 2 has a P-type body region 61. This is the same as the DMOS transistor of the second embodiment described above. In this embodiment, as shown in FIG. 6, two DMOS transistors share one drain electrode 29, and two DMOS transistors are arranged symmetrically with respect to the position of the drain electrode 29. When a large current is required, the unit cell can be repeatedly formed using the region shown in FIG. 6 as a unit cell. In such a case, if the length of the drift region 23 in a part of the plurality of unit cells is smaller than the other unit cells, the breakdown voltage of the entire semiconductor device is reduced due to the influence of some of the unit cells. End up. However, according to the manufacturing method described later, the sidewalls 26 of the DMOS transistors in these unit cells are made to have the same thickness for all the unit cells without being affected by the mask misalignment in the lithography process. The length of 23 is equal in all unit cells. Therefore, a desired breakdown voltage can be obtained.

  Further, as will be described later, this embodiment is different in the formation process of the sidewall 26 from the above-described embodiment. Therefore, the sidewall 26B on the drain side has a wedge shape as shown in FIG. 6A. It has a shape with a depressed portion.

  Next, a method for manufacturing the semiconductor device according to this embodiment will be described with reference to FIGS. 7A to 7K.

  First, as shown in FIG. 7A, a p-type well 2 is formed in a predetermined region on the surface of the p-type silicon semiconductor substrate 1. Thereafter, a gate oxide film 31 is formed on the entire surface. Impurity ion implantation for adjusting the threshold value may be performed before the gate oxide film 31 is formed.

  Subsequently, as shown in FIG. 7B, a polysilicon film to be the gate electrode 27 is formed on the gate oxide film 31, and is patterned by lithography and RIE. At this time, the dummy electrode 27D is left not only in the gate electrode 27 but also in a region to be the drain. As described later, the dummy electrode 27D is used only as a mask and is finally removed.

  All the intervals between the adjacent gate electrode 27 and the dummy electrode 27D are set to equal predetermined values. As will be apparent from the description below, the length of the drift region 23 is determined by this interval, so this interval is determined so as to obtain a necessary breakdown voltage. For example, in order to obtain a breakdown voltage of 10 V, the length of the n-type drift region 23 needs to be about 200 nm. The length of the drift region 23 is slightly shorter than the distance between the gate electrode 27 and the dummy electrode 27D. For this reason, the interval between the gate electrode 27 and the dummy electrode 27D is made uniform at about 250 nm. Since the gate electrode 27 and the dummy electrode 27D are subjected to lithography using the same mask, the mutual alignment can be performed accurately.

  Next, as shown in FIG. 7C, a mask 64 that covers part of the dummy electrode 27D and the gate electrode 27 is formed, only the source region is exposed, and the other part is covered with the mask 64. After p-type impurities are ion-implanted using this mask 64, the mask 64 is removed and the p-type impurities are diffused to form the p-type body region 61 in a self-aligning manner.

  Subsequently, as shown in FIG. 7D, n-type impurities for forming the drift region 23 are ion-implanted using the gate electrode 27 and the dummy electrode 27D as a mask. An n − type diffusion layer 25 ′ is also formed in the source region.

  Thereafter, as shown in FIG. 7E, a mask 64 'covering a part of the dummy electrode 27D and the gate electrode 27 is formed, only the source region is exposed, and the other part is covered with the mask 64'. An n-type impurity is ion-implanted using this mask 64 'to form an n-type LDD region 25 in a self-aligning manner. Thereafter, the resist 64 'is removed.

  Subsequently, the insulating film 65 (for example, a silicon nitride film) to be the sidewalls 26A and 26B is formed by a low pressure CVD method at 50% or more and less than 100%, more preferably about 50 to 60% of the distance between the gate electrode 27 and the dummy electrode 27D. Deposit thick. Thereby, the insulating film 65 is deposited so as to have a recess 65h between the gate electrode 27 and the dummy electrode 27D.

  Next, as shown in FIG. 7G, the sidewalls 26A and 26B are formed by etching back the deposited insulating film 65 by anisotropic etching such as RIE. The sidewall 26B is etched to such an extent that the bottom of the recess 65h does not reach the gate oxide film 31, and has a substantially V-letter shape as shown in FIG. 7G.

  Subsequently, as shown in FIG. 7H, a mask 66 is deposited so that only the dummy electrode 27D is exposed and the gate electrode 27 and the source region (including the LDD region 25) are covered. Thereafter, as shown in FIG. 27D, isotropic etching is performed using the mask 66 to remove the dummy electrode 27D. Thereafter, as shown in FIG. 7J, the mask 66 is removed.

  Thereafter, ion implantation of n-type impurities is performed using the sidewalls 26A and 26B, the gate electrode 27, and a photoresist (not shown) as a mask, and a high impurity concentration n + is formed in a self-aligned manner with respect to the sidewalls 26A and 26B. A type source region 24 and an n + type drain region 21 are formed. Further, a p + type contact region 22 is formed.

  The length of the n-type drift region 23 is determined by the thickness of the sidewall 26B. The thickness of the side wall 26B is equal to the interval between the gate electrode 27 and the dummy electrode 27D, and this interval is determined by one lithography as described above, so that it can be formed accurately and uniformly. Therefore, the length of the n-type drift region 23 can be formed exactly equal among a plurality of cells without being affected by the mask misalignment.

  Thereafter, the structure shown in FIG. 6 is obtained through an annealing process for activating each impurity layer and an interlayer insulating film and electrode forming process.

[Fourth Embodiment]
FIG. 8 schematically shows a sectional view of the structure of a semiconductor device according to the fourth embodiment. Since the CMOS transistor region is the same as that in the first embodiment, the description thereof is omitted. The DMOS transistor of the semiconductor device according to the present embodiment has a P-type body region 61 in the P − -type semiconductor layer 2, the two DMOS transistors share one drain electrode 29, and the position of the drain electrode 29 The second embodiment is the same as the third embodiment in that two DMOS transistors are arranged line-symmetrically with respect to. However, the third embodiment is different from the third embodiment in that the drift region is formed in two stages of the first drift region 23A and the second drift region 23B. The former impurity concentration is higher than that of the latter. In this way, the on-breakdown voltage can be increased by configuring the drift region in two stages.

  A method of manufacturing the semiconductor device of this embodiment will be described with reference to FIGS. 9A to 9K.

  First, as shown in FIG. 9A, a p-type well 2 is formed in a predetermined region on the surface of the p-type silicon semiconductor substrate 1. Thereafter, a gate oxide film 31 is formed on the entire surface. Impurity ion implantation for adjusting the threshold value may be performed before the gate oxide film 31 is formed.

  Subsequently, as shown in FIG. 9B, a polysilicon film to be the gate electrode 27 is formed on the gate oxide film 31, and this is patterned by lithography and RIE. At this time, the dummy electrode 27E is left not only in the gate electrode 27 but also in a region to be a drain. As described later, the dummy electrode 27E is used only as a mask and is finally removed.

  All the intervals between the adjacent gate electrode 27 and the dummy electrode 27E are set to equal predetermined values. Since the length of the drift region 23B is determined by this interval, this interval is determined so that the required breakdown voltage can be obtained. Since the gate electrode 27 and the dummy electrode 27E are subjected to lithography using the same mask, the mutual alignment can be performed accurately.

  Next, as shown in FIG. 9C, a mask 68 that covers part of the dummy electrode 27 </ b> E and the gate electrode 27 is formed, only the source region is exposed, and the other part is covered with the mask 68. After ion implantation of p-type impurities using this mask 68, the mask 68 is removed and the p-type impurities are diffused to form a p-type body region 61 in a self-aligned manner.

  Subsequently, as shown in FIG. 9D, n-type impurities for forming the second drift region 23B are ion-implanted using the gate electrode 27 and the dummy electrode 27E as a mask. An n − type diffusion layer 25 ′ is also formed in the source region.

  Thereafter, as shown in FIG. 9E, a mask 69 that covers part of the dummy electrode 27E and the gate electrode 27 is formed, only the source region is exposed, and the other part is covered with the mask 69. An n-type impurity is ion-implanted using this mask 69 to form an n-type LDD region 25 in a self-aligning manner. Thereafter, the resist 69 is removed.

  Subsequently, as shown in FIG. 9F, an insulating film 65 (for example, a silicon nitride film) to be the sidewalls 26A and 26B is deposited by a low pressure CVD method to a thickness of about 50 to 60% of the distance between the gate electrode 27 and the dummy electrode 27E. Let Thereby, the insulating film 65 is deposited so as to have a recess 65h between the gate electrode 27 and the dummy electrode 27E.

  Next, as shown in FIG. 9G, the sidewalls 26A and 26B are formed by etching back the deposited insulating film 65 by anisotropic etching such as RIE. The sidewall 26B is etched to such an extent that the bottom of the recess 65h does not reach the gate oxide film 31, and has a substantially V-letter shape as shown in FIG. 9G.

  Subsequently, as shown in FIG. 9H, a mask 71 is deposited so that only the dummy electrode 27E is exposed and the gate electrode 27 and the source region (including the LDD region 25) are covered. Thereafter, as shown in FIG. 9I, isotropic etching is performed using the mask 71 to remove the dummy electrode 27E. Thereafter, as shown in FIG. 9J, n-type impurity ions are implanted in a self-aligned manner into the sidewall 26B using the mask 71 and the sidewall 26B as a mask to form the first drift region 23A.

  Thereafter, as shown in FIG. 9K, after removing the mask 71, a source region 25, an n + -type drain region 21, and a contact region 22 are formed using a resist or the like (not shown). Also in this embodiment, the length of the drift region 23B can be accurately formed between a plurality of cells without being affected by the mask misalignment. Thereafter, the structure shown in FIG. 8 is obtained through an annealing process for activating each impurity layer and an interlayer insulating film and electrode forming process.

  Although the embodiments of the invention have been described above, the present invention is not limited to these embodiments, and various modifications and additions can be made without departing from the spirit of the invention. For example, in the above embodiment, the source electrode 28 is commonly connected to the source region 24 and the contact region 22, but the source electrode 28 is connected only to the source region 24 as shown in FIG. A back gate electrode 28A connected to the contact region 22 may be provided separately.

1 schematically illustrates a cross-sectional structure of a semiconductor device according to a first embodiment of the present invention. It is a cross-sectional schematic diagram explaining the process of manufacturing the semiconductor device which concerns on the 1st Embodiment of this invention. It is a cross-sectional schematic diagram explaining the process of manufacturing the semiconductor device which concerns on the 1st Embodiment of this invention. It is a cross-sectional schematic diagram explaining the process of manufacturing the semiconductor device which concerns on the 1st Embodiment of this invention. It is a cross-sectional schematic diagram explaining the process of manufacturing the semiconductor device which concerns on the 1st Embodiment of this invention. It is a cross-sectional schematic diagram explaining the process of manufacturing the semiconductor device which concerns on the 1st Embodiment of this invention. It is a cross-sectional schematic diagram explaining the process of manufacturing the semiconductor device which concerns on the 1st Embodiment of this invention. It is a cross-sectional schematic diagram explaining the process of manufacturing the semiconductor device which concerns on the 1st Embodiment of this invention. It is a cross-sectional schematic diagram explaining the process of manufacturing the semiconductor device which concerns on the 1st Embodiment of this invention. It is a cross-sectional schematic diagram explaining the process of manufacturing the semiconductor device which concerns on the 1st Embodiment of this invention. It is a cross-sectional schematic diagram explaining the process of manufacturing the semiconductor device which concerns on the 1st Embodiment of this invention. It is a cross-sectional schematic diagram explaining the process of manufacturing the semiconductor device which concerns on the 1st Embodiment of this invention. It is a cross-sectional schematic diagram explaining the process of manufacturing the semiconductor device which concerns on the 1st Embodiment of this invention. It is a cross-sectional schematic diagram explaining the process of manufacturing the semiconductor device which concerns on the 1st Embodiment of this invention. It is a cross-sectional schematic diagram explaining the process of manufacturing the semiconductor device which concerns on the 1st Embodiment of this invention. It is a cross-sectional schematic diagram explaining the process of manufacturing the semiconductor device which concerns on the 1st Embodiment of this invention. It is a cross-sectional schematic diagram explaining the process of manufacturing the semiconductor device which concerns on the 1st Embodiment of this invention. It is a cross-sectional schematic diagram explaining the process of manufacturing the semiconductor device which concerns on the 1st Embodiment of this invention. It is a cross-sectional schematic diagram explaining the process of manufacturing the semiconductor device which concerns on the 1st Embodiment of this invention. It is a cross-sectional schematic diagram explaining the process of manufacturing the semiconductor device which concerns on the 1st Embodiment of this invention. It is a cross-sectional schematic diagram explaining the process of manufacturing the semiconductor device which concerns on the 1st Embodiment of this invention. It is a cross-sectional schematic diagram explaining the process of manufacturing the semiconductor device which concerns on the 1st Embodiment of this invention. It is a cross-sectional schematic diagram explaining the process of manufacturing the semiconductor device which concerns on the 1st Embodiment of this invention. It is a cross-sectional schematic diagram explaining the process of manufacturing the semiconductor device which concerns on the 1st Embodiment of this invention. FIG. 3 schematically shows a cross-sectional structure of a semiconductor device according to a second embodiment of the present invention. It is a cross-sectional schematic diagram explaining the process of manufacturing the semiconductor device which concerns on the 2nd Embodiment of this invention. It is a cross-sectional schematic diagram explaining the process of manufacturing the semiconductor device which concerns on the 2nd Embodiment of this invention. FIG. 9 schematically shows a cross-sectional structure of a semiconductor device according to a third embodiment of the present invention. It is a cross-sectional schematic diagram explaining the process of manufacturing the semiconductor device which concerns on the 3rd Embodiment of this invention. It is a cross-sectional schematic diagram explaining the process of manufacturing the semiconductor device which concerns on the 3rd Embodiment of this invention. It is a cross-sectional schematic diagram explaining the process of manufacturing the semiconductor device which concerns on the 3rd Embodiment of this invention. It is a cross-sectional schematic diagram explaining the process of manufacturing the semiconductor device which concerns on the 3rd Embodiment of this invention. It is a cross-sectional schematic diagram explaining the process of manufacturing the semiconductor device which concerns on the 3rd Embodiment of this invention. It is a cross-sectional schematic diagram explaining the process of manufacturing the semiconductor device which concerns on the 3rd Embodiment of this invention. It is a cross-sectional schematic diagram explaining the process of manufacturing the semiconductor device which concerns on the 3rd Embodiment of this invention. It is a cross-sectional schematic diagram explaining the process of manufacturing the semiconductor device which concerns on the 3rd Embodiment of this invention. It is a cross-sectional schematic diagram explaining the process of manufacturing the semiconductor device which concerns on the 3rd Embodiment of this invention. It is a cross-sectional schematic diagram explaining the process of manufacturing the semiconductor device which concerns on the 3rd Embodiment of this invention. It is a cross-sectional schematic diagram explaining the process of manufacturing the semiconductor device which concerns on the 3rd Embodiment of this invention. FIG. 10 schematically shows a cross-sectional structure of a semiconductor device according to a fourth embodiment of the present invention. It is a cross-sectional schematic diagram explaining the process of manufacturing the semiconductor device which concerns on the 4th Embodiment of this invention. It is a cross-sectional schematic diagram explaining the process of manufacturing the semiconductor device which concerns on the 4th Embodiment of this invention. It is a cross-sectional schematic diagram explaining the process of manufacturing the semiconductor device which concerns on the 4th Embodiment of this invention. It is a cross-sectional schematic diagram explaining the process of manufacturing the semiconductor device which concerns on the 4th Embodiment of this invention. It is a cross-sectional schematic diagram explaining the process of manufacturing the semiconductor device which concerns on the 4th Embodiment of this invention. It is a cross-sectional schematic diagram explaining the process of manufacturing the semiconductor device which concerns on the 4th Embodiment of this invention. It is a cross-sectional schematic diagram explaining the process of manufacturing the semiconductor device which concerns on the 4th Embodiment of this invention. It is a cross-sectional schematic diagram explaining the process of manufacturing the semiconductor device which concerns on the 4th Embodiment of this invention. It is a cross-sectional schematic diagram explaining the process of manufacturing the semiconductor device which concerns on the 4th Embodiment of this invention. It is a cross-sectional schematic diagram explaining the process of manufacturing the semiconductor device which concerns on the 4th Embodiment of this invention. It is a cross-sectional schematic diagram explaining the process of manufacturing the semiconductor device which concerns on the 4th Embodiment of this invention. It is a cross-sectional schematic diagram explaining the process of manufacturing the semiconductor device which concerns on the 4th Embodiment of this invention. The modification of embodiment of this invention is shown.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... CMOS transistor, 2 ... P-type semiconductor layer, 3 ... Source region, 4 ... Drain region, 5 ... Insulating film, 6, 6 '... LDD region, 7 * ··· Channel region, 9 ... Gate electrode, 10 ... Source electrode, 11 ... Drain electrode, 12 ... Gate oxide film, 20 ... DMOS transistor, 21 ... Drain region, 22 .. Contact region, 23... Drift region, 24... Source region, 25... LDD region, 26 .. Side wall, 27 ... Gate electrode, 28. -Drain electrode, 30 ... insulating film, 31 ... gate oxide film, 61 ... body region.

Claims (5)

A CMOS transistor and a DMOS transistor are formed in the same semiconductor layer of the first conductivity type,
The CMOS transistor is
A first gate electrode formed on the semiconductor layer via a first insulating film;
A first source region of a second conductivity type provided adjacent to the first gate electrode on the surface of the semiconductor layer;
A second conductivity type first drain region provided on the surface of the semiconductor layer so as to sandwich the first gate electrode together with the first source region;
The DMOS transistor is
A second gate electrode formed on the semiconductor layer via a second insulating film;
A second source region of a second conductivity type provided adjacent to the second gate electrode on the surface of the semiconductor layer;
A drift region of a second conductivity type provided on the surface of the semiconductor layer so as to sandwich the second gate electrode together with the second source region;
A second drain region of a second conductivity type provided on the surface of the semiconductor layer so as to be adjacent to the drift region and sandwich the second gate electrode together with the second source region;
A first sidewall is provided on a side surface of the first gate electrode, and a second sidewall is provided on a side surface of the second gate electrode;
The semiconductor device according to claim 1, wherein the second sidewall on the second drain region side is thicker in the direction along the second gate insulating film than the second sidewall on the second source region side.   The semiconductor device according to claim 1, wherein the first sidewall and the second sidewall are formed by stacking a plurality of types of insulating layers.   The semiconductor device according to claim 1, wherein the second sidewall on the second drain region side has a recess on an upper surface thereof. A method of manufacturing a semiconductor device in which a CMOS transistor and a DMOS transistor are formed in the same first conductivity type semiconductor layer,
Forming a first gate electrode for the CMOS transistor and a second gate electrode for the DMOS transistor on the semiconductor layer via an insulating film;
Laminating a plurality of types of insulating layers on the semiconductor layer including the first and second gate electrodes;
A step of covering the drain region side of the DMOS transistor of the second gate electrode with a mask and then etching a part of the insulating layer using the mask;
Performing anisotropic etching on the plurality of types of insulating layers to leave the insulating layers on the side walls of the first gate electrode and the second gate electrode, and forming a sidewall. A method for manufacturing a semiconductor device. A method of manufacturing a semiconductor device including a DMOS transistor,
Forming a plurality of gate electrodes on the semiconductor layer via an insulating film, and forming a dummy electrode at a position between the gate electrodes at a first interval between the gate electrodes; When,
Forming a drift region of the DMOS transistor by ion-implanting the semiconductor layer using the gate electrode and the dummy electrode as a mask;
Depositing an insulating film on the semiconductor layer including the gate electrode and the dummy electrode to a second thickness that is smaller than the first interval and larger than ½ of the first interval; When,
Performing anisotropic etching on the insulating film to form a sidewall on the side wall of the gate electrode;
And a step of forming a drain region and a source region of the DMOS transistor by implanting ions into the semiconductor layer after removing the dummy electrode.

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