JP2009272314A - Multilayer silicon semiconductor wafer and method of manufacturing the same - Google Patents

Multilayer silicon semiconductor wafer and method of manufacturing the same Download PDF

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JP2009272314A
JP2009272314A JP2008118573A JP2008118573A JP2009272314A JP 2009272314 A JP2009272314 A JP 2009272314A JP 2008118573 A JP2008118573 A JP 2008118573A JP 2008118573 A JP2008118573 A JP 2008118573A JP 2009272314 A JP2009272314 A JP 2009272314A
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silicon semiconductor
semiconductor wafer
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JP5240651B2 (en
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Toshimi Tobe
敏視 戸部
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Shin Etsu Handotai Co Ltd
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a multilayer silicon semiconductor wafer capable of having gettering capability in a multilayer silicon semiconductor wafer where thin-layer silicon semiconductor wafers are laminated, and to provide a manufacturing method of the multilayer silicon semiconductor wafer. <P>SOLUTION: The multilayer silicon semiconductor wafer is manufactured by polishing the backside of a silicon semiconductor wafer of which devices have already been formed for thinning, forming a damage layer on the polishing surface on the backside of the thinned silicon semiconductor wafer for manufacturing individual silicon semiconductor wafers, and laminating a plurality of individual silicon semiconductor wafers where the plurality of devices have already been formed and the damage layer is formed on the backside. In the multilayer silicon semiconductor wafer, each laminated layer has each individual device and damage layer, and even a multilayer structure of a thin layer has gettering capability. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

本発明は、デバイス動作に悪影響を及ぼす重金属不純物を除去する技術であるゲッタリング方法に関し、高いゲッタリング能力を持った多層シリコン半導体ウェーハ及びその作製方法に関する。   The present invention relates to a gettering method that is a technique for removing heavy metal impurities that adversely affect device operation, and relates to a multilayer silicon semiconductor wafer having high gettering capability and a method for manufacturing the same.

半導体集積回路等のデバイスの高密度化、高集積化に伴い、デバイス動作の安定化が頓に望まれてきている。特にリーク電流や酸化膜耐圧等の特性値改善は重要な課題である。   As the density of devices such as semiconductor integrated circuits is increased and the integration is increased, stabilization of device operation has been desired. In particular, improvement of characteristic values such as leakage current and oxide film breakdown voltage is an important issue.

しかるに半導体集積回路の製造工程において、望まれざる重金属、例えばCu、Fe、Niといった不純物に汚染される可能性が現在においても否定できていない。これらの重金属不純物はシリコン単結晶中に固溶した状態で、前述のリーク電流や酸化膜耐圧特性を著しく劣化させることが広く知られている。   However, in the manufacturing process of semiconductor integrated circuits, the possibility of contamination with impurities such as undesired heavy metals such as Cu, Fe, and Ni cannot be denied. It is widely known that these heavy metal impurities are significantly dissolved in the silicon single crystal and the above-described leakage current and oxide film breakdown voltage characteristics are remarkably deteriorated.

そのためこれら重金属不純物をデバイス動作領域外へ取り除く方法として、種々のゲッタリング技術が開発されてきている。例えばCZ法で製造されたシリコン単結晶中に含まれる酸素原子を析出させ、その析出物周囲の歪みに重金属を捕獲するIG(Internal Gettering)法や、シリコンウェーハの裏面に多結晶シリコン膜を形成し、その多結晶粒界の歪みに不純物を捕獲する方法などである。後者はEG法(External Gettering)法の代表例である。また、シリコン半導体ウェーハ中の不純物を金属層や酸化層によってゲッタリングする技術についても知られている(例えば、特許文献1〜4)。   Therefore, various gettering techniques have been developed as a method for removing these heavy metal impurities out of the device operating region. For example, oxygen atoms contained in a silicon single crystal produced by the CZ method are deposited, and an IG (Internal Gettering) method that captures heavy metals in the strain around the precipitate, or a polycrystalline silicon film is formed on the back surface of a silicon wafer And a method of trapping impurities in the distortion of the polycrystalline grain boundary. The latter is a representative example of the EG method (External Gettering) method. A technique for gettering impurities in a silicon semiconductor wafer with a metal layer or an oxide layer is also known (for example, Patent Documents 1 to 4).

しかるに、デバイスを高集積化する方法の一つとして、最近、通常のシリコンウェーハにデバイスを作製後、裏面を研磨することで薄膜化し、そのように製造した薄膜シリコンウェーハを複数層堆積させる方法が使われるようになった(例えば、特願2007−176310)。これをマルチチップパッケージ(MCP)というが、この構造は、デバイスをウェーハの深さ方向に複数形成できるため、従来の製法よりも高集積化が可能になるという利点がある反面、重金属汚染にさらされた場合、各層にそれぞれ形成されたデバイス領域の格子歪みに金属が集まることになり、動作不良が多くなるという欠点がある。コスト面でも全層が不良になるため、損失が大きい。しかもこの構造では、従来の不純物ゲッタリング技術、例えば裏面多結晶シリコン層やIG法は有効に機能しない。前者は各層に存在するデバイス層が金属不純物を裏面多結晶層までの拡散工程を妨害し、後者ではゲッタリングサイトとなりうるBMD(Bulk Micro Defect)層が研磨で削り落とされるため、薄膜化以降はほとんどゲッタリング層が残存していないことが、それぞれゲッタリングの機能しない理由である。
特開2002−323795 特開2004−327489 特開2005−64341 特開2005−311126
However, as one of the methods for highly integrating devices, recently, after fabricating a device on a normal silicon wafer, the back surface is polished to form a thin film, and the thin film silicon wafer thus manufactured is deposited in a plurality of layers. (For example, Japanese Patent Application No. 2007-176310). This structure is called a multi-chip package (MCP), but this structure has the advantage that higher integration is possible than conventional methods because multiple devices can be formed in the depth direction of the wafer. In this case, the metal collects in the lattice distortion of the device region formed in each layer, and there is a disadvantage that operation failures increase. In terms of cost, all the layers are defective, so the loss is large. Moreover, in this structure, conventional impurity gettering techniques such as the backside polycrystalline silicon layer and the IG method do not function effectively. In the former, the device layer existing in each layer interferes with the diffusion process of metal impurities to the backside polycrystalline layer, and in the latter, the BMD (Bulk Micro Defect) layer that can be a gettering site is scraped off by polishing. The fact that almost no gettering layer remains is the reason why gettering does not function.
JP 2002-323795 JP 2004-327489 A JP-A-2005-64341 JP2005-311126

本発明は、このような問題点に鑑みてなされたもので、薄層のシリコン半導体ウェーハを積層してなる多層のシリコン半導体ウェーハにおいてもゲッタリング能力を持たせることができるようにした多層シリコン半導体ウェーハ及びその作製方法を提供することを目的とする。   The present invention has been made in view of such problems, and a multi-layer silicon semiconductor capable of providing a gettering capability even in a multi-layer silicon semiconductor wafer formed by laminating thin silicon semiconductor wafers. An object of the present invention is to provide a wafer and a manufacturing method thereof.

上記課題を解決するため、本発明の多層シリコン半導体ウェーハは、デバイス形成済みのシリコン半導体ウェーハの裏面を研磨して薄膜化し、前記薄膜化したシリコン半導体ウェーハの裏面研磨面にダメージ層を形成して個別のシリコン半導体ウェーハを作製し、前記デバイス形成済でかつ裏面にダメージ層を形成した個別のシリコン半導体ウェーハの複数枚を積層して作製された多層シリコン半導体ウェーハであって、当該積層した各層がそれぞれ個別のデバイス及びダメージ層を具備し、かつ薄層の多層構造であってもゲッタリング能力を有することを特徴とする。本発明の半導体デバイスは上記多層シリコン半導体ウェーハからなることを特徴とする。   In order to solve the above problems, the multilayer silicon semiconductor wafer of the present invention is formed by polishing the back surface of a silicon semiconductor wafer on which devices have been formed, and forming a damaged layer on the back surface of the thinned silicon semiconductor wafer. A multi-layered silicon semiconductor wafer produced by laminating a plurality of individual silicon semiconductor wafers having individual devices formed and having a damaged layer formed on the back surface, wherein each of the laminated layers is Each device has an individual device and a damage layer, and has a gettering ability even in a thin multilayer structure. A semiconductor device according to the present invention comprises the above-described multilayer silicon semiconductor wafer.

本発明の多層シリコン半導体ウェーハの作製方法は、デバイス形成済みのシリコン半導体ウェーハの裏面を研磨し薄膜化する工程と、前記薄膜化したシリコン半導体ウェーハの裏面研磨面にダメージ層を形成して個別のシリコン半導体ウェーハを作製する工程と、前記デバイス形成済でかつ裏面にダメージ層を形成した個別のシリコン半導体ウェーハの複数枚を積層する工程と、を有し、当該積層した各層がそれぞれ個別のデバイス及びダメージ層を具備し、かつ薄層の多層構造であってもゲッタリング能力を有する多層シリコン半導体ウェーハを作製することを特徴とする。本発明の半導体デバイスの作製方法は、上記方法において、多層シリコン半導体ウェーハを半導体デバイスとするものである。   The method for producing a multilayer silicon semiconductor wafer of the present invention comprises a step of polishing and thinning the back surface of a silicon semiconductor wafer on which devices have been formed, and forming a damage layer on the back surface of the thinned silicon semiconductor wafer to form individual layers. A step of fabricating a silicon semiconductor wafer, and a step of laminating a plurality of individual silicon semiconductor wafers on which the device has been formed and a damage layer is formed on the back surface, and each of the laminated layers is an individual device and A multilayer silicon semiconductor wafer having a damaged layer and having a gettering ability even in a thin multilayer structure is manufactured. The method for producing a semiconductor device of the present invention is the above method, wherein a multilayer silicon semiconductor wafer is used as the semiconductor device.

サンドブラストを施すことにより、又は機械的研削より、又はレーザー照射によって裏面に研磨傷やダメージを残存させることにより、前記ダメージ層を形成するのが好適である。また、前記ダメージ層をレーザー照射によって形成することもできる。   It is preferable to form the damaged layer by sandblasting, by mechanical grinding, or by leaving polishing scratches or damage on the back surface by laser irradiation. The damaged layer can be formed by laser irradiation.

多層構造の各層で有害な不純物を除去するためには、各層の最下部にゲッタリング層を設ける必要がある。しかし現状のMCP工程では、薄膜化した後に何らゲッタリング層と見なせる層は存在しておらず、そのため汚染された不純物金属は大抵の場合デバイス層中に入り込む。なぜなら単結晶シリコンの領域よりもデバイス層の方が歪みを持っているため、かえってデバイス層に不純物金属が析出するからである。   In order to remove harmful impurities in each layer of the multilayer structure, it is necessary to provide a gettering layer at the bottom of each layer. However, in the current MCP process, there is no layer that can be regarded as a gettering layer after the film is thinned. Therefore, the contaminated impurity metal usually enters the device layer. This is because the device layer is more distorted than the single crystal silicon region, and impurity metals are deposited in the device layer.

本発明はその点を考慮して案出されたもので、薄膜化されたシリコンウェーハ裏面にダメージ層(又は歪み層ともいう)を形成することを構成的な特徴とする。このダメージ層(歪み層)を形成する方法としては、例えば、サンドブラスト法のようにアルミナ粉、あるいはシリカ粉を裏面に衝突させて歪みを形成する方法が有効であり、あるいは研磨の際、あえて歪みを形成するために機械研削を用いる方法も十分使用できる。さらに、レーザー照射によって歪み層(ダメージ層)を形成することも可能である。   The present invention has been devised in view of this point, and is characterized by forming a damage layer (also referred to as a strained layer) on the back surface of a thinned silicon wafer. As a method of forming this damaged layer (strained layer), for example, a method of forming strain by colliding alumina powder or silica powder with the back surface, such as a sandblast method, is effective. A method using mechanical grinding to form the film can also be used sufficiently. Furthermore, a strained layer (damaged layer) can be formed by laser irradiation.

本発明の多層シリコン半導体ウェーハによれば、薄層の多層構造においても有効なゲッタリング能力を付与することができる。また、本発明方法によれば、本発明の多層シリコン半導体ウェーハを効果的に作製することができるという利点がある。   According to the multilayer silicon semiconductor wafer of the present invention, effective gettering ability can be imparted even in a thin multilayer structure. Moreover, according to the method of the present invention, there is an advantage that the multilayer silicon semiconductor wafer of the present invention can be effectively produced.

以下に、本発明の実施の形態を添付図面に基づいて説明するが、これらの実施の形態は例示として示されるもので、本発明の技術思想から逸脱しない限り種々の変形が可能なことはいうまでもない。図1は本発明の多層シリコン半導体ウェーハの作製方法の工程順を示すフローチャートである。図2は本発明の多層シリコン半導体ウェーハの作製方法の作製手順を示す模式的説明図である。図3は本発明の多層シリコン半導体ウェーハの構造を示す断面的説明図である。   Embodiments of the present invention will be described below with reference to the accompanying drawings. However, these embodiments are shown as examples, and various modifications can be made without departing from the technical idea of the present invention. Not too long. FIG. 1 is a flowchart showing a process sequence of a method for producing a multilayer silicon semiconductor wafer according to the present invention. FIG. 2 is a schematic explanatory view showing a production procedure of the method for producing a multilayer silicon semiconductor wafer of the present invention. FIG. 3 is a cross-sectional explanatory view showing the structure of the multilayer silicon semiconductor wafer of the present invention.

本発明の多層シリコン半導体ウェーハの作製方法は、図1及び図2に示すような作製工程を有している。まず、デバイス形成済みの複数枚(図2の例では3枚)のシリコン半導体ウェーハ10,10,10を準備する(図1のステップ100及び図2(a))。次に、上記シリコン半導体ウェーハ10の裏面を研磨し、該シリコン半導体ウェーハ10を薄膜化する。つまり、シリコン半導体ウェーハ10の裏面を研削して裏面部分10bを削除し、薄膜化したシリコン半導体ウェーハ10aとする(図1のステップ102及び図2(b))。   The method for manufacturing a multilayer silicon semiconductor wafer of the present invention includes manufacturing steps as shown in FIGS. First, a plurality of (three in the example of FIG. 2) silicon semiconductor wafers 10, 10, 10 on which devices have been formed are prepared (step 100 in FIG. 1 and FIG. 2 (a)). Next, the back surface of the silicon semiconductor wafer 10 is polished to thin the silicon semiconductor wafer 10. That is, the back surface portion 10b is removed by grinding the back surface of the silicon semiconductor wafer 10 to obtain a thinned silicon semiconductor wafer 10a (step 102 in FIG. 1 and FIG. 2B).

続いて、前記薄膜化したシリコン半導体ウェーハ10aにダメージ層12を形成して個別のシリコン半導体ウェーハ10cを作製する(図1のステップ104及び図2(c))。このダメージ層12をシリコン半導体ウェーハ10aの裏面に形成する手法としては、例えば、サンドブラスト法のようにアルミナ粉、あるいはシリカ粉を裏面に衝突させて歪みを形成する方法が有効であり、あるいは研磨の際、あえて歪みを形成するために機械研削を用いる方法も十分使用できる。さらに、レーザー照射によって歪み層(ダメージ層)12を形成することも可能である。   Subsequently, a damage layer 12 is formed on the thinned silicon semiconductor wafer 10a to produce individual silicon semiconductor wafers 10c (step 104 in FIG. 1 and FIG. 2C). As a method of forming the damaged layer 12 on the back surface of the silicon semiconductor wafer 10a, for example, a method of forming strain by colliding alumina powder or silica powder with the back surface, such as sandblasting, is effective. At this time, a method using mechanical grinding can be sufficiently used to form a strain. Furthermore, the strained layer (damaged layer) 12 can be formed by laser irradiation.

前記デバイス形成済みでかつ裏面にダメージ層12を形成した個別のシリコン半導体ウェーハ10cの複数枚(図示例では、3枚)を積層し貼り合わせる(図1のステップ106及び図2(d))。このようにして多層シリコン半導体ウェーハ10dが完成する(図1のステップ108及び図2(e))。   A plurality (three in the illustrated example) of individual silicon semiconductor wafers 10c on which the device has been formed and the damage layer 12 is formed on the back surface are stacked and bonded together (step 106 in FIG. 1 and FIG. 2 (d)). In this way, the multi-layered silicon semiconductor wafer 10d is completed (step 108 in FIG. 1 and FIG. 2E).

図3に多層シリコン半導体ウェーハ10dの断面説明図を拡大して示した。3枚のデバイス形成済みでかつ裏面にダメージ層12を形成した個別のシリコン半導体ウェーハ10cを積層し、接着剤を用いて貼り合わせて、多層シリコン半導体ウェーハ10dを作製したものである。この多層シリコン半導体ウェーハ10dは後述する実施例に記載したように高いゲッタリング能力を有することが確認された。   FIG. 3 is an enlarged cross-sectional explanatory view of the multilayer silicon semiconductor wafer 10d. The individual silicon semiconductor wafers 10c having three devices already formed and the damage layer 12 formed on the back surface are stacked and bonded together using an adhesive to produce a multilayer silicon semiconductor wafer 10d. This multi-layered silicon semiconductor wafer 10d was confirmed to have a high gettering capability as described in the examples described later.

以下、本発明の実施例及び比較例を挙げて具体的に説明するが、本発明はこれらに限定されるものではない。   Hereinafter, although an example and a comparative example of the present invention are given and explained concretely, the present invention is not limited to these.

(実施例1)
CZ法により、直径6インチ、初期酸素濃度14ppmaJEIDA、方位<100>の結晶棒を、通常の引き上げ速度(1.2mm/min)で引き上げた。この結晶棒を加工してシリコン半導体ウェーハとし、その表面にデバイスを形成した。ついで、このデバイス形成済みのシリコン半導体ウェーハの裏面を50μm厚まで研磨することで薄膜化したシリコン半導体ウェーハを得た。その薄膜化シリコン半導体ウェーハの裏面にサンドブラストを施すことによって、歪み層(ダメージ層)を形成し、個別シリコン半導体ウェーハを3枚作製し、これら3枚の個別シリコン半導体ウェーハを重ね、接着剤を用いて貼りあわせた。
Example 1
A crystal rod having a diameter of 6 inches, an initial oxygen concentration of 14 ppma JEIDA, and an orientation <100> was pulled at a normal pulling speed (1.2 mm / min) by the CZ method. This crystal rod was processed into a silicon semiconductor wafer, and a device was formed on the surface. Next, a silicon semiconductor wafer having a reduced thickness was obtained by polishing the back surface of this device-formed silicon semiconductor wafer to a thickness of 50 μm. By applying sand blasting to the back surface of the thinned silicon semiconductor wafer, a strained layer (damage layer) is formed, three individual silicon semiconductor wafers are produced, and the three individual silicon semiconductor wafers are stacked and an adhesive is used. And pasted together.

こうして1枚に重ねた多層シリコン半導体ウェーハの表面にFeを4×1013cm−2の濃度で塗布し、1000℃、1時間の熱処理で当該多層シリコン半導体ウェーハの内部にFeを拡散させた。その後、600℃、10時間の熱処理を施し、室温まで冷却後の多層シリコン半導体ウェーハの表面からSIMSにてFe濃度の深さ方向分布を測定した。その結果、多層シリコン半導体ウェーハの単結晶シリコン部分ではFeは検出下限以下であったのに対し、多層シリコン半導体ウェーハのダメージ層(サンドブラスト部分)ではFeが高濃度に分布している様子が確認された。これは多層シリコン半導体ウェーハの多層構造になっている3層全てにおいて見られ、各層裏面に形成したダメージ層(歪み層)が強いゲッタリング能力を発揮したためと考えられる。 Fe was applied at a concentration of 4 × 10 13 cm −2 to the surface of the multi-layered silicon semiconductor wafer thus laminated, and Fe was diffused into the multi-layered silicon semiconductor wafer by heat treatment at 1000 ° C. for 1 hour. Thereafter, heat treatment was performed at 600 ° C. for 10 hours, and the depth direction distribution of Fe concentration was measured by SIMS from the surface of the multilayer silicon semiconductor wafer after cooling to room temperature. As a result, it was confirmed that Fe was below the lower limit of detection in the single crystal silicon portion of the multilayer silicon semiconductor wafer, whereas Fe was distributed in a high concentration in the damaged layer (sandblast portion) of the multilayer silicon semiconductor wafer. It was. This is seen in all three layers having a multilayer structure of the multilayer silicon semiconductor wafer, and it is considered that a damaged layer (strained layer) formed on the back surface of each layer exhibited a strong gettering ability.

(実施例2)
CZ法により、直径6インチ、初期酸素濃度14ppmaJEIDA、方位<100>の結晶棒を、通常の引き上げ速度(1.2mm/min)で引き上げた。この結晶棒を加工してシリコン半導体ウェーハとし、その表面にデバイスを形成した。ついで、このデバイス形成済みのシリコン半導体ウェーハの裏面を50μm厚まで機械研削を施すことで歪み層(ダメージ層)を形成するとともに薄膜化したシリコン半導体ウェーハを得た。この個別シリコン半導体ウェーハを3枚作製し、これら3枚の個別シリコン半導体ウェーハを重ね、接着剤を用いて貼りあわせた。
(Example 2)
A crystal rod having a diameter of 6 inches, an initial oxygen concentration of 14 ppma JEIDA, and an orientation <100> was pulled at a normal pulling speed (1.2 mm / min) by the CZ method. This crystal rod was processed into a silicon semiconductor wafer, and a device was formed on the surface. Subsequently, the back surface of this device-formed silicon semiconductor wafer was mechanically ground to a thickness of 50 μm to form a strained layer (damaged layer) and a thinned silicon semiconductor wafer. Three individual silicon semiconductor wafers were prepared, and the three individual silicon semiconductor wafers were stacked and bonded together using an adhesive.

こうして1枚に重ねた多層シリコン半導体ウェーハの表面にFeを4×1013cm−2の濃度で塗布し、1000℃、1時間の熱処理でウェーハ内部にFeを拡散させた。その後、600℃、10時間の熱処理を施し、室温まで冷却後の多層シリコン半導体ウェーハの表面からSIMSにてFe濃度の深さ方向分布を測定した。その結果、多層シリコン半導体ウェーハの単結晶シリコン部分ではFeは検出下限以下であったのに対し、多層シリコン半導体ウェーハの研削面である裏面側ではFeが高濃度に分布している様子が確認された。これは多層シリコン半導体ウェーハの多層構造になっている3層全てにおいて見られ、各層裏面に形成した歪み層(ダメージ層)が強いゲッター能力を発揮したためと考えられる。 Fe was applied at a concentration of 4 × 10 13 cm −2 on the surface of the multi-layered silicon semiconductor wafer thus stacked, and Fe was diffused inside the wafer by heat treatment at 1000 ° C. for 1 hour. Thereafter, heat treatment was performed at 600 ° C. for 10 hours, and the depth direction distribution of Fe concentration was measured by SIMS from the surface of the multilayer silicon semiconductor wafer after cooling to room temperature. As a result, it was confirmed that Fe was below the lower limit of detection in the single crystal silicon portion of the multilayer silicon semiconductor wafer, whereas Fe was distributed at a high concentration on the back side, which is the ground surface of the multilayer silicon semiconductor wafer. It was. This is seen in all three layers having a multilayer structure of the multilayer silicon semiconductor wafer, and it is considered that the strained layer (damage layer) formed on the back surface of each layer exhibited a strong getter ability.

(実施例3)
CZ法により、直径6インチ、初期酸素濃度14ppmaJEIDA、方位<100>の結晶棒を、通常の引き上げ速度(1.2mm/min)で引き上げた。この結晶棒を加工してシリコン半導体ウェーハとし、その表面にデバイスを形成した。ついで、このデバイス形成済みのシリコン半導体ウェーハの裏面を50μm厚まで研磨することで薄膜化したシリコン半導体ウェーハを得た。その薄膜化シリコン半導体ウェーハの裏面に10J/cmのエネルギー密度でYAGレーザーを照射して歪み層(ダメージ層)を形成し、個別シリコン半導体ウェーハを3枚作製し、これら3枚の個別シリコン半導体ウェーハを重ね、接着剤を用いて貼りあわせた。
(Example 3)
A crystal rod having a diameter of 6 inches, an initial oxygen concentration of 14 ppma JEIDA, and an orientation <100> was pulled at a normal pulling speed (1.2 mm / min) by the CZ method. This crystal rod was processed into a silicon semiconductor wafer, and a device was formed on the surface. Next, a silicon semiconductor wafer having a reduced thickness was obtained by polishing the back surface of this device-formed silicon semiconductor wafer to a thickness of 50 μm. The back surface of the thinned silicon semiconductor wafer is irradiated with a YAG laser at an energy density of 10 J / cm 2 to form a strained layer (damage layer), and three individual silicon semiconductor wafers are produced. These three individual silicon semiconductors The wafers were stacked and bonded using an adhesive.

こうして1枚に重ねた多層シリコン半導体ウェーハの表面にFeを4×1013cm−2の濃度で塗布し、1000℃、1時間の熱処理で当該多層シリコン半導体ウェーハの内部にFeを拡散させた。その後、600℃、10時間の熱処理を施し、室温まで冷却後の多層シリコン半導体ウェーハの表面からSIMSにてFe濃度の深さ方向分布を測定した。その結果、多層シリコン半導体ウェーハの単結晶シリコン部分ではFeは検出下限以下であったのに対し、多層シリコン半導体ウェーハのレーザー照射を行った歪み層(ダメージ層)部分ではFeが高濃度に分布している様子が確認された。これは多層シリコン半導体ウェーハの多層構造になっている3層全てにおいて見られ、各層裏面に形成した歪み層(ダメージ層)が強いゲッター能力を発揮したためと考えられる。 Fe was applied at a concentration of 4 × 10 13 cm −2 to the surface of the multi-layered silicon semiconductor wafer thus laminated, and Fe was diffused into the multi-layered silicon semiconductor wafer by heat treatment at 1000 ° C. for 1 hour. Thereafter, heat treatment was performed at 600 ° C. for 10 hours, and the depth direction distribution of Fe concentration was measured by SIMS from the surface of the multilayer silicon semiconductor wafer after cooling to room temperature. As a result, while Fe was below the lower limit of detection in the single crystal silicon portion of the multilayer silicon semiconductor wafer, Fe was distributed at a high concentration in the strained layer (damage layer) portion of the multilayer silicon semiconductor wafer that was irradiated with laser. It was confirmed. This is seen in all three layers having a multilayer structure of the multilayer silicon semiconductor wafer, and it is considered that the strained layer (damage layer) formed on the back surface of each layer exhibited a strong getter ability.

(比較例1)
CZ法により、直径6インチ、初期酸素濃度14ppmaJEIDA、方位<100>の結晶棒を、通常の引き上げ速度(1.2mm/min)で引き上げた。この結晶棒を加工してシリコン半導体ウェーハとし、このシリコン半導体ウェーハの裏面を50μm厚まで研磨することで薄膜化したシリコン半導体ウェーハを得た。この薄膜化したシリコン半導体ウェーハ3枚を重ね、接着剤を用いて貼りあわせ、1枚の多層シリコン半導体ウェーハとした。
(Comparative Example 1)
A crystal rod having a diameter of 6 inches, an initial oxygen concentration of 14 ppma JEIDA, and an orientation <100> was pulled at a normal pulling speed (1.2 mm / min) by the CZ method. The crystal rod was processed into a silicon semiconductor wafer, and the back surface of the silicon semiconductor wafer was polished to a thickness of 50 μm to obtain a silicon semiconductor wafer having a reduced thickness. The three thinned silicon semiconductor wafers were stacked and bonded using an adhesive to form a single multilayer silicon semiconductor wafer.

こうして1枚に積層された多層シリコン半導体ウェーハの表面にFeを4×1013cm−2の濃度で塗布し、1000℃、1時間の熱処理で多層シリコン半導体ウェーハの内部にFeを拡散させた。その後、600℃、10時間の熱処理を施し、室温まで冷却後の多層シリコン半導体ウェーハの表面からSIMSにてFe濃度の深さ方向分布を測定した。その結果、表面からFeが検出され、その濃度3×1015cm−3という値は多層シリコン半導体ウェーハの裏面近傍でも変化が見られず、多層シリコン半導体ウェーハの表面から数えて2層目に移っても、その濃度に変化はなく、多層シリコン半導体ウェーハの深さ方向に均一に分布している様子がわかった。これは上記多層シリコン半導体ウェーハにはゲッタリング層となりうる部分が存在していないことを示している。 Fe was applied at a concentration of 4 × 10 13 cm −2 on the surface of the multilayer silicon semiconductor wafer thus laminated, and Fe was diffused into the multilayer silicon semiconductor wafer by heat treatment at 1000 ° C. for 1 hour. Thereafter, heat treatment was performed at 600 ° C. for 10 hours, and the depth direction distribution of Fe concentration was measured by SIMS from the surface of the multilayer silicon semiconductor wafer after cooling to room temperature. As a result, Fe was detected from the surface, and its value of 3 × 10 15 cm −3 did not change even near the back surface of the multilayer silicon semiconductor wafer, and moved to the second layer counted from the surface of the multilayer silicon semiconductor wafer. However, the density did not change, and it was found that the multilayer silicon semiconductor wafer was uniformly distributed in the depth direction. This indicates that the multilayer silicon semiconductor wafer does not have a portion that can be a gettering layer.

なお、本発明は上記実施形態に限定されるものではない。上記形態は例示であり、本発明の特許請求の範囲に記載された技術的思想と実質的に同一な構成を有し、かつ同様な作用効果を奏するものは、いかなるものであっても本発明の技術的範囲に包含される。   The present invention is not limited to the above embodiment. The above embodiment is an exemplification, and the present invention has any configuration that has substantially the same configuration as the technical idea described in the claims of the present invention and that exhibits the same effects. Are included in the technical scope.

例えば本発明において、使用される歪み層形成法はサンドブラスト、機械的研削又はレーザー照射に限定するものではない。それら以外のダメージ層形成方法も本発明の範囲に含まれることはいうまでもない。   For example, in the present invention, the strained layer forming method used is not limited to sandblasting, mechanical grinding, or laser irradiation. Needless to say, other damage layer forming methods are also included in the scope of the present invention.

本発明の多層シリコン半導体ウェーハの作製方法の工程順を示すフローチャートである。It is a flowchart which shows the process order of the manufacturing method of the multilayer silicon semiconductor wafer of this invention. 本発明の多層シリコン半導体ウェーハの作製方法の作製手順を示す模式的説明図である。It is typical explanatory drawing which shows the preparation procedure of the manufacturing method of the multilayer silicon semiconductor wafer of this invention. 本発明の多層シリコン半導体ウェーハの構造を示す断面的説明図である。It is sectional explanatory drawing which shows the structure of the multilayer silicon semiconductor wafer of this invention.

符号の説明Explanation of symbols

10:シリコン半導体ウェーハ、10a: 薄膜化したシリコン半導体ウェーハ、10b:削除した裏面部分、10c:個別のシリコン半導体ウェーハ、10d:多層シリコン半導体ウェーハ、12:ダメージ層。   10: silicon semiconductor wafer, 10a: thinned silicon semiconductor wafer, 10b: deleted back surface portion, 10c: individual silicon semiconductor wafer, 10d: multilayer silicon semiconductor wafer, 12: damaged layer.

Claims (6)

デバイス形成済みのシリコン半導体ウェーハの裏面を研磨して薄膜化し、前記薄膜化したシリコン半導体ウェーハの裏面研磨面にダメージ層を形成して個別のシリコン半導体ウェーハを作製し、前記デバイス形成済でかつ裏面にダメージ層を形成した個別のシリコン半導体ウェーハの複数枚を積層して作製された多層シリコン半導体ウェーハであって、当該積層した各層がそれぞれ個別のデバイス及びダメージ層を具備し、かつ薄層の多層構造であってもゲッタリング能力を有することを特徴とする多層シリコン半導体ウェーハ。   The back surface of the silicon semiconductor wafer on which the device has been formed is polished to form a thin film, and a damaged layer is formed on the back polished surface of the thinned silicon semiconductor wafer to produce an individual silicon semiconductor wafer. A multilayer silicon semiconductor wafer produced by laminating a plurality of individual silicon semiconductor wafers each having a damaged layer formed thereon, each of the laminated layers having an individual device and a damaged layer, and a thin multilayer A multilayer silicon semiconductor wafer characterized by having a gettering ability even in a structure. サンドブラストを施すことにより、又は機械的研削により、又はレーザー照射によって裏面に研磨傷やダメージを残存させることにより、前記ダメージ層を形成することを特徴とする請求項1記載の多層シリコン半導体ウェーハ。   The multilayer silicon semiconductor wafer according to claim 1, wherein the damaged layer is formed by sandblasting, mechanical grinding, or by leaving polishing scratches or damage on the back surface by laser irradiation. 請求項1又は2記載の多層シリコン半導体ウェーハからなることを特徴とする半導体デバイス。   A semiconductor device comprising the multilayer silicon semiconductor wafer according to claim 1. デバイス形成済みのシリコン半導体ウェーハの裏面を研磨し薄膜化する工程と、前記薄膜化したシリコン半導体ウェーハの裏面研磨面にダメージ層を形成して個別のシリコン半導体ウェーハを作製する工程と、前記デバイス形成済でかつ裏面にダメージ層を形成した個別のシリコン半導体ウェーハの複数枚を積層する工程と、を有し、当該積層した各層がそれぞれ個別のデバイス及びダメージ層を具備し、かつ薄層の多層構造であってもゲッタリング能力を有する多層シリコン半導体ウェーハを作製することを特徴とする多層シリコン半導体ウェーハの作製方法。   Polishing the back surface of the silicon semiconductor wafer on which the device has been formed, thinning it, forming a damaged layer on the back polished surface of the thinned silicon semiconductor wafer, and manufacturing the individual silicon semiconductor wafer; and forming the device And laminating a plurality of individual silicon semiconductor wafers having a damaged layer formed on the back surface thereof, each of the laminated layers having an individual device and a damaged layer, and a thin multilayer structure Even so, a method for producing a multilayer silicon semiconductor wafer comprising producing a multilayer silicon semiconductor wafer having gettering ability. サンドブラストを施すことにより、又は機械的研削により、又はレーザー照射によって裏面に研磨傷やダメージを残存させることにより、前記ダメージ層を形成することを特徴とする請求項4記載の方法。   5. The method according to claim 4, wherein the damaged layer is formed by sandblasting, mechanical grinding, or by leaving polishing scratches or damage on the back surface by laser irradiation. 前記多層シリコン半導体ウェーハが半導体デバイスであることを特徴とする請求項4又は5記載の方法。   6. The method according to claim 4, wherein the multilayer silicon semiconductor wafer is a semiconductor device.
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