JP2009267053A - Method for manufacturing of wiring structure, display apparatus, and method for manufacturing thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To simultaneously form a wiring part 26 and a contact part 25, with no use of a CMP method. <P>SOLUTION: A second film 24 is formed in predetermined thickness along the surface of an interlayer insulating film 23 where a contact hole 27 and a wiring groove 28 are formed. Thus, a hole 31 is formed by the second film 24 in the contact hole 27 while a groove 32 is formed by the second film 24 in the wiring groove 28. After a resist is formed on the second film 24 so as to close the opening end of the hole 31 and the groove 32, such second film 24 as exposed around the hole 31 and the groove 32 by etching back is removed by etching, and a contact part 25 is formed in the contact hole 27 while a wiring part 26 is formed in the wiring groove 28. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a wiring structure, a display device, and a method for manufacturing the same.

  In recent years, semiconductor devices have been increasingly miniaturized and multi-layered due to high integration, and accordingly, planarization technology at the time of wiring formation, processing technology for fine wiring, and reliability of fine wiring. Demands for ensuring safety are becoming stricter. Further, as the internal wiring is miniaturized and multilayered, the accompanying increase in cost becomes a serious problem.

  On the other hand, a so-called damascene method has been studied in which, when a wiring is multilayered, the wiring and the interlayer insulating film are not simply laminated, but the wiring is embedded in the interlayer insulating film (for example, Patent Document 1). Etc.). In the damascene method, when the wiring is embedded in the interlayer insulating film, a conductive film is embedded also in the connection hole for conducting the upper layer wiring and the lower layer wiring, so that the wiring portion and the contact portion are simultaneously formed with a single conductive film. The so-called Dual Damascene method, which makes it possible to form, is attracting particular attention.

  Here, the wiring formation by the dual damascene method will be described with reference to FIGS.

  First, as shown in FIG. 8, the interlayer insulating film 102 formed on the lower layer wiring 101 on the insulating substrate 100 is etched to form a connection hole 102a facing the lower layer wiring 101, and further, the interlayer insulating film 102 Is etched to form a wiring groove 102b corresponding to the upper layer wiring. Thus, the structure in which the connection hole 102a and the wiring groove 102b are formed in the interlayer insulating film 102 is called a dual damascene structure.

  Next, as shown in FIG. 9, a base barrier metal 103 made of a laminated film of a Ti film and a TiN film or the like is formed on the interlayer insulating film 102 having a dual damascene structure by sputtering. A conductive film 104 made of a conductive material such as Al or an Al alloy is formed on the substrate 103 by sputtering.

  Normally, the conductive film 104 is not formed so as to completely fill the inside of the connection hole 102a and the wiring groove 102b, and as shown in FIG. 9, a gap 104a is generated in the connection hole 102a and the wiring groove 102b. . Therefore, a reflow process is performed on the conductive film 104 so as to eliminate the gap 104a. That is, the fluidity of the conductive film 104 is increased by heating the conductive film 104 to near the melting point in a high vacuum. As a result, as shown in FIG. 10, the conductive film 104 is buried in the wiring groove 102b and the connection hole 102a without any gap.

  Next, as shown in FIG. 11, polishing is performed from the surface of the conductive film 104 to the interlayer insulating film 102 by a chemical mechanical polishing method (hereinafter referred to as a CMP method), so that a connection hole 102a and a wiring groove 102b are obtained. The surface of the conductive film 104 embedded inside is flattened together with the base barrier metal 103 and the interlayer insulating film 102. Thus, the upper layer wiring is formed by the conductive film 104 embedded in the connection hole 102a and the wiring groove 102b.

In the dual damascene method, the formation of the wiring and the filling of the connection hole are performed simultaneously, so that the number of steps can be reduced and the cost can be reduced.
JP-A-9-223731

  By the way, in recent years, liquid crystal display devices have been increased in size of display screens as represented by so-called liquid crystal televisions. Along with this, the substrate size of the liquid crystal display device is also increased, and it is difficult to planarize the film surface over the entire substrate by CMP. Therefore, it is extremely difficult to apply the above-described dual damascene method to a large liquid crystal display device.

  The present invention has been made in view of such a point, and the main object of the present invention is to manufacture the wiring portion and the contact portion at the same time in spite of not using the CMP method. The purpose is to reduce this.

  In order to achieve the above object, a method of manufacturing a wiring structure according to the present invention includes a first film forming step of forming a first film on a substrate, and an interlayer insulation on the substrate so as to cover the first film. Forming an insulating film, forming a contact hole in the interlayer insulating film through the interlayer insulating film to expose a part of the first film, and forming a wiring groove on the surface of the interlayer insulating film; A conductive film is formed on the patterning step to be formed, the surface of the interlayer insulating film including the inside of the contact hole and the inside of the wiring groove, and the surface of the first film exposed inside the contact hole. By forming a second film with a predetermined thickness along each of the surfaces, a hole is formed by the second film in the contact hole, and a groove is formed by the second film in the wiring groove. Two film formation steps; A resist forming step for filling the hole portion and the groove portion with a resist and forming the resist on the second film so as to close the opening ends of the hole portion and the groove portion, and the periphery of the hole portion and the groove portion described above. Etching back the resist until the second film is exposed, and removing the exposed second film by etching, thereby making the second film remaining in the contact hole a contact portion, And an etching step using the second film remaining in the wiring trench as a wiring portion.

  In the patterning step, it is preferable that the contact hole and the wiring groove are formed by photolithography in which the interlayer insulating film is half-exposed.

  The first film may be a semiconductor layer.

  It is preferable that at least a part of the inner peripheral surface of the contact hole is formed in a taper shape extending toward the side opposite to the substrate.

  It is preferable that at least a part of the inner side surface of the wiring groove is formed in a taper shape extending toward the side opposite to the substrate.

  The display device manufacturing method according to the present invention manufactures a display device by bonding a first substrate having a plurality of switching elements and wiring structures formed on the substrate to a second substrate via a display medium layer. A first film forming step of forming a first film on the substrate; an insulating film forming step of forming an interlayer insulating film on the substrate so as to cover the first film; and the interlayer insulating film Forming a contact hole penetrating the interlayer insulating film to expose a part of the first film, and forming a wiring groove on the surface of the interlayer insulating film; and the inside of the contact hole and the wiring With respect to the surface of the interlayer insulating film including the inside of the trench and the surface of the first film exposed inside the contact hole, a second film that is a conductive film has a predetermined thickness along each surface. By forming with A second film forming step of forming a hole by the second film in the contact hole and forming a groove by the second film in the wiring groove, filling the hole and the groove with a resist, Forming a resist on the second film so as to close the opening ends of the hole and groove, and etching back the resist until the second film is exposed around the hole and groove. And removing the exposed second film by etching, whereby the second film remaining in the contact hole is used as a contact portion, while the second film remaining in the wiring groove is used as a wiring portion. An etching process.

  In the patterning step, it is preferable that the contact hole and the wiring groove are formed by photolithography in which the interlayer insulating film is half-exposed.

  The first film may be a semiconductor layer.

  It is preferable that at least a part of the inner peripheral surface of the contact hole is formed in a taper shape extending toward the side opposite to the substrate.

  It is preferable that at least a part of the inner side surface of the wiring groove is formed in a taper shape extending toward the side opposite to the substrate.

  The display medium layer may be a liquid crystal layer.

  The display device according to the present invention includes a first substrate having a plurality of switching elements and a wiring structure formed on the substrate, a second substrate disposed to face the first substrate, the first substrate, A display device comprising a display medium layer provided between the second substrates, wherein the first substrate comprises a first film formed on the substrate and an interlayer insulating film covering the first film And a contact portion and a wiring portion formed of a conductive second film, each of which is formed to be recessed in the interlayer insulating film, and the second film of the contact portion is formed on the interlayer insulating film. A contact hole formed so as to be exposed through the inner peripheral surface of the contact hole and the exposed surface of the first film are formed with a predetermined thickness along each surface, and the second film of the wiring portion is The inner surface of the wiring trench formed in the interlayer insulating film, along the surface It is formed at a constant thickness.

  The first film may be a semiconductor layer.

  It is preferable that at least a part of the inner peripheral surface of the contact hole is formed in a taper shape extending toward the side opposite to the substrate.

  It is preferable that at least a part of the inner side surface of the wiring groove is formed in a taper shape extending toward the side opposite to the substrate.

  The display medium layer may be a liquid crystal layer.

-Action-
Next, the operation of the present invention will be described.

  When manufacturing the wiring structure or the display device, first, a first film forming step is performed to form a first film on the substrate. For example, a semiconductor layer can be applied to the first film. Next, an insulating film forming step is performed to form an interlayer insulating film on the substrate so as to cover the first film. Next, a patterning step is performed to form a contact hole that penetrates the interlayer insulating film and exposes a part of the first film in the interlayer insulating film, and forms a wiring groove on the surface of the interlayer insulating film.

  In this patterning step, for example, contact holes and wiring grooves can be formed by photolithography in which the interlayer insulating film is half-exposed. As a result, the contact hole and the wiring groove are collectively formed by one exposure.

  Further, if at least one of the inner peripheral surface of the contact hole and the inner side surface of the wiring groove is formed in a tapered shape in which a part thereof extends toward the opposite side of the substrate, in the subsequent second film forming step, The second film is easily deposited by sputtering or the like.

  Next, a second film forming step is performed, and a second film, which is a conductive film, is formed along each surface with respect to the surface of the interlayer insulating film and the surface of the first film exposed inside the contact hole. It is formed with a predetermined thickness. Thus, a hole is formed by the second film in the contact hole, and a groove is formed by the second film in the wiring groove. Next, a resist formation step is performed to fill the hole and groove with resist, and the resist is formed on the second film so as to close the opening ends of the hole and groove.

  Next, an etch back process is performed to etch back the resist until the second film is exposed around the hole and the groove. Next, an etching process is performed to etch and remove the exposed second film, whereby the second film remaining in the contact hole is used as a contact portion, while the second film remaining in the wiring trench is used as a wiring. Part.

  Therefore, according to the present invention, although the CMP method is not used, the wiring portion and the contact portion are simultaneously formed in the interlayer insulating film.

  According to the present invention, after forming a second film along the surface of the contact hole and wiring groove formed in the interlayer insulating film, the resist is etched back on the second film, and the contact hole and wiring groove are formed. Since the second film exposed around is removed by etching, the wiring portion and the contact portion can be formed at the same time regardless of not using the CMP method. As a result, the number of steps can be reduced, and the manufacturing cost can be reduced.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The present invention is not limited to the following embodiment.

Embodiment 1 of the Invention
1 to 7 show Embodiment 1 of the present invention.

  FIG. 1 is an enlarged sectional view showing a sectional structure of a TFT substrate. FIG. 2 is a cross-sectional view showing a resist formed on the interlayer insulating film. FIG. 3 is a cross-sectional view showing an interlayer insulating film in which contact holes and concave grooves are formed. FIG. 4 is a cross-sectional view showing a second film formed on the surface of an interlayer insulating film or the like. FIG. 5 is a cross-sectional view showing the resist formed on the second film. FIG. 6 is a cross-sectional view showing the second film partially exposed by etch back. FIG. 7 is a cross-sectional view illustrating a schematic configuration of the liquid crystal display device.

  As shown in FIG. 7, the liquid crystal display device 1 is not illustrated, but the TFT substrate 11 that is the first substrate, the counter substrate 12 that is the second substrate disposed to face the TFT substrate 11, and the above-mentioned And a liquid crystal layer 13 which is a display medium layer provided between the counter substrate 12 and the TFT substrate 11. The liquid crystal layer 13 is sealed between the substrates 11 and 12 by a sealing member 14. On the counter substrate 12, a color filter, a common electrode, a black matrix, and the like (not shown) are formed.

  The TFT substrate 11 is configured as a so-called active matrix substrate. Although not shown, the TFT substrate 11 has a plurality of pixels, which are display unit areas, arranged in a matrix. A plurality of gate wirings (not shown) are formed on the TFT substrate 11 so as to extend in parallel with each other. In addition, a plurality of source wirings (not shown) are formed on the TFT substrate 11 in parallel with each other, and are arranged so as to be orthogonal to the gate wiring. As a result, the TFT substrate 11 is formed with a pattern of gate lines and source lines in a grid pattern. Each pixel is formed by a substantially rectangular region partitioned by the gate wiring and the source wiring. Each pixel has a pixel electrode (not shown) for driving the liquid crystal layer. Each pixel is provided with a TFT (thin film transistor) 16 which is a switching element for switching the pixel electrode. That is, a plurality of TFTs 16 and a wiring structure 10 are formed on the TFT substrate 11.

  As shown in FIG. 1, the TFT substrate 11 includes a glass substrate 15 that is a transparent substrate, and a semiconductor layer 17 that is a first film constituting the TFT 16 is patterned in an island shape on the glass substrate 15. . A gate insulating film 18 is formed on the glass substrate 15 so as to cover the semiconductor layer 17. Further, a gate electrode 19 is formed on the surface of the gate insulating film 18 so as to overlap a part of the semiconductor layer 17. In the semiconductor layer 17, a channel region 20 facing the gate electrode 19 and a source region 21 and a drain region 22 adjacent to the channel region 20 are formed.

  An interlayer insulating film 23 is formed on the gate insulating film 18 so as to cover the gate electrode 19 and the semiconductor layer 17 below the gate electrode 19. In the interlayer insulating film 23, a contact portion 25 and a wiring portion 26 are formed which are formed in a concave shape and are made of a conductive film 24 which is a second film. The contact portion 25 and the wiring portion 26 constitute the wiring structure 10.

  Contact holes 27 are formed through the interlayer insulating film 23 so that the source region 21 and the drain region 22 of the semiconductor layer 17 are exposed. As shown in FIG. 1, the contact hole 27 is formed in a stepped shape having a two-step longitudinal section, and the inner peripheral surface of the contact hole 27 extends toward the side opposite to the glass substrate 15 (that is, upward in FIG. 1). Is formed.

  The interlayer insulating film 23 is formed with a plurality of concave-shaped wiring grooves 28 that open upward on the surface of the interlayer insulating film 23. As shown in FIG. 1, the inner surface of the wiring groove 28 is formed in a tapered shape that expands toward the side opposite to the glass substrate 15.

  The conductive film 24 of the contact portion 25 is formed on the inner peripheral surface of the contact hole 27 formed in the interlayer insulating film 23 and the surface of the semiconductor layer 17 exposed inside the contact hole 27 along the respective surfaces. It is formed with a thickness. On the other hand, the conductive film 24 of the wiring portion 26 is formed on the inner surface of the wiring groove 28 formed in the interlayer insulating film 23 with a predetermined thickness along the surface.

  Thus, the hole portion 31 is formed by the surface of the recessed contact portion 25, while the groove portion 32 is formed by the surface of the recessed wiring portion 26. Although not shown, the hole 31 and the groove 32 are filled with an insulating film.

-Manufacturing method-
Next, a manufacturing method of the liquid crystal display device 1 including the wiring structure 10 will be described.

  The liquid crystal display device 1 is manufactured by bonding a TFT substrate 11 in which a plurality of TFTs 16 and a wiring structure 10 are formed on a glass substrate 15 to a counter substrate 12 through a liquid crystal layer 13.

  Since the manufacturing method according to the present invention is characterized in the process of manufacturing the TFT substrate 11, it will be described in detail below with reference to FIGS.

  First, the first film forming step is performed to form the semiconductor layer 17 as the first film on the glass substrate 15. The semiconductor layer 17 is patterned into an island shape by photolithography.

  Next, an insulating film forming step is performed to form an interlayer insulating film 23 on the glass substrate 15 so as to cover the semiconductor layer 17.

  Next, a patterning process is performed. First, as shown in FIG. 2, a resist mask 33 having a through hole 37 having the same shape as the contact hole 27 and a concave groove 38 having the same shape as the wiring groove 28 is not shown. It forms on the surface of the interlayer insulation film 23 using a mask. Then, photolithography is performed in which the interlayer insulating film 23 is half-exposed with the resist mask 33. As a result, as shown in FIG. 3, a contact hole 27 that penetrates the interlayer insulating film 23 and exposes a part of the semiconductor layer 17 is transferred to the interlayer insulating film 23, and the wiring groove 28 is formed in the interlayer insulating film. It is formed by transferring onto the surface of the film 23.

  Next, as shown in FIG. 4, a second film formation step is performed to expose the surface of the interlayer insulating film 23 including the inside of the contact hole 27 and the inside of the wiring groove 28 and the inside of the contact hole 27. A conductive material is deposited on the surface of the semiconductor layer 17 by sputtering. Thereby, the conductive film 24 as the second film is formed with a predetermined thickness along the surface of the interlayer insulating film 23 and the exposed surface of the semiconductor layer 17. As a result, the hole 31 is formed by the conductive film 24 in the contact hole 27, and the groove 32 is formed by the conductive film 24 in the wiring groove 28.

  Next, as shown in FIG. 5, a resist forming step is performed to fill the hole 31 and the groove 32 with the resist 40 and to conduct the resist 40 so as to close the opening ends of the hole 31 and the groove 32. It is formed on the film 24.

  Next, as shown in FIG. 6, an etch back process is performed to etch back the resist 40 until the conductive film 24 is exposed around the hole 31 and the groove 32. At this time, as shown in FIG. 6, the resist 40 is filled and remains inside the hole 31 and the groove 32.

  Next, as shown in FIG. 1, an etching process is performed, and the exposed conductive film 24 is removed by etching using the resist 40 as a mask. Thus, the conductive film 24 remaining in the contact hole 27 is used as the contact portion 25, while the conductive film 24 remaining in the wiring groove 28 is used as the wiring portion 26. Subsequently, after removing the resist 40 from the inside of the hole portion 31 and the groove portion 32, an insulating film (not shown) is filled in the inside of the hole portion 31 and the groove portion 32. Thus, the TFT substrate 11 including the wiring structure 10 is manufactured.

-Effect of Embodiment 1-
Therefore, according to the first embodiment, after the conductive film 24 is formed along the surface of the contact hole 27 and the wiring groove 28 formed in the interlayer insulating film 23 by half exposure, the resist 40 is formed on the conductive film 24. Since the conductive film 24 exposed around the contact hole 27 and the wiring groove 28 is etched and removed, the wiring portion 26 and the contact portion 25 are connected to each other even though the CMP method is not used. They can be formed simultaneously. As a result, the number of steps can be reduced, and the manufacturing cost can be reduced.

  In particular, according to the present embodiment, since the CMP method is not used, there is a remarkable effect that the wiring structure 10 can be formed with high accuracy even at a low cost even for a large-sized liquid crystal display device.

  Further, since the contact hole 27 and the wiring groove 28 are formed in a taper shape that extends in the direction opposite to the glass substrate 15, a conductive material is applied to the inner peripheral surface of the contact hole 27 and the inner side surface of the wiring groove 28. It can be deposited more reliably by sputtering.

<< Other Embodiments >>
The present invention may be configured as follows with respect to the first embodiment.

  In the first embodiment, the example in which the inner peripheral surface of the contact hole 27 is tapered has been described. However, at least a part of the inner peripheral surface of the contact hole 27 may be tapered. Also by this, sputtering film formation of the conductive film 24 can be preferably promoted. From the viewpoint of more effectively promoting the sputtering film formation, it is desirable that the entire inner peripheral surface of the contact hole 27 is tapered. Similarly, at least a part of the inner surface of the wiring groove 28 may be tapered.

  In the first embodiment, the example in which the first film is the semiconductor layer 17 has been described. However, the present invention is not limited thereto, and the wiring structure in which the first film is another conductive layer such as a metal layer is also provided. The same can be applied.

  Moreover, in the said Embodiment 1, although the liquid crystal display device 1 whose display medium layer is the liquid crystal layer 13 was mentioned as an example, this invention is not limited to this, For example, a display medium layer is an organic light emitting layer. The same applies to display devices such as organic EL display devices.

  As described above, the present invention is useful for a method for manufacturing a wiring structure, a display device, and a method for manufacturing the same, and particularly suitable for forming a wiring portion and a contact portion simultaneously without using the CMP method. ing.

FIG. 1 is an enlarged sectional view showing a sectional structure of a TFT substrate. FIG. 2 is a cross-sectional view showing a resist formed on the interlayer insulating film. FIG. 3 is a cross-sectional view showing an interlayer insulating film in which contact holes and wiring trenches are formed. FIG. 4 is a cross-sectional view showing a second film formed on the surface of an interlayer insulating film or the like. FIG. 5 is a cross-sectional view showing the resist formed on the second film. FIG. 6 is a cross-sectional view showing the second film partially exposed by etch back. FIG. 7 is a cross-sectional view illustrating a schematic configuration of the liquid crystal display device. FIG. 8 is a cross-sectional view showing a conventional interlayer insulating film in which connection holes and wiring grooves are formed. FIG. 9 is a cross-sectional view showing a conductive film formed by sputtering on a conventional interlayer insulating film. FIG. 10 is a cross-sectional view showing a conventional reflow-treated conductive film. FIG. 11 is a cross-sectional view showing a conductive film whose surface is polished by a conventional CMP method.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Liquid crystal display device 10 Wiring structure 11 TFT substrate (1st substrate)
12 Counter substrate (second substrate)
13 Liquid crystal layer (display medium layer)
15 Glass substrate (substrate)
16 TFT (switching element)
17 Semiconductor layer (first film)
19 Gate electrode 23 Interlayer insulating film 24 Conductive film (second film)
25 contact portion 26 wiring portion 27 contact hole 28 wiring groove 31 hole portion 32 groove portion 40 resist

Claims (16)

A first film forming step of forming a first film on the substrate;
An insulating film forming step of forming an interlayer insulating film on the substrate so as to cover the first film;
Forming a contact hole in the interlayer insulating film through the interlayer insulating film to expose a part of the first film, and forming a wiring groove on the surface of the interlayer insulating film;
A second film, which is a conductive film, is formed on the surface of the interlayer insulating film including the inside of the contact hole and the inside of the wiring groove, and the surface of the first film exposed inside the contact hole. A second film forming step of forming a hole by the second film in the contact hole and forming a groove by the second film in the wiring groove by forming each surface with a predetermined thickness;
A resist forming step of filling the hole and the groove with a resist and forming the resist on the second film so as to close the opening ends of the hole and the groove;
An etch back step of etching back the resist until the second film is exposed around the hole and the groove;
Etching to remove the exposed second film by etching, so that the second film remaining in the contact hole is used as a contact portion, and the second film remaining in the wiring trench is used as a wiring portion; A method for manufacturing a wiring structure, comprising: In the manufacturing method of the wiring structure according to claim 1,
In the patterning step, the contact hole and the wiring groove are formed by photolithography for half exposure of the interlayer insulating film. In the manufacturing method of the wiring structure according to claim 1,
A method for manufacturing a wiring structure, wherein the first film is a semiconductor layer. In the manufacturing method of the wiring structure according to claim 1,
The method of manufacturing a wiring structure according to claim 1, wherein at least a part of the inner peripheral surface of the contact hole is formed in a taper shape extending toward the side opposite to the substrate. In the manufacturing method of the wiring structure according to claim 1,
A method of manufacturing a wiring structure, wherein at least a part of the inner side surface of the wiring groove is formed in a tapered shape that extends toward the side opposite to the substrate. A method of manufacturing a display device by bonding a first substrate having a plurality of switching elements and wiring structures formed on a substrate to a second substrate via a display medium layer,
A first film forming step of forming a first film on the substrate;
An insulating film forming step of forming an interlayer insulating film on the substrate so as to cover the first film;
Forming a contact hole in the interlayer insulating film through the interlayer insulating film to expose a part of the first film, and forming a wiring groove on the surface of the interlayer insulating film;
A second film, which is a conductive film, is formed on the surface of the interlayer insulating film including the inside of the contact hole and the inside of the wiring groove, and the surface of the first film exposed inside the contact hole. A second film forming step of forming a hole by the second film in the contact hole and forming a groove by the second film in the wiring groove by forming each surface with a predetermined thickness;
A resist forming step of filling the hole and the groove with a resist and forming the resist on the second film so as to close the opening ends of the hole and the groove;
An etch back step of etching back the resist until the second film is exposed around the hole and the groove;
Etching to remove the exposed second film by etching, so that the second film remaining in the contact hole is used as a contact portion, and the second film remaining in the wiring trench is used as a wiring portion; A method for manufacturing a display device, comprising: In the manufacturing method of the display device according to claim 6,
In the patterning step, the contact hole and the wiring groove are formed by photolithography for half exposure of the interlayer insulating film. In the manufacturing method of the display device according to claim 6,
The method for manufacturing a display device, wherein the first film is a semiconductor layer. In the manufacturing method of the display device according to claim 6,
A method for manufacturing a display device, wherein at least a part of an inner peripheral surface of the contact hole is formed in a taper shape extending toward a side opposite to the substrate. In the manufacturing method of the display device according to claim 6,
A method of manufacturing a display device, wherein at least a part of the inner side surface of the wiring groove is formed in a tapered shape extending toward the opposite side of the substrate. In the manufacturing method of the display device according to claim 6,
The method for manufacturing a display device, wherein the display medium layer is a liquid crystal layer. A first substrate having a plurality of switching elements and a wiring structure formed on the substrate;
A second substrate disposed opposite the first substrate;
A display device comprising a display medium layer provided between the first substrate and the second substrate,
The first substrate is formed of a first film formed on the substrate, an interlayer insulating film covering the first film, and a recess recessed in the interlayer insulating film, and a conductive second film. A contact portion and a wiring portion,
The second film of the contact portion is formed on the inner peripheral surface of the contact hole formed through the interlayer insulating film so as to expose the first film and on the surface of the exposed first film. Is formed with a predetermined thickness along,
The display device according to claim 1, wherein the second film of the wiring portion is formed on the inner surface of the wiring groove formed in the interlayer insulating film with a predetermined thickness along the surface. The display device according to claim 12,
The display device, wherein the first film is a semiconductor layer. The display device according to claim 12,
At least a part of the inner peripheral surface of the contact hole is formed in a taper shape extending toward the side opposite to the substrate. The display device according to claim 12,
The display device according to claim 1, wherein at least a part of the inner surface of the wiring groove is formed in a taper shape extending toward the side opposite to the substrate. The display device according to claim 12,
The display device, wherein the display medium layer is a liquid crystal layer.

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