JP2009265575A - Driving circuit and method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a driving circuit and method of a display element having display memory property in which coloring and color erasing are switched over by potential difference of applied voltages. <P>SOLUTION: The driving circuit includes a display electrode driving circuit and an counter electrode driving circuit. The display electrode driving circuit selects either of a power supply voltage or a ground voltage based on a signal for selecting coloring or color erasing for each display element, and applies the selected voltage on a display electrode. The counter electrode driving circuit selects either the power supply voltage or the ground voltage, based on the signal for selecting coloring or color erasing for a segment display element of a display switching object, applies the selected voltage on the counter electrode of the segment display element of the display switching object, and applies a bias voltage Vb for maintaining a display state of the segment display element for the counter electrode of the segment display element other than the display switching object. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a driving circuit and a driving method for a display element having display memory characteristics, and more particularly to a driving circuit and a driving method for a display element having display memory characteristics for switching between coloring and decoloring depending on a potential difference between applied voltages.

  In recent years, display elements that have display memory properties such as electrochromic and cholesteric liquid crystal systems that switch between coloring and decoloring depending on the potential difference of the applied voltage, once applied to the colored or decolored state, are applied with voltage. The state can be maintained for a certain period without continuing. In addition, compared with conventional liquid crystal display elements such as LCDs, there are features such as high contrast, less viewing angle dependency, and light and thin characteristics, and applications such as electronic paper are expanding.

  In a conventional segment display element driving method using a display element having a display memory property that switches between coloring and decoloring according to a potential difference of applied voltage, the segment display element is composed of a column electrode (segment) and a row electrode (common). As a matrix configuration (XY coordinates) in the X direction and the Y direction, a voltage is applied to each electrode, and coloring and decoloring are performed on a desired portion.

  In addition, there is a technique in which a driving circuit using CMOS transistors is connected to column electrodes and row electrodes, and a coloring voltage and a decoloring voltage are applied to segment elements having arbitrary XY coordinates (see Patent Document 1). In this technique, after coloring and erasing, the operation of maintaining the display state using the memory property is performed by opening the row electrode and separating the circuit.

By the way, when the number of segment elements to be displayed is increased, the connection lines to the column electrodes and the row electrodes and the drive circuits for applying potentials to the column electrodes and the row electrodes are increased in accordance with the increase of the segment elements. Difficult due to restrictions on layout area and cost.
In view of this, it is conceivable to use a common connection line to the column electrodes of a plurality of segment elements and a drive circuit for applying a potential to the column electrodes.

  FIG. 7 is a schematic diagram showing an equivalent circuit showing an example at the time of matrix drive connection in which column electrodes are shared using the technique disclosed in Patent Document 1. In FIG. The display element is represented as a capacitor in an electrical equivalent circuit, and as shown in the figure, three column electrodes 91a, 92a, 93a and row electrodes 91b, 92b for selecting segment elements are arranged so as to cross each other. Six display elements 94 to 99 are arranged at the intersections.

  Each of the display elements 94 to 99 has the column electrodes 91a, 92a, 93b at a potential of + V volts, the row electrodes 91b, 92b at a potential of 0 V volts, and the display elements in the direction from the column electrodes to the row electrodes. When a voltage of + V volts is applied to, it is colored. Further, the display elements 94 to 99 are decolored when the potentials of the column electrodes 91a, 92a, 93a and the row electrodes 91b, 92b are switched and a voltage of + V volts is applied to the display elements in the direction from the row electrodes to the column electrodes. To do. Further, the threshold values of the coloring voltage and the decoloring voltage are approximately one half of V volts, although depending on the display element to be used.

  In the illustrated example, the column electrodes 91a and 92a are set to a potential of + V volts, the column electrodes 93a and the row electrodes 92b are set to a potential of 0 volts, and a voltage + V volts is applied to the display elements 97 and 98. The row electrode 91b is opened as a non-selected state. Thus, by applying a voltage to each row electrode, the display elements 97 and 98 are colored, and the operation | movement which hold | maintains the state of the display elements 94-96, 99 is intended.

  FIG. 8 is an equivalent circuit when a voltage is applied to the electrical equivalent circuit shown in FIG. As shown in the figure, a voltage of + V volts is applied to the display elements 97 and 98, while the display elements 94 to 96 connected to the row electrode 91b include the display element 94 and the display element 95, and the display element 96. Are connected in series, and the voltage divided by the capacitance ratio of the display elements 94 to 96 is generated in the row electrode 91b.

  At this time, the potential of the open row electrode 91b varies depending on the combination of voltages applied to the column electrodes 91a to 93a and the row electrodes 91b and 92b. For this reason, when the potential of the row electrode 91b exceeds the threshold voltage for coloring or decoloring, the display elements 94 to 96 are not set in the coloring operation (the setting operation is performed under the condition voltage condition). Hereinafter, there is a possibility that an abnormal erasing operation) or a non-setting erasing operation (hereinafter referred to as abnormal erasing) may occur.

  Further, FIG. 9 is a schematic diagram showing an internal configuration of a display device 900 as a specific example of the prior art. The display device 900 includes display electrode drive circuits 1a to 1g, counter electrode drive circuits 9a and 9b, a power supply terminal 6 for supplying a potential of + V volts, an open terminal 8 for opening, and 7-segment display elements 3 and 4. Have. The 7-segment display element 3 representing ten digits includes display electrodes 3a to 3g and a counter electrode 5a. The 7-segment display element 4 representing one digit includes display electrodes 4a to 4g and a counter electrode 5b. The display electrode drive circuits 1a to 1g have the same configuration.

  The 7-segment display element 3 includes seven display elements having a display memory property that switches between coloring and decoloring according to the potential difference of the applied voltage. Each display element includes display electrodes 3a to 3g and a counter electrode 5a. The 7-segment display element 3 applies a potential of + V volts to the display electrodes 3a to 3g, applies a potential of 0 V to the counter electrode 5a, and applies a voltage of + V volts from the counter electrode 5a to the display electrodes 3a to 3g. Colors when applied. In addition, the 7-segment display element 3 has polarity, and a potential of 0 V is applied to the display electrodes 3a to 3g, a potential of + V volts is applied to the counter electrode 5a, and the display electrodes 3a to 3g are connected to the counter electrode 5a. When a voltage of + V volts is applied in the direction, the color disappears. In addition, the 7-segment display element 3 has a memory property even if the voltage application is stopped after coloring or decoloring, and thus the display state can be maintained for a certain period.

  The 7-segment display element 4 has the same configuration as the 7-segment display element 3 and includes display electrodes 4a to 4g and a counter electrode 5b. The 7-segment display element 4 has the same conditions for coloring and decoloring.

  The display electrode drive circuits 1a to 1g select one of 0 volt and + V volt as the potential applied to the display electrode. The display electrode driving circuit 1a is connected in common to the display electrode 3a and the display electrode 4a via the segment line Seg (a), and applies the selected potential to the display electrodes 3a and 4a. The display electrode drive circuit 1b is connected in common to the display electrode 3b and the display electrode 4b via the segment line Seg (b), and applies the selected potential to the display electrodes 3b and 4b. The display electrode drive circuit 1c is connected in common to the display electrode 3c and the display electrode 4c via the segment line Seg (c), and applies the selected potential to the display electrodes 3c and 4c. The display electrode drive circuit 1d is connected in common to the display electrode 3d and the display electrode 4d via the segment line Seg (d), and applies the selected potential to the display electrodes 3d and 4d.

  The display electrode drive circuit 1e is connected in common to the display electrode 3e and the display electrode 4e via the segment line Seg (e), and applies the selected potential to the display electrodes 3e and 4e. The display electrode drive circuit 1f is commonly connected to the display electrode 3f and the display electrode 4f via the segment line Seg (f), and applies the selected potential to the display electrodes 3f and 4f. The display electrode drive circuit 1g is commonly connected to the display electrode 3g and the display electrode 4g via the segment line Seg (g), and applies the selected potential to the display electrodes 3g and 4g.

  The counter electrode drive circuits 9a and 9b select either one of 0 volts and + V volts as the potential to be applied to the counter electrodes, or no operation in the open state. .

  FIG. 10 is a time chart showing an example of an operation for displaying “86” on the display device 900. The horizontal axis direction represents time and operation, and the vertical axis direction represents the potential of each segment line and common line. The display operation is performed in the order of ten-digit coloring (b), ten-digit decoloring (b), one-digit coloring (c), and one-digit decoloring (d).

  First, in order to display “8” in the ten-digit coloring (A), the display electrode driving circuits 1 a to 1 g select + V volts by connecting to the power supply terminal 6, and the counter electrode driving circuit 9 a Select 0 volts by connecting to ground. As a result, a potential of + V volts and 0 volts are applied to the display electrodes 3a to 3g of all the display elements of the 7-segment display element 3, and a voltage of V volts is applied to the counter electrode 5a. As a result, the seven display elements of the 7-segment display element 3 are colored. At this time, the counter electrode drive circuit 9b selects open (high impedance) by connecting to the open terminal 8 in order to put the 7-segment display element 4 of one digit into a non-selected state.

  Next, in the 10-digit decoloring (b), the counter electrode drive circuit 9 a selects + V volts by connecting to the power supply terminal 6. At this time, a potential of + V volt and + V volt are applied to the display electrodes 3a to 3g of all the display elements of the 7-segment display element 3 and + V volt to the counter electrode 5a, and 0 volt is applied between the display electrodes 3a to 3g and the counter electrode 5a. Is applied. At this time, the seven display elements of the 7-segment display element 3 are not colored and are kept in a colored state because the voltage for coloring is set.

Subsequently, in order to display “6” in the color (c) of the first digit, the display electrode driving circuits 1 a and 1 c to 1 g select + V volts by connecting to the power supply terminal 6 to drive the display electrode. The circuit 1b selects 0 volts by connecting to the ground, and the counter electrode drive circuit 9b selects 0 volts by connecting to the ground. As a result, a potential of + V volts is applied to the display electrodes 4a, 4c to 4g excluding the display electrodes 4b of the 7-segment display element 4, and a potential of 0 volts is applied to the display electrodes 4b and the counter electrode 5b. As a result, a voltage of V volts is applied between the display electrodes 4a, 4c to 4g and the counter electrode 5b, and the six display elements other than the display electrode 4b of the 7-segment display element 4 are colored.
At this time, similarly to the 7-segment display element 4, a potential of + V volts is applied to the display electrodes 3a, 3c to 3g of the 7-segment display element 3. A potential of 0 volt is applied to the display electrode 3 b of the 7-segment display element 3.

  As the last operation, in the erasing of the first digit (d), the counter electrode drive circuit 9b changes the connection to the power supply terminal 6 to select + V volts. Thereby, a voltage of V volts is applied between the display electrode 4b of the 7-segment display element 4 and the counter electrode 5b, and the display element of the display electrode 4b is decolored. The 7-segment display element 4 of the first digit displays “6” by the operations (c) and (d).

  However, in the operations (c) and (d), an electrical equivalent circuit of the display element composed of the display electrodes 3a to 3g and the counter electrode 5a included in the ten-segment 7-segment display element 3 is illustrated in FIG. It becomes a circuit. The electrical equivalent circuit of the 7-segment display element 3 includes a capacitor C3a composed of the display electrode 3a and the counter electrode 5a, a capacitor C3a composed of the display electrode 3a and the counter electrode 5a, a display electrode 3b and the counter electrode 5a. Capacitor C3b composed of display electrode 3c and counter electrode 5a, capacitor C3d composed of display electrode 3d and counter electrode 5a, capacitor C3e composed of display electrode 3e and counter electrode 5a, and display electrode 3f The capacitor C3f is composed of the counter electrode 5a, and the capacitor C3g is composed of the display electrode 3g and the counter electrode 5a.

  The display electrode drive circuits 1a, 1c to 1g apply a potential of + V volts, the display electrode drive circuit 1b applies a potential of 0 volts, and the counter electrode drive circuit 9a does not apply a potential to the counter electrode 5a. Thereby, the capacitors C3a, C3c to C3g are connected in parallel between the power supply terminal 6 for supplying + V volts and the counter electrode 5a, and further, the capacitor C3b is connected between the counter electrode 5a and the ground, and the capacitor C3a , C3c to C3g and the capacitor C3b are expressed as a circuit connected in series via the counter electrode 5a.

  When the areas of the respective display elements are the same and the capacitances of the capacitors formed by the display elements are the same, the capacitors C3a, C3c to C3g have directions (coloring) from the counter electrode 5a to the display electrodes 3a, 3c to 3g. Direction), a voltage divided by 1/7 of + V volts is applied. On the other hand, a voltage divided by 6/7 of + V volts is applied to the capacitor 3b in the direction from the display electrode 3b to the counter electrode 5a (decoloring direction).

  At this time, abnormal decoloring occurs in which the display element corresponding to the colored display electrode 3b is decolored by the applied voltage divided by 6/7. Although an example in which abnormal decoloring occurs is shown, abnormal coloring similarly occurs depending on the combination of the display state of each display element and the potential selected by the display electrode driving circuits 1a to 1g.

FIG. 12 is a circuit diagram showing a general form of an equivalent circuit of the 7-segment display element 3 when the areas of the display elements are the same and the capacitances of the capacitors constituting the display elements are the same. The total capacitance of the display element (capacitor) to which + V volt is applied among the display electrodes 3a to 3g is represented by ΣCv, and the total capacitance of the display element to which 0 volt is applied among the display electrodes 3a to 3g is represented by ΣCg. Is shown.
The voltage V1 applied to the display element connected to the segment line to which + V volt is applied is + V × (ΣCg / (ΣCv + ΣCg)) volt in the direction from the counter electrode to the display electrode (coloring direction). The voltage V2 applied to the display element connected to the segment line to which 0 volt is applied is + V × (ΣCv / (ΣCv + ΣCg)) volt in the direction from the display electrode to the counter electrode (decoloring direction). is there.
Thus, when the counter electrode drive circuit 2a sets the output to a high impedance state, the potential of the counter electrode 5a changes depending on the potential applied to the segment line, and abnormal coloring or abnormal decoloring occurs. .
JP 54-83797 A

  As described above, a general example and a specific example have been described. However, a display element having a display memory property that switches between coloring and decoloring according to a potential difference between applied voltages, a plurality of methods are used by using the method disclosed in Patent Document 1. When the drive circuit and connection line for applying a voltage to the display electrode are made common to the segment elements and the voltage is applied in a time-sharing manner, abnormal decoloring and abnormal coloring occur.

  The present invention has been made to solve the above-described problems, and an object of the present invention is to provide a display element driving circuit and a driving method having a display memory property in which coloring and decoloring are switched by a potential difference between applied voltages. .

In order to solve the above problems, the present invention provides a plurality of display elements having display memory properties for switching between coloring and decoloring according to a potential difference of applied voltages, and a plurality of display electrodes for applying a voltage to each of the plurality of display elements. A plurality of segment display elements each having a common counter electrode for the plurality of display elements, the display electrodes corresponding to the respective segment display elements are connected in common, and one segment display among the plurality of segment display elements A drive circuit for the segment display element in a display device that applies a voltage sequentially in a time division manner to color and decolor the element,
A display electrode driving circuit that selects either the first voltage or the ground voltage based on a signal that determines whether each display element is colored or erased, and applies the selected voltage to the display electrode. And selecting one of the first voltage and the ground voltage based on a signal that determines whether the segment display element to be displayed is to be colored or erased, and selects the selected voltage to be the display switching target. For each of the plurality of segment display elements, a second voltage that is applied to the counter electrode of the segment display element and maintains the display state of the segment display element is applied to the counter electrode of the segment display element that is not subject to display switching. And a counter electrode driving circuit provided in the driving circuit.

  In the present invention, the first voltage is a power supply voltage supplied to the drive circuit, and the second voltage is obtained by stepping down the first voltage. It is a voltage.

  Further, the present invention is the invention described above, wherein the second voltage is higher than a voltage obtained by subtracting a decoloring operation threshold voltage when the display element performs a decoloring operation from the first voltage, and The display element has a voltage lower than a coloring operation threshold voltage when performing a coloring operation.

  According to the present invention, in the above-described invention, the display electrode driving circuit includes a first input terminal to which a signal for determining whether to color or decolor the display element is input, and the first input terminal to which the first electrode is applied. A voltage is supplied, a first PMOS transistor having a gate connected to the first input terminal, a drain connected to the drain of the first PMOS transistor, a source grounded, and a gate connected to the first input. A first NMOS transistor connected to a terminal; a drain of the first PMOS transistor; and a first output terminal connected to a point where the drain of the first NMOS transistor is connected. The first output terminal is connected to the display electrode.

  According to the present invention, in the above-described invention, the counter electrode drive circuit includes a second input terminal to which a signal for determining whether the segment display element is colored or decolored is input, and the segment display element. NAND of a third input terminal to which a signal for selecting whether or not to apply a voltage is input, a signal input from the second input terminal, and a signal input from the third input terminal A NOR gate that calculates a negative OR of a signal input from the second input terminal and a negative signal of the signal input from the third input terminal, and the source The first voltage is supplied, the second PMOS transistor whose gate is connected to the output of the NAND gate, and the drain are connected to the drain of the second PMOS transistor at the connection point, and the source is connected. A second NMOS transistor having a gate connected to the output of the NOR gate, a second voltage supplied to a source, a gate connected to the third input terminal, and a drain connected to the connection. A third PMOS transistor connected to a point; and a second output terminal connected to the second connection point, wherein the second output terminal is connected to the counter electrode. To do.

  According to the present invention, in the above-described invention, the counter electrode drive circuit includes a second input terminal to which a signal for determining whether the segment display element is colored or decolored is input, and the segment display element. NAND of a third input terminal to which a signal for selecting whether or not to apply a voltage is input, a signal input from the second input terminal, and a signal input from the third input terminal A NOR gate that calculates a negative OR of a signal input from the second input terminal and a negative signal of the signal input from the third input terminal, and the source The first voltage is supplied, the second PMOS transistor whose gate is connected to the output of the NAND gate, and the drain are connected to the drain of the second PMOS transistor at the connection point, and the source is connected. A second NMOS transistor having a gate connected to the output of the NOR gate, a first resistor having one end supplied with the first voltage and the other end connected to the connection point; A second resistor having one end grounded and the other end connected to the connection point; and a second output terminal connected to the connection point, wherein the second output terminal is the counter electrode It is connected to.

  Further, according to the present invention, in the above-described invention, a plurality of display elements having a display memory property for switching between coloring and decoloring according to a potential difference of applied voltages, and a plurality of display electrodes for applying a voltage to each of the plurality of display elements A plurality of segment display elements each having a common counter electrode for the plurality of display elements, the display electrodes corresponding to the respective segment display elements are connected in common, and one segment display among the plurality of segment display elements A method for driving the segment display element in a display device in which a voltage is applied to the elements in order and colored and decolored in order, wherein the display electrode driving circuit colors or decolors each of the display elements Selecting either one of the first voltage and the ground voltage based on the signal that determines the voltage, and applying the selected voltage to the display electrode; The electrode drive circuit selects one of the first voltage and the ground voltage based on a signal that determines whether the segment display element to be switched is colored or erased, and switches the selected voltage for display switching. Applying a second voltage that is applied to the counter electrode of the target segment display element and maintains the display state of the segment display element to the counter electrode of the segment display element that is not subject to display switching. This is a driving method characterized by this.

According to the present invention, the counter electrode driving circuit included in the driving circuit is configured to apply the second voltage to the counter electrode of the segment display element that is not subject to display switching. As a result, it is possible to avoid abnormal coloring and abnormal decoloring due to the application of the divided voltage based on the capacitance ratio when the display elements having capacitance are connected in series and in parallel.
In addition, the display electrode driving circuit for applying a voltage to the display electrode and the connection line for connecting the display electrode driving circuit and the display electrode can be shared, thereby reducing the mounting area of the display electrode driving circuit and the connection line. It is possible to reduce the production cost.

  According to the present invention, the second voltage used in the counter electrode drive circuit is configured to use a voltage obtained by stepping down the first voltage used by the drive circuit. Accordingly, since the driving circuit is driven by a single power source, it can be configured with a simple CMOS digital circuit, and design costs and manufacturing costs can be reduced.

  Hereinafter, a display device, a display electrode driving circuit, and a counter electrode driving circuit according to an embodiment of the present invention will be described with reference to the drawings.

  FIG. 1 is a schematic block diagram showing the internal configuration of the display device 100 according to the present embodiment. The display device 100 includes display electrode drive circuits 1a to 1g, counter electrode drive circuits 2a and 2b, a power supply terminal 6 for supplying a power supply voltage + V volt, a power supply terminal 7 for supplying a bias voltage + Vb volt, and a 7-segment display. Elements 3 and 4 are included. The 7-segment display element 3 represents ten digits, and the 7-segment display element 4 represents one digit. In the display device 100, the configuration other than the counter electrode drive circuits 2a and 2b and the power supply terminal 7 is the same as that of the display device 900 of the conventional example shown in FIG. The counter electrode drive circuits 2a and 2b and the power supply terminal 7 will be described. The counter electrode drive circuits 2a and 2b have the same configuration, and hereinafter, when one or both of the counter electrode drive circuits 2a and 2b are shown, they are referred to as the counter electrode drive circuit 2.

  The counter electrode drive circuits 2a and 2b select one of 0, + V (power supply potential), and + Vb volts as the potential applied to the counter electrode. The counter electrode driving circuit 2a applies the selected potential to the counter electrode 5a through the common line Com10. The counter electrode driving circuit 2b applies the selected potential to the counter electrode 5b through the common line Com1.

FIG. 2 is a diagram showing a possible range of a bias potential (bias voltage) of + Vb volts. The bias potential varies depending on the type of display element used for the 7-segment display elements 3 and 4 and the characteristics of the material. This bias potential is determined by measuring the coloring operation threshold voltage and the decoloring operation threshold voltage of the display elements used for the 7-segment display elements 3 and 4.
The coloring operation threshold voltage Von is a minimum potential when a potential of 0 V is applied to the counter electrode 5a and the display elements applied to the display electrodes 3a to 3g perform a coloring operation. The decoloring operation threshold Voff volt is a minimum potential when a potential of 0 volt is applied to the display electrodes 3a to 3g and the display element applied to the counter electrode 5a performs a decoloring operation.
As the bias potential Vb, a range shown by hatching, that is, a voltage not higher than Von volts and not lower than (+ V−Voff) volts is selected.

FIG. 3 is a circuit diagram showing a configuration example of the display electrode driving circuits 1a to 1g. The display electrode drive circuit 1 has an input terminal A, an output terminal B, a PMOS transistor 11 and an NMOS transistor 12. In the PMOS transistor 11, a power supply potential (+ V volts) is applied to the source, the drain is connected to the drain of the NMOS transistor 12, and the gate is connected to the input terminal A. In the NMOS transistor 12, a ground potential (0 volt) is applied to the source, and the gate is connected to the input terminal A. The output terminal B is connected to the drain of the PMOS transistor 11 and the drain of the NMOS transistor 12.
When the “H” (High: power supply potential) level signal is input from the input terminal A, the display electrode driving circuit 1 outputs a “L” (Low: 0 volt) level signal from the output terminal B. . Further, when an “L” level signal is input from the input terminal A, the display electrode drive circuit 1 outputs an “H” level signal from the output terminal B.

FIG. 4 is a circuit diagram illustrating a configuration example of the counter electrode drive circuit 2. The counter electrode drive circuit 2 includes an input terminal C, an output terminal D, a non-selection terminal E, a NAND gate 21, a NOR gate 22, PMOS transistors 23 and 25, and an NMOS transistor 24.
The NAND gate 21 calculates a negative logical product of the signals input from the input terminal C and the non-selection terminal E and outputs the result to the gate of the PMOS transistor 23. The NOR gate 22 receives a signal from the input terminal C, receives an inverted signal of the non-selection terminal E, calculates a negative logical sum of the two input signals, and outputs the result to the gate of the NMOS transistor 24.

The PMOS transistor 23 has a power supply potential (+ V volts) applied to the source, a drain connected to the connection point S 1, and a gate connected to the output of the NAND gate 21. In the NMOS transistor 24, the ground potential (0 volts) is applied to the source, the drain is connected to the connection point S1, and the gate is connected to the output of the NOR gate 22.
In the PMOS transistor 25, a bias potential (+ Vb volts) is applied to the source, the drain is connected to the connection point S1, and the gate is connected to the non-selection terminal E. The output terminal D is connected to the connection point S.

Next, the operation of the counter electrode drive circuit 2 will be described.
When an “L” level signal is input to the non-selection terminal E, the PMOS transistor 23 is turned off because the “H” level signal is input to the gate regardless of the signal input to the input terminal C. In the NMOS transistor 24, an “L” level signal is input to the gate, and the NMOS transistor 24 is turned off. When an “L” level signal is input to the non-selection terminal E, an “L” level signal is input to the gate of the PMOS transistor 25 and the PMOS transistor 25 is turned on. As a result, the potential of the connection point S1 becomes + Vb volts, and the potential of + Vb volts is output from the output terminal D.

  When an “H” level signal is input to the non-selected terminal E and an “L” level signal is input from the input terminal C, “H” is applied to the gate of the PMOS transistor 23 and the gate of the MOS transistor 24. ”Level signal is input. Only the NMOS transistor 24 is turned on, the potential of the connection point S1 becomes 0 volt, and the potential of 0 volt is output from the output terminal D.

  When an “H” level signal is input to the non-selected terminal E and an “H” level signal is input from the input terminal C, “L” is input to the gate of the PMOS transistor 23 and the gate of the NMOS transistor 24. A level signal is input. Only the PMOS transistor 23 is turned on, the potential of the connection point S1 becomes + V volts, and the potential of + V volts is output from the output terminal D.

FIG. 5 is a circuit diagram showing a different configuration example of the counter electrode driving circuit 2 and the counter electrode driving circuit 2A. The counter electrode drive circuit 2A includes an input terminal C, an output terminal D, a non-selection terminal E, a NAND gate 21, a NOR gate 22, a PMOS transistor 23, an NMOS transistor 24, a resistor 26, and a resistor 27.
The NAND gate 21 calculates a negative logical product of the signals input from the input terminal C and the non-selection terminal E and outputs the result to the gate of the PMOS transistor 23. The NOR gate 22 receives a signal from the input terminal C, receives an inverted signal of the non-selection terminal E, calculates a negative logical sum of the two input signals, and outputs the result to the gate of the NMOS transistor 24.

The PMOS transistor 23 has a power supply potential (+ V volts) applied to the source, a drain connected to the connection point S 1, and a gate connected to the output of the NAND gate 21. In the NMOS transistor 24, the ground potential (0 volts) is applied to the source, the drain is connected to the connection point S1, and the gate is connected to the output of the NOR gate 22.
The resistor 26 has one side applied with a power supply potential (+ V volts) and the other connected to the connection point S2. One of the resistors 27 is grounded and the other is connected to the connection point S2.

Next, the operation of the counter electrode drive circuit 2A will be described.
When an “L” level signal is input to the non-selection terminal E, an “H” level signal is input to the gate of the PMOS transistor 23 regardless of the signal input to the input terminal C. An “L” level signal is input to the gates of the first and second gates. As a result, the PMOS transistor 23 and the NMOS transistor 24 are turned off. At this time, the potential of the connection point S2 is a potential obtained by dividing + V volts by the ratio of the resistance values of the resistors 26 and 27. The resistance values of the resistors 26 and 27 are set in advance so that the divided voltage becomes Vb volts. As a result, the potential of the connection point S2 becomes + Vb volts, and the potential of + Vb volts is output from the output terminal D.

  When an “H” level signal is input to the non-selected terminal E and an “L” level signal is input from the input terminal C, “H” is applied to the gate of the PMOS transistor 23 and the gate of the MOS transistor 24. ”Level signal is input. Only the NMOS transistor 24 is turned on, the potential at the connection point S2 becomes 0 volts, and a potential of 0 volts is output from the output terminal D.

  When an “H” level signal is input to the non-selected terminal E and an “H” level signal is input from the input terminal C, “L” is input to the gate of the PMOS transistor 23 and the gate of the NMOS transistor 24. A level signal is input. Only the PMOS transistor 23 is turned on, the potential of the connection point S2 becomes + V volts, and the potential of + V volts is output from the output terminal D.

Next, FIG. 6 is a time chart showing an example of an operation for displaying “86” on the display device 100. The horizontal axis direction represents time and operation, and the vertical axis direction represents the potential of each segment line and common line. The display operation is performed in the order of ten-digit coloring (b), ten-digit decoloring (b), one-digit coloring (c), and one-digit decoloring (d).
The display electrode driving circuits 1a to 1g are configured by the display electrode driving circuit 1, and the counter electrode driving circuits 2a and 2b are configured by the counter electrode driving circuit 2 or the counter electrode driving circuit 2A. As the input signals to the display electrode driving circuits 1a to 1g and the input signals to the counter electrode driving circuits 2a and 2b, signals corresponding to the numbers to be displayed are input from the outside of the display device 100.

First, in order to display “8” in the ten-digit coloring (A), the display electrode driving circuits 1 a to 1 g receive an “L” level signal at the input terminal A, and + V volts from the output terminal B. Is output. In the counter electrode driving circuit 2a, an “H” level signal is input to the non-selection terminal E, an “L” level signal is input to the input terminal C, and a potential of 0 volt is output from the output terminal D. As a result, a potential of + V volts and 0 volts are applied to the display electrodes 3a to 3g of all the display elements of the 7-segment display element 3, and a voltage of V volts is applied to the counter electrode 5a. As a result, the seven display elements of the 7-segment display element 3 are colored.
At this time, in order to put the 7-segment display element 4 of one digit into a non-selected state, the counter electrode driving circuit 9b receives an “L” level signal at the non-selected terminal E and a potential of + Vb volts from the output terminal D. Is output.

  Next, in the 10-digit decoloring (b), the input signal to the input terminal C of the counter electrode drive circuit 2a changes, and the counter electrode drive circuit 2a receives an "H" level signal at the input terminal C. Then, a potential of + V volts is output from the output terminal D to the counter electrode 5a. At this time, since a potential of + V volt is applied to the display electrodes 3a to 3g, a voltage of 0 volt is applied between the display electrodes 3a to 3g and the counter electrode 5a. At this time, the seven display elements of the 7-segment display element 3 are not colored and are kept in a colored state because the voltage for coloring is set.

Subsequently, in order to display “6” in the color (c) of the first digit, the display electrode driving circuits 1a and 1c to 1g receive the “L” level signal at the input terminal A and the output terminal B. To + V volts is output to the display electrodes 4a, 4c to 4g. The display electrode drive circuit 1b receives an “H” level signal at the input terminal A and outputs a potential of 0 volt from the output terminal B to the display electrode 3b. In the counter electrode driving circuit 2b, an “H” level signal is input to the non-selection terminal E, an “L” level signal is input to the input terminal C, and a potential of 0 volt is output from the output terminal D to the counter electrode 5b. To do. As a result, a voltage of + V volts is applied between the display electrodes 4a, 4c to 4g of the 7-segment display element 4 and the counter electrode 5b, and the six display elements corresponding to the display electrodes 4a, 4c to 4g are colored. The
At this time, in order to put the ten-digit 7-segment display element 3 into a non-selected state, the counter electrode driving circuit 2a receives an “L” level signal at the non-selected terminal E and a potential of + Vb volts from the output terminal D. Is output.

As the last operation, the input signal to the input terminal C of the counter electrode drive circuit 2b changes in the one-digit decoloring (d), and the counter electrode drive circuit 2b receives a signal of “H” level at the input terminal C. , And a potential of + V volts is output from the output terminal D to the counter electrode 5b. As a result, a potential of 0 volts is applied to the display electrode 4b, a potential of + V volts is applied to the counter electrode 5b, and the display element corresponding to the display electrode 4b is decolored.
As described above, the 7-segment display element 4 of one digit displays “6” by the coloring / decoloring operations (C) and (D).

In operations (c) and (d), a potential of + Vb volts is applied to the counter electrode 5a of the 7-segment display element 3 from the output terminal D of the counter electrode drive circuit 2a. Thereby, the potential of the counter electrode 5a becomes constant at + Vb volts regardless of the potential applied to the segment lines by the display electrode driving circuits 1a to 1g. As a result, the 7-segment display element 3 can hold the display state without causing abnormal coloring or abnormal coloring.
As described above, the display state of the 7-segment display element other than the display state update target can be held by using the counter electrode driving circuit 2 or the counter electrode driving circuit 2A. Furthermore, the display can be changed by applying a voltage to the segment display elements 3 and 4 selected in a time division manner.

  In this embodiment, the display electrode driving circuit 1 and the counter electrode driving circuit 2 are used for the two 7-segment display elements 3 and 4. However, a dot display element in which display elements are arranged in a horizontal row is used. You may use for the display apparatus etc. of the dot matrix type combined in the vertical direction. Further, the order of the coloring operation and the decoloring operation and the operations (A) to (D) shown in FIG. 6 may be switched.

  In addition to the electrochromic display element, as a display element having a display memory property that switches between coloring and decoloring according to the potential difference of the applied voltage, an electrophoretic system that moves charged particles in a solvent, a cholesteric liquid crystal system, Alternatively, a display element to which a charged toner type display method, an electronic powder fluid method, or the like is applied may be used.

The first voltage described in the present invention corresponds to the power supply voltage (+ V volts), and the second voltage described in the present invention corresponds to the bias voltage (Vb volts).
The first input terminal according to the present invention corresponds to the input terminal A, the first output terminal according to the present invention corresponds to the output terminal B, and the first PMOS transistor according to the present invention. Corresponds to the PMOS transistor 11, and the first NMOS transistor described in the present invention corresponds to the NMOS transistor 12.

  Further, the second input terminal described in the present invention corresponds to the input terminal C, the third input terminal described in the present invention corresponds to the non-selection terminal E, and the second output terminal described in the present invention. The terminal corresponds to the output terminal D, the second PMOS transistor described in the present invention corresponds to the PMOS transistor 23, the second NMOS transistor described in the present invention corresponds to the NMOS transistor 24, and the present invention. The third PMOS transistor described in (1) corresponds to the PMOS transistor 25. Further, the connection point described in the present invention corresponds to the connection point S1 and the connection point S2, the first resistor described in the present invention corresponds to the resistor 26, and the second resistor described in the present invention is: This corresponds to the resistor 27.

It is the schematic which shows the internal structure of the display apparatus by this embodiment. It is a figure which shows the range which the value of the bias voltage Vb in the same embodiment can take. FIG. 3 is a circuit diagram showing a configuration of a display electrode drive circuit in the same embodiment. It is a circuit diagram which shows one structure of the counter electrode drive circuit in the embodiment. It is a circuit diagram which shows one different structure of the counter electrode drive circuit in the embodiment. 6 is a time chart showing an operation of displaying “86” on the display device in the embodiment. It is an equivalent circuit diagram at the time of matrix drive connection of the display element in the conventional example. It is an equivalent circuit diagram when a voltage is applied to the display element in the conventional example. It is the schematic which shows the internal block diagram of the display apparatus in a prior art example. It is a time chart which showed the operation | movement which displays "86" on the display apparatus in a prior art example. FIG. 10 is an equivalent circuit diagram of a display element with ten digits when a voltage is applied to one digit in a conventional example. It is the equivalent circuit diagram of the general form of the 7 segment display element in a prior art example.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Display electrode drive circuit, 1a ... Display electrode drive circuit, 1b ... Display electrode drive circuit 1c ... Display electrode drive circuit, 1d ... Display electrode drive circuit, 1e ... Display electrode drive circuit 1f ... Display electrode drive circuit, 1g ... Display Electrode drive circuit 2 ... counter electrode drive circuit, 2A ... counter electrode drive circuit,
2a ... counter electrode drive circuit, 2b ... counter electrode drive circuit 3 ... 7 segment display element, 3a ... display electrode, 3b ... display electrode, 3c ... display electrode 4 ... 7 segment display element, 4a ... display electrode, 4b ... display electrode 4c ... Display electrode 5a ... Counter electrode, 5b ... Counter electrode 6 ... Power supply terminal, 7 ... Power supply terminal, 8 ... Open terminal 9a ... Counter electrode drive circuit, 9b ... Counter electrode drive circuit 11 ... PMOS transistor, 12 ... NMOS transistor 21 ... NAND gate, 22 ... NOR gate, 23 ... PMOS transistor 24 ... NMOS transistor, 25 ... PMOS transistor,
26 ... resistor, 27 ... resistor A ... input terminal, B ... output terminal, C ... input terminal, D ... output terminal, E ... non-selection terminal

Claims (4)

A plurality of display elements having a display memory property for switching between coloring and decoloring according to a potential difference of applied voltages, a plurality of display electrodes for applying a voltage to each of the plurality of display elements, and a common electrode common to the plurality of display elements A plurality of segment display elements, and corresponding display electrodes of each of the segment display elements are connected in common, and one of the plurality of segment display elements is colored by sequentially applying a voltage in a time-sharing manner. And a drive circuit for the segment display element in the display device to be erased,
A display electrode driving circuit that selects either the first voltage or the ground voltage based on a signal that determines whether each display element is colored or erased, and applies the selected voltage to the display electrode. When,
Based on a signal that determines whether to color or decolor the segment display element to be switched, one of the first voltage and the ground voltage is selected, and the selected voltage is the segment display to be switched. Provided for each of the plurality of segment display elements, which is applied to the counter electrode of the element and applies a second voltage for maintaining the display state of the segment display element to the counter electrode of the segment display element that is not subject to display switching. A counter electrode driving circuit,
A drive circuit comprising: The first voltage is a power supply voltage supplied to the drive circuit;
The drive circuit according to claim 1, wherein the second voltage is a voltage obtained by stepping down the first voltage. The second voltage is higher than a voltage obtained by subtracting a decoloring operation threshold voltage when the display element performs a decoloring operation from the first voltage, and a coloring operation when the display element performs a coloring operation The drive circuit according to claim 1, wherein the drive circuit is a voltage lower than a threshold voltage. A plurality of display elements having a display memory property for switching between coloring and decoloring according to a potential difference of applied voltages, a plurality of display electrodes for applying a voltage to each of the plurality of display elements, and a common electrode common to the plurality of display elements A plurality of segment display elements, and corresponding display electrodes of each of the segment display elements are connected in common, and one segment display element among the plurality of segment display elements is colored by sequentially applying voltage in a time-sharing manner And a method for driving the segment display element in the display device to be erased,
The display electrode driving circuit selects one of the first voltage and the ground voltage based on a signal that determines whether each display element is colored or erased, and the selected voltage is selected for display switching. Applying to the display electrode of the segment display element;
The counter electrode drive circuit selects one of the first voltage and the ground voltage based on a signal that determines whether the segment display element to be switched is colored or decolored, and the selected voltage is opposed. Applying a second voltage that is applied to the electrode and maintains the display state of the segment display element to the counter electrode of the segment display element that is not subject to display switching;
A driving method characterized by comprising:

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