JP2009253365A - Phase control circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To output a phase difference signal of a pulse width corresponding to a phase difference regardless of the phase difference between a data signal and a clock signal. <P>SOLUTION: The phase control circuit comprises: a first holding means for inputting the data signals and inverted signals Y, holding the inverted signals Y at transition timing of the data signals and outputting signals X; a second holding means for inputting the clock signals and the signals X, holding the signals X at transition timing of the clock signals and outputting the signals Y; and a comparison means for inputting the signals X and the signals Y, generating the phase difference signals having the pulse width corresponding to the phase difference, and outputting them as the phase difference signals having the pulse width corresponding to the phase difference between the data signals and the clock signals. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a phase comparison circuit that compares phases of a data signal and a clock signal and outputs a phase difference signal having a pulse width corresponding to the phase difference.

  In order to receive data reliably in the digital data transmission system, it is necessary to synchronize between the clock of the receiving apparatus and the received data. When the operating clocks of the transmission system and the reception system are generated as designed, it is relatively easy to synchronize, but in fact, the exact same due to conditions such as manufacturing variations and temperature. It is difficult to obtain the clock frequency.

  On the other hand, digital data such as an NRZ signal to be transmitted includes frequency information of a clock used for generating the signal. Therefore, a CDR (Clock and Data Recovery) circuit that extracts a clock signal from the frequency information of the clock included in the data signal and identifies the data signal using the clock signal is used. In this CDR circuit, a phase comparison circuit for constantly comparing the extracted clock signal and data signal and detecting a phase difference is used.

  FIG. 6 shows a configuration example and an operation example of a conventional phase comparison circuit (Non-Patent Document 1). In the figure, a data signal and a clock signal are input to a D terminal and a CK terminal of a DFF (D flip-flop) 61, respectively, and a signal X obtained by capturing the data signal as a clock signal is output. The EXOR circuit 62 is configured to input the signal X and the data signal, take an exclusive OR, and output a phase difference signal between the data signal and the clock signal. In this configuration, if the phases of the data signal and the clock signal are appropriate, a phase difference signal having the same pulse width as that of the clock signal can be obtained as shown in FIG. 6 (2), but if the phase of the clock signal advances. As shown in FIG. 6 (3), when the pulse width of the phase difference signal is narrowed and the rising edges of the data signal and the clock signal are close to each other, the operation becomes unstable.

Therefore, a circuit has been proposed in which a half-rate clock signal is used for a data signal so that a phase difference signal having a wider pulse width can be obtained (Non-Patent Document 2).
C.HOGGE, "A Self Correcting Recovery Circuit", IEEE TRANSACTIONS ON ELECTRON DEVICES, Vol.ED-32, No.12, December 1985 Y.Ohtomo, et al., "A 12.5-Gb / s Parallel Phase Detection Clock and Data Recovery Circuit in 0.13-μm CMOS", IEEE JOURNAL OF SOLID-STATE CIRCUITS, Vol.41, No.9, September 2006

  When receiving burst data that requires phase synchronization for each reception, it is necessary to finish the phase synchronization processing in a short time. However, the conventional phase comparator circuit becomes unstable when the rising edge of the data signal and the rising edge of the clock signal are simultaneous or close to each other, and during that time, an inaccurate phase difference signal is output, and the phase synchronization is long before it becomes stable. Since it took time, it could not be used for phase synchronization of burst data.

  Note that this problem can be solved by using a clock signal faster than the data signal or a multiphase clock. However, it is difficult to generate and handle a clock signal that is faster than a data signal, and when a multi-phase clock is used, an increase in circuit complexity is inevitable.

  An object of the present invention is to provide a phase comparison circuit capable of outputting a phase difference signal having a pulse width corresponding to the phase difference regardless of the phase difference between the data signal and the clock signal.

  The phase comparison circuit of the present invention includes a first holding means for inputting a data signal and an inverted signal Y, holding the inverted signal Y at the transition timing of the data signal, and outputting a signal X; a clock signal and a signal X , A second holding means for holding the signal X at the transition timing of the clock signal and outputting the signal Y, and the phase difference signal having the pulse width corresponding to the phase difference by inputting the signal X and the signal Y And a comparison means for outputting as a phase difference signal having a pulse width corresponding to the phase difference between the data signal and the clock signal.

  The first holding unit may be a flip-flop that takes in the inverted signal Y at the transition timing of the data signal, and the second holding unit may be a flip-flop that takes in the signal X at the transition timing of the clock signal. The comparison means may be an EXOR circuit that takes an exclusive OR of the signal X and the signal Y and outputs a phase difference signal.

  The first holding means is a first flip-flop that takes in the inverted signal Y at the transition timing of the data signal, and the second holding means is a second flip-flop that takes in the signal X at the transition timing of the clock signal. And the comparison means takes the exclusive OR of the signal X and the signal Y and outputs a phase difference signal as a first EXOR circuit, and further includes a third flip-flop that takes in the signal Y at the transition timing of the clock signal. , An exclusive OR of the signal Y and the output Y ′ of the third flip-flop has a pulse width of one cycle of the clock signal at the timing when the phase difference signal is output, and the pulse width of the phase difference signal And a second EXOR circuit that outputs a reference signal that serves as a criterion for determining whether the data signal and the clock signal are synchronous or asynchronous.

  The present invention can generate a phase difference signal having a pulse width corresponding to the phase difference regardless of the phase relationship between the data signal and the clock signal. In particular, even if the rising edges of the data signal and the clock signal are the same or close to each other, the phase difference signal having the corresponding phase difference information can be generated without malfunction of the holding means (flip-flop).

  Furthermore, it is possible to generate a reference signal that is a criterion for determining whether the data signal and the clock signal are in a synchronous state or an asynchronous state, and to obtain a phase difference signal indicating synchronous or asynchronous (advanced phase or delayed phase).

(First embodiment)
FIG. 1 shows a first embodiment of the phase comparison circuit of the present invention. FIG. 2 shows an operation example of the first embodiment of the phase comparison circuit of the present invention.

  In FIG. 1, the phase comparison circuit according to this embodiment includes two DFFs (D flip-flops) 11, 12, an inverter 13, and an EXOR circuit 14. A data signal is input to the CK terminal of the DFF 11, a clock signal is input to the CK terminal of the DFF 12, an output X of the DFF 11 is input to the D terminal of the DFF 12, and an output Y of the DFF 12 is inverted by the inverter 13 and the D terminal of the DFF 11 To enter. Further, the output X of the DFF 11 and the output Y of the DFF 12 are input to the EXOR circuit 14, and a phase difference signal is output from the EXOR circuit 14.

  Here, FIG. 3 shows a configuration example and an operation example of a general frequency divider. The frequency divider has a configuration in which the output of the DFF 11 and the D terminal are connected via the inverter 13, and an output signal that changes from logic 0 to logic 1 and from logic 1 to logic 0 at the rising edge of the input signal IN of the CK terminal of the DFF 11. OUT is obtained.

  In the configuration of the first embodiment of the phase comparison circuit shown in FIG. 1, when the data signal and the clock signal are at the same rate, the relationship between the data signal and the output X of the DFF 11 is the input signal in the frequency divider of FIG. This corresponds to the relationship between IN and the output signal OUT. That is, as shown in FIG. 2, the output X of the DFF 11 is a signal having a half rate of the data signal that changes from logic 0 to logic 1 and from logic 1 to logic 0 at the rising edge of the data signal. The output Y of the DFF 12 is a signal obtained by taking the output X of the DFF 11 with a clock signal.

  Therefore, if the exclusive OR of the outputs X and Y is taken by the EXOR circuit 14, an output signal that changes from logic 0 to logic 1 at the rising edge of the data signal and changes from logic 1 to logic 0 at the rising edge of the clock signal is obtained. It is done. That is, this output signal becomes a signal having a pulse width from the rising edge of the data signal to the rising edge of the clock signal, and becomes a phase difference signal having a pulse width corresponding to the phase difference between the data signal and the clock signal.

  Here, even if the rising edge (falling edge) of the output X and the rising edge of the clock signal are at the same time or very close to each other, the output Y does not become the broken line shown in FIG. Change. Unlike the case where the conventional data signal is directly captured by the clock signal, the output X is half the rate of the data signal. Therefore, even when the data signal is captured by the next clock signal, the output X does not change and is captured correctly. Is possible. Thus, when the phase difference between the data signal and the clock signal is the same or close, the pulse width of the phase difference signal is secured for one period of the clock signal, and the phase difference always has a pulse width greater than a certain value. A signal will be output.

(Second Embodiment)
FIG. 4 shows a second embodiment of the phase comparison circuit of the present invention. FIG. 5 shows an operation example of the second embodiment of the phase comparison circuit of the present invention.

  In FIG. 4, the phase comparison circuit of the present embodiment has the same configuration as that of the first embodiment in the DFFs 11 and 12, the inverter 13, and the EXOR circuit 14, and further has a configuration in which a DFF 15 and an EXOR circuit 16 are added. The clock signal is input to the CK terminal of the DFF 15, the output Y of the DFF 12 is input to the D terminal of the DFF 15, the output Y of the DFF 12 and the output Y ′ of the DFF 15 are input to the EXOR circuit 16, and a reference signal is output from the EXOR circuit 16 To do.

  The output Y ′ of the DFF 15 is obtained by taking the output Y of the DFF 12 with a clock signal, and is a signal in which the output Y of the DFF 12 is shifted by exactly one clock. Therefore, the exclusive OR output of the output Y of the DFF 12 and the output Y ′ of the DFF 15 is generated every time the phase difference signal is output from the EXOR circuit 14 as shown in FIG. The reference signal has a pulse width of.

  Therefore, by comparing the pulse widths of the phase difference signal output from the EXOR circuit 14 and the reference signal output from the EXOR circuit 16 in the subsequent circuit (not shown), the data signal is compared with the clock signal. Thus, it is possible to determine a synchronous state and an asynchronous state (advanced phase, delayed phase) and to determine the phase difference between the data signal and the clock signal from the pulse width of the phase difference signal.

  In the time chart shown in FIG. 5, the delay time of each part, the rise time and the fall time of the pulse are omitted, but actually each has a finite time. By comparing the pulse widths of the phase difference signal and the reference signal in consideration of these, it is possible to determine whether the data signal is synchronized, advanced, or delayed with respect to the clock signal.

The figure which shows 1st Embodiment of the phase comparison circuit of this invention. The time chart which shows the operation example of 1st Embodiment of the phase comparison circuit of this invention. The figure which shows the structural example and operation example of a frequency divider. The figure which shows 2nd Embodiment of the phase comparison circuit of this invention. The time chart which shows the operation example of 2nd Embodiment of the phase comparison circuit of this invention. The figure which shows the structural example and operation example of the conventional phase comparison circuit.

Explanation of symbols

11, 12, 15, 61 DFF (D flip-flop)
13 Inverter 14, 16, 62 EXOR circuit (exclusive OR circuit)

Claims (4)

First holding means for inputting the data signal and the inverted signal Y, holding the inverted signal Y at the transition timing of the data signal, and outputting the signal X;
Second holding means for inputting a clock signal and the signal X, holding the signal X at a transition timing of the clock signal, and outputting the signal Y;
The signal X and the signal Y are input, a phase difference signal having a pulse width corresponding to the phase difference is generated, and output as a phase difference signal having a pulse width corresponding to the phase difference between the data signal and the clock signal A phase comparison circuit. The phase comparison circuit according to claim 1,
The first holding means is a flip-flop that takes in the inverted signal Y at the transition timing of the data signal,
The phase comparison circuit, wherein the second holding unit is a flip-flop that takes in the signal X at a transition timing of the clock signal. The phase comparison circuit according to claim 1,
The phase comparison circuit, wherein the comparison means is an EXOR circuit that takes an exclusive OR of the signal X and the signal Y and outputs the phase difference signal. The phase comparison circuit according to claim 1,
The first holding means is a first flip-flop that takes in the inverted signal Y at the transition timing of the data signal,
The second holding means is a second flip-flop that takes in the signal X at a transition timing of the clock signal,
The comparison means is a first EXOR circuit that takes an exclusive OR of the signal X and the signal Y and outputs the phase difference signal;
further,
A third flip-flop that captures the signal Y at the transition timing of the clock signal;
An exclusive OR of the signal Y and the output Y ′ of the third flip-flop is obtained, and the phase difference signal has a pulse width corresponding to one cycle of the clock signal at the timing when the phase difference signal is output. A phase comparison circuit comprising: a second EXOR circuit that outputs a reference signal that is used as a determination criterion for a synchronous state or an asynchronous state of the data signal and the clock signal by comparison with a pulse width of the data signal.

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