JP2009253180A5 - - Google Patents
Download PDFInfo
- Publication number
- JP2009253180A5 JP2009253180A5 JP2008102089A JP2008102089A JP2009253180A5 JP 2009253180 A5 JP2009253180 A5 JP 2009253180A5 JP 2008102089 A JP2008102089 A JP 2008102089A JP 2008102089 A JP2008102089 A JP 2008102089A JP 2009253180 A5 JP2009253180 A5 JP 2009253180A5
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- forming
- region
- semiconductor layer
- single crystal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Claims (8)
前記単結晶半導体基板にイオンを照射して脆化領域を形成する工程と、Irradiating the single crystal semiconductor substrate with ions to form an embrittled region;
前記脆化領域を形成した後に前記第1絶縁膜上に導電膜を形成する工程と、Forming a conductive film on the first insulating film after forming the embrittled region;
前記導電膜上にレジストを形成する工程と、Forming a resist on the conductive film;
前記レジストをマスクとして前記導電膜をエッチングして所定の形状に加工された導電層を形成する工程と、Etching the conductive film using the resist as a mask to form a conductive layer processed into a predetermined shape;
前記第1絶縁膜及び前記レジスト上に前記導電層よりも膜厚が大きい第2絶縁膜を形成する工程と、Forming a second insulating film having a thickness larger than that of the conductive layer on the first insulating film and the resist;
前記レジストを除去するとともに、前記レジスト上の前記第2絶縁膜をリフトオフ法により除去する工程と、Removing the resist and removing the second insulating film on the resist by a lift-off method;
前記第2絶縁膜及び前記導電層上に第3絶縁膜を形成する工程と、Forming a third insulating film on the second insulating film and the conductive layer;
前記導電層と重なる領域の前記第3絶縁膜と、支持基板との間に隙間が形成されるように前記単結晶半導体基板と前記支持基板とを貼り合わせる工程と、Bonding the single crystal semiconductor substrate and the support substrate so that a gap is formed between the third insulating film in a region overlapping the conductive layer and the support substrate;
加熱処理を行い、前記脆化領域に沿って前記単結晶半導体基板を分離することにより、前記支持基板上に半導体層を形成する工程と、を有する半導体装置の作製方法。Forming a semiconductor layer over the supporting substrate by performing heat treatment and separating the single crystal semiconductor substrate along the embrittled region.
前記単結晶半導体基板にイオンを照射して脆化領域を形成する工程と、Irradiating the single crystal semiconductor substrate with ions to form an embrittled region;
前記脆化領域を形成した後に前記第1絶縁膜上に導電膜を形成する工程と、Forming a conductive film on the first insulating film after forming the embrittled region;
前記導電膜上にレジストを形成する工程と、Forming a resist on the conductive film;
前記レジストをマスクとして前記導電膜をエッチングして第1ゲート電極となる導電層を形成する工程と、Etching the conductive film using the resist as a mask to form a conductive layer to be a first gate electrode;
前記第1絶縁膜及び前記レジスト上に前記導電層よりも膜厚が大きい第2絶縁膜を形成する工程と、Forming a second insulating film having a thickness larger than that of the conductive layer on the first insulating film and the resist;
前記レジストを除去するとともに、前記レジスト上の前記第2絶縁膜をリフトオフ法により除去する工程と、Removing the resist and removing the second insulating film on the resist by a lift-off method;
前記第2絶縁膜及び前記導電層上に第3絶縁膜を形成する工程と、Forming a third insulating film on the second insulating film and the conductive layer;
前記導電層と重なる領域の前記第3絶縁膜と、支持基板との間に隙間が形成されるように前記単結晶半導体基板と前記支持基板とを貼り合わせる工程と、Bonding the single crystal semiconductor substrate and the support substrate so that a gap is formed between the third insulating film in a region overlapping the conductive layer and the support substrate;
加熱処理を行い、前記脆化領域に沿って前記単結晶半導体基板を分離することにより、前記支持基板上に半導体層を形成する工程と、Forming a semiconductor layer over the support substrate by performing heat treatment and separating the single crystal semiconductor substrate along the embrittled region;
前記半導体層をエッチングして島状半導体層を形成する工程と、Etching the semiconductor layer to form an island-shaped semiconductor layer;
前記島状半導体層に一導電型を付与する不純物を添加してソース領域及びドレイン領域を形成する工程と、Adding an impurity imparting one conductivity type to the island-shaped semiconductor layer to form a source region and a drain region;
前記島状半導体層上に第2ゲート絶縁膜となる第4絶縁膜を形成する工程と、Forming a fourth insulating film to be a second gate insulating film on the island-shaped semiconductor layer;
前記第4絶縁膜上に第2ゲート電極を形成する工程と、を有する半導体装置の作製方法。Forming a second gate electrode over the fourth insulating film.
前記半導体層をエッチングして島状半導体層を形成する工程と、Etching the semiconductor layer to form an island-shaped semiconductor layer;
前記島状半導体層に一導電型を付与する不純物を添加してソース領域及びドレイン領域を形成する工程と、Adding an impurity imparting one conductivity type to the island-shaped semiconductor layer to form a source region and a drain region;
前記ソース領域上にソース電極と、前記ドレイン領域上にドレイン電極とを形成する工程と、Forming a source electrode on the source region and a drain electrode on the drain region;
前記ソース電極と前記ドレイン電極の間の露出する前記島状半導体層表面に対しドライエッチング処理を行う工程と、を有する半導体装置の作製方法。Performing a dry etching process on the exposed surface of the island-shaped semiconductor layer between the source electrode and the drain electrode.
前記島状半導体層の上面形状は、前記ソース領域または前記ドレイン領域の一方が他方を囲む形状である半導体装置の作製方法。The top surface shape of the island-shaped semiconductor layer is a method for manufacturing a semiconductor device in which one of the source region and the drain region surrounds the other.
前記半導体層表面にエッチング処理をして前記半導体層表面の凹凸または欠陥を低減した後に前記半導体層表面にレーザ光を照射して前記半導体層を平坦化する工程を有する半導体装置の作製方法。A method for manufacturing a semiconductor device, comprising: etching a surface of the semiconductor layer to reduce irregularities or defects on the surface of the semiconductor layer and then irradiating the surface of the semiconductor layer with a laser beam to planarize the semiconductor layer.
前記隙間は前記単結晶半導体基板の面積の50%以下である半導体装置の作製方法。The method for manufacturing a semiconductor device, wherein the gap is 50% or less of the area of the single crystal semiconductor substrate.
前記脆化領域を形成する工程において、前記単結晶半導体基板にハロゲンガス又はハロゲン化合物ガスを用いてイオンを照射し、次いで水素ガスを含むガスを用いてイオンを照射して前記脆化領域を形成する半導体装置の作製方法。In the step of forming the embrittled region, the single crystal semiconductor substrate is irradiated with ions using a halogen gas or a halogen compound gas, and then irradiated with ions using a gas containing hydrogen gas to form the embrittled region. A method for manufacturing a semiconductor device.
前記支持基板上に前記半導体層を形成する工程において、前記単結晶半導体基板と前記支持基板との貼り合わせ領域にマイクロ波を照射して接合強度を高めた後に前記加熱処理を行い前記脆化領域に沿って前記単結晶半導体基板を分離する半導体装置の作製方法。In the step of forming the semiconductor layer over the supporting substrate, the embrittlement region is formed by irradiating microwaves to the bonding region between the single crystal semiconductor substrate and the supporting substrate to increase the bonding strength and then performing the heat treatment. A method for manufacturing a semiconductor device in which the single crystal semiconductor substrate is separated along a line.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2008102089A JP5284669B2 (en) | 2008-04-10 | 2008-04-10 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2008102089A JP5284669B2 (en) | 2008-04-10 | 2008-04-10 | Method for manufacturing semiconductor device |
Publications (3)
Publication Number | Publication Date |
---|---|
JP2009253180A JP2009253180A (en) | 2009-10-29 |
JP2009253180A5 true JP2009253180A5 (en) | 2011-04-14 |
JP5284669B2 JP5284669B2 (en) | 2013-09-11 |
Family
ID=41313561
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2008102089A Expired - Fee Related JP5284669B2 (en) | 2008-04-10 | 2008-04-10 | Method for manufacturing semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP5284669B2 (en) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR102250803B1 (en) | 2009-12-04 | 2021-05-11 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | Semiconductor device |
US8431994B2 (en) * | 2010-03-16 | 2013-04-30 | International Business Machines Corporation | Thin-BOX metal backgate extremely thin SOI device |
KR101981808B1 (en) * | 2010-12-28 | 2019-08-28 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | Semiconductor device and method for manufacturing the same |
JP2019032557A (en) * | 2018-11-06 | 2019-02-28 | 株式会社ジャパンディスプレイ | Display device |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH1145862A (en) * | 1997-07-24 | 1999-02-16 | Denso Corp | Manufacture of semiconductor substrate |
JP2000106333A (en) * | 1998-09-29 | 2000-04-11 | Sony Corp | Manufacture of semiconductor substrate having soi structure and manufacture of semiconductor device |
JP2002057309A (en) * | 2000-08-08 | 2002-02-22 | Sony Corp | Method of forming soi substrate |
JP4837240B2 (en) * | 2002-09-25 | 2011-12-14 | シャープ株式会社 | Semiconductor device |
KR100879047B1 (en) * | 2005-03-25 | 2009-01-15 | 샤프 가부시키가이샤 | Semiconductor device and method for manufacturing same |
-
2008
- 2008-04-10 JP JP2008102089A patent/JP5284669B2/en not_active Expired - Fee Related
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP2013102154A5 (en) | Method for manufacturing semiconductor device | |
JP2009135473A5 (en) | ||
JP2009135464A5 (en) | ||
JP2009260295A5 (en) | Method of manufacturing semiconductor substrate | |
JP2013153156A5 (en) | ||
JP2010093240A5 (en) | ||
JP2016021559A5 (en) | Semiconductor device and manufacturing method of semiconductor device | |
JP2010135771A5 (en) | ||
JP2013016862A5 (en) | ||
JP2012023356A5 (en) | ||
JP2009278073A5 (en) | ||
JP2010080947A5 (en) | Method for manufacturing semiconductor device | |
JP2010056542A5 (en) | ||
JP2009027156A5 (en) | ||
JP2013042125A5 (en) | ||
JP2008177553A5 (en) | ||
JP2015135953A5 (en) | ||
JP2012069935A5 (en) | Method for manufacturing semiconductor device | |
JP2013016785A5 (en) | ||
JP2009278075A5 (en) | ||
JP2010034523A5 (en) | ||
JP2009135454A5 (en) | ||
JP2012054540A5 (en) | Method of manufacturing SOI substrate | |
JP2016066792A5 (en) | ||
JP2015073092A5 (en) | Method for manufacturing semiconductor device |