JP2009239728A - Decoding method and decoder of unorganized folded-in code using sum-product algorithm - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an encoding method and an encoder of an unorganized folded-in code of using SPA, speeding up encoding processing, by improving an encoding characteristic. <P>SOLUTION: In this encoding method and the encoder of the unorganized folded-in code of using Sum-Product algorithm SPA, a parity bit SPA encoding part 4 encodes a parity bit by SPA encoding using a parity inspection expression including only the parity bit. An information bit SPA encoding part 5 encodes an information bit by hard determination encoding or the SPA encoding by using the parity inspection expression including an encoding result (an ex-post value of the parity bit) and the information bit. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a decoding method for unorganized convolutional codes using a Sum-Product algorithm, and more particularly to a decoding method and a decoder for improving decoding characteristics.

Soft input / soft output (SISO) decoding of convolutional codes is used for decoding turbo codes and serial concatenated codes.
It can also be used for turbo equalization when a convolutional code is used. A modified BCJR (Bahl-Cocke-Jeinek-Raviv) algorithm or the like is used as the SISO decoding algorithm for this convolutional code, but there is a problem that the processing amount is large.

On the other hand, it is known that Sum-Product Algorithm (SPA) used for decoding of low-density parity-check (LDPC) code attracting attention in recent years has a small amount of processing and is suitable for parallel processing. Yes.
Therefore, if this decoding algorithm can be applied to a convolutional code, an increase in speed of SISO decoding can be expected.

As related prior art, there is International Publication WO 2004/107585 (Patent Document 1).
Patent Document 1 discloses a decoding method in the case of decoding code data encoded with a linear code on ring R. However, Patent Document 1 does not provide SPA decoding of unorganized convolutional codes.

Non-patent documents 1 to 4 shown below will be briefly described.
Non-Patent Document 1 is a technique applicable only to QLI (Quick-Look-In) codes. For example, since the code of the wireless LAN standard is not a QLI code, this method cannot be used.
In Non-Patent Document 2, the decoding method of the convolutional code by the Sum-Product Algorithm is merely an interpretation of the conventional decoding method (BCJR) as SPA, and speeding up of the decoding process by SPA cannot be realized.
Non-Patent Document 3 and Non-Patent Document 4 deal with the problem of constructing a convolutional code with good SPA decoding characteristics. Therefore, the SPA decoding characteristics of a predetermined convolutional code (for example, a code determined by the wireless LAN standard) cannot be improved.

International Publication WO2004 / 107585 M.R.Zahabi, V. Meghdadi, J.-P. Cances, "Analogue decoding of tail-biting convolutional codes based on Tanner graph," Electronics Letters, vol.42, no.20, pp.1167-1169, 2006. Frank R. Kschischang, Brendan J. Frey, Hans-Andrea Loeliger, Factor Graphs and the Sum-Product Algorithm, IEEE Trans. Inform. Theory, pp. 498.519, 2001 A. J. Flstrom and K. S. Zigangirov, Time-varying periodic convolutional codes with low-density parity-check matrix, IEEE Trans. Inform. Theory, vol. 45, no. 6, pp. 2181.2191, Sep. 1999. Z. Chen and S. Bates, Construction of low-density parity-check convolutional codes through progressive edge-growth, IEEE Commun. Lett.vol.9, no.12, pp.1058.1060, Dec. 2005.

  However, the conventional technique has a problem in that when performing SPA decoding with a convolutional code of the wireless LAN standard, the decoding characteristics cannot be improved and the decoding process cannot be speeded up.

  Specifically, the SPA decoding method for the convolutional code has been introduced in Non-Patent Document 2 so far. In this method, the state of the convolutional code is hidden variables, the code bit is visible variables, the code trellis is represented by a Wiberg-type Tanner graph, and SPA is executed on the Tanner graph.

  The SPA in this case is completely the same as the BCJR algorithm. This is merely an interpretation of BCJR as SPA, and speeding up of decoding processing by SPA cannot be realized. To avoid confusion, this method is simply called BCJR, not SPA.

  In the present invention, a parity check matrix of a convolutional code is expressed in a Tanner graph, and the SPA decoding method on that is handled. This is different from the above-described approach in which the code trellis is a Tanner graph, and is the same approach as the LDPC code in which the parity check matrix is a Tanner graph. In the case of this method, speeding up of the decoding process can be expected.

  In the present invention, first, the problem of setting a target convolutional code and improving the SPA decoding characteristics using the parity check matrix is dealt with.

  Non-Patent Documents 3 and 4 deal with the problem of searching for a convolutional code with good SPA decoding characteristics, and are different from the present invention. In these methods, the target convolutional code is set first, and the SPA decoding characteristics for the code cannot be improved.

  Therefore, the SPA decoding characteristics of the convolutional code adopted in the wireless LAN standard cannot be improved. On the other hand, the present invention can improve the SPA decoding characteristics of the convolutional code adopted in the wireless LAN standard.

  The present invention proposes a method of decoding a convolutional code adopted in the wireless LAN standards (IEEE 802.11a) and (IEEE 802.11n) using SPA. The parity check matrix of this code is represented by a Tanner graph, and SPA decoding is performed on the graph. However, a decoding characteristic that can simply use this method cannot be obtained. Here, the cause is clarified and a characteristic improvement plan is proposed.

  The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a decoding method and decoder for an unstructured convolutional code using SPA that can improve decoding characteristics and speed up decoding processing.

  The present invention for solving the problems of the conventional example described above is a decoding method of an unorganized convolutional code using the Sum-Product algorithm (SPA), in which a parity including only parity bits is used as the first decoding process. Parity bit decoding is performed by SPA decoding using a check equation, and information bits are decoded by hard decision decoding or SPA decoding using a parity check equation including the decoding result and information bits as a second decoding process. It is characterized by that.

  According to the present invention, in the decoding method, in the first decoding process, SPA decoding is repeated until the parity check equation is satisfied or a preset maximum number of repetitions is reached, and a posterior value of the parity bit is output as a decoding result. It is characterized by that.

  The present invention is characterized in that, in the above decoding method, in the second decoding process, the posterior value of the parity bit obtained in the first decoding process is used as the initial value of the logarithmic probability ratio of the variable node.

  The present invention is characterized in that, in the decoding method, in the second decoding process, the parity check expression includes one information bit, and hard decision decoding or SPA decoding is performed only once.

  The present invention is characterized in that, in the above decoding method, SPA decoding is performed using a parity check equation having a long constraint length in the first decoding process.

  The present invention is a decoder for an unorganized convolutional code using the Sum-Product algorithm (SPA), and performs first decoding of parity bits by SPA decoding using a parity check expression including only parity bits. It has a processing unit and a second decoding processing unit for decoding information bits by hard decision decoding or SPA decoding using a parity check expression including the decoding result and information bits.

  According to the present invention, in the decoder, the first decoding processing unit repeats SPA decoding until the parity check equation is satisfied or a preset maximum number of repetitions is reached, and outputs a posterior value of the parity bit as a decoding result Then, the second decoding processing unit uses the posterior value of the parity bit obtained by the first decoding processing unit as the initial value of the logarithmic probability ratio of the variable node, and the parity check expression includes one information bit, The decision decoding or SPA decoding is performed only once.

  The present invention is characterized in that, in the above decoder, the first decoding processing unit performs SPA decoding using a parity check equation having a long constraint length.

  According to the present invention, there is provided a decoding method for a non-organizational convolutional code using a Sum-Product algorithm (SPA), in which a parity is obtained by SPA decoding using a parity check expression including only parity bits as a first decoding process. Bit decoding is performed, and as a second decoding process, information bits are decoded by hard decision decoding or SPA decoding using a parity check expression including the decoding result and information bits, and the decoding characteristics are improved. This has the effect of speeding up the decoding process.

  According to the present invention, as the first decoding process, the above-described decoding method that performs SPA decoding using a parity check equation having a long constraint length is used, so that the SPA decoding characteristics of parity bits can be further improved.

  According to the present invention, a decoder for an unorganized convolutional code using the Sum-Product algorithm (SPA), in which the first decoding processing unit performs parity by SPA decoding using a parity check expression including only parity bits. Bit decoding is performed, and the second decoding processing unit performs decoding of information bits by hard decision decoding or SPA decoding using a parity check expression including the decoding result and information bits, thereby improving decoding characteristics. This has the effect of speeding up the decoding process.

Embodiments of the present invention will be described with reference to the drawings.
[Outline of the embodiment]
In the decoding method of the unorganized convolutional code according to the embodiment of the present invention, SPA decoding is performed first, parity bits are decoded by SPA decoding using a parity check expression including only parity bits, and secondly The result and the parity check expression including one information bit are used to perform two-stage decoding, in which information bits are decoded by hard decision decoding or SPA decoding, thereby improving the decoding characteristics, The decoding process can be speeded up.

[Constitution]
A convolutional code decoder (present decoder) according to an embodiment of the present invention is realized by, for example, an LSI (Large Scale Integrated Circuit), an FPGA (Filed Programmable Gate Array), a DSP (Digital Signal Processor), or the like. It is.
The functional configuration of this decoder will be described later.

[SUM-PRODUCT ALGORITHM]
The Sum-Product Algorithm is an algorithm that repeats message exchanges along the branches of the Tanner graph. The Tanner graph is a bipartite graph representing a parity check matrix. The graph includes variable nodes corresponding to code bits and check nodes corresponding to code parity check expressions. Here, a log probability ratio (LLR) is used as the message. The processing is as shown in equation (1).

  n represents a variable node number, and m represents a check node number. Um, n represents a message sent from the check node m to the variable node n. Vm, n represents a message sent from the variable node n to the check node m. N (m) represents a set of variable nodes adjacent to the check node m. The processing of the variable node is as shown in equation (2).

  M (n) represents a set of check nodes adjacent to the variable node n. λn is an LLR obtained from the received signal and is called a channel value. In the case of an additive white Gaussian noise (AWGN) communication path, it is obtained by equation (3).

yn represents a received signal corresponding to the variable node n, and σ ² represents noise variance. Since the initial value of Um, n is Um, n = 0, the initial value of Vm, n is the communication path value Vm, n = λn.
The LLR corresponding to each variable node is called a posterior value Λn. The a posteriori value Λn is calculated by equation (4).

[SUM-PRODUCT decoding of standard convolutional codes]
[Encoder for unorganized convolutional code: Fig. 1]
FIG. 1 shows an encoder of an unorganized convolutional code adopted in IEEE802.11a and IEEE802.11n. FIG. 1 is a schematic configuration diagram of an encoder of an unorganized convolutional code.
As shown in FIG. 1, the encoder includes a plurality of delay circuits (D) 1-1 to 1-6, a first adder 2, and a second adder 3.

The plurality of delay circuits are connected in multiple stages in series, and the information bit x is input.
The first and second adders 2 and 3 branch out the outputs from the delay circuit, add them, and output parity bits p ₁ and p ₂ .

[Standard convolution decoding]
Here, the information bit sequence _{x 0, x 1, ...,} x k, ..., represent the x _N-1, the parity bit sequence _{1 p 1,0, p 1,1, ...} , p 1, k, ..., p _{1, N-1} and represents, represents a parity bit sequence _{2 p 2,0, p 2,1, ...} , p 2, k, ..., and p _{2, N-1.} Also, the polynomials X (D), P ₁ (D), and P ₂ (D) of each series are expressed as in equations (5), (6), and (7).

  At this time, the relationship between the information bits and the parity bits is expressed as in equations (8) to (11).

For simplicity, X (D), P ₁ (D), and P ₂ (D) may be expressed as X, P ₁ , and P ₂ .

[Parity check polynomial of convolutional code]
Consider the parity check polynomial of the current code. Expressions (12) and (13) are obtained from Expressions (8) and (9).

  The left side of the above equation is defined as a parity check polynomial, and equations (14) and (15) are obtained.

Then, (X, P ₁ , P ₂ ) satisfying the following expressions (16) and (17) is a code word.

When the maximum degree of the coefficient term of the parity check polynomial is ν-1, ν is defined as the constraint length of the parity check expression. For example, since the coefficient term of H _{org, 1} (X, P ₁ ) is {G ₁ (D), 1}, the maximum order ν−1 is the maximum order ν−1 = 6 of G ₁ (D). .

Therefore, the constraint length of H _{org, 1} (X, P ₁ ) is ν = 7. Similarly, the constraint length of H _{org, 2} (X, P ₂ ) is ν = 7. This is consistent with the encoder constraint length ν = 7. Hereinafter, the constraint length of the encoder is defined as the original constraint length and is represented by the symbol K.

[Parity check matrix of standard convolutional code]
From equations (12) and (13), it can be seen that the parity check equation at time k is given by the following equations (18) and (19).

Here, a vector v composed of information bits x and parity bits p ₁ and p ₂ is considered. The vector v is expressed by Expression (20).

  The parity check matrix H is obtained as a 2N × 3N matrix H as shown in Equation (21).

  Here, k that satisfies 0 ≦ k ≦ N−1 is considered. The k-th line of Expression (21) is expressed by Expression (18). In addition, the k + N-th row in Expression (21) is expressed by Expression (19).

[Simulation conditions: Fig. 6]
Simulation conditions are shown in FIG. 6 (TABLE1). FIG. 6 is a diagram showing simulation conditions.
When the decoding result satisfies the parity check expression, the SPA decoding is set to end. Even when the parity check equation is not satisfied, the SPA decoding is set to end when the number of decoding times reaches the preset maximum number of repetitions.

[Simulation result: Fig. 2]
The simulation result is shown in FIG. FIG. 2 is a diagram illustrating a simulation result. For comparison, the decoding result by BCJR is also shown. It can be seen that at Eb / No = 5.0 [dB], BCJR is BER = 6 × 10 ⁻⁷ , whereas the SPA decoding characteristic is BER = 4 × 10 ⁻¹ . Thus, it can be seen that the SPA decoding characteristics are very poor.

[Discussion]
Consider the cause of the very poor SPA decoding characteristics. As shown in FIG. 1, the current encoder is a non-systematic encoder, and no information bit is directly transmitted (a puncture bit). Therefore, since there is no received signal corresponding to the information bit, the channel value is 0.

  Two or more information bit nodes are connected to each check node. This can be seen from equations (18) and (19). A variable x representing information bits includes at least 2 bits in each parity check. Since the communication channel value corresponding to this is 0, no increase in reliability can be obtained by the processing of the check node no matter how many times the processing is repeated. This is apparent when looking at equation (1). Therefore, it is considered that good decoding characteristics cannot be obtained by this method.

[Proposed method (1)]
[Decoding of parity bits]
The reason why the reliability is not updated by the check node processing is that it includes two or more information bits (puncture bits). Therefore, it is proposed that the equations (8) to (11) are modified so as not to include information bits.
When Expression (22) is obtained from Expression (8) and substituted into Expression (9), Expressions (23) and (24) are obtained.

  It can be seen that the check node does not include information bits (puncture bits). Therefore, it can be expected that the reliability is updated in the processing of the check node.

In this method, the reliability is updated only for the parity bits p ₁ and p _{2, and the} reliability related to the information bits is not updated. That is, the information bits are not decoded. Next, consider a method of decoding information bits.

[Decoding information bits]
[Decoding method of information bits (1)]
Equations (8) and (9) can be transformed as equations (25) and (26).

If P ₁ and P ₂ are hard-decision-decoded, the information bit X can be hard-decision-decoded using any of the above equations. Looking at equation (25), it can be seen that decoding of the information bit X can be realized using a recursive convolutional encoder with P ₁ as input and X as output.

Therefore, a 1-bit error of the parity bit P ₁ may propagate over a wide range. For this reason, it is expected that good decoding characteristics cannot be obtained. The same applies to equation (26).

[Decoding method of information bits (2)]
The above-described method is a method of decoding the information bit X using either P ₁ or P ₂ . For this reason, it is considered that a recursive convolutional encoder is required. Here, consider decoding information bit X using both P ₁ and P ₂ . That is, consider the decoding of the information bit X according to equation (27).

  Substituting equations (8) and (9) into equation (27) yields equations (28) and (29).

That is, it is understood that G _{info, 1} (D) and G _{info, 2} (D) that satisfy Equation (30) may be obtained.

Since G ₁ (D) and G ₂ (D) that are the objects are relatively prime, there exists G _{info, 1} (D), G _{info, 2} (D) that satisfies Expression (30). It can be determined by the extended Euclidean algorithm. The obtained G _{info, 1} (D) and G _{info, 2} (D) are expressed by equations (31) and (32).

If P ₁ and P ₂ are hard-decided, information bit X can be hard-decided using equation (27). From the equations (27), (31), and (32), it can be seen that the decoding of the information bit X can be realized using a non-recursive convolutional encoder having P ₁ and P ₂ as inputs and X as an output. In this case, an error of one bit of the parity bits P ₁ and P ₂ propagates only in a finite range, so that it is expected that good error characteristics can be obtained.
It is also possible to SPA-decode information bit X using equation (27) as a parity check equation.

[Parity check formula and decoding method of proposed method (1)]
Consider the parity check equation of the proposed method (1). Expressions (33) and (34) are obtained from Expressions (24) and (27). Expressions (35) and (36) define the left side of this expression as a parity check expression.

Then, (X, P ₁ , P ₂ ) satisfying the following expressions (37) and (38) is a code word.

The constraint length of H _p1,1 (P ₁ , P ₂ ) is ν = 7 and is equal to the original constraint length K. The constraint length of H _p1,2 (X, P ₁ , P ₂ ) is ν = 5.

[Decoding method of proposed method (1)]
SPA decoding is performed as follows.
SPA decoding is performed using H _p1,1 (P ₁ , P ₂ ) as a parity check polynomial. The SPA is repeated until the parity check expression is satisfied or the maximum number of repetitions is reached. Thereby, the a posteriori values of the parity bits P ₁ and P ₂ are obtained.

Next, the obtained posterior values of the parity bits P ₁ and P ₂ are set as the initial value of the LLR of the variable node. The information bit X is decoded by performing SPA decoding with H _p1,2 (X, P ₁ , P ₂ ) as a parity check polynomial only once.

[Configuration of Decoder: Fig. 3]
A functional configuration of the decoder according to the embodiment of the present invention will be described with reference to FIG. FIG. 3 is a functional block diagram of the decoder.
As shown in FIG. 3, the decoder includes a parity bit SPA decoding unit 4 that performs SPA decoding on parity bits and an information bit SPA decoding unit 5 that decodes information bits.

The parity bit SPA decoding unit (first decoding processing unit) 4 inputs the parity bits P ₁ and P ₂ , or until the parity check expression of only the parity bits is satisfied or at a preset maximum number of repetitions SPA decoding is repeatedly performed until the value reaches the posterior value of the parity bits P ₁ and P ₂ .

The information bit SPA decoding unit (second decoding processing unit) 5 uses the posterior values of the parity bits P ₁ and P ₂ calculated by the parity bit SPA decoding unit 4 as the initial value of the LLR of the conversion node, SPA decoding with a parity check polynomial including bits is performed only once to decode information bits.

[Result: Fig. 4]
The simulation conditions are the same as in FIG. The simulation results are shown in FIG. FIG. 4 is a diagram illustrating a simulation result of the proposed method 1.
It can be seen that at E _b / E _o = 5.0 [dB], the conventional SPA has BER = 4 × 10 ⁻¹ , whereas the proposed method (1) has BER = 6 × 10 ^−4. . Thus, it can be seen that the SPA decoding characteristics can be greatly improved by the proposed method (1).

It can be seen that at BER = 10 ⁻⁵ , the decoding characteristic of the information bit of the proposed method (1) is inferior by 0.2 [dB] than the decoding characteristic of the parity bit. In the proposed method (1), it is considered that the information bit X is decoded using the decoding result of the parity bits P ₁ and P ₂ .

It can also be seen that at BER = 10 ⁻⁵ , the difference between the BCJR characteristics and the information bit characteristics of the proposed method (1) is 2.2 [dB]. Thus, since the difference with BCJR was large, it was thought that the further characteristic improvement was required.

[Proposed method (2) (LCL-PCE)]
Proposed method (1) performs SPA decoding of parity bits and SPA decoding of information bits using the result. That is, the decoding characteristics of information bits depend on the decoding characteristics of parity bits. Therefore, in order to improve the decoding characteristics of information bits, it is considered necessary to improve the decoding characteristics of parity bits.

[Decoding using a long constraint length (LCL) parity check expression]
Non-Patent Document 5 proposes a SPA decoding characteristic improving method for systematic convolutional codes. In this method, SPA decoding is performed using a parity check polynomial having a constraint length longer than the original constraint length K. Here, the method is applied to improve the SPA decoding characteristics of parity bits.
Now, in order to improve the SPA decoding characteristics of parity bits by the proposed method (1), a parity check equation (LCL-PCE) with a long constraint length equivalent to the parity check polynomial H _p1,1 (P ₁ , P ₂ ) is used. To perform SPA decoding. Here, the following LCL-PCE was used.

The constraint length of H _{LC, 1} (P ₁ , P ₂ ) is ν = 14, which is twice the original constraint length K = 7.

[Decoding method of proposed method (2)]
SPA decoding is performed as follows.
First, SPA decoding is performed using H _{LC, 1} (P ₁ , P ₂ ) as a parity check polynomial. The SPA is repeated until the parity check expression is satisfied or the maximum number of repetitions is reached. Thereby, the a posteriori values of the parity bits P ₁ and P ₂ are obtained.

Second, the obtained posterior values of the parity bits P ₁ and P ₂ are used as the initial value of the LLR of the variable node. The information bit X is decoded by performing SPA decoding with H _p1,1 (P ₁ , P ₂ ) as a parity check polynomial only once.

[Result: Fig. 5]
The simulation conditions are the same as in FIG. The simulation result is shown in FIG. FIG. 5 is a diagram illustrating a simulation result of the proposed method 2.
From FIG. 5, it can be seen that at BER = 10 ⁻⁵ , the SPA decoding characteristic of the parity bit of the proposed method (2) is improved by 1.2 [dB] than that of the proposed method (1).

It can also be seen that at BER = 10 ⁻⁵ , the SPA decoding characteristic of the information bits of the proposed method (2) is improved by 1.5 [dB] compared to that of the proposed method (1). This is an effect using a parity check polynomial having a long constraint length.

Further, FIG. 5 shows that the difference between the BCJR characteristic and the characteristic of the proposed method (2) is 0.7 [dB] at BER = 10 ⁻⁵ . From this, it is understood that the characteristic close to BCJR can be obtained by the proposed method (2).

[Processing amount: FIGS. 7 and 8]
The amount of decoding processing of the proposed method (2) is shown in FIG. 7 (TABLE II). FIG. 7 is a diagram illustrating the amount of decoding processing in Proposed Method 2. The number of special operations in the table represents the number of tanh (•) and tanh ⁻¹ (•). The BCJR decoding processing amount is shown in FIG. 8 (TABLE III). FIG. 8 is a diagram illustrating the amount of BCJR decoding processing. The number of special operations in the table represents the number of exp (•) and log (•). FIG. 7 and FIG. 8 show calculation fees necessary for decoding one code sequence once. Here, one code sequence is a sequence obtained by encoding the number of information bits N = 1030 including the termination bits.

  Comparing FIG. 7 and FIG. 8, it can be seen that the processing amount of the proposed method (2) is 0.29 times the processing amount of BCJR. Thus, the processing amount of the proposed method (2) is significantly smaller than that of BCJR.

Next, the processing amount is evaluated in consideration of the number of repetitions of the proposed method (2). At E _b / E _o = 6.0 [dB], the average number of repetitions of the proposed method (2) was 1.3. Considering this, the processing amount of the proposed method (2) is 0.34 times the processing amount of BCJR (note that only parity bit decoding is repeated). Even in consideration of the number of repetitions, the processing amount of the proposed method (2) is smaller than the processing amount of BCJR.

[Conclusion]
The Sum-Product Algorithm (SPA) is simple in processing and suitable for parallel processing, so high-speed decoding processing can be expected. Here, a method of decoding a convolutional code adopted in the wireless LAN standard (IEEE 802.11a) using SPA is proposed. Decoding characteristics that can simply apply SPA to this code cannot be obtained. It has been clarified that the first cause is that a received signal corresponding to the information bit cannot be obtained.

Thus, a method has been proposed in which only the parity bits are first subjected to SPA decoding, and the obtained result is further subjected to SPA decoding to decode information bits (proposed method (1)).
At BER = 10 ⁻⁵ , the difference between the BCJR characteristics and the information bit characteristics of the proposed method (1) was 2.2 [dB]. Therefore, in order to further improve the decoding characteristics, it has been proposed to perform SPA decoding using a parity check equation with a long constraint length (proposed method (2)).

At BER = 10 ⁻⁵ , the SPA decoding characteristic of the information bits of the proposed method (2) is improved by 1.5 [dB] than that of the proposed method (1). At BER = 10 ⁻⁵ , the difference between the BCJR characteristics and the proposed method (2) was 0.7 [dB]. It was shown that characteristics similar to BCJR can be obtained by the proposed method (2).

  INDUSTRIAL APPLICABILITY The present invention is suitable for a decoding method and a decoder for an unstructured convolutional code using SPA that can improve decoding characteristics and speed up decoding processing.

It is a schematic block diagram of the encoder of a non-systematic convolutional code. It is a figure which shows a simulation result. It is a functional block diagram of a decoder. It is a figure which shows the simulation result of the proposal method 1. It is a figure which shows the simulation result of the proposal method 2. It is a figure which shows simulation conditions. It is a figure which shows the decoding processing amount of the proposal method 2. FIG. It is a figure which shows the decoding processing amount of BCJR.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Delay circuit, 2 ... 1st adder, 3 ... 2nd adder, 4 ... Parity bit SPA decoding part, 5 ... Information bit SPA decoding part

Claims (8)

A decoding method of unorganized convolutional code using Sum-Product algorithm (SPA),
As a first decoding process, parity bits are decoded by SPA decoding using a parity check expression including only parity bits,
A decoding method characterized by decoding information bits by hard decision decoding or SPA decoding using a parity check expression including the decoding result and information bits as a second decoding process.   2. The first decoding process, wherein the SPA decoding is repeated until the parity check equation is satisfied or a preset maximum number of repetitions is reached, and a posterior value of the parity bit is output as a decoding result. Decryption method.   3. The decoding method according to claim 2, wherein, as the second decoding process, the posterior value of the parity bit obtained in the first decoding process is used as an initial value of the logarithmic probability ratio of the variable node.   4. The decoding method according to claim 1, wherein, as the second decoding process, the parity check expression includes one information bit, and hard decision decoding or SPA decoding is performed only once.   5. The decoding method according to claim 1, wherein SPA decoding is performed using a parity check expression having a long constraint length as the first decoding process. A decoder for unorganized convolutional codes using the Sum-Product algorithm (SPA),
A first decoding processing unit for decoding parity bits by SPA decoding using a parity check expression including only parity bits;
A decoder comprising: a second decoding processing unit that decodes information bits by hard decision decoding or SPA decoding using a parity check expression including the decoding result and information bits. The first decoding processing unit repeats SPA decoding until the parity check equation is satisfied or a preset maximum number of repetitions is reached, and outputs a posterior value of the parity bit as a decoding result,
The second decoding processing unit uses the posterior value of the parity bit obtained by the first decoding processing unit as the initial value of the logarithmic probability ratio of the variable node, the parity check expression includes one information bit, and hard decision decoding The decoder according to claim 6, wherein the SPA decoding is performed only once.   The decoding method according to claim 6 or 7, wherein the first decoding processing unit performs SPA decoding using a parity check equation having a long constraint length.

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