JP2009238783A - Method for manufacturing semiconductor substrate, semiconductor substrate, light-emitting element and electronic element - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor substrate capable of manufacturing a semiconductor substrate having no mismatch in symmetry of crystals at high throughput and low cost, and to provide a semiconductor substrate, a light-emitting element and an electronic element. <P>SOLUTION: A Si substrate is used, thereby remarkably reducing a manufacturing cost compared to the case where a sapphire substrate or a SiC substrate is used. A group XIII nitride is grown not on a (100) plane of a conventional Si substrate but on a (110) surface of the Si substrate, thereby solving the mismatch in symmetry of crystals. Further, since the group XIII nitride is grown by a pulse sputter deposition method, semiconductor devices can be manufactured even on a substrate with a large area of ≥12 inch at high throughput. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a semiconductor substrate, a semiconductor substrate, a light emitting element, and an electronic element.

  Elements such as short-wavelength LEDs and lasers using PN junctions of AlN, GaN, InN, and their mixed crystal phases, which are 13 nitrides, have been widely used so far. However, these devices have been manufactured by using a low-throughput metal organic chemical vapor deposition method (MOCVD method) on a sapphire or SiC substrate having a diameter of 4 inches or less, which is expensive and has many defects.

  On the other hand, the Si substrate is inexpensive and of high quality, and a substrate having a diameter of 12 inches can be obtained stably. Further, by using the Si substrate, it is possible to manufacture an optoelectronic integrated circuit by mixing Si integrated circuits and nitride compound semiconductor elements on one chip. For this reason, many research institutions have developed technology for forming a group 13 nitride semiconductor layer on a Si substrate.

  It has been difficult to grow a hexagonal nitride semiconductor single crystal on the (100) plane on which a normal Si device is fabricated because of crystal symmetry mismatch. In addition, the generation of cracks due to mismatches in the thermal expansion coefficients and lattice constants of Si and Group 13 nitrides has been a serious problem.

Also, from the viewpoint of crystal symmetry, the Si (111) plane has usually been used when growing group 13 nitrides on Si. However, even if a MOS element is formed on the (111) plane, the performance of the MOS element is lowered, making it difficult to manufacture an optoelectronic element. In recent years, there has been a report that a high-quality MOS device can also be fabricated for Si (110) (see Non-Patent Document 1, for example). If a group 13 nitride can be grown on the (110) plane, a high-performance optoelectronic device can be manufactured.
http://techon.nikkeibp.co.jp/article/NEWS/20061213/125395/

  However, there is no report that a group 13 nitride is grown on the (110) plane of Si on which a circuit is formed, and realization of such a semiconductor substrate is required. Moreover, it is preferable that it can be manufactured with high throughput in industrial use.

  In view of the circumstances as described above, an object of the present invention is to provide a semiconductor substrate manufacturing method, a semiconductor substrate, a light emitting element, and an electronic device capable of manufacturing a semiconductor substrate having no crystal symmetry mismatch at high throughput and low cost. It is to provide an element.

  In order to achieve the above object, a method for manufacturing a semiconductor substrate according to the present invention is characterized in that a semiconductor layer containing a group 13 nitride is formed on a (110) surface of a Si substrate by a pulse sputter deposition method.

  According to the present invention, by using the Si substrate, the manufacturing cost can be significantly reduced as compared with the case of using the sapphire substrate or the SiC substrate. Further, by growing group 13 nitride on the (110) plane of the Si substrate instead of the (100) plane of the conventional Si substrate, the crystal symmetry mismatch can be eliminated. Furthermore, since the group 13 nitride is grown by the pulse sputter deposition method, it can be manufactured even on a substrate having a large area of, for example, 12 inches or more, and can be manufactured with high throughput.

The semiconductor substrate manufacturing method is characterized in that a circuit is formed on a (110) surface of the Si substrate, and the semiconductor layer is formed after the circuit is formed.
In general, when a group 13 nitride is grown by MOCVD or MOVPE, it is necessary to grow at a high temperature of 1150 ° C. or higher, for example. On the other hand, in the case of an electronic circuit such as a MOS transistor, the function of the circuit formed on the Si substrate is impaired when the temperature is 1000 ° C. or higher. In other circuits, the function is likely to be impaired at the high temperature. Therefore, it is difficult to grow group 13 nitride directly on the Si substrate on which the circuit is formed.

  On the other hand, when the group 13 nitride is grown by the pulse sputter deposition method, the mixed crystal of the group 13 nitride and the group 13 nitride can be grown even at a temperature of 950 ° C. or lower, for example, about 300 ° C. to 700 ° C. It is possible to grow directly on the Si substrate without impairing the function of the circuit. Therefore, in the present invention, a circuit is formed on the (110) plane of the Si substrate, and the semiconductor layer is formed by the pulse sputter deposition method after the circuit is formed. Thereby, for example, the formation of the circuit and the formation of the semiconductor layer can be incorporated into a series of manufacturing steps of the Si substrate. In addition, the semiconductor substrate can be manufactured without greatly changing the conventional manufacturing process of the Si substrate.

In the semiconductor substrate manufacturing method, the group 13 nitride includes at least one of AlN, GaN, and InN.
According to the present invention, since the group 13 nitride includes at least one of AlN, GaN, and InN, a semiconductor substrate having high electrical characteristics and optical characteristics can be obtained.

The semiconductor substrate manufacturing method is characterized in that the semiconductor layer containing Si is formed on a (110) plane of a Si substrate.
According to the present invention, since the semiconductor layer containing Si, which is the same element as that constituting the substrate, is formed on the (110) plane of the Si substrate, the (110) plane of the Si substrate, the semiconductor layer, The lattice mismatch between can be made smaller.

In the semiconductor substrate manufacturing method, a first semiconductor layer containing at least one of HfN and ZrN is formed on the (110) surface of the Si substrate by a pulse sputtering deposition method, and a group 13 is formed on the first semiconductor layer. A second semiconductor layer of nitride is formed.
According to the present invention, the first semiconductor layer containing at least one of HfN and ZrN is formed on the (110) surface of the Si substrate by pulse sputter deposition, and the group 13 nitride first layer is formed on the first semiconductor layer. Since the two semiconductor layers are formed, the first semiconductor layer functions as a reflective layer of the second semiconductor layer. Thereby, a semiconductor substrate having high optical characteristics can be obtained.

  A semiconductor substrate according to the present invention includes: a Si substrate having a circuit on a (110) plane; and a semiconductor layer provided on the (110) plane of the Si substrate and including a group 13 nitride. To do.

  According to the present invention, since the Si substrate provided with the circuit on the (110) plane and the semiconductor layer including the group 13 nitride provided on the (110) plane of the Si substrate are provided, A high-performance semiconductor substrate having high characteristics and optical characteristics can be obtained.

In the semiconductor substrate, the group 13 nitride includes at least one of AlN, GaN, and InN.
According to the present invention, since the group 13 nitride includes at least one of AlN, GaN, and InN, a semiconductor substrate having high electrical characteristics and optical characteristics can be obtained.

In the semiconductor substrate described above, the semiconductor layer contains Si.
According to the present invention, since the semiconductor layer contains Si, which is the same element as that constituting the substrate, the lattice mismatch between the (110) plane of the Si substrate and the semiconductor layer is further reduced. be able to.

The semiconductor substrate is provided on the (110) plane of the Si substrate, and is provided on the first semiconductor layer including a first semiconductor layer including at least one of HfN and ZrN that is a group 13 nitride, And a second semiconductor layer including a group 13 nitride second semiconductor layer.
According to the present invention, the first semiconductor layer including at least one of HfN and ZrN which is a group 13 nitride provided on the (110) plane of the Si substrate, and the group 13 nitride provided on the first semiconductor layer. Since the second semiconductor layer including the second semiconductor layer is provided, the first semiconductor layer functions as a light reflecting layer. Thereby, a semiconductor substrate having high optical characteristics can be obtained.

In the semiconductor substrate, the circuit is an electronic circuit including a MOS transistor.
According to the present invention, since the circuit is an electronic circuit including a MOS transistor, a semiconductor substrate having high performance and high versatility can be obtained.

A light-emitting element according to the present invention includes the above-described semiconductor substrate.
According to the present invention, since the semiconductor substrate having high electrical characteristics and optical characteristics is provided, a light emitting element having high light emission characteristics can be obtained.

An electronic device according to the present invention includes the semiconductor substrate described above.
According to the present invention, since a semiconductor substrate having high electrical characteristics and optical characteristics is provided, a high-performance electronic device can be obtained.

  According to the present invention, by using the Si substrate, the manufacturing cost can be significantly reduced as compared with the case of using the sapphire substrate or the SiC substrate. Further, by growing group 13 nitride on the (110) plane of the Si substrate instead of the (100) plane of the conventional Si substrate, the crystal symmetry mismatch can be eliminated. Furthermore, since the group 13 nitride is grown by the pulse sputter deposition method, it can be manufactured even on a substrate having a large area of, for example, 12 inches or more, and can be manufactured with high throughput.

Embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a diagram showing a configuration of a semiconductor substrate 1 according to the present embodiment.
As shown in the figure, the semiconductor substrate 1 is provided with a buffer layer 3 on a Si substrate 2, a functional layer 4 is laminated on the buffer layer 3, and the Si substrate 2 and the functional layer 4 are connected by a wiring 5. It has been configured. The semiconductor substrate 1 is used for light emitting elements such as LEDs and semiconductor lasers, and electronic elements such as semiconductor chips.

  In the Si substrate 2, an electronic circuit 2a such as a MOS transistor is formed on the (110) plane shown in the upper side of the drawing. The circuit 2a is partially exposed, and the wiring 5 is connected to the exposed portion of the circuit 2a.

  The buffer layer 3 is a semiconductor layer made of zirconium nitride (ZrN (111)), which is a group 13 nitride, and is formed on the (110) plane of the Si substrate 2. FIG. 2 is a graph showing the light reflectance of zirconium nitride. The horizontal axis of the graph indicates the wavelength, and the vertical axis of the graph indicates the light reflectance. FIG. 3 is a table showing the correspondence between the light reflectance of zirconium nitride and the wavelength of the light.

  As shown in FIGS. 2 and 3, the light reflectance at 470 nm that is the wavelength range of blue light in zirconium nitride is 65.6%. Based on this, it can be said that the buffer layer 3 made of zirconium nitride can reflect almost 65% or more of light when irradiated with blue light.

The functional layer 4 is a semiconductor layer made of, for example, a group 13 nitride semiconductor, and can function as a light emitting part of a light emitting element or a conductive part of an electronic element. The group 13 nitride, for example, GaN (gallium nitride), AlN (aluminum nitride), etc. InN (indium nitride), with the general formula _{In X Ga Y Al 1-X} -Y N (0 ≦ X ≦ 1, 0 ≦ Y ≦ 1, 0 ≦ X + Y ≦ 1). Moreover, you may be the structure which consists of other group 13 nitride semiconductors, such as MgN.

FIG. 4 is a diagram showing a configuration of a sputtering apparatus which is a manufacturing apparatus for the functional layer 4 and the buffer layer 3 described above.
As shown in the figure, the sputtering apparatus 20 includes a chamber 21, a substrate heating mechanism 22, a substrate holding unit 23, a sputtering gun 24, a pulse power supply 25, and a control unit 26. In the sputtering apparatus 20, the substrate 2 can be heated by the substrate heating mechanism 22 in a state where the substrate 2 is held on the substrate holding part 23 in the chamber 21. Further, a sputter beam is emitted from the plurality of sputter guns 24 toward the substrate 2 while the substrate 2 is held on the substrate holding portion 23.

  The plurality of sputter guns 24 are, for example, a sputter gun 24a that emits a beam of Ga and Ga alloy, a sputter gun 24b that emits a beam of Al and Al alloy, a sputter gun 24c that emits a beam of In and In alloy, Si and Si A sputter gun 24d for injecting an alloy beam and a sputter gun 24e for injecting a Zr and Zr alloy beam are provided. About the kind of metal which comprises the beam from each sputter gun 24a-24e, it is possible to replace | exchange suitably. Therefore, a group 13 metal element other than those described above, for example, Mg or Hf, and a beam made of these metals may be emitted.

  Each of the plurality of sputter guns 24 is connected to a pulse power source 25. The pulse power source 25 is a power source that applies a pulse voltage to the sputter gun 24. Pulse power sources 25a to 25e corresponding to the sputter guns 24a to 24e are provided. The output timing, output period, frequency, amplitude and the like of the pulse voltage output from these pulse power supplies 25a to 25e are controlled by a control unit 26 such as a control computer.

Next, a process for manufacturing the semiconductor substrate 1 configured as described above will be described.
First, as shown in FIG. 5, an electronic circuit 2a such as a MOS transistor is formed on the (110) surface of the Si substrate 2 by a known method. After forming the electronic circuit 2a, as shown in FIG. 6, the buffer layer 3 is formed on the (110) surface of the Si substrate 2 on which the electronic circuit 2a is formed so that a part of the electronic circuit 2a is exposed. .

  The buffer layer 3 is formed using the sputtering apparatus 20 described above. In the present embodiment, a PSD method (pulse sputter deposition method) in which a pulse DC voltage is applied between the substrate and the target will be described as an example. In particular, in this embodiment, since the semiconductor thin film is formed on the Si substrate 2 capable of increasing the area, it is significant to perform the PSD method, for example, the manufacturing cost is reduced and the throughput can be improved. I can say that.

  First, argon gas and nitrogen gas are supplied into the chamber 21. After the inside of the chamber 21 reaches a predetermined pressure by argon gas and nitrogen gas, the Si substrate 2 is held on the substrate holding part 23. After the Si substrate 2 is held by the substrate holder 23, the ambient temperature of the Si substrate 2 is adjusted by the substrate heating mechanism 22. When the ambient temperature of the Si substrate 2 is adjusted, the pulse power source 25 is driven, and a Zr beam is emitted from the sputter gun 24e toward the (110) plane of the Si substrate 2.

  While the pulse voltage is applied, the ejected Zr atoms are supplied onto the Si substrate 2 with high energy. On the surface of the Si substrate 2, nitrogen in the chamber is nitrogen radicals. A large amount of Zr atoms having high energy is supplied onto the (110) plane of the Si substrate 2, and the surface of the Si substrate 2 is in a metal-rich state.

  In a metal-rich state, Zr atoms migrate to stable lattice positions. Zr atoms migrated to a stable lattice position react with nitrogen radicals activated in the chamber 21 to form metal nitride (ZrN) crystals. Each time a pulse voltage is applied, ZrN having a stable crystal structure is intermittently deposited.

After forming the buffer layer 3, as shown in FIG. 7, the functional layer 4 is formed on the buffer layer 3 by the same method, and the exposed portion of the electronic circuit 2a and the functional layer 4 are connected by the wiring 5. To do.
In this way, the semiconductor substrate 1 is completed.

  According to the present embodiment, the use of the Si substrate 2 can significantly reduce the manufacturing cost compared to the case of using a sapphire substrate or a SiC substrate. Further, by growing group 13 nitride on the (110) plane of the Si substrate instead of the conventional (100) plane of the Si substrate, the crystal symmetry mismatch can be eliminated. Furthermore, since the group 13 nitride is grown by the pulse sputter deposition method, it can be manufactured even on a substrate having a large area of, for example, 12 inches or more, and can be manufactured with high throughput.

  In the present embodiment, the electronic circuit 2a is formed on the (110) plane of the Si substrate 2, and after the formation of the electronic circuit 2a, the buffer layer 3 and the functional layer 4 are formed as semiconductor layers. The formation of the electronic circuit 2a and the formation of the buffer layer 3 and the functional layer 4 can be incorporated into a series of manufacturing steps of the Si substrate 2. In addition, the semiconductor substrate can be manufactured without greatly changing the conventional manufacturing process of the Si substrate.

The technical scope of the present invention is not limited to the above-described embodiment, and appropriate modifications can be made without departing from the spirit of the present invention.
For example, in the above embodiment, both the buffer layer 3 and the functional layer 4 are formed by the pulse sputter deposition method. However, the functional layer 4 is not limited to this. For example, the PLD method (pulse laser deposition method) Alternatively, it may be formed by other thin film forming methods such as a PXD method (Pulsed Excitation Deposition), an organic metal growth method, a molecular beam epitaxy method or the like including a PED method (Pulsed Electron Deposition Method).

  In the above embodiment, the buffer layer 3 made of ZrN is formed on the Si substrate 2, but the present invention is not limited to this. For example, the buffer layer 3 made of HfN may be formed. Absent. Further, as shown in FIG. 8, the functional layer 4 may be grown directly on the (110) plane of the Si substrate 2 without forming the buffer layer 3. In this case, the functional layer 4 is formed by the above-described pulse sputtering deposition method. Further, a configuration in which the functional layer 4 is stacked, for example, a configuration of GaN layer / AlN layer / Si (110) may be used.

  In the above embodiment, the group 13 nitride semiconductor layer is formed on the (110) surface of the Si substrate on which the electronic circuit 2a is formed. However, the present invention is not limited to this. It goes without saying that the present invention is applicable even when a semiconductor layer is formed on the (110) surface of a Si substrate on which 2a is not formed by pulse sputtering deposition.

  Further, when performing pulse sputtering, a beam may be emitted by doping a group 13 nitride with Si or the like. In this case, for example, control is performed so that the beam is simultaneously emitted from the sputter gun 24a and the sputter gun 24d. By doping Si, which is the same material as the substrate, the lattice mismatch between the layer to be formed and the (110) plane of the Si substrate can be further reduced.

Next, Example 1 according to the present invention will be described. In this example, the Si substrate was annealed at 930 ° C. for 30 minutes, and then AlN was grown on the (110) plane of the Si substrate. As growth conditions, the growth temperature is 930 ° C., the growth pressure is 5.0 × 10 ⁻³ Torr, the nitrogen gas flow rate is 4.0 sccm, the argon gas flow rate is 6.0 sccm, the duty ratio of the pulse voltage (the voltage is turned on within one pulse). 5%, specifically, an on time of 5 μsec, an off time of 95 μsec, a voltage of 650 V, and a current of 0.20 A.

FIG. 9 is a [11-20] reflection high-energy electron diffraction (RHEED) diagram of the AlN layer. FIG. 10 is a [10-10] RHEED diagram of the AlN layer.
As shown in these figures, it can be seen that the diffraction spots clearly appear. From this, it can be said that a good quality AlN single crystal has grown on the (110) plane of the Si substrate.

  FIG. 11 is an EBSD pole figure for the (110) plane of the AlN layer and the Si substrate. For the AlN layer, measurements were performed on the [0001] plane, the [11-20] plane, and the [10-10] plane. For the Si substrate, the measurement was performed on the [110] plane, the [001] plane, and the [1-11] plane. From the figure, it can be seen that (1) AlN [0001] and Si [110] are parallel, and (2) AlN [10-10] and Si [001] are parallel.

  Among these, in the case of (1), the lattice mismatch is an extremely small value of about 0.7%. Therefore, when AlN is formed on the (110) plane of the Si substrate, almost no lattice mismatch is observed, which is a preferable mode.

  Next, a second embodiment according to the present invention will be described. In this example, a Si-doped GaN semiconductor layer (Si-doped semiconductor layer) was formed on a Fe-doped GaN substrate by a pulse sputtering deposition method. Further, a GaN semiconductor layer doped with Si was compared with a GaN semiconductor layer (undoped semiconductor layer) formed without doping Si.

  As conditions for the pulse sputtering, the voltage of the sputtering gun for GaN was 600 V, the current was 0.045 A, the pulse frequency was 10 kHz, and the duty ratio was 5%. The voltage of the Si sputtering gun was 800 V, the current was 0.02 A, the pulse frequency was 10 kHz, and the duty ratio was 5%.

  FIG. 12 is an RHEED diagram of the formed semiconductor layer. 12A shows an RHEED diagram of the undoped semiconductor layer, and FIG. 12B shows an RHEED diagram of the Si-doped semiconductor layer. Moreover, FIG. 13 is a photograph when the surface of the formed semiconductor layer is imaged with a scanning electron microscope (SEM). FIG. 13A shows an SEM photograph of the undoped semiconductor layer, and FIG. 13B shows an SEM photograph of the Si doped semiconductor layer.

  As shown in FIG. 12, it can be seen that diffraction spots clearly appear in both the undoped semiconductor layer and the Si doped semiconductor layer. From this, it is possible to grow a high-quality AlN single crystal even when Si is doped. In addition, as shown in FIG. 13, the unevenness was hardly observed in the non-doped semiconductor layer, whereas some unevenness was observed on the surface of the Si-doped semiconductor layer.

  The EBSD half-value width in the tilt direction of the undoped semiconductor layer was 0.12 ° and the EBSD half-value width in the twist direction was 0.25 °, whereas the EBSD half-value width in the tilt direction of the Si-doped semiconductor layer was The EBSD half width in the twist direction was 0.12 ° and 0.24 °, and there was almost no difference between the two. Thus, it can be seen that even when Si is doped, a high-quality crystal similar to the undoped semiconductor layer grows.

Next, a third embodiment according to the present invention will be described. In this example, an AlGaN semiconductor layer was formed on the (110) surface of the Si substrate by pulse sputtering deposition using the above sputtering apparatus. The growth temperature of the semiconductor layer was 300 ° C., and the growth pressure was 20 mTorr. Further, the voltage of the Ga sputtering gun was 607 V, the current was 0.05 A, the output was 30.4 W, the duty ratio was 5%, and the instantaneous supply current amount was 1.0 A. The voltage of the Al sputtering gun was 412 V, the current was 0.10 A, the output was 41.2 W, the duty ratio was 5%, and the instantaneous supply current amount was 2.0 A. The pulse frequency of both sputter guns was 10 kHz. As a result, in this example, a semiconductor layer having a composition of Al _0.35 Ga _0.65 N was obtained. Thus, a thin film of a group 13 nitride having a plurality of types of group 13 elements can be obtained in the sputtering apparatus. At this time, the growth rate of the semiconductor layer was 100 nm / hr.

  Next, a fourth embodiment according to the present invention will be described. In this example, an AlN semiconductor layer was formed on the (110) surface of the Si substrate by the pulse sputtering deposition method using the above sputtering apparatus. In this example, the growth temperature of the semiconductor layer was set to 700 ° C. and 1000 ° C.

  FIG. 14 is an RHEED diagram of a semiconductor layer formed according to this example. FIG. 14A shows a case where the growth temperature is 700 ° C., and FIG. 14B shows a case where the growth temperature is 1000 ° C. As shown in these figures, it can be seen that the diffraction spots clearly appear in both the growth temperature of 700 ° C. and the growth temperature of 1000 ° C. From this, it can be said that a good quality AlN single crystal can be grown even at a relatively low growth temperature of about 700 ° C. to 1000 ° C.

Next, a fifth embodiment according to the present invention will be described. In this example, an AlN semiconductor layer was formed on the (110) surface of the Si substrate by the pulse sputtering deposition method using the above sputtering apparatus. In this example, the semiconductor layers were formed when the partial pressure ratios of nitrogen gas and argon gas in the sputtering apparatus were different. Specifically, when the N ₂ / Ar ratio is 4.0, 0.83, 0.67, 0.43, 0.38, and 0.25, respectively. A semiconductor layer was formed. In this example, the semiconductor layer was formed at a growth temperature of 900.degree.

FIG. 15 is an RHEED diagram of the semiconductor layer obtained in this example. 15A shows a case where the N ₂ / Ar ratio is 4.0, FIG. 15B shows a case where the N ₂ / Ar ratio is 0.83, and FIG. 15C shows a case where the N ₂ / Ar ratio is 0.8. for 67, FIG. 15 (d) if _N 2 / Ar ratio of 0.43, FIG. 15 (e) if _N 2 / Ar ratio of 0.38, FIG. 15 (f) is _N 2 / Ar It is a RHEED figure in case a ratio is 0.25.

As shown in FIGS. 15A and 15B, a ring pattern can be confirmed at the diffraction spot. This shows that the semiconductor layer contains polycrystals when the N ₂ / Ar ratio is 4.0 and 0.83. Further, as shown in FIG. 15F, it can be seen that when the N ₂ / Ar ratio is 0.25, precipitation of Al occurs. In these cases, a high-quality single crystal was not formed.

As shown in FIGS. 15C to 15E, it can be seen that the diffraction spots clearly appear. From this, it can be said that a good quality AlN crystal is formed in each case where the N ₂ / Ar ratio is 0.67, 0.43, and 0.38. Further, it can be seen that the flatness improves as the N ₂ partial pressure ratio is lower between the three cases.

The figure which shows the structure of the semiconductor substrate which concerns on embodiment of this invention. The graph which shows the light reflectivity of a zirconium nitride. The figure which shows the light reflectance of a zirconium nitride, and the correspondence of a reflective wavelength. The figure which shows the structure of the sputtering device which concerns on this embodiment. Process drawing which shows the manufacture process of a semiconductor substrate. The process drawing. The process drawing. The figure which shows the other structure of the semiconductor substrate which concerns on this invention. The RHEED figure of the semiconductor layer which concerns on Example 1 of this invention. The RHEED figure of the semiconductor layer which concerns on a present Example. The EBSD pole figure of the semiconductor layer concerning a present Example. The RHEED figure of the semiconductor layer which concerns on Example 2 of this invention. The SEM photograph of the semiconductor layer which concerns on a present Example. The RHEED figure of the semiconductor layer which concerns on Example 4 of this invention. The RHEED figure of the semiconductor layer which concerns on Example 4 of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate 2 ... Si substrate 2a ... Electronic circuit 3 ... Buffer layer 4 ... Functional layer 5 ... Wiring 20 ... Sputtering device

Claims (12)

A method of manufacturing a semiconductor substrate, comprising: forming a semiconductor layer containing a group 13 nitride on a (110) surface of a Si substrate by pulse sputtering deposition. Forming a circuit on the (110) surface of the Si substrate;
The method for manufacturing a semiconductor substrate according to claim 1, wherein the semiconductor layer is formed after forming the circuit. The method for manufacturing a semiconductor substrate according to claim 1, wherein the group 13 nitride includes at least one of AlN, GaN, and InN. The method for manufacturing a semiconductor substrate according to any one of claims 1 to 3, wherein the semiconductor layer containing Si is formed on a (110) plane of the Si substrate. Forming a first semiconductor layer containing at least one of HfN and ZrN on the (110) surface of the Si substrate by pulse sputtering deposition;
5. The method for manufacturing a semiconductor substrate according to claim 1, wherein a group 13 nitride second semiconductor layer is formed on the first semiconductor layer. 6. A Si substrate provided with a circuit on a (110) plane;
And a semiconductor layer including a group 13 nitride provided on a (110) plane of the Si substrate. The semiconductor substrate according to claim 6, wherein the group 13 nitride includes at least one of AlN, GaN, and InN. The semiconductor substrate according to claim 6, wherein the semiconductor layer includes Si. A first semiconductor layer provided on the (110) surface of the Si substrate and including at least one of HfN and ZrN which is a group 13 nitride;
The semiconductor according to any one of claims 6 to 8, further comprising: a second semiconductor layer provided on the first semiconductor layer and including a second semiconductor layer of a group 13 nitride. substrate. The semiconductor circuit according to any one of claims 6 to 9, wherein the circuit is an electronic circuit including a MOS transistor.   A light emitting device comprising the semiconductor substrate according to claim 6.   An electronic device comprising the semiconductor substrate according to any one of claims 6 to 10.

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