JP2009237666A - Electronic appliance - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a technology for constructing a highly versatile control system in an electronic appliance whose operation is controlled by a processor executes a prescribed control program. <P>SOLUTION: When the power source of electronic equipment 1 is inputted, a CPU core 101 executes a boot program stored in a boot ROM 103. An initialization program for initializing an RAM controller 104 stored in a flash ROM 112 is transferred to an SRAM 102, and executed by a boot program. Thus, an RAM controller 104 is initialized so as to be fitted to the type or size of an SDRAM 111, and put into such a state that the SDRAM 111 is accessible. Afterwards, a control program stored in a flash ROM 112 as compressed data is extended and restored on the SDRAM 111, and the restored control program is executed, so that a normal operating state can be set. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to an electronic device whose operation is controlled by a control program executed by a processor, and more particularly to its activation process.

  In an electronic device whose operation is controlled by a processor executing a predetermined control program, it is widely performed that the processor and a data holding unit in which the control program is written in advance are separate devices. This is because a general-purpose processor can be used, and it is possible to cause the same processor to perform various operations by changing the control program. For example, Patent Document 1 discloses an electronic device configured to transfer and execute a boot program stored in advance on a ROM (read-only memory) to a RAM (rewritable memory) when the device is turned on. ing.

JP 2006-72989 A

  By the way, since the size of a control program for operating an electronic device is large, DRAM (Dynamic RAM) or SDRAM (Synchronous Dynamic RAM) having a large storage capacity is generally used as a RAM to store the program. Since this type of memory device cannot be connected to the system bus of the processor, the DRAM and SDRAM are connected to the processor via a RAM controller. However, the RAM controller cannot start data exchange between the processor and the RAM unless initialization is performed to match the type and capacity of the connected RAM. That is, in the above prior art, it is necessary to initialize the RAM controller before starting to transfer the program to the RAM.

  In order to cope with this problem, in the above prior art, the RAM controller is initialized by mounting a peripheral circuit including the RAM controller on a dedicated ASIC (Application Specific Integrated Circuit). The setting contents of the RAM controller are fixed in advance according to the specifications of the ASIC. For this reason, when it is desired to change the type and capacity of the RAM to be used, it is necessary to change both the ASIC, increasing the apparatus cost, and the control system lacking versatility.

  This invention is made in view of the said subject, and provides the technique which can construct | assemble a highly versatile control system in the electronic device by which operation is controlled by a processor executing a predetermined control program. Objective.

  In order to achieve the above object, an electronic device according to the present invention includes a processor that executes a control program for operating an electronic device, a first RAM directly connected to a system bus of the processor, and the RAM via a RAM controller. Data in which a second RAM connected to the system bus, the control program connected to the system bus, and RAM controller setting data for initializing the RAM controller in association with the second RAM are written Holding means, and the processor transfers the RAM controller setting data from the data holding means to the first RAM, initializes the RAM controller based on the data, and then executes the control program from the data holding means. Read and transfer to the second RAM, the second It is characterized by performing the activation process to be executed starting the control program on the RAM.

  In the invention thus configured, the RAM controller setting data written in advance in the data holding means is transferred to the first RAM that can be directly accessed by the processor, and the processor initializes the RAM controller based on the RAM controller setting data. . Thereafter, the processor can access the second RAM via the RAM controller. In other words, the control program read from the data holding means is transferred to the second RAM and is ready to be executed by the processor.

  Thus, by writing the RAM controller setting data used for initialization of the RAM controller into the data holding means, the data can be changed for various types and capacities of storage elements that can be used as the second RAM. It is possible to respond by simply doing. For this reason, the versatility of the control system of an electronic device can be improved. Further, since the RAM controller setting data is transferred from the data holding means to the first RAM when the device is activated, the RAM controller can be initialized based on the RAM controller setting data on the first RAM that can be directly accessed by the processor. . For this reason, the RAM controller can be initialized in a short time to shift to a state where the second RAM can be accessed, and the start-up process can be completed in a short time.

  The first RAM must be one that can be directly connected to the system bus of the processor. This type of storage element is generally expensive with respect to the storage capacity. In the present invention, however, the RAM controller setting data described above is used. Since a data capacity for temporary storage is sufficient, the first RAM needs only a very small capacity.

  In the electronic device according to the present invention, for example, an initialization program for initializing the RAM controller is written as the RAM controller setting data in the data holding means, and the processor is stored in the first RAM. The RAM controller may be initialized by executing the transferred initialization program.

  According to such a configuration, since the initialization program on the first RAM directly connected to the system bus of the processor is executed, the initialization of the RAM controller is performed in a short time so that the second RAM can be accessed quickly. Can be migrated.

  Further, for example, the data holding means is written with compressed data obtained by compressing the control program, and a decompressed program for decompressing the compressed data and restoring the control program. The control program may be restored on the second RAM by executing the expansion program.

  By compressing the control program, the capacity of the control program in the data holding unit can be reduced. In addition, since a decompression program for decompressing compressed data is integrally written in the same data holding means, it is not necessary to fix the compression method used for compressing the program in advance, and any compression method can be applied. Can do. This also makes it possible to further increase the versatility of the control system.

  In this case, the processor transfers the decompression program read from the data holding means to the first RAM and executes it on the first RAM, or transfers the decompression program to the second RAM and executes it on the second RAM. Preferably it is performed. By doing so, the compressed data can be decompressed in a shorter time than when the decompression program is executed on the data holding means. In particular, when the decompression program is executed on the first RAM, the decompression process can be performed at high speed. Further, when the decompression program is executed on the second RAM, the decompression program having an arbitrary length can be used. The RAM controller setting data is preferably written in the data holding means without compression. This is because the amount of data for RAM controller setting data is not so large, so the effect of compression is small, and non-compression makes it possible to omit the decompression step and initialize the RAM controller in a shorter time. .

  In the electronic device according to the present invention, the control program includes an interrupt processing program executed in response to an interrupt request, and the data holding means includes the interrupt processing program in the second RAM. Is stored, and the processor reads out the position information from the data holding means and stores it in the first RAM. When the interrupt request is received, the processor stores the position information in the first RAM. The interrupt processing program on the second RAM specified by the position information may be executed.

  The first RAM can be used for any purpose after it is used for the startup process, but it is preferable in that it can execute various processes in response to an interrupt request, particularly when configured as described above. A processor that accepts an interrupt caused by various factors is configured to forcibly execute an instruction stored in an address assigned in advance according to the interrupt factor in the memory space when an interrupt request is generated. Yes. In other words, the storage destination of the processing program that is executed when an interrupt request is generated is predetermined and fixed. Therefore, the position information read from the data holding means is stored in the first RAM, and when an interrupt request is received, the interrupt processing program on the second RAM specified by the position information stored in the first RAM is executed. In this case, a processing program stored in an arbitrary position in the second RAM with an arbitrary length can be executed as an interrupt process.

  In each of the above inventions, the processor and the first RAM may be mounted in a single package. In the present invention, the first RAM needs to be directly connectable to the system bus of the processor, but a large data capacity is not required. Further, it is not necessary to change the first RAM depending on the capacity of the data holding means, the data content, the type and capacity of the second RAM. For this reason, the first RAM can be mounted in the same package as the processor without impairing the versatility of the control system. In addition, a large number of signal lines are required between the processor and the first RAM that are directly connected via the system bus. However, by mounting these in a single package, these can be separated from each other. In comparison, the number of signal lines connecting between packages can be reduced, and a high communication speed can be ensured.

  Further, the data holding means includes a boot ROM that stores a boot process program for causing the processor to execute the boot process, and a storage medium that stores the control program and the RAM controller setting data. May be. The contents of the control program to be stored in the data holding means and the data size thereof need to be changed according to the specifications of the device. The contents of the RAM controller setting data also need to be changed according to the second RAM to be used. On the other hand, the contents of the activation process itself do not need to be changed even if they are changed. Therefore, a startup process program that does not need to be changed may be stored in a non-rewritable ROM.

  In this case, the processor, the first RAM, and the boot ROM may be mounted in a single package. As described above, since these configurations do not need to be changed even if the specifications of the electronic device are changed, a device in which these configurations are mounted in a single package can be applied to electronic devices of various specifications. Will be expensive.

  For example, a flash memory can be used as the storage medium for storing the control program and the RAM controller setting data. By using a flash ROM as the storage medium for storing the control program and RAM controller setting data that need to be changed according to the specifications of the device, it becomes possible to easily rewrite these data. It is possible to improve the specifications and performance of the system afterwards by rewriting data.

  The first RAM may be an SRAM (Static RAM). In general, a large-capacity SRAM has not been commercialized and requires a large capacity, resulting in a high cost. However, the SRAM can be directly connected to the processor system bus and can be connected to the processor at high speed. Access is possible. On the other hand, in the present invention, direct connection to the system bus and high-speed access are required for the first RAM, but a large capacity is not required. Therefore, an SRAM can be suitably used as the first RAM of the present invention. In addition, by transferring the data required at the time of startup to an SRAM that can be accessed at high speed, the processing time required for the startup process can be shortened and the device can be started up in a short time.

  Further, since the capacity of the second RAM is required rather than high speed, for example, a DRAM (Dynamic RAM) can be used for such a purpose. Further, the use of SDRAM (Synchronous Dynamic RAM) can improve the access speed.

  FIG. 1 is a block diagram showing an embodiment of an electronic apparatus according to the present invention. The electronic device 1 implements a predetermined function when a processor executes a predetermined control program such as a printer or a game machine. In the electronic apparatus 1, an ASIC (Application Specific Integrated Circuit) 100 is provided. The ASIC 100 is provided with a CPU core 101, an SRAM (Static RAM) 102, a boot ROM 103, a RAM controller 104, and a serial memory controller 105, which are connected to each other via a system bus 109.

  The CPU core 101 controls the operation of each unit by executing a control program. The SRAM 102 has a data capacity of about 1 kbyte, for example, and is directly connected to the CPU core 101 via the system bus 109. The CPU core 101 is provided with a port for receiving an interrupt request signal IRQ (Interrupt Request) as a hardware interrupt request signal and an FIQ (Fast Interrupt Request) signal having a higher priority and capable of handling an interrupt more quickly. It has been.

  The boot ROM 103 has a data capacity of, for example, about 4 kbytes, and the minimum data necessary for starting the device is written in advance. Data contents and functions will be described later.

  The RAM controller 104 is connected to an SDRAM (Synchronous Dynamic RAM) 111 provided outside the ASIC 100, and controls data communication between the CPU core 101 and the SDRAM 111 via the system bus 109. The SDRAM 111 functions as a main memory that temporarily holds control programs and data necessary for the operation of the electronic device, and has a data capacity of, for example, about 8 M to 32 Mbytes depending on the function to be realized. The ASIC 100 is connected to a flash ROM 112 capable of serial communication, and the serial memory controller 105 controls data communication between the CPU core 101 and the flash ROM 112 via the system bus 109.

  In the flash ROM 112, a control program for the electronic device 1 to perform an intended operation is compressed and written. Further, as will be described in detail later, the flash ROM 112 is also written with programs and data necessary for starting up the electronic device 1 when the power is turned on and shifting to the normal operation state.

  Further, an I / O interface 113 provided outside the ASIC 100 is connected to the system bus 109, and a functional block 114 for realizing various functions of the electronic device is connected to the I / O interface 113. ing. For example, if the electronic device is a printer, a functional unit 114 corresponds to a printer engine for printing an image, operation buttons for receiving an instruction input from a user, a display for displaying an image, and the like. .

  In the electronic device 1, when the device is turned on or a reset button provided as necessary is operated, the CPU core 101 executes a predetermined activation process so that the device can be normally operated. To a different state. As described above, in the electronic device 1, the control program to be executed by the CPU core 101 is written in the flash ROM 112 in a compressed state. In the startup process, the compressed data read from the flash ROM 112 is decompressed and stored in the SDRAM 111. The control program is restored as an executable control program, and the execution of this control program causes the device to shift to a normal operation state. Hereinafter, the start-up process in the electronic apparatus 1 and the structural features for enabling it to be performed in a short time will be described.

  FIG. 2 is a diagram showing a memory map in this embodiment. The CPU core 101 assigns peripheral devices such as the SRAM 102, the boot ROM 103, the SDRAM 111, and the flash ROM 112 to each area of the memory space, and controls each peripheral device. Among the peripheral devices, the boot ROM 103, the SRAM 102, and the SDRAM 111 have a one-to-one correspondence between the addresses on the memory and the addresses on the memory space. By doing so, it is possible to access these memories in units of one address, and it is possible to cause the electronic device 1 to perform various operations.

  The boot ROM 103 is assigned to the youngest address in the memory space. Therefore, the CPU core 101 executes the program written in the boot ROM 103 immediately after the device is turned on.

  For the flash ROM 112, only a 2-byte virtual address is assigned. This is because, as will be described later, the data written in the flash ROM 112 is read out sequentially at the time of startup processing or the like and does not require addressing in fine address units. In this way, the memory space can be used effectively, and when viewed from the CPU core 101, the flash ROM 112 can be accessed by the same access method regardless of the data capacity of the flash ROM 112.

  Further, a part of the memory space is allocated to registers that respectively control the interrupt controller, the serial memory controller 105, and the RAM controller 104 (not shown).

  FIG. 3 is a view showing the contents of data written in the boot ROM. In the boot ROM 103, when an interrupt request is made to the CPU core 101, an exception vector indicating an address to which program execution is to be transferred is written according to the cause. Interrupt factors include hardware interrupts such as IRQ and FIQ described above, as well as software interrupts requested by the control program and interrupts caused by operation errors, and an exception vector is set for each of these factors. . In the following, a set of these exception vectors is represented by a symbol P10.

  In this embodiment, the address specified by the exception vector is set to the address assigned to the SRAM 102. Therefore, when an interrupt request is generated in the CPU core 101 for some reason, the CPU core 101 interrupts the program being executed and transfers execution to the address on the SRAM 102 specified by the exception vector according to the interrupt factor. The reason for this will be described later.

The boot ROM 103 stores a boot program that is first executed by the CPU core 101 immediately after the device is turned on or immediately after the reset button is pressed. The boot program is as follows:
A program P11 for initializing the serial memory controller 105 and enabling communication between the CPU core 101 and the flash ROM 112;
A program P12 for reading a series of data having a predetermined address on the flash ROM 112 as a head address from the flash ROM 112 and transferring it to the SRAM 102;
A program P13 for transferring the execution of the program to a predetermined address on the SRAM 103;
A program P14 for reading a series of data starting from a predetermined address on the flash ROM 112 from the flash ROM 112 and transferring it to the SDRAM 111; and a program P15 for transferring program execution to a predetermined address on the SDRAM 111,
Is included.

  FIG. 4 is a view showing the contents of data written in the flash ROM. In the flash ROM 112, as shown in FIG. 4, the interrupt calling program P20 and the main programs P30 and P31 are written in a compressed state, while the startup programs P21 to P24 are written in an uncompressed state. In FIG. 4, the square brackets attached to the code of the program represent data in which the program is compressed. For example, [P20] represents compressed data obtained by compressing the program P20. In addition, when it is necessary to specifically indicate that a program is in an uncompressed state in order to distinguish it from compressed data, parentheses are added to the code representing the program. For example, (P21) represents data corresponding to the uncompressed program P21. A program code without parentheses also represents that the program is in an uncompressed state. The same expression is used in the following description and drawings.

  The interrupt calling program P20 is composed of a group of jump instructions for transferring the execution of the program to a predetermined address on the SDRAM 111 that stores a processing routine to be executed corresponding to the interrupt factor.

The startup program is as follows:
An initialization program P21 for initializing the RAM controller 104 to match the main memory;
A program P22 for transferring the execution of the program to a predetermined address on the boot ROM 103;
A program P23 for decompressing the compressed data on the SDRAM 111 and developing it on the SDRAM 111;
A program P24 for transferring program execution to a predetermined address on the SDRAM 111;
These programs are written in the flash ROM 112 as uncompressed data.

The main program is the following programs:
An interrupt processing routine group P30 provided corresponding to various interrupt factors for executing predetermined interrupt processing;
A normal operation routine P31 for causing the electronic device 1 to perform a predetermined operation;
These programs are written in the flash ROM 112 as compressed data.

  FIG. 5 is a diagram showing a flow of activation processing in this embodiment. FIG. 6 shows the data contents of each RAM at each time. When the device is turned on or the reset button is pressed by the user at time T0, the CPU core 101 is configured to read out and start executing the program written at the youngest address in the memory space. In this embodiment, execution of the boot program written in the boot ROM 103 is started.

  First, a program P11 for initializing the serial memory controller 105 is executed, whereby the CPU core 101 is ready to read data from the flash ROM 112 via the serial memory controller 105. Subsequently, the program P11 is executed, whereby the interrupt call program P20 written in the flash ROM 112 and the programs P21 and P22 among the startup programs are read and transferred onto the SRAM 102. At time T1 when this transfer is executed, the programs P20, P21 and P22 written in the flash ROM 112 are stored in the SRAM 102 as shown in FIG.

  Subsequently, by executing the program P13, the execution of the program is moved onto the SRAM 102. More specifically, in the program P13, the head address of the program P21 transferred onto the SRAM 102 is designated, and therefore the program P21 on the SRAM 102 is read and executed by the CPU core 101. By executing the program P21, the RAM controller 104 is initialized, and thereafter, data can be transferred between the CPU core 101 and the SDRAM 111 via the RAM controller 104.

  Next, by executing the program P22 on the SRAM 102, the execution of the program is transferred to the boot ROM 103. The address on the boot ROM 103 designated at this time is the head address of the program P14. Therefore, the program P14 is subsequently executed.

  In the program P 14, a series of data starting from a predetermined address on the flash ROM 112 is read and transferred to the SDRAM 111. Here, by setting the address on the flash ROM 112 corresponding to the head of the program P23 as the start address, the uncompressed programs (P23) and (P24) and the compressed programs [P30] and [P31] are read from the flash ROM 112. Transferred to the SDRAM 111. At this time T2, the programs [P30] and [P31] remain compressed data. That is, as shown in FIG. 6B, at time T2, uncompressed programs (P23) and (P24) and compressed programs [P30] and [P31] are stored on the SDRAM 111. Yes. On the other hand, the contents of the SRAM 102 have not changed since time T1.

  Subsequently, the program P15 on the boot ROM 103 is executed, and the execution of the program moves to a predetermined address on the SDRAM 111, specifically, to the top address of the program P23. The program P23 is written on the SDRAM 111 in an uncompressed state, and its contents are such that the compressed programs [P30] and [P31] transferred to the SDRAM 111 are decompressed and stored in the SDRAM 111. Therefore, at time T3 after executing the program P23, the restored programs (P30) and (P31) are stored in the SDRAM 111 as shown in FIG. The SRAM 102 is still in a state where the programs P20, P21 and P22 are stored.

  In FIG. 6C, the compressed data [P30] and [P31] before decompression remain on the SDRAM 111, but these may be overwritten by the restored programs (P30) and (P31). Alternatively, it may be deleted from the SDRAM 111 after decompression. Also, it is arbitrary where the restored programs (P30) and (P31) are allocated in the memory space of the SDRAM 111.

  When the main programs P30 and P31 are thus expanded on the SDRAM 111, the program P24 is finally executed, and execution is transferred to a predetermined address on the SDRAM 111, specifically, to the top address of the program P31 describing the normal operation routine. The electronic device 1 shifts to the normal operation state, and the activation process is completed.

  The electronic device of the present embodiment configured as described above can achieve the following operational effects. First, in addition to the main memory that requires initialization of the RAM controller, an SRAM 102 that can be accessed directly from the CPU core 101 at a high speed and does not need to be initialized is provided, and the RAM controller 104 is initialized at startup. Since the program P21 is executed on the SRAM 102, the SDRAM 111 as the main memory can be shifted to a usable state in a short time, and the time required for the startup process can be shortened.

  The SRAM 102 does not require a particularly large capacity, and at least a capacity capable of storing the program P21 for initializing the RAM controller 104 is sufficient. Therefore, an increase in the cost of the apparatus can be suppressed. In the configuration of this embodiment, the data capacity of the SRAM 102 is about 1 kbyte.

  In addition, since the program P21 for initializing the RAM controller 104 is written not in the boot ROM 103 of the same package as the CPU core 101 but in the external flash ROM 112, this is transferred to the SRAM 102 and executed at startup. The change of the type and capacity of the external main memory can be dealt with only by changing the program P21 in the flash ROM 112. For this reason, the degree of freedom in selecting a device used as the main memory is increased, and the versatility of the system is increased.

  Further, since the main program is written in the flash ROM 112, it is possible to rewrite the main program later as necessary, and it is possible to upgrade the existing function of the device or add a new function. .

  In addition, by writing the main program as compressed data in the flash ROM 112, the data capacity of the ROM is kept small. Further, the decompression program P23 for decompressing the compressed data and decompressing the main program is written in the same flash ROM 112, and the decompression program P23 is executed at the time of activation so that the main program is restored. Any compression method for the program written in the ROM 112 can be applied.

  Further, since the SRAM 102 does not need to be changed depending on peripheral devices or control programs, it can be incorporated in the same package as the CPU core 101. The CPU core 101 and the SRAM 102 that are directly connected via the system bus 109 are connected by a large number of signal lines. However, if these are provided in separate packages, the number of pins of the package increases. Therefore, if these are housed in the same package as, for example, an ASIC, the number of pins of the package can be greatly reduced, and the device can be reduced in size and cost. In addition, by connecting the CPU core 101 and the SRAM 102 with a short signal line in the same package, high-speed and stable communication can be performed.

  In this embodiment, a program for operating the device is stored in the boot ROM 103 and the flash ROM 112 separately. That is, a minimum boot program that does not need to be changed according to the type of peripheral device and the function of the electronic device is written in the boot ROM 103, while all data that may be changed is written in the flash ROM 112. By doing so, the combination of the CPU core 101 and the boot ROM 103 can be fixed regardless of peripheral devices and functions, and these can be incorporated into the same package. Further, the CPU core and the boot ROM combined in this way can be used to realize various functions in combination with various peripheral devices and control programs. For example, the same ASIC can be used in common among a plurality of types of electronic devices having completely different functions by simply changing the contents of peripheral devices and control programs. Therefore, the device cost can be further reduced.

  Further, the RAM controller 104 can be arbitrarily initialized by the initialization program P21 written in the external flash ROM 112, and therefore can be accommodated in the same package as the CPU core 101. In this embodiment, the CPU core 101, the SRAM 102, the boot ROM 103, the RAM controller 104, and the serial memory controller 105 are packaged as an ASIC 100 to reduce the size and cost of the device. In addition, the ASIC 100 packaged in one package does not need to be changed in accordance with changes in peripheral devices and control programs, and constitutes a highly versatile control system that can be incorporated into various electronic devices.

  On the other hand, the main memory whose type and capacity may be changed according to the function of the device and the flash ROM that may be written with various control programs are packaged separately from the CPU core 101. The combination of the CPU core 101 and peripheral devices can be easily changed.

  As described above, the control system of this embodiment is extremely versatile because various functions can be realized by combining with various peripheral devices and control programs.

  Note that it is also possible to replace the function of the SRAM 102 used in this embodiment with a cache memory provided incidentally to the CPU core. However, in the initial state, a physical address is not assigned to the cache memory, and the cache memory is mapped in the memory space only when a certain program is executed by the CPU core 101 and an address is assigned in the program. Therefore, in order to substitute the function of the SRAM 102 in this embodiment with the cache memory, the cache memory must be mapped by the program on the boot ROM. Since the contents of the boot ROM itself are fixed, the mapping is always constant, and eventually such a method lacks versatility.

  Next, interrupt processing in this embodiment will be described. For example, when an interrupt request signal is given due to some interrupt factor such as a user operation input or a fluctuation in power supply voltage, the CPU core 101 temporarily interrupts the operation being executed and executes interrupt processing. Specifically, program execution is forcibly transferred to an address determined in accordance with an interrupt factor. Since the jump destination address is determined in advance as an exception vector, when the interrupt processing routine is directly described at the jump destination address, the content of the processing becomes fixed and lacks versatility. Therefore, in this embodiment, an rewritable address on the SRAM 102 is designated in advance as the exception vector, and an instruction to jump to the interrupt processing routine on the SDRAM 111 is written in the designated address on the SRAM 102. This makes it possible to execute an interrupt processing routine described in an arbitrary length at an arbitrary position on the SDRAM 111. Hereinafter, the operation will be described in more detail with reference to FIGS.

  FIG. 7 is a diagram showing the flow of processing when an interrupt occurs. FIG. 8 is a conceptual diagram showing a transition of a program reading source after accepting an interrupt. Consider a case where an interrupt request is generated at time T4 during execution of the normal operation routine P31 on the SDRAM 111 as shown in FIG. When receiving the interrupt request, the CPU core 101 refers to the exception vector corresponding to the interrupt factor.

  In this embodiment, an exception vector P10 is allocated on the boot ROM 103. Therefore, when an interrupt request is generated at time T4, the program execution refers to one of the exception vectors P10 on the boot ROM 103 corresponding to the interrupt factor, and the execution is transferred to the designated address.

  In the exception vector P10, as shown in FIG. 8, for example, addresses A11, A12, and A13 on the SRAM 102 are associated with the interrupt factors X1, X2, and X3, respectively. All of these addresses are included in an area in the SRAM 102 where the program P20 is stored. Addresses in the program P20 on the SRAM 102 are designated for other interrupt factors. Therefore, the execution of the program is transferred to the program P20 on the SRAM 102 via the exception vector P10 on the boot ROM 103.

  In the program P20, a jump instruction for transferring execution to a predetermined address on the SDRAM 111 in which an interrupt processing routine corresponding to the interrupt factor is stored is described corresponding to each interrupt factor. Therefore, the interrupt processing routine on the SDRAM 112 described corresponding to the interrupt factor is finally executed.

  For example, when an interrupt request due to the interrupt factor X 1 occurs, the CPU core 101 refers to the exception vector P 10 on the boot ROM 103 and transfers the program execution to the address A 11 on the SRAM 102. Since the address A11 describes a jump instruction to the address A21 where the interrupt processing routine P30 on the SDRAM 111 corresponding to the interrupt factor X1 is stored, the CPU core 101 starts from the address A21 on the SDRAM 111. The interrupt processing routine corresponding to the interrupt factor X1 is executed.

  Similarly, when an interrupt request due to the interrupt factor X2 is generated, an interrupt processing routine corresponding to the factor X2 starting from the address A22 on the SDRAM 111 is executed from the exception vector on the boot ROM 103 via the address A12 on the SRAM 102. The When an interrupt request due to the interrupt factor X3 occurs, an interrupt processing routine corresponding to the factor X3 starting from the address A23 on the SDRAM 111 is sent via the address A13 on the SRAM 102 specified by the exception vector on the boot ROM 103. Executed. The same applies to other interrupt factors.

  As described above, in this embodiment, an address on the SRAM 102 is designated in the exception vector P10 on the boot ROM 103, while an instruction for jumping to the interrupt processing routine on the SDRAM 111 is stored at the designated address on the SRAM 102. ing. As a result, the execution of the program when an interrupt request is generated transitions in the order of the boot ROM 103, the SRAM 102, and the main memory SDRAM 111. By doing in this way, the following effects are obtained.

  First, an interrupt processing routine having an arbitrary length can be described corresponding to each interrupt factor. In order to jump directly from the exception vector on the boot ROM to the interrupt processing routine on the SDRAM, it is necessary to write the start address of the interrupt processing routine on the SDRAM in the boot ROM. In this case, it is necessary to rewrite the contents of the boot ROM in accordance with the contents of the interrupt processing routine, or it is necessary to reserve a storage area on the SDRAM in advance for the interrupt processing routine in order to cope with a long interrupt processing routine. For example, it is not preferable in terms of efficient use of hardware resources.

  On the other hand, in the present embodiment, since the jump to the interrupt processing routine on the SDRAM 111 is performed via the address on the SRAM 102, the above problem does not occur. That is, since the address of the interrupt processing routine on the SDRAM 111 is specified by data stored at a predetermined address on the SRAM 102, the specific address on the SRAM 102 is fixed as an exception vector on the boot ROM 103 regardless of the contents of the interrupt processing routine. You just have to specify it. This eliminates the need to change the contents of the boot ROM 103 in accordance with the contents of the interrupt processing routine. The start address of the interrupt processing routine specified by the data on the SRAM 102 can be freely set from the outside (more specifically, based on the program P20 written in the flash ROM 112). For this reason, each interrupt processing routine can be described in an arbitrary length from an arbitrary address on the SDRAM 111, and the memory resources of the SDRAM 111 are not wasted.

  In addition, since the instruction for jumping to the interrupt processing routine is stored in the SRAM 102 which can be accessed at high speed, it is possible to quickly shift to the interrupt processing routine on the SDRAM 111. In addition, the SRAM 102 that is temporarily used at the time of startup can be effectively used even during normal operation.

  As described above, in this embodiment, the CPU core 101 functions as the “processor” of the present invention. Further, the SRAM 102 and the SDRAM 111 function as “first RAM” and “second RAM” of the present invention, respectively. In addition, the boot ROM 103 and the flash ROM 112 function as the “starting ROM” and “storage medium” of the present invention, respectively, and these function integrally as “data holding means” of the present invention.

  In this embodiment, the program P21 for initializing the RAM controller corresponds to “RAM controller setting data” and “initialization program” of the present invention. The main programs P30 and P31 correspond to the “control program” of the present invention, and the program P30 particularly corresponds to the “interrupt processing program” of the present invention. Further, the data [P30] and [P31] obtained by compressing these correspond to the “compressed data” of the present invention, and the program P23 for decompressing the data corresponds to the “expanded program” of the present invention. Further, the information included in the interrupt call program P20 and indicating the start address of the interrupt processing routine on the SDRAM corresponds to the “position information” of the present invention.

  The present invention is not limited to the above-described embodiment, and various modifications other than those described above can be made without departing from the spirit of the present invention. For example, in the above embodiment, the main programs P30 and P31 are written in the flash ROM 112 as compressed data. However, the present invention is also effective in an electronic device in which a control program is written in the ROM in an uncompressed state. Conversely, any program that is in an uncompressed state in this embodiment may be compressed and written to the ROM. However, the program P23 for initializing the RAM controller 104 is preferably uncompressed. This is because such a program is simple and short so that the compression effect is not very much obtained, and it is written in an executable state without being decompressed. This is because the RAM controller 104 can be initialized.

  In the above embodiment, the SDRAM is used as the main memory and the flash ROM is used as the data holding means for storing the program. However, the present invention is not limited to this. For example, a DRAM or a ferroelectric memory can be used as the main memory. The data holding means may be a hard disk or an optical disk, for example. Further, it may be a storage medium that is detachable from the apparatus main body, such as a memory card. A mask ROM may be used if the device does not require rewriting of the program.

  In the above embodiment, the interrupt call program P20 and the startup programs P21 and P22 on the flash ROM 112 are transferred to the SRAM 102 at the same time. However, the interrupt call program P20 is not required at the time of startup, while the startup program at the normal operation time. Therefore, these may be transferred to the SRAM 102 at another timing. For example, at startup, only the startup program may be transferred to the SRAM 102 and executed, and the interrupt calling program P20 may be transferred to the SRAM 102 later. In this case, the activation program on the SRAM 102 is unnecessary after activation, and may be overwritten by the interrupt call program P20.

  In the above embodiment, the program P23 for decompressing the compressed data is executed on the SDRAM 111. However, the program may be transferred from the flash ROM to the SRAM and executed on the SRAM. When the decompression program is executed on the SRAM, the decompression process can be performed at high speed. However, when there is a possibility that the size of the decompression program becomes large, it is desirable to execute it on the SDRAM. If the program compression method may be fixed, the decompression program may be written in advance in the boot ROM.

  In the above embodiment, the RAM controller 104 is initialized by executing the initialization program P21 written in the flash ROM 112 on the SRAM 102. Instead, for example, the initialization program itself is the boot ROM 103. Are written in advance and control parameters necessary for the initialization process are written in the flash ROM 103, and the RAM controller is executed by the initialization program executed on the boot ROM 103 at the time of startup and the control parameters transferred from the flash ROM 112 to the SRAM 102. 104 may be initialized.

  Further, the present invention is not limited to the above-described printer, but is applied to all electronic devices configured to realize a desired function by executing a predetermined control program by a processor, such as a game device or an audio / video device. It is possible to apply.

1 is a block diagram showing an embodiment of an electronic device according to the present invention. The figure which shows the memory map in this embodiment. The figure which shows the content of the data written in boot ROM. The figure which shows the content of the data written in flash ROM. The figure which shows the flow of the starting process in this embodiment. The figure which shows the data content of each RAM in each time. The figure which shows the flow of a process at the time of interruption generation | occurrence | production. The conceptual diagram which shows the transition of the reading origin of the program after interrupt reception.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 100 ... ASIC, 101 ... CPU core (processor), 102 ... SRAM (first RAM), 103 ... Boot ROM (ROM for starting, data holding means), 104 ... RAM controller, 109 ... System bus, 111 ... SDRAM (second RAM) 112 ... Flash ROM (storage medium, data holding means), P21 ... Initialization program (RAM controller setting data, initialization program), P23 ... Expansion program, P31 ... Main program (control program), P30 ... Interrupt processing Program, [P30], [P31] ... compressed data

Claims (11)

A processor that executes a control program for operating the electronic device;
A first RAM directly connected to the system bus of the processor;
A second RAM connected to the system bus via a RAM controller;
A data holding unit connected to the system bus and having written therein the control program and RAM controller setting data for initializing the RAM controller in association with the second RAM;
The processor transfers the RAM controller setting data from the data holding unit to the first RAM, initializes the RAM controller based on the data, and then reads the control program from the data holding unit to read the second An electronic apparatus that transfers to a RAM and executes an activation process for starting execution of the control program on the second RAM.   In the data holding means, an initialization program for initializing the RAM controller is written as the RAM controller setting data, and the processor executes the initialization program transferred to the first RAM. The electronic device according to claim 1, wherein the RAM controller is initialized.   In the data holding means, compressed data obtained by compressing the control program and an decompression program for decompressing the compressed data and restoring the control program are written, and the processor stores the decompressed program. The electronic device according to claim 1, wherein the control program is restored on the second RAM by execution.   The electronic device according to claim 3, wherein the processor transfers the decompressed program read from the data holding unit to the first RAM and executes the decompressed program on the first RAM.   The electronic device according to claim 3, wherein the processor transfers the decompressed program read from the data holding unit to the second RAM and executes the decompressed program on the second RAM. The control program includes an interrupt processing program that is executed in response to an interrupt request. On the other hand, location information indicating the storage location of the interrupt processing program in the second RAM is written in the data holding means. And
The processor reads out the position information from the data holding means and stores it in the first RAM, and when receiving the interrupt request, the processor specifies the second RAM on the second RAM specified by the position information stored in the first RAM. 6. The electronic device according to claim 1, wherein the electronic device executes an interrupt processing program.   The electronic device according to claim 1, wherein the processor and the first RAM are mounted in a single package.   The data holding unit includes a boot ROM that stores a boot process program for causing the processor to execute the boot process, and a storage medium that stores the control program and the RAM controller setting data. 6. The electronic device according to any one of 6.   The electronic device according to claim 8, wherein the processor, the first RAM, and the boot ROM are mounted in a single package.   The electronic device according to claim 8, wherein the storage medium is a flash memory.   The electronic device according to claim 1, wherein the first RAM is an SRAM.

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