JP2009232445A - Mixer circuit and communication device including the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a mixer circuit that operates for a high-frequency wide-band signal like a UWB-IR signal and also intermittently operates. <P>SOLUTION: The mixer circuit 1 includes first and second source-grounded amplifying circuits 11 and 12, first and second signal output units 21 and 22, and first to fourth transistor groups 31 to 34 including transistors in (n) rows and (m) columns connected between the first and second source-grounded amplifying circuits, and first and second signal output ports, the first to fourth transistor groups 31 to 34 being driven with n×m control signals (G1 to G4). <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a mixer circuit used in a communication device, and more particularly to a mixer circuit suitable for UWB (Ultra Wide Band) communication and a communication device including the mixer circuit.

  UWB communication is a communication method that performs high-speed and large-capacity data communication using a very wide frequency band. There are conventional spread spectrum methods and Orthogonal Frequency Division Multiplexing (OFDM) as communication methods using wideband signals, but UWB uses wide-band communication using very short pulses. This is a system, and is also called impulse radio (IR) system communication. Hereinafter, this is referred to as UWB-IR or simply IR method. In the IR method, modulation / demodulation is possible only by time axis operation not based on conventional modulation, and it is expected that simplification of the circuit and reduction in power consumption can be expected (see Patent Documents 1, 2, and 3).

  First, FIG. 12A shows a typical block diagram of a conventional IR UWB transmitter / receiver, and FIGS. 12B and 12C are timing diagrams for explaining the outline of the operation. The operation and principle will be briefly described using these.

  Data to be transmitted is input to the terminal 1201. The pulse generation circuit 1202 generates a broadband pulse. At that time, the transmission data signal input to the terminal 1201 is received, and the generated pulse is subjected to predetermined modulation. As the modulation method, PPM (Pulse Position Modulation) for shifting the generation position of the generated pulse, two-phase modulation (BPM: Bi-Phase Modulation) for inverting the polarity of the generated pulse, etc. are often used. FIG. 12B shows the waveform of FIG. 12, and FIG. 12C shows the waveform of BPM. In the figure, a solid line and a broken line represent bit 1 or 0, respectively. The pulse thus generated and modulated is radiated to the space through the transmission antenna 1203.

  Next, an outline of a conventional typical receiving apparatus will be described. A signal received by the receiving antenna 1204 is amplified by a low noise amplifier (LNA) 1205 and sent to a mixer circuit 1206. At this time, equalization processing for removing distortion caused in the transmission path is appropriately performed. Examples of distortion include multipath distortion and frequency shift due to the Doppler effect.

  The reception signal amplified by the LNA 1205 is sent to the mixer circuit 1206 and multiplied with the template pulse generated by the template pulse generation circuit 1208. The mixer circuit 1206 is a kind of multiplication circuit and outputs a multiplication value of two signals (in this case, a reception signal and a template pulse). The signal output from the mixer circuit 1206 is smoothed by the integrating circuit 1210, and the bit information transmitted from the result is determined by the determining circuit 1212 and output from the terminal 1213 as a demodulated output. That is, the mixer circuit 1206 and the integrating circuit 1210 constitute a correlator, and the received signal and the template pulse correlation are calculated by this circuit. The determination circuit 1212 determines (demodulates) the transmitted signal based on the correlation calculation result.

  Based on the timing charts of FIGS. 12B and 12C, an outline of the operation of a conventional IR UWB transmitting / receiving apparatus is shown.

  The received signal b received by the receiving antenna 1204 and amplified by the LNA 1205 has a waveform as shown in FIG. In the following description, it is assumed that a solid line indicates that bit 1 is sent and a broken line indicates that bit 0 is sent. The template pulse generation circuit 1208 generates a template pulse c of bit 1 as shown in FIG. The mixer circuit 1206 multiplies the received signal b and the template pulse c and outputs a multiplication result signal e. The multiplication result signal e is integrated by the integration circuit 1210 and the high frequency component is removed, and then input to the determination circuit 1212. The determination circuit 1212 determines the information transmitted from the magnitude of the correlation value.

  In the above, the case where the signal of bit 1 is detected is shown. However, when the signal of bit 0 is detected, the template pulse generation circuit 1208 replaces the template pulse c for bit 1 with the template pulse d for bit 0. And the received signal b and the template pulse d are multiplied, and the mixer circuit 1206 multiplies the received signal b and the template pulse d, and outputs a multiplication result signal f.

  A reception method for calculating and demodulating the correlation with the template pulse as described above is generally called a synchronous detection method. In the synchronous detection method, the timing of the template pulse and the received signal must completely match. In the conventional example shown here, the synchronization tracking adjusts the template pulse generation timing of the template generation circuit 1208 so that the correlation value is always maximized from the determination result of the determination circuit 1212. Although this operation is generally not easy, it is said that stable operation can be performed even at a high frequency by making full use of recent device technology and digital signal processing technology.

  FIG. 12C is a diagram for explaining the outline of the operation of a conventional IR UWB transmitting / receiving apparatus in the case of BPM. The reception signal g received by the reception antenna 1204 and amplified by the LNA 1205 is multiplied by the template pulse h generated by the template generation circuit 1208 by the mixer circuit 1206 to become a multiplication result signal i. The multiplication result signal i can be determined whether the bit information transmitted is 1 or 0 by removing the high frequency component by the integrating circuit 1210 and determining the positive / negative by the determining circuit 1212. Even if a low-pass filter (LPF) is used instead of the integrating circuit 1210, it may be substantially equivalent to taking a correlation.

  In IR UWB communication, the signal is intermittent, and the signal is not continuous as in conventional narrowband communication. For this reason, by supplying power to the receiver circuit only when there is a received signal (or when the signal is expected to be received) and shutting off the circuit when there is no signal, the power consumption of the entire receiver is greatly increased. It is known that it can be reduced (see, for example, Non-Patent Document 1).

  In FIG. 12A, for example, the circuits shown in Non-Patent Document 1 and Non-Patent Document 2 can be used as the pulse generation circuit 1202 and the template generation circuit 1208. These circuits can be configured by digital circuits, and use CMOS (Complementary Metal Oxide Semiconductor) to consume power only when there is a signal, and consume power when there is no signal. Can be designed not to. In particular, Non-Patent Document 2 can generate a high-frequency short pulse near the limit of a semiconductor element constituting a circuit, and can generate a pulse having a very wide band, that is, a short width that can be used for UWB. Moreover, the power consumption when no signal is generated, that is, during standby, can be extremely reduced.

  Further, for example, Non-Patent Document 1 and Non-Patent Document 3 introduce a low-noise amplifier circuit 1205 that is operated only when there is a signal and in which power consumption is minimal at other times.

  FIG. 13 shows a low noise amplifier circuit 1300 of Non-Patent Document 3. The low noise amplifier circuit 1300 uses two identical circuits 1311 and 1312 for amplifying differential signals. In the circuit 1311, N-channel transistors 1301 and 1302 are called cascode connections, and are amplifier circuits in which a source-grounded N-channel transistor 1301 and a gate-grounded N-channel transistor 1302 are vertically connected, and are low-noise amplifier circuits. Often used.

  The differential signal RF + is applied to the terminal 1308, and is applied to the gate of the N-channel transistor 1301 that is grounded through the matching circuit including the capacitor 1305 and the inductance 1304. The signal amplified by the N-channel transistor 1301 is applied to the N-channel transistor 1302 whose gate is grounded (Bias2) by the terminal 1306 and is amplified. Then, the signal IF + is extracted by a voltage drop caused by the inductance 1303.

  A terminal 1309 is a terminal for applying a bias (Bias1) to the gate of the N-channel transistor 1301 having a common source, and a bias (Bias1) is applied through a resistor 1310. A terminal 1306 is a terminal that applies a bias (Bias2) to the gate of the N-channel transistor 1302. By controlling this bias (Bias2), a current flowing through the amplifier circuits (N-channel transistors 1301 and 1302) can be controlled. That is, when the amplifier circuit is operated, an appropriate bias voltage (Bias2) is applied, and when there is no need to operate the amplifier circuit, this voltage value is minimized (for example, ground potential). At this time, the current flowing through the path of the inductance 1303 and the N-channel transistors 1302 and 1301 becomes zero. Therefore, when there is no need to operate the amplifier circuit, the potential (Bias2) applied to the terminal 1306 is minimized. It can be stopped and the circuit current can be made zero. In UWB-IR, the power consumption of the low-noise amplifier circuit can be reduced by minimizing the potential of the terminal 1306 when there is no signal.

  As the mixer circuit 1206, a commonly used double balanced circuit type mixer (also referred to as a Gilbert circuit) can be used. However, when power is particularly concerned, a passive device using a switching element such as a CMOS transistor is used. A type mixer can also be used.

US Pat. No. 6,421,389 US Patent Application Publication No. 2003 / 0108133A1 US Patent Application Publication No. 2001/0033576 A CMOS IMPULSE RADIO ULTRA-WIDEBAND TRANCEIVER FOR 1Mb / s DATA COMMUNICATION AND ± 2.5cm RANGE FINDINGS T. Terada et.al, 2005 Symposium on VLSI Circuits Digest of Technical Papers, pp.30-33 A Low-Power Template Generator for Coherent Impulse-RadioUltra Wide-Band Receivers. Jose Luis et.al, Proceedings IEEE ICUWB, 2006 pp97-102 A 0.18μm CMOS Switchable Low-Power LNA for Impulse Radio Ultra Wide-Band Receivers. E. Barajas et.al, Proceedings IEEE ICUWB, 2006

  In the UWB-IR communication apparatus shown in FIG. 12A, it has been described that the power consumption of the entire circuit can be reduced by the intermittent operation technique in which the circuit is activated only when there is a signal. Naturally, each circuit element constituting the communication device is required to operate at a high speed enough to handle a UWB-IR high-frequency wideband signal. In particular, the pulse generation circuit 1202, the template generation circuit 1208, and the low-noise amplification circuit 1205 are An excellent circuit having the high-speed operation performance and the intermittent operation function has been devised. However, the mixer circuit (multiplier circuit) 1206 has no circuit suitable for such an operation. The conventional double balanced circuit type mixer cannot perform the intermittent operation as described above, and the passive mixer that does not consume power has a problem that the conversion gain is small.

  In addition, according to the conventional technology, a UWB-IR communication device, particularly a low noise amplifier circuit, a mixer, and a template generation circuit, which are essential components in the receiving device, must be individually designed and combined. There are challenges.

  SUMMARY An advantage of some aspects of the invention is to solve at least a part of the problems described above, and the invention can be implemented as the following forms or application examples.

[Application Example 1]
A mixer circuit for outputting a first output signal obtained by mixing a first input signal and a second input signal and a second output signal, wherein the first source grounding amplifies the first input signal. An amplifier circuit; a second common-source amplifier circuit that amplifies the second input signal; a first signal output unit that outputs the first output signal; and a second signal that outputs the second output signal. N-row m-column (n is an integer of 2 or more, m is an integer of 2 or more) transistor connected between the signal output section of the first and second common source amplifier circuits and the first signal output section A second transistor group including n rows and m columns of transistors connected between the first common-source amplifier circuit and the second signal output unit; and N-row m-column connected between the common-source amplifier circuit and the first signal output section A third transistor group including a transistor; a fourth transistor group including an n-row m-column transistor connected between the second common-source amplifier circuit and the second signal output unit; 1. A mixer circuit, comprising: n × m control signals for driving one transistor group, the second transistor group, the third transistor group, and the fourth transistor group.

  According to this configuration, the first to fourth transistor groups are appropriately biased by n × m control signals, so that the mixer circuit can have the function of a low noise amplifier circuit. Further, various mixing operations can be performed depending on how to give n × m control signals to the gates of the first to fourth transistor groups. That is, when a potential that interrupts the first to fourth transistor groups is included in the n × m control signals, the circuit can be shut off and the operation can be stopped by applying this potential. As a result, the operation of the circuit when it is not necessary can be cut off to reduce power consumption. In addition, a signal input operation having a frequency higher than that of the control signal can be equivalently performed by a combination of n × m control signals. Particularly, since the control of the first to fourth transistor groups can be controlled by n × m control signals, the combination of n × m control signals is equivalent to a signal input having a frequency higher than that of the control signal. Operation is possible. In particular, when dealing with UWB-IR signals, it is possible to synthesize equivalently internally by a control signal without using a UWB-IR template pulse, and to multiply the equivalently synthesized template pulse and the input signal. Is possible.

[Application Example 2]
In the mixer circuit described above, at least one of the n × m control signals includes the first transistor group, the second transistor group, the third transistor group, and the fourth transistor group. A mixer circuit characterized in that it includes a potential for interrupting.

  According to this configuration, when the operation of the circuit is unnecessary, the circuit can be shut off and the operation can be stopped by applying a potential for shutting off the first to fourth transistor groups. This makes it possible to reduce the power consumption by interrupting the operation of the mixer circuit when unnecessary. In particular, when handling an intermittent signal such as UWB-IR, it is possible to reduce the power consumption by stopping the operation of the circuit when no pulse signal is input.

[Application Example 3]
In the mixer circuit described above, the n × m control signals are binary, and one potential of the binary values is the first transistor group, the second transistor group, and the third transistor. The potential that cuts off the transistor group and the fourth transistor group, and the other potential is applied to the first transistor group, the second transistor group, the third transistor group, and the fourth transistor group. A mixer circuit having a predetermined bias value to be given.

  According to this configuration, when the operation of the mixer circuit is unnecessary, the mixer circuit can be cut off and the operation can be stopped by applying a potential to cut off the first to fourth transistor groups. In addition, by using a bias value to apply other potentials to the first to fourth transistor groups, the mixer circuit can be a cascode amplifier circuit, thereby having the function of a low noise amplifier circuit in addition to the mixer function. It becomes possible to make it.

[Application Example 4]
A communication apparatus comprising the mixer circuit described above.

  According to this configuration, the mixer circuit has the functions of a low-noise amplifier circuit, the function of the mixer circuit, various control functions based on n × m control signals, and the function of cutting off the mixer circuit and saving power consumption. The configuration of the communication device using this mixer circuit can be greatly simplified.

[Application Example 5]
A communication apparatus that receives a UWB-IR signal including the mixer circuit described above, wherein the n × m control signals of the mixer circuit are wider than a template pulse of the UWB-IR signal. A communication device including a wide pulse signal.

  According to this configuration, the first to fourth transistor groups are controlled by the control signal having a width (that is, low frequency) wider than the UWB-IR template pulse having the above configuration, so that the UWB is equivalently equivalent in the mixer circuit. Since a -IR template signal can be generated, it is not necessary to input a high-frequency broadband signal such as a UWB-IR template pulse to the mixer circuit. Furthermore, the mixer circuit has the functions of a low-noise amplifier circuit, the function of the mixer circuit, the function of synthesizing the template signal by the control signal, and the function of cutting off the mixer circuit and saving power consumption. The configuration of the device can be greatly simplified. This is particularly effective in a communication apparatus that handles intermittent signals such as UWB-IR.

[Application Example 6]
A communication apparatus including the mixer circuit described above, wherein the n × m control signals of the mixer circuit include a signal having at least a frequency f ₁ component and a frequency f ₂ component. hints, frequency f _r of the received signal, the communication apparatus characterized by matching either one of the sum or difference between the frequency f ₁ and the frequency f _2.

According to this configuration, the mixer circuit has the functions of a low-noise amplifier circuit, the function of the mixer circuit, various control functions based on the control signal, and the function of cutting off the mixer circuit and saving power consumption. The configuration of the existing communication apparatus can be greatly simplified. In particular, when a signal having two frequency components of frequencies f ₁ and f ₂ is used as a control signal, a signal of f _r − (f ₁ ± f ₂ ) can be obtained as an output signal. Accordingly, when (f ₁ + f ₂ ) or (f ₁ −f ₂ ) is selected so as to coincide with f _r , the received signal can be directly frequency-converted to baseband. As a result, a receiving device configuration by direct conversion becomes possible, and since the same local oscillation frequency as the frequency of the received signal is not used, the problem of DC offset which is a problem in the conventional direct conversion type receiving device can be avoided.

  Hereinafter, embodiments of the mixer circuit will be described with reference to the drawings.

(First embodiment)
<Configuration of mixer circuit>
First, the configuration of the mixer circuit according to the first embodiment will be described with reference to FIGS. 1 and 2. FIG. 1 is a circuit diagram showing a configuration of a mixer circuit according to the first embodiment. FIG. 2 is a timing chart showing the operation of the mixer circuit according to the first embodiment.

  As shown in FIG. 1, the mixer circuit 1 includes a common source amplifier circuit 11 that is a first common source amplifier circuit, a common source amplifier circuit 12 that is a second common source amplifier circuit, and a first signal output unit. , A signal output unit 22 that is a second signal output unit, a transistor group 31 that is a first transistor group, a transistor group 32 that is a second transistor group, and a third transistor The transistor group 33 is a group, and the transistor group 34 is a fourth transistor group.

  The common source amplifier circuit 11 includes an N-channel transistor 101 having a source terminal grounded and a drain terminal connected to the wiring 13, a capacitor 105, an inductance 107, and a resistor 109. The capacitor 105 and the inductance 107 are connected in series between the input terminal 103 and the gate terminal of the N-channel transistor 101. The resistor 109 is connected between a connection line between the capacitor 105 and the inductance 107 and the input terminal 111. A differential signal RF + that is a first input signal is input to the input terminal 103.

  The grounded source amplifier circuit 12 includes an N-channel transistor 102 having a source terminal grounded and a drain terminal connected to the wiring 14, a capacitor 106, an inductance 108, and a resistor 110. The capacitor 106 and the inductance 108 are connected in series between the input terminal 104 and the gate terminal of the N-channel transistor 102. The resistor 110 is connected between a connection line between the capacitor 106 and the inductance 108 and the input terminal 111. The differential signal RF− that is the second input signal is input to the input terminal 104.

  A bias voltage Bias is supplied to the input terminal 111. The bias voltage Bias is applied to the gate terminal of the N-channel transistor 101 via the resistor 109 and the inductance 107. The bias voltage Bias is applied to the gate terminal of the N-channel transistor 102 via the resistor 110 and the inductance 108.

  The signal output unit 21 includes an inductance 134 connected between a power supply terminal 136 for applying the power supply voltage VDD and the wiring 23. An output terminal 121 that outputs an output signal IF− that is a first output signal is connected to the wiring 23.

  The signal output unit 22 includes an inductance 135 connected between the power supply terminal 136 and the wiring 24. An output terminal 120 that outputs an output signal IF + that is a second output signal is connected to the wiring 24.

  The transistor group 31 includes (n =) 2 rows (m =) 2 columns of N-channel transistors 112, 113, 114, and 115. The N channel transistors 112 and 113 are connected in series between the wiring 23 and the wiring 13. The N channel transistors 114 and 115 are connected in series between the wiring 23 and the wiring 13. The gate terminal of the N-channel transistor 112 is connected to the input terminal 130. The gate terminal of the N channel transistor 113 is connected to the input terminal 131. The gate terminal of the N channel transistor 114 is connected to the input terminal 132. The gate terminal of the N channel transistor 115 is connected to the input terminal 133.

  The transistor group 32 is composed of N-channel transistors 116, 117, 118, and 119 of 2 rows and 2 columns. The N channel transistors 116 and 117 are connected in series between the wiring 24 and the wiring 13. The N channel transistors 118 and 119 are connected in series between the wiring 24 and the wiring 13. The gate terminal of the N channel transistor 116 is connected to the input terminal 131. The gate terminal of the N channel transistor 117 is connected to the input terminal 132. The gate terminal of the N channel transistor 118 is connected to the input terminal 133. The gate terminal of the N-channel transistor 119 is connected to the input terminal 130.

  The transistor group 33 is composed of N-channel transistors 126, 127, 128, and 129 of 2 rows and 2 columns. The N channel transistors 126 and 127 are connected in series between the wiring 23 and the wiring 14. The N channel transistors 128 and 129 are connected in series between the wiring 23 and the wiring 14. The gate terminal of the N channel transistor 126 is connected to the input terminal 131. The gate terminal of the N-channel transistor 127 is connected to the input terminal 132. The gate terminal of the N-channel transistor 128 is connected to the input terminal 133. The gate terminal of the N channel transistor 129 is connected to the input terminal 130.

  The transistor group 34 is composed of N-channel transistors 122, 123, 124, and 125 of 2 rows and 2 columns. The N channel transistors 122 and 123 are connected in series between the wiring 24 and the wiring 14. The N channel transistors 124 and 125 are connected in series between the wiring 24 and the wiring 14. The gate terminal of the N-channel transistor 122 is connected to the input terminal 130. The gate terminal of the N-channel transistor 123 is connected to the input terminal 131. The gate terminal of the N-channel transistor 124 is connected to the input terminal 132. The gate terminal of the N-channel transistor 125 is connected to the input terminal 133.

  Four (n × m = 2 × 2 =) four control signals G1, G2, G3, and G4 are input to the input terminals 130, 131, 132, and 133, respectively.

  In the present embodiment, a case of a UWB-IR signal is shown as an example of the differential signals RF + and RF−, and a pulse train having a period T and a number of pulse fingers = 4 periods as shown in FIG. The differential signals RF + and RF− as shown in FIG. 2 can be obtained, for example, when the above UWB-IR signal is received by a balanced antenna. These differential signals RF + and RF− are applied to the gate terminals of the N-channel transistors 101 and 102 through the input matching circuits by the capacitors 105 and 106 and the inductances 107 and 108, respectively.

  The N-channel transistors 112 and 113 connected in series can be regarded as one transistor having a channel length of L1 + L2 if the same voltage is applied to each gate terminal. Here, L1 and L2 are the channel lengths of the N-channel transistors 112 and 113, respectively. If the N-channel transistors 112 and 113 connected in series are considered as one transistor and the drain of the N-channel transistor 101 is connected to this, these N-channel transistors 112, 113 and 101 are shown in FIG. It can be regarded as a conventional cascode connection.

  In addition to the above N channel transistors 112 and 113, N channel transistors 114 and 115 connected in series, N channel transistors 116 and 117, and N channel transistors 118 and 119 are connected in parallel to the N channel transistor 101. Is done. The gate terminals of these eight N-channel transistors 112 to 119 are controlled by control signals G1, G2, G3, and G4 given to the input terminals 130, 131, 132, and 133 by connection as shown in FIG.

Control signals G1, G2, G3, and G4 as shown in FIG. 2 are applied to the input terminals 130, 131, 132, and 133, respectively. These control signals G1 to G4 take a binary value of a minimum value V ₀ and a maximum value V ₁ and change with a small transition time in the order as shown in FIG. How to make such a signal will be described later. Further, for the sake of later explanation, the time points at which each signal transitions are defined as t1, t2, and t9 as shown in FIG. In FIG. 2, only the portion where the intermittent UWB-IR signal exists is shown enlarged. Actually, the time before the time point t1 without the signal and after the time point t9 is much longer than the period of the time points t1 to t9.

Now, the minimum value V ₀ is set to a low voltage value that cuts off the N-channel transistors 112 to 119 and the N-channel transistors 122 to 129 in FIG. 1, and the maximum value V ₁ is set to the N-channel transistors 112 to 112 connected in series. 119 and 122 to 129 are gate bias values when viewed as one transistor in the common-gate stage. When the minimum value V ₀ and the maximum value V ₁ are selected as described above, the N-channel transistors 112 and 113 have a period of time t2 to t3 when both of the control signals G1 and G2 become the maximum value V ₁ as shown in FIG. It operates as a gate grounding stage during a period of time t6 to t7. Similarly, N-channel transistors 114 and 115, the control signal G3, G4 operates as a gate grounded stage during the period and the time t8~t9 time t4~t5 together a maximum value V _1, also N-channel transistor 126 , 127, operates as a grounded gate stage during the period and the time t7~t8 time t3~t4 the control signal G2, G3 is the maximum value V ₁ together, N-channel transistors 128 and 129, control signals G1, G4 is operated as grounded gate stage during the period and the time t5~t6 time t1~t2 together a maximum value V _1.

  Therefore, a signal amplified (inverted) by the N-channel transistor 102 and amplified by the grounded gate stage by the N-channel transistors 128 and 129 is detected in the inductance 134 during the period from the time point t1 to t2. Similarly, during the period from time t2 to time t3, the signal amplified by the N-channel transistor 101 and further amplified by the N-channel transistors 112 and 113 connected in series is detected by the inductance 134. Similarly, the drain outputs of the N-channel transistors 101 and 102 are switched every period T / 2, and a signal amplified in the grounded gate stage by the series transistor is detected by the inductance 134 and output to the output terminal 121 as the output signal IF−. Is done.

  On the other hand, the inductance 135 is connected to the inductance 135 in a complementary manner, that is, the period from the time t3 to the time t4 and the period from the time t7 to the time t8 by the N channel transistors 116 and 117, and the time t1 to the time t2 by the N channel transistors 118 and 119. During the period and time t5 to t6, the drain output of the N-channel transistor 101 is gate-grounded and amplified by the N-channel transistors 122 and 123, and from time t2 to t3 and from time t6 to t7, By 125, the drain output of the N-channel transistor 102 is grounded at the gate during the period from time t4 to t5 and from time t8 to t9, and output to the output terminal 120 as the output signal IF +.

In summary, when the maximum value V ₁ and the minimum value V ₀ are applied to the true and false values of the binary signal, respectively, when the logical expression Ga = G1 × G4 + G2 × G3 is true, the output terminal 120 is connected to the input terminal 103. The input differential signal RF + is (inverted) amplified and output, and the differential signal RF− input to the input terminal 104 is (inverted) amplified and output to the output terminal 121. When the logical expression Gb = G1 × G2 + G3 × G4 is true, the differential signal RF− input to the input terminal 104 is amplified (inverted) and output to the output terminal 120, and the input terminal 121 is input to the output terminal 121. The differential signal RF + entered in 103 is amplified and output. When neither of the two logical expressions Ga and Gb is true, that is, before time t1 or after time t9, the mixer circuit 1 is cut off and does not consume power. This means that the multiplication result of the binary signal difference Ga−Gb and the differential signals RF + and RF− by the two logical expressions Ga and Gb is output.

  By setting the control signals G1 to G4 as shown in FIG. 2, the binary signal difference Ga-Gb shown in FIG. 2 becomes equivalent to the template signal used for UWB-IR communication. It is possible to provide some functions of the multiplication circuit and the template generation circuit. That is, in the conventional UWB-IR receiver configuration diagram shown in FIG. 12A, the low noise amplification circuit 1205, the multiplication circuit 1206, and a part of the template generation circuit 1208 can be used. In the mixer circuit 1 of this embodiment, it is not necessary to supply a template pulse from the outside. In UWB-IR communication, a template pulse used as a template signal is very high speed and is often about the limit frequency of the elements constituting the device, but the mixer circuit 1 of this embodiment generates such a high speed signal. There is no need to do. Further, since the mixer circuit 1 of the present embodiment does not consume power when there is no template pulse, there is no need for a switch circuit for controlling on / off of the circuit power supply as in the prior art.

  FIG. 3 is an example of the logic circuit 300 that generates the control signals G1 to G4 described above, and FIG. 4 is a timing diagram of the logic circuit 300 that generates the control signals G1 to G4. Hereinafter, for the sake of explanation, the outputs of the NOR circuits (NOR) 301, 302, 303, and 304 are Q1, Q2, Q3, and Q4, respectively, and for example, (Q1, Q2, Q3) , Q4) = (L, L, H, H) or simply (LLHH). This indicates that the output values of the NORs 301 and 302 are false and the output values of the NORs 303 and 304 are true.

  The control circuit 305 receives the activation signal SS shown in FIG. 4 input to the terminal 311 and generates an initialization signal IS for initializing the logic circuit 300. Further, false (L) is always input to the terminal 310. The NORs 301 and 304 may be 2-input NORs, but 3-input NORs are connected in order to maintain symmetry with the NORs 302 and 303. In the logic circuit 300, the output signal Q1 of the NOR 301 is Q1 = X (Q2 + Q4), the output signal Q2 of the NOR 302 is Q2 = X (Q1 + Q3 + IS), the output signal Q3 of the NOR 303 is Q3 = X (Q1 + Q4 + IS), and the output of the NOR 304 The signal Q4 is Q4 = X (Q2 + Q3). Here, X is a symbol representing the negation of logic and represents the negation of the logic in front of a logical expression or logical value.

  The operation of the logic circuit 300 of FIG. 3 will be described below with reference to the timing diagram of FIG.

  First, in a stationary state before time tb, the initialization signal IS generated by the control circuit 305 is H, and therefore (Q2, Q3) = (L, L). As a result, (Q1, Q4) = (L, H). That is, the state of (Q1, Q2, Q3, Q4) = (L, L, L, H) is continuously held before time tb.

  When the activation signal SS rises at the time ta, in response to this, the control circuit 305 falls the initialization signal IS in order to operate the circuit. That is, IS = L is changed at time tb with a delay from time ta.

  When the initialization signal IS = L, NOR 301 and NOR 302 form an RS flip-flop circuit. Since the NOR 303 and the NOR 304 similarly form an RS flip-flop circuit and are connected so that positive feedback is applied, the logic circuit 300 starts oscillation. That is, Q1, Q2, Q3, and Q4 after time t1 change in the order of (LHLH) → (LHHL) → (HLHL) → (HLLH) with a delay in the circuit operation of NOR. The control circuit 305 monitors Q3 or Q4. If the initialization signal IS = H when the number of pulse fingers reaches a predetermined value, the control circuit 305 can stop the oscillation and return to the initial stationary state. be able to.

  The output signals Q1, Q2, Q3, and Q4 become the control signals G1, G2, G3, and G4 in FIG. 1 by corresponding to G1 = Q2, G2 = Q3, G3 = Q1, G4 = Q4. The template pulse generated by synthesizing the output signals Q1, Q2, Q3, and Q4 generated by the logic circuit 300 can be set to a transition time determined by the delay amount of the NORs 301 to 304. Although it is possible to cope with short template pulses that can be used for UWB-IR communication, the control signals G1, G2, G3, and G4 are signals that are much slower than the template pulses. Make configuration very easy. The frequency adjustment when used as a template pulse is controlled by a method such as controlling the power supply voltage of the NOR 301 to 304 or adjusting the load amount by adding a small-capacity capacity as a load to the output. It is possible to adjust to the frequency.

  FIG. 5 shows an example of another logic circuit 500 that generates the control signals G1 to G4. In FIG. 5, a differential amplifier circuit is formed by transistors 501, 502, 503, 504, and 505. The N-channel transistor 501 forms a current source that limits the circuit current and limits the circuit current. By controlling this circuit current, the response time of the differential amplifier circuit changes, and the amount of delay for signal transmission can be controlled. That is, the pulse width of a signal generated at the gate of the N-channel transistor 501 can be controlled in accordance with the voltage VS applied from the terminal 516.

  P-channel transistors 504 and 505 are loads of a differential amplification stage formed by N-channel transistors 502 and 503. The gates of P-channel transistors 504 and 505 are connected to the drains of each other, and a so-called cross-coupled circuit is formed. Form. This connection emphasizes each other's changes and minimizes signal transitions. The N-channel transistor 507 is a switch for setting an initial state, and can be switched between an initial state and an operating state by an initialization signal IS applied to the terminal 515. That is, when the potential of the initialization signal IS is high, the N-channel transistor 507 is forcibly turned on, the drain potential (Q2) of the P-channel transistor 505 is forcibly set to L, and the logic circuit 500 is set to the initial state. . When the potential of the initialization signal IS is low, the N-channel transistor 507 is turned off and the logic circuit 500 is in an operating state. The N-channel transistor 506 is always off because the gate potential is always set to the ground potential. The N-channel transistor 506 is added to obtain a good balance (symmetry) of the operation of the differential amplifier, although it does not directly affect the operation.

  The circuit composed of the transistors 508 to 514 constitutes a differential amplifier circuit similarly to the circuit composed of the transistors 501 to 507 described above. By cascading these two differential amplifier circuits and connecting them as shown in FIG. 5, when the output is returned to the input side to be positive feedback, an oscillation circuit having a four-phase output is obtained. The control signals G1, G2, G3, and G4 can be obtained by controlling the initialization signal IS applied to the terminal 515 by the same operation as the circuit of FIG. That is, when the output signals of the drains of the transistors 504, 505, 511, and 512 are Q1, Q2, Q3, and Q4, and are buffered and amplified by the buffer 518, the control signals G3, G1, G2, and G4 are obtained.

  According to the present embodiment described above, the following effects can be obtained.

  In the mixer circuit 1 of the present embodiment, an intermittent operation that shuts off the mixer circuit 1 can be performed by the control signals (G1 to G4) given to the series-connected transistors when the circuit operation is not necessary. As a result, if the mixer circuit 1 is used in a communication device such as UWB-IR using intermittent signals, the power consumption of the entire device can be reduced.

  In addition, the mixer circuit 1 of the present embodiment can be regarded as a circuit in which a mixer is incorporated in the grounded gate stage in the cascode connection of the low noise amplifier circuit, so that the function of the low noise amplifier circuit is provided in addition to the mixer function. Can do. In addition, current flows from the power source separately in the low-noise amplifier circuit and the mixer circuit, whereas in the mixer circuit 1, the current flows through one path. Therefore, the power consumed by the circuit can be reduced as compared with the circuit configuration according to the conventional technique.

  Further, conventionally, a template waveform is input to the mixer and multiplication with the received signal is performed, whereas in the mixer circuit 1, a template pulse is synthesized by logic synthesis of the grounded gate stage. For this reason, it is not necessary to input a template pulse to the mixer circuit 1, and it is only necessary to input a signal having a frequency extremely lower than that of the template pulse. That is, it is not necessary to generate a template pulse for the input of the mixer circuit 1. This greatly facilitates circuit design in cases such as UWB-IR where high frequency template pulses that are close to the limits of the circuit elements must be handled.

  In the conventional UWB-IR receiver configuration, the template pulse input to the mixer is required to have a large amplitude, and therefore a drive circuit for amplifying the template pulse generated by an appropriate template generation circuit is required. The design of these circuits is difficult because the frequency to be handled is high, but in this embodiment, a template pulse can be synthesized by a combination of control signals input to the mixer circuit 1, so that the signal input to the mixer circuit 1 is A signal having a frequency considerably lower than that of the template pulse is sufficient and the design is easy. It is possible to omit a circuit such as a drive circuit that is necessary in the prior art, which also enables further reduction in power consumption.

  Furthermore, when configuring a so-called direct conversion receiver that uses a conventional mixer circuit to drop the received signal directly to the baseband, the local signal generated by the local oscillator is transferred to the radio signal (differential signal RF) side. There is a serious problem that a leak occurs and the signal is reflected by a circuit mismatch or the like, and this causes a so-called DC offset that is converted into a direct current component by its own local signal. In the mixer circuit 1 of the present embodiment, the signal corresponding to the local signal can be prevented from having the same frequency component as that of the radio signal, so that the problem such as the DC offset as described above does not occur. The mixer circuit 1 of the present embodiment is highly effective in communication using conventional narrow band signals.

(Second Embodiment)
Next, a second embodiment of the mixer circuit will be described. In the first embodiment, using the inductances 134 and 135 in the signal output units 21 and 22, the amplified current signal is converted into a voltage and extracted. In general, when a mixer circuit (multiplier circuit) is used for frequency conversion as a multiplier circuit used for UWB-IR or a mixer circuit of a receiver, the frequency of a signal to be extracted is lower than that of an input signal. In such a case, a large value of inductance is required to extract a signal by the inductance. When an inductance is formed on an integrated circuit, it is difficult to mount a large inductance with a sufficient amplitude value. In such a case, the signal amplitude may be reduced.

  In the second embodiment, two examples corresponding to the above cases are shown. FIG. 6 shows an example of a mixer circuit 600 using signal output units 621 and 622 in which resistors 601 and 602 are connected instead of the inductances 134 and 135 shown in FIG. With this configuration, the mixer circuit 600 can extract a signal having a low frequency component regardless of the inductance value. In the mixer circuit 600 of FIG. 6, a large voltage drop is caused by the resistors 601 and 602 in order to extract a large signal. Therefore, it is necessary to increase the power supply voltage VDD in order to obtain a large signal.

  FIG. 7 shows an example of a mixer circuit 700 using signal output units 721 and 722 instead of the signal output units 21 and 22 of FIG. The mixer circuit 700 can extract a large signal without a large voltage drop. P-channel transistors 703 and 704 are diode-connected, and each of P-channel transistors 705 and 706 forms a current mirror circuit. That is, the signal current detected by the P channel transistors 703 and 704 is copied and output by the P channel transistors 705 and 706. Since these current mirror circuits are current sources and have a sufficiently high impedance, it is easy to design an integration circuit connected to a subsequent stage for forming a correlation circuit. That is, sufficient performance can be obtained by simply connecting the capacitors 707 and 709 as shown in the figure. The switches 708 and 710 are reset switches for discharging the charge charged in the capacitor at the start of integration and returning it to the initial state.

(Third embodiment)
Next, a third embodiment of the mixer circuit will be described. In the first embodiment, the case where the transistor groups 31 to 34 are configured by transistors of 2 rows and 2 columns is shown. When the number of transistors in the transistor groups 31 to 34 is increased, the pulse width of the control signal can be further increased. This lowers the frequency component of the control signal and facilitates circuit design. In the third embodiment, a mixer circuit 800 using transistor groups 831 to 834 configured by transistors in 2 rows and 4 columns will be described. The mixer circuit 800 can multiply the template pulse having the number of pulse fingers of 4 as in the first embodiment as an example by only one transition of each control signal. However, the present invention is not limited to this case. Increasing the number of grounding stages makes it possible to detect pulses with a larger number of pulse fingers.

  FIG. 8A shows a mixer circuit 800 of the third embodiment, and FIG. 8B is an example of a circuit diagram for generating a control signal. 8A is the same as FIG. 1 except for the gate-grounded stage using a series transistor, and the same operation as that of the circuit of FIG. Omitted.

  In FIG. 8A, a terminal group surrounded by an alternate long and short dash line ellipse 835 is a terminal for inputting 16 control signals D1 to D8 and XD2 to XD9. The gates 801 to 832 are connected. A method for generating the control signals D1 to D8 and XD2 to XD9 will be described later with reference to FIG. FIG. 9 shows control signals D1 to D8, XD2 to XD9 and timing charts for supplementary explanation of their operations.

  The N-channel transistors 801 to 808 of the transistor group 831 amplify the signal amplified by the N-channel transistor 101 in the common-source stage, and output the signal to the output terminal 121 by the inductance 134.

  The N-channel transistors 809 to 816 of the transistor group 832 amplify the signal amplified by the N-channel transistor 101 in the common-source stage, and output the signal to the output terminal 120 by the inductance 135.

  The N-channel transistors 817 to 824 in the transistor group 834 amplify the signal amplified by the N-channel transistor 102 in the common-source stage, and output the signal to the output terminal 120 through the inductance 135.

  The N-channel transistors 825 to 832 in the transistor group 833 amplify the signal amplified by the N-channel transistor 102 in the common-source stage and output the signal to the output terminal 121 through the inductance 134.

Similarly to the description in the first embodiment, the control signals D1 to D8 and XD2 to XD9 take the binary values of the minimum value V ₀ and the maximum value V _1. 801 and 802 operate as a grounded gate amplifier circuit when the logical product of the control signals D1 and XD2 is true, and are cut off at other times. The other N-channel transistors 803 to 808 of the transistor group 831 form three series pairs, and each pair has a gate-grounded amplification when the logical product of D3 and XD4, D5 and XD6, D7 and XD8 is true. Operates as a circuit and shuts off at other times. That is, the transistor group 831 operates as a common-gate amplifier circuit when the logical product of D _i-1 and XD _i is true when i is an even number, and is cut off at other times.

Since the N-channel transistors 817 to 824 of the transistor group 834 have exactly the same connection as the N-channel transistors 801 to 808 of the transistor group 831, when the logical product of D _i−1 and XD _i is true, the gate-grounded amplifier circuit Operates at other times and shuts off at other times.

The N-channel transistors 809 to 816 of the transistor group 832 and the N-channel transistors 825 to 832 of the transistor group 833 operate as a gate-grounded amplifier circuit when the logical product of D _i and XD _{i + 1} is true, and otherwise Cut off.

Therefore, when the logical product of D _i−1 and XD _i is true, the signal that is grounded by the N channel transistor 101 is grounded by the N channel transistors 801 to 808 of the transistor group 831 and is output to the output terminal 121. Is output. At this time, the signal ground-amplified by the N-channel transistor 102 is gate-grounded by the N-channel transistors 817 to 824 of the transistor group 834 and output to the output terminal 120.

When the logical product of D _i and XD _{i + 1} is true, the signal that is ground-amplified by the N-channel transistor 101 is gate-grounded by the N-channel transistors 809 to 816 of the transistor group 832 and output to the output terminal 120. The At this time, the signal ground-amplified by the N-channel transistor 102 is gate-grounded by the N-channel transistors 825 to 832 of the transistor group 833 and output to the output terminal 121.

In the logical product of D _i-1 and XD _{i and} the logical product of D _i and XD _{i + 1} , the sum (total logical sum) is obtained for all cases where i = 2 to 8, and SUM1 and SUM2 in FIG. It becomes like this. When these two signals SUM1 and SUM2 are regarded as differential signals, they are template signals used for UWB-IR.

As described above, the control signals D1 to D8 and XD2 to XD9 are appropriately generated, and the signals generated by the logical product of D _i-1 and XD _{i and} the logical product of D _i and XD _{i + 1} are templates. If the pulse is used, the output terminals 120 and 121 of the mixer circuit 800 are subjected to multiplication after amplification of the template pulse and the differential signals RF + and RF− applied to the input terminals 103 and 104. Is obtained.

  Hereinafter, a method for generating the control signals D1 to D8 and XD2 to XD9 will be described with reference to the logic circuit of FIG. 8B and the timing chart showing the operation of FIG.

  The delay circuits 841 to 849 are differential delay circuits. The delay circuits 841 to 849 are delay circuits that differentially output a differential signal with a predetermined delay. The delay circuits 841 to 849 include a flip-flop circuit configured by the NORs 301 and 302 (or 303 and 304) in FIG. A differential amplifier circuit using transistors 501 to 505 (or 508 to 512) can be used. A circuit in which the output of a current-limited inverter is coupled with a cross-coupled inverter is also often used.

  When D0 and XD0 are input to the delay circuit 841 as activation signals, the control signals XD1 and D1 are output with a predetermined delay (FIG. 9). Thereafter, the delay circuits 842 to 849 sequentially output the signals with delay, and D2 to D9 and XD2 to XD9 are output. In the mixer circuit 800 of the third embodiment, XD1 and D9 are not used.

In the logical product of D _i-1 and XD _{i and} the logical product of D _i and XD _{i + 1} , the sum (total logical sum) is obtained for all cases where i = 2 to 8, and SUM1 and SUM2 in FIG. It becomes like this. When these two waveforms are viewed as differential signals, they are pulses of 4 pulse fingers used for UWB-IR, and the delay amount of delay circuits 841 to 849 is controlled to coincide with the pulse period used for UWB-IR. If it does, it will become a template waveform used for UWB-IR. In the first embodiment, the control circuit 305 that counts the number of fingers is required to define the number of pulse fingers. However, in the third embodiment, the number of pulse fingers depends on the number of delay circuits and the number of gate ground amplification stages. Such a circuit is not necessary because it is automatically determined by the number of series transistors. As the number of pulse fingers increases, the number of series transistors also increases, and there are concerns about the effects of parasitic elements such as parasitic capacitance, but the number increases in the grounded gate stage. The impedance is sufficiently lower than that of the parasitic element, and its influence does not increase.

  Therefore, by using the mixer circuit 800 of the third embodiment, it is possible to amplify the received signal with low noise without generating a UWB-IR template signal and obtain a multiplication result with the template signal. Moreover, when there is no signal reception, the circuit current can be turned off, so that standby power consumption is extremely low. In addition, since it is not necessary to generate a template pulse and one template pulse can be generated by one state transition of the delay circuit array, a circuit that requires high-speed operation can be minimized.

In the above description, a signal based on the logical product of D _i−1 and XD _{i and} the logical product of D _i and XD _{i + 1} is generated at the rising edge of the activation signal D0, and multiplication with the received signal is performed at that time. If the circuit is slightly changed, it is possible to execute multiplication with the template signal even at the fall of D0. At this time, multiplication is possible at both rising and falling signal transitions in which the delay circuit array consumes power, so that the amount of information that can be received per circuit power consumption can be increased. For this purpose, each control signal is applied to the gate of the series transistor in the common-gate amplification stage so that the circuit operates in the state of the logical product of D _i-1 and XD _{i and} the logical product of D _i and XD _{i + 1.} Further, in addition to the transistor groups 831 to 834, four transistor groups are formed and connected in parallel.

  In the mixer circuit 800 of the third embodiment, low-noise amplification, UWB-IR that performs multiplication of the amplified signal and the template signal without inputting a high-speed template signal from the outside, and handles intermittent signals. Such a communication apparatus also has a switch function that enables intermittent operation that consumes power only when there is a particularly effective signal. As a result, when the mixer circuit 800 of the third embodiment is used in a UWB-IR communication device, particularly a receiving device, the power consumption of the device can be greatly reduced and the configuration can be simplified.

(Fourth embodiment)
Next, a fourth embodiment of the mixer circuit will be described. FIG. 10 shows an example of configuring a UWB-IR communication apparatus using the mixer circuit of the above embodiment. FIG. 10A illustrates a transmission device. Data to be transmitted is input to the terminal 1001. The pulse generation circuit 1002 generates a broadband pulse. At that time, a transmission data signal input to the terminal 1001 is received, and a predetermined modulation is performed on the generated pulse. As a modulation method, pulse position modulation (PPM) for shifting the generation position of the generated pulse, two-phase modulation (BPM: Bi-Phase Modulation) for inverting the polarity of the generated pulse, and the like are often used. The generated and modulated pulse is radiated to the space through the transmission antenna 1003.

  Here, the mixer circuit of the above embodiment can be used for the pulse generation circuit 1002. That is, the serialized information to be transmitted may be input as the baseband signal to the input terminals 103 and 104 (FIGS. 1, 6, 7, and 8) as the input signal of the source ground stage. In this case, when transmitting by PPM, the timing of the start signal (the initialization signal IS in FIG. 3 and signals corresponding to D0 and XD0 in FIG. 8) is adjusted in order to shift the pulse position. In the case of BPM, the polarity of the signal input to the input terminals 103 and 104 is changed in synchronization with the activation signal. The mixer circuit of the above embodiment has a baseband signal and control signals G1 to G4 (FIGS. 1, 3, 6, and 7), or D1 to D8 and XD2 to XD9 (FIGS. 8 and 9). Since the synthesized template pulse (Ga-Gb in FIG. 2, SUM1, SUM2 in FIG. 9) and the product of the baseband signal are output, UWB-IR modulation can be performed simultaneously.

  Next, a configuration of a receiving device using the mixer circuit of the above embodiment will be described with reference to FIG. A signal received by the antenna 1004 is input to the mixer circuit 1005 of the above embodiment. As the mixer circuit 1005, the mixer circuits 1, 600, 700, and 800 shown in FIGS. Since these mixer circuits 1, 600, 700, and 800 can process differential signals, the antenna 1004 can also use a balanced antenna. By handling differential signals, it is possible to reduce the power supply voltage of the circuit and reduce signal distortion. The mixer circuit of the above embodiment has both the function of low noise amplification and the function of generating a template signal and multiplying the amplified signal. The circuit 1006 is a circuit that generates a control signal to be sent to the mixer circuit 1005, and the circuit shown in FIG. 3, FIG. 5, or FIG. 8B can be used.

  The received signal amplified by the mixer circuit 1005 and multiplied by the template pulse is smoothed by the integrating circuit 1007, and the bit information transmitted from the result is discriminated by the discriminating circuit 1008 and output from the terminal 1009 as a demodulated output. . That is, the mixer circuit 1005 and the integrating circuit 1007 constitute a correlator, and the received signal and the template pulse correlation are calculated by this circuit. From the correlation calculation result, the transmitted signal is judged (demodulated). The discriminating circuit 1008 also takes control of the entire circuit, synchronizes with the demodulated signal, estimates the timing when the next signal arrives, sends a start signal to the circuit 1006 that generates the control signal of the mixer circuit 1005, and supplies the mixer circuit 1005 A control signal to be applied is generated.

  The mixer circuit of the above embodiment has both a low-noise amplification function and a template signal generation function and a multiplication function of the amplified input signal and the template signal, so that the circuit configuration is greatly simplified. Further, in the mixer circuit of the above embodiment, in a stationary state (standby state) in which no activation signal is input, the current consumption is only a leakage current of the circuit element and is extremely small. As a result, the power consumption of the system can be extremely reduced.

  In the above-described configuration according to the fourth embodiment, the same mixer circuit can be shared by the transmission device and the reception device. This makes it possible to further simplify the configuration when configuring a transceiver device in which a transceiver is integrated.

(Fifth embodiment)
Next, a fifth embodiment of the mixer circuit will be described. In the above embodiment, the control signal input to the mixer circuit has been described as a digital value that takes two values, but an analog signal such as a sine wave can also be input.

In the circuits of FIGS. 1, 6, and 7 that require four control signals when inputting an analog signal, the control signals are divided into two sets of G1 and G3 or G2 and G4, and differential signals are respectively provided. Input v _b1 ± v ₁ and v _b2 ± v ₂ . Here, v _b1 and v _b2 are in-phase components of each pair of signals, and are biases applied to the signals. As v _b1 and v _b2 , a direct current with a constant voltage is given. Further, v ₁ and v ₂ are differential components and analog control signals.

When the signal is applied in this way, if the input signal (the differential component of the signal applied to the input terminals 103 and 104) is v _r , the output signal appearing at the output terminal is the product of these three differential components. contains signal components v ₁ × v ₂ × v _r represented. Therefore, when sine waves of frequencies f _r , f ₁ , and f ₂ are considered as v _r , v ₁ , and v ₂ , the output includes a signal having a frequency component of f _r ± f ₁ ± f ₂ .

If f _r = f ₁ + f ₂ (or f ₁ = f ₂ = f _r / 2) is set, v _r can be frequency converted and dropped directly to baseband. In this case, because not the same as the frequency of the local oscillator circuit is v _r, no DC offset to be a problem in the receiver a number of direct conversion system. As a result, not only UWB but also a communication receiver using a narrowband signal using normal phase modulation, frequency modulation, or amplitude modulation can be greatly simplified.

  FIG. 11 is a block diagram when the receiver is configured according to the above principle. A reception signal received by the antenna 1101 is directly input to the mixer circuit 1102 of the above embodiment. Since the mixer circuit of the above embodiment also has a low noise amplification function, it is not necessary to place a low noise amplification circuit in front of the mixer. Here, the circuit described in FIG. 1, FIG. 6, or FIG. 7 can be used.

Local oscillation circuits 1103 and 1104 oscillate frequencies f ₁ and f ₂ , respectively. Now, if the frequency of the signal to be received is set to f _r and set to f _r = f ₁ + f ₂ , the received signal is converted to baseband. The circuit 1105 includes a filter and a demodulation circuit that extract only a baseband component from the signal converted by the mixer circuit 1102. The received signal is demodulated and the received information is restored in accordance with the modulation scheme (such as phase modulation, frequency modulation, amplitude modulation) of the received signal. The local oscillation circuits 1103 and 1104 can track the received signal by a phase locked loop or the like and always perform control such as keeping the phase difference between the received signal and the carrier wave constant, thereby obtaining high receiver performance.

  According to the above configuration, a direct conversion receiver can be easily configured. The direct conversion receiver has no intermediate frequency amplification stage, so the configuration itself is simple, and it has higher sensitivity than the heterodyne system that repeats the conversion many times. But it is very resistant. In addition, the conventional direct conversion method has a serious problem of DC offset, but this mixer circuit does not cause DC offset. Furthermore, since this mixer circuit also has a low noise amplification function, the circuit can be further simplified. Further, as described above, by setting the output potential of the local oscillation circuits 1103 and 1104 given as the control voltage to the mixer circuit 1102 to a predetermined value, the operation of the mixer circuit is stopped and the circuit current is minimized ( Can be set to almost zero). This is extremely effective for reducing power consumption during circuit standby.

In the above, the case where two local oscillation circuits are provided has been described, but more signals may be input. Hereinafter, the case where an integer n signals of 2 or more are input will be described. The circuit shown in FIG. 8A further includes four transistor groups that operate in the state of the logical product of D _i−1 and XD _{i and} the logical product of D _i and XD _{i + 1} described in the third embodiment. The added circuit is an example of n = 8. Here, the signal sequence v _i (i = 1 to n) is given to D _i and XD _i as differential signals. However, in FIG. 8A, although there is no XD1 terminal, XD9 is substituted for XD1. The switch group of the logical product of D _i-1 and XD _{i and} the logical product of D _i and XD _{i + 1} requires the signal of D9, which is substituted by D1. In general, when n sets of series transistors are arranged in each group, up to n + 1th control signals are required, but Dn _{+ 1} and XDn _{+ 1} are respectively assigned D1 and XD1. When the signal sequence v _i is given as a differential signal between D _i and XD _i according to the above rules, the input signal v _r and the product of those products, that is, v _r × v ₁ × v ₂ × component of ·· × v _n appears. This allows mixing of four or more frequencies. If they are used well, they can be applied to simplify equipment and remove specific interference frequencies.

  Although the embodiment of the mixer circuit has been described above, the present invention is not limited to such an embodiment, and can be implemented in various forms without departing from the spirit of the mixer circuit. Hereinafter, a modification will be described.

  (Modification 1) Modification 1 of the mixer circuit will be described. In the first embodiment, the case where a MOS transistor is used has been described as an example. However, the present invention is not limited to this. For example, a bipolar transistor is used, and the corresponding electrodes are changed from source to emitter and gate, respectively. It can be operated in exactly the same way by replacing the base, drain and collector with an appropriate bias.

  (Modification 2) Modification 2 of the mixer circuit will be described. If the number of transistors constituting the grounded gate stage is not two, but three or more, various control by combinations of control signals becomes possible, and if there are some restrictions on the generation of control signals, the restrictions are relaxed.

  (Modification 3) Modification 3 of the mixer circuit will be described. In the first embodiment, the differential signal is handled using two identical circuits. However, the source grounded stage transistors (N-channel transistors 101 and 102 in FIGS. 1, 6, 7 and 8A) are used. If each source is connected to a current source and the current flowing through both transistors is controlled so as to be always constant, the common-mode gain can be further reduced, and the effect of differential amplification can be further enhanced.

  (Modification 4) Modification 4 of the mixer circuit will be described. In the first embodiment, differential signals are handled using two identical circuits. Conversely, a single-ended signal can be handled by using only one of the two circuits. In this case, the gain decreases, but the number of elements used is halved and the power consumption is also halved. The control signal may be a single-ended signal, and the circuit is further simplified.

  As described above, according to the present mixer circuit, it is possible to provide a mixer circuit having a function of a low noise amplifier circuit, a function of generating a template pulse, and a function of minimizing standby power consumption. By using this, an efficient UWB-IR receiver can be configured. In addition, since this mixer circuit can provide a mixer circuit that does not have a problem of DC offset even when used in a receiver in a conventional narrow-band communication system, a direct conversion system receiver configuration with high performance and simple configuration can be provided. Is possible.

1 is a circuit diagram showing a configuration of a mixer circuit according to a first embodiment. FIG. 4 is a timing chart for explaining the operation of the mixer circuit according to the first embodiment. The circuit diagram which shows the structure of the logic circuit which emits the control signal given to a mixer circuit. FIG. 5 is a timing chart for explaining the operation of a logic circuit that issues a control signal to be supplied to the mixer circuit. The circuit diagram which shows the structure of the logic circuit which emits the control signal given to a mixer circuit. A circuit diagram explaining a mixer circuit concerning a 2nd embodiment. The circuit diagram explaining another example of the mixer circuit concerning a 2nd embodiment. A circuit diagram explaining a mixer circuit concerning a 3rd embodiment. The timing diagram explaining operation | movement of the circuit which emits the control signal given to the mixer circuit which concerns on 3rd Embodiment. The UWB-IR communication apparatus comprised using the mixer circuit which concerns on 4th Embodiment. The receiver comprised using the mixer circuit which concerns on 5th Embodiment. The block diagram and timing diagram explaining the conventional UWB-IR communication apparatus. Conventional low noise amplifier circuit.

  DESCRIPTION OF SYMBOLS 1,600,700,800 ... Mixer circuit, 101,102 ... N channel transistor, 112-119, 122-129 ... N channel transistor, 801-832 ... N channel transistor, 300 ... Logic circuit, 305 ... Control circuit, 500 ... Logic circuit, 1002 ... Pulse generation circuit, 1003 ... Transmission antenna, 1004 ... Antenna, 1005 ... Mixer circuit, 1006 ... Circuit, 1007 ... Integration circuit, 1008 ... Discrimination circuit, 1009 ... Terminal, 1101 ... Antenna, 1102 ... Mixer circuit , 1103, 1104... Local oscillator circuit, 1105... Circuit, 1205... Low noise amplifier circuit, 1206.

Claims (6)

A mixer circuit that outputs a first output signal and a second output signal obtained by mixing a first input signal and a second input signal,
A first common-source amplifier circuit for amplifying the first input signal;
A second common-source amplifier circuit for amplifying the second input signal;
A first signal output unit for outputting the first output signal;
A second signal output unit for outputting the second output signal;
A first transistor including a transistor of n rows and m columns (n is an integer of 2 or more and m is an integer of 2 or more) connected between the first common-source amplifier circuit and the first signal output unit; Group,
A second transistor group including n rows and m columns of transistors connected between the first common-source amplifier circuit and the second signal output unit;
A third transistor group including n rows and m columns of transistors connected between the second common-source amplifier circuit and the first signal output unit;
A fourth transistor group including n rows and m columns of transistors connected between the second common-source amplifier circuit and the second signal output unit;
N × m control signals for driving the first transistor group, the second transistor group, the third transistor group, and the fourth transistor group;
including,
A mixer circuit characterized by that.   2. The mixer circuit according to claim 1, wherein at least one of the n × m control signals includes the first transistor group, the second transistor group, the third transistor group, and the fourth transistor group. A mixer circuit including a potential for shutting off a transistor group.   3. The mixer circuit according to claim 1, wherein the n × m control signals are binary, and one potential of the binary values is the first transistor group and the second transistor group. The third transistor group is a potential that cuts off the fourth transistor group, and the other potential is the first transistor group, the second transistor group, the third transistor group, and the fourth transistor group. A mixer circuit having a predetermined bias value given to a transistor group.   A communication apparatus comprising the mixer circuit according to any one of claims 1 to 3.   4. A communication device that receives a UWB-IR signal including the mixer circuit according to claim 1, wherein the n × m control signals of the mixer circuit are the UWB signals. A communication apparatus comprising a pulse signal having a width wider than a template pulse of an IR signal. 4. The communication apparatus including the mixer circuit according to claim 1, wherein the n × m control signals of the mixer circuit are signals having a component of at least a frequency f _{1. 5.} and wherein a signal having a component of the frequency f _2, the frequency f _r of the received signal, the communication apparatus characterized by matching either one of the sum or difference between the frequency f ₁ and the frequency f _2.

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